JP5990502B2 - Control device, control system, control method and control program for electric power equipment - Google Patents

Description

  The present invention relates to an apparatus, a system, a method, and a computer program for controlling a power electronics product.

  Power electronics products such as power supplies and motors are often controlled by dedicated control devices. For example, in the case of an in-vehicle motor, the control program sends a control signal based on various parameters (control variables) to the motor, and the motor operates according to these parameters. Examples of parameters include P value, I value, and D value of PID (Proportional, Integral, Differential) control. The control program also reads various state data of the motor. The state data includes a motor current value. Setting of parameters and reading of status data by the control program are performed at high speed and periodically, generally 20 to 50 kHz (once / 50 μsec to 1 time / 20 μsec), and in some cases 200 kHz (once) It is necessary to control the motor at a high frequency of about 5 μsec).

  When developing a motor, the developer develops a control program at the same time as the motor, and checks the product performance while moving the motor by the control program (see Patent Document 1 and Non-Patent Document 1). Even during development, the control program needs to “interact” with the motor at high speed and regularly.

JP 2004-38703 A

Masashi Fukuda, Masayasu Hamada, Takanori Sugita, Sanao Sakamoto “Proposal of New Development Environment for Power Electronics”, 2008 Annual Conference of the Institute of Electrical Engineers of Japan, March 19, 2008 (issued), p. 254-255

  In Non-Patent Document 1, a control device (Control CPU in FIG. 4) is connected to a PC via a hardware product called a wave unit (WAVE2Unit in FIG. 4). In the PC, various state data are displayed in waveform like an oscilloscope. In the case of Non-Patent Document 1, the control program executed by the control device reads the status data triggered by a timer interrupt from the power electronics product, and transmits it to the wave unit. In addition, the control program acquires parameters written in the I / O memory of the wave unit from the PC, and sets control conditions for the power electronics product.

  The control program of Non-Patent Document 1 is in charge of two processes of access to a power electronics product and communication with a wave unit. For this reason, communication with the wave unit is an overhead for the control program. If the control frequency of power electronics products increases, there is a possibility that such overhead will be unacceptable in the future.

  A main object of the present invention is to operate a control program for a power electronics product at high speed and stably.

The power equipment control apparatus according to the present invention includes both a first processor that executes a first control program, a second processor that executes a second control program, and both the first and second control programs. A first storage section having a parameter area and a data area accessible from the first storage section.
The first control program controls the power equipment according to the parameters set in the parameter area, and records the status data of the power equipment in the data area. The second control program records the parameter received from the external device in the parameter area, reads the status data from the data area, and transmits it to the external apparatus.

The power equipment control system according to the present invention includes a power equipment control device connected to the power equipment and a user terminal connected to the power equipment control device. The power control apparatus includes a parameter accessible from both the first processor that executes the first control program, the second processor that executes the second control program, and both the first and second control programs. A first storage unit having an area and a data area is provided. The user terminal includes a third processor that executes a monitoring program that transmits parameters to the power control apparatus.
The first control program controls the power equipment according to the parameters set in the parameter area, and records the status data of the power equipment in the data area. The second control program sets the parameter received from the user terminal in the parameter area, reads the state data from the data area, and transmits it to the user terminal.

  The power equipment control program according to the present invention is a program executed in a multi-core processor. This program has a function of reading parameters recorded in the cache memory, a function of setting control conditions of the power device according to the read parameters, and a function of reading the status data of the power device and recording it in the cache memory. A first control program realized by one processor, a function of recording parameters transmitted from an external device in a cache memory, and a function of transmitting status data recorded in the cache memory to an external device; And a second control program realized by the processor.

  In the power device control method according to the present invention, the first processor reads the parameter recorded in the cache memory, sets the control condition of the power device according to the read parameter, and the power device status data. Reading and recording in the cache memory repeatedly, the second processor recording the parameter transmitted from the external device in the cache memory, and transmitting the status data recorded in the cache memory to the external device And repeatedly executing the step.

  ADVANTAGE OF THE INVENTION According to this invention, the execution efficiency of the control program of power electronics products can be improved.

It is a system configuration figure of an electric power equipment control system. It is a hardware block diagram of an electric power equipment control apparatus. It is a figure which shows the relationship of the various programs performed in an electric power equipment control apparatus and a user terminal. It is a flowchart of a 1st control program. It is a sequence diagram of a wave and a view. It is a sequence diagram of an inspector and a view.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a system configuration diagram of a power equipment control system 100. In the present embodiment, the motor 106 is described as a control target as a kind of power electronics product. The power equipment control system 100 includes a motor 106, a power equipment control device 102, and a user terminal 104. The motor 106 and the power device control apparatus 102 are connected by an external bus, and the power device control apparatus 102 and the user terminal 104 are connected via a communication line such as a LAN (Local Area Network) or a dedicated cable such as an optical cable. Although details will be described later, the power device control apparatus 102 is a device that executes a power device control program as a multi-core system. The user terminal 104 is a general PC.

  The user terminal 104 displays various state data indicating the control state of the motor 106 on a screen like an oscilloscope (not shown; see Non-Patent Document 1). The user terminal 104 transmits a parameter indicating the control condition of the motor 106 to the power device control apparatus 102.

  The power device control apparatus 102 determines the control condition of the motor 106 based on the parameter specified from the user terminal 104. For example, a control condition such as a P value for PID control is set as a parameter. The power equipment control apparatus 102 periodically acquires the state data of the motor 106 and transmits it to the user terminal 104.

  The motor 106 operates according to the control conditions specified by the power equipment control device 102. The motor 106 may periodically issue a hardware interrupt to the power device control apparatus 102 to notify the status data, but in the present embodiment, a first control program (described later) of the power device control apparatus 102 is used. A description will be given assuming that state data is polled from the motor 106 by loop processing.

  FIG. 2 is a hardware configuration diagram of the power device control apparatus 102. The power device control apparatus 102 is a so-called multi-core system, and includes a core 0 package 108 and a core 1 package 110. The core 0 package 108 and the core 1 package 110 include CORE0 (second processor) and CORE1 (first processor), respectively. CORE0 and CORE1 are processors such as a CPU (Central Processing Unit) and a DSP (Digital Signal Processor).

  In the core 0 package 108, CORE0 is attached with a primary cache L1-0 and a secondary cache L2-0. Similarly, in the core 1 package 110, the primary cache L1-1 and the secondary cache L2-1 are attached to the CORE1. In the present embodiment, it is assumed that the primary cache L1 is 64 KB and the secondary cache L2 is 1024 KB. Further, the primary cache L1 may be an aggregate of a plurality of caches.

  The power device control apparatus 102 includes an SRAM (Static Random Access Memory) 112 and a DRAM (Dynamic Random Access Memory) 114. In the present embodiment, the size of the SRAM 112 is 1 MB. The DRAM 114 is a so-called DDR3 (Double-Data-Rate 3) type, and its size is 512 MB.

  The access speed is higher in the order of the primary cache L1 and the secondary cache L2 (local cache memory), the SRAM 112, and the DRAM 114, and the storage capacity is larger in the order of the DRAM 114, the SRAM 112, and the local cache memory.

  All of the SRAM 112 and a part of the DRAM 114 constitute a shared memory space (first storage unit). In addition, the characteristic point in this embodiment is that the primary cache L1-1 of the core 1 package 110 also constitutes a part of the shared memory space. That is, the cache function of the primary cache L1-1 is set off. In FIG. 2, areas constituting the shared memory space (hereinafter referred to as “shared areas”) are indicated by hatching. The shared memory space is an area accessible from both CORE0 and CORE1, and is assigned a global address. In the present embodiment, the primary cache L1-1 does not function as a cache, but is used as an ultra-high-speed, small-capacity shared area that can be accessed from both CORE0 and CORE1 by a global address. Note that a local area (area accessible only to CORE0) in the DRAM 114 that does not form a shared area corresponds to the “second storage unit”. Further, the entire DRAM 114 may be set as a local memory of CORE0.

  The primary cache L1-1 is directly accessible not only from CORE1, but also from CORE0. The primary cache L1-0 is accessible only from CORE0 (local cache memory). The primary cache L1-0 can send and receive data to and from the SRAM 112 and the DRAM 114 based on the control of CORE0.

  In this embodiment, only the primary cache L1-1 is used as a shared area, but all or part of the secondary cache L2-1, the primary cache L1-0, and the secondary cache L2-0 are similarly used as shared areas. You may release.

  FIG. 3 is a diagram illustrating a relationship between various programs executed in the power device control apparatus 102 and the user terminal 104. The second control program 118 executed by CORE0 and the first control program 116 executed by CORE1 are collectively referred to as “power control program”.

  In the shared area 126, a parameter area 128 for storing parameters and a data area 130 for storing state data are secured. In particular, in the present embodiment, since the total size of the parameter area 128 and the data area 130 is several hundred to several thousand bytes, it is secured in the primary cache L1-1. Of course, other caches such as the primary cache L1-0 and the secondary cache L2-0 may be released as the shared area 126, and the parameter area 128 and the like may be set in these cache memories. When the size of the parameter or state data becomes too large to fit in the primary cache L1 or the secondary cache L2, all or part of the parameter area 128 or the data area 130 is secured in the shared area 126 such as the SRAM 112 or the DRAM 114. Also good.

  In the user terminal 104, a view 124 (monitoring program) that is a display program is executed. The user terminal 104 may have a single processor (third processor) or may be a multi-core system such as the power device control apparatus 102. The view 124 transmits various parameters to the power device control apparatus 102, receives state data from the power device control apparatus 102, and updates the display image. The view 124 can also display a waveform image such as an oscilloscope.

  The first control program 116 is executed in the CORE 1, reads parameters from the parameter area 128, and controls the motor 106. Further, the state data of the motor 106 is overwritten and recorded in the data area 130.

The second control program 118 receives parameters from the view 124 and writes them in the parameter area 128. In addition, the state data written in the data area 130 is transmitted to the view 124. The second control program 118 includes two processes, an inspector 120 and a wave 122. The inspector 120 reads the specified state data in one shot based on the parameter specified from the view 124. Specifically, when receiving an instruction specifying a parameter or state data to be read from the view 124, the inspector 120 records the parameter in the parameter area 128, reads the specified state data from the data area 130, and immediately displays it in the view 124. send. On the other hand, the wave 122 periodically reads the status data from the data area 130 and stores it in the DRAM 114. Then, when the state data is accumulated in a predetermined amount, for example, about 9000 bytes, it is collectively transmitted to the view 124. The data is transmitted after being stored in order to increase the data size per packet and increase the communication efficiency. The view 124 draws a graph based on the received state data.
The second control program 118 may store intermediate data in the primary cache L1-0 as appropriate, or may store intermediate data in the SRAM 112 or DRAM 114 as necessary.

  The first control program 116 does not directly interact with the second control program 118 or the user terminal 104. The first control program 116 only controls the motor 106 based on the parameters in the parameter area 128 and only records the state data in the data area 130. Moreover, in the case of the present embodiment, the parameter area 128 and the data area 130 are secured in the primary cache L1-1 of the CORE1, so that the access speed to these areas is as high as that of the cache. The first control program 116 does not need to go to the second control program 118 or the view 124 and wait for the second control program 118 to write parameters to the parameter area 128. Therefore, the first control program 116 can operate stably at high speed without being interrupted by the execution state of other programs. Although not essential, in this embodiment, the calculation resource of CORE 0 is allocated only to the first control program 116.

  The writer in the parameter area 128 is the second control program 118, the reader is the first control program 116, the writer in the data area 130 is the first control program 116, and the reader is the second control program 118. Therefore, regarding the access to the parameter area 128 and the data area 130, the second control program 118 and the first control program 116 do not have a logical competitive relationship, so exclusive control by a mutex or the like is unnecessary, and the first control program 116 and the second control program 118 can operate asynchronously with each other.

  In general, the first control program 116 is loaded into the DRAM 114 or the SRAM 112 and is executed by the CORE1 while using the primary cache L1 or the secondary cache L2. In the present embodiment, the entire first control program 116 may be loaded into the primary cache L1-1 (shared area 126) from the beginning. When the size of the first control program 116 does not fit in the primary cache L1-1, the secondary cache L2 may be released as the shared area 126 and loaded into the secondary cache L2. Since the primary cache L1 and the secondary cache L2 are originally high-speed cache memories, if the entire first control program 116 can be loaded into the primary cache L1-1 or the secondary cache L2-1, it will be more loaded than the SRAM 112 or the DRAM 114. High-speed execution is possible. When the size of the first control program 116 exceeds the total of the primary cache L1-1 and the secondary cache L2-1, the first control program 116 is loaded into the SRAM 112 and the DRAM 114.

  Since the first control program 116 is often a relatively simple program, it is sufficiently possible to load the whole into these local cache memories. Furthermore, if the first control program 116 is stored in the cache, the processing speed of the first control program 116 does not change depending on the presence or absence of a cache hit. In particular, in the control of power electronics products with severe control conditions, it is desirable to release all or part of the cache memory as a memory area not only from the processing speed of the first control program 116 but also from the viewpoint of speed stability.

  For the same reason, the second control program 118 may also be stored in the primary cache L1-0 or the secondary cache L2-0.

  FIG. 4 is a flowchart of the first control program 116. First, the first control program 116 reads state data from the motor 106 (S10), reads parameters and control conditions from the parameter area 128 (S12), and sets command values such as the rotation speed and current value to a predetermined arithmetic expression. Therefore, calculation is performed (S13), and this is set in the motor 106 (S14). The arithmetic expression may be arbitrarily designed by the developer of the first control program 116. Next, the state data read in S10 is overwritten in the data area 130 (S18). If stop is not instructed (N in S20), the process returns to S10. Basically, it is feedback control in which an appropriate command value is recalculated in S13 based on the state data read in S10 and the control condition read in S12. In addition, parameter setting by the second control program 118 is performed. The processing content is to change the control conditions as appropriate.

  In the present embodiment, since both the parameter area 128 and the data area 130 are stored in the primary cache L1-1, the first control program 116 accesses only the primary cache L1-1 except for the motor 106 access. Not. Further, access to the primary cache L1-1 does not logically compete with other processes. For this reason, the first control program 116 can be repeatedly executed stably at high speed without the overhead of waiting for execution of another process. The process shown in FIG. 4 may be executed as a loop process, or may be periodically executed by a hardware interrupt by the motor 106 or the timer of CORE1.

  FIG. 5 is a sequence diagram of the wave 122 and the view 124. First, if there is a parameter input by the user of the view 124 (Y in S30), the view 124 transmits the parameter to the wave 122 (S32). As a parameter, not only the control variable of the motor 106 but also state data to be checked may be designated. The wave 122 records the specified parameter in the parameter area 128 (S34), and notifies the view 124 of the completion of recording (setting of the motor 106 by the first control program 116) (S35). Next, the view 124 transmits a data request signal (S36). If no parameter is input (N in S30), the process skips to the data request process in S36.

  The wave 122 reads the state data from the data area 130 (S37) and records it in the DRAM 114 (S38). If the size of the state data stored in the DRAM 114 has not reached the predetermined amount (N in S40), the process returns to S37, and if it has reached the predetermined amount (Y in S40), the wave 122 (S42). The view 124 updates the drawing according to the received state data (S44). If the view 124 is not instructed to stop (N in S45), the process returns to S30. When the stop is instructed (Y of S46), a stop command is transmitted to the wave 122 (S46), and the process is terminated. When the wave 122 receives the stop command in S46 (Y in S48), the process ends. If the stop command is not received (N in S48), the process returns to S37 and repeats the reading of the state data.

  In S40, when a predetermined time has elapsed since the previous transmission of the state data, the state data may be transmitted even if the state data is not sufficiently accumulated.

  FIG. 6 is a sequence diagram of the inspector 120 and the view 124. The inspector 120 is not a process of automatically repeating access to the shared area 126 like the wave 122, but a process of executing parameter setting and reading of state data in one shot according to an explicit instruction from the view 124. It is.

  First, the user of the view 124 inputs parameters (S50). As a parameter, not only the control variable of the motor 106 but also state data to be confirmed may be designated. The view 124 transmits the parameter to the inspector 120 (S52). The inspector 120 records the designated parameter in the parameter area 128 (S54), reads the status data from the data area 130 (S58), and transmits it as it is (S60). After recording the parameters, a handshake such as a setting completion notice or a data request may be performed in the same manner as the wave 122. The view 124 updates the drawing according to the received state data (S62). Although not shown in FIG. 6, it is also possible to send a stop command from the view 124 to the inspector 120.

  The power device control system 100 has been described above based on the embodiment. The first control program 116 and the second control program 118 send and receive parameters and status data via the shared area 126. Since the first control program 116 does not include a process waiting for processing of another program such as the second control program 118, the first control program 116 can be executed stably and at high speed.

  Furthermore, the first control program 116 specializes in accessing the primary cache L1-1 and does not need to access the lower speed SRAM 112 or DRAM 114. The first control program 116 is stored in the primary cache L1-1 as a whole, and the processing speed is stable because the cache function is not used.

  When the developer develops the first control program 116, it is not necessary to write a code for interacting with other processes such as the second control program 118, so there is an advantage that the first control program 116 can be simplified. Similarly, the second control program 118 and the view 124 can be completely hidden from the developer. The first control program 116 can be freely developed according to the power electronics product to be controlled, but there is also an advantage that the second control program 118 and the view 124 can be made common regardless of the type of power electronics product. No additional hardware such as the wave unit of Non-Patent Document 1 is required, and the second control program 118 executed by CORE0 is in charge of the interaction with the user terminal 104.

  Since the wave 122 stores a certain amount of state data in the low-speed and large-capacity DRAM 114 and then transmits the state data to the user terminal 104, the state data is transmitted at a sufficient speed in terms of human cognitive ability while ensuring communication efficiency. You can draw on the display. The developer can execute writing / reading of parameters and state data by the view 124 while moving the motor 106 by the first control program 116.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  In the present embodiment, the control target has been described as the motor 106, but the present invention is not limited to this. The electric energy and other energy (for example, dynamic energy and light energy) such as an air conditioner, a refrigerator, a water heater, a generator, and a solar cell are used. ), And more preferably a power electronics product whose control conditions should be changed every moment according to the user's operation and environment.

DESCRIPTION OF SYMBOLS 100 Electric power apparatus control system 102 Electric power apparatus control apparatus 104 User terminal 106 Motor 108 Core 0 package 110 Core 1 package 112 SRAM
114 DRAM
116 First control program 118 Second control program 120 Inspector 122 Wave 124 View 126 Shared area 128 Parameter area 130 Data area L1 Primary cache L2 Secondary cache

Claims (7)

A first processor that executes a first control program for controlling the power device;
A second processor for executing a second control program for receiving a parameter for controlling the power device from an external device;
A first storage unit having a parameter area and a data area accessible from both the first and second control programs;
The first control program controls the power device according to the parameter set in the parameter area, records state data of the power device in the data area,
The second control program records the parameter received from the external device in the parameter area, reads the status data from the data area, and transmits it to the external device .
The power device control device, wherein the first control program and the second control program asynchronously transmit and receive the parameter and the state data via the first storage unit . A cache memory attached to both or one of the first and second processors is set as a part of the first storage unit,
The power device control apparatus according to claim 1, wherein both the parameter area and the data area are set in the cache memory.   The power device control apparatus according to claim 2, wherein a cache memory attached to the first processor is set as a part of the first storage unit. A second storage unit having a larger capacity than the first storage unit,
The second control program accumulates the state data read from the data area in the second storage unit, and when the state data is accumulated in a predetermined amount or more in the second storage unit, the second control program power controlling apparatus according to any one of the state data stored in the storage unit of claim 1, characterized by transmitting to the external device 3. A power device controller connected to the power device;
A user terminal connected to the power equipment control device,
The power control device
A first processor that executes a first control program for controlling the power device;
A second processor for executing a second control program for receiving a parameter for controlling the power device from the user terminal;
A first storage unit having a parameter area and a data area accessible from both the first and second control programs;
The user terminal is
A third processor for executing a monitoring program for transmitting the parameter to the power control device;
The first control program controls the power device according to the parameter set in the parameter area, records state data of the power device in the data area,
The second control program sets the parameter received from the user terminal in the parameter area, reads the status data from the data area, and transmits it to the user terminal .
The electric power equipment control system, wherein the first control program and the second control program asynchronously transmit and receive the parameter and the state data via the first storage unit . The power device control system according to claim 5 , wherein the monitoring program of the user terminal displays the state data transmitted from the second control program on a screen. The power device control system according to claim 5 or 6 , wherein the cache memory attached to the first processor is set as a part of the first storage unit with a cache function turned off.

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