JP5980669B2 - Light emitting diode - Google Patents

Description

  The present invention relates to a light emitting diode.

  LEDs made of semiconductors using gallium nitride (GaN) have excellent light emission rates, long lifetimes, and advantages such as energy saving. In recent years, lighting for display devices, electric bulletin boards, street lamps, automobiles, etc. Widely used as an element.

  Conventional LEDs generally include an n-type semiconductor layer, a p-type semiconductor layer, an active layer, an n-type electrode, and a p-type electrode. The active layer is located between the n-type semiconductor layer and the p-type semiconductor layer. The p-type electrode is disposed on the p-type semiconductor layer, and the n-type electrode is disposed on the n-type semiconductor layer. The p-type electrode is a transparent electrode. When using an LED, by applying a positive voltage and a negative voltage to the p-type semiconductor layer and the n-type semiconductor layer, respectively, electrons and holes from the p-type semiconductor layer and the n-type semiconductor layer are converted into active layers. And radiate visible light in combination with each other (see Patent Document 1).

  However, the conventional LED has a disadvantage that the light emission rate is low. This is because the contact area between the active layer and the n-type semiconductor layer or p-type semiconductor layer is small, and the amount of electrons and holes generated is small.

JP 2005-197505 A

  Therefore, in order to solve the above problems, the present invention provides a light emitting diode having a high light emission rate.

  The light-emitting diode of the present invention includes a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode, and the first semiconductor layer has the first surface and the second surface facing each other. A first semiconductor layer, an active layer, and a second semiconductor layer are sequentially stacked on the first electrode along a direction away from the first electrode, and the first electrode covers the first surface of the first semiconductor layer The second electrode is electrically connected to the second semiconductor layer, the surface of the second semiconductor layer away from the active layer is a light emitting surface of the light emitting diode, and the plurality of three-dimensional nanostructures are The semiconductor layer, the active layer, or the second semiconductor layer is disposed on the surface of one layer, two layers, or three layers in the form of a one-dimensional array, and each three-dimensional nanostructure has one first protrusion and one surface. Two first protrusions, the first protrusion and the second protrusion are parallel to each other and extend in the same direction, One first groove is formed between the first protrusion and the second protrusion of the three-dimensional nanostructure, and one second groove is formed between each two adjacent three-dimensional nanostructures. A groove is formed, and the depth of the second groove is deeper than the depth of the first groove.

  In the light emitting diode of the present invention, a plurality of three-dimensional nanostructures are installed on the second surface of the first semiconductor layer in the form of a one-dimensional array.

  In the light emitting diode of the present invention, the plurality of three-dimensional nanostructures are formed on both the second surface of the first semiconductor layer and the surface of the active layer that is separated from the first semiconductor layer, or on the second surface and the first surface of the first semiconductor layer. Placed in the form of a one-dimensional array on both the active layer and the remote surface of the two semiconductor layers, or on both the first surface of the first semiconductor layer and the second surface of the first semiconductor layer.

  In the light emitting diode of the present invention, a plurality of three-dimensional nanostructures are formed at three locations: the second surface of the first semiconductor layer, the surface of the active layer that is separated from the first semiconductor layer, and the surface of the second semiconductor layer that is separated from the active layer. Alternatively, the first semiconductor layer is disposed in a three-dimensional array format at three locations on the first surface of the first semiconductor layer, the second surface of the first semiconductor layer, and the surface of the active layer away from the first semiconductor layer.

  Compared with the prior art, the light-emitting diode of the present invention has a three-dimensional structure array. In the three-dimensional structure array, a plurality of M-type three-dimensional nanostructures are arranged in the form of a one-dimensional array. Thereby, since the contact area of the active layer with the n-type semiconductor layer or the p-type semiconductor layer increases, the amount of electrons and holes generated increases, and the light emission rate can be increased.

It is a figure which shows the structure of the light emitting diode which concerns on Example 1 of this invention. It is a figure which shows the three-dimensional nanostructure in FIG. It is a scanning electron micrograph of the three-dimensional nanostructure array in FIG. It is sectional drawing along IV-IV in FIG. It is a figure which shows the manufacturing process of the light emitting diode shown in FIG. It is a figure which shows the manufacturing process of the three-dimensional nanostructure array shown in FIG. It is a figure which shows the structure of the light emitting diode which concerns on Example 2 of this invention. It is a figure which shows the active layer in FIG. It is a figure which shows the manufacturing process of the light emitting diode shown in FIG. It is a figure which shows the structure of the light emitting diode which concerns on Example 3 of this invention. It is a figure which shows the 2nd semiconductor layer in FIG. It is a figure which shows the structure of the light emitting diode which concerns on Example 4 of this invention. It is a figure which shows the structure of the light emitting diode which concerns on Example 5 of this invention. It is a figure which shows the structure of the light emitting diode which concerns on Example 6 of this invention.

  Hereinafter, examples of the light emitting diode and the method for manufacturing the same of the present invention will be described. In each of the following embodiments, the same member is labeled with the same symbol.

Example 1
Referring to FIG. 1, the light emitting diode 10 according to the first embodiment includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120.

  The first semiconductor layer 110 and the second semiconductor layer 130 are each composed of one of two types of an n-type semiconductor layer and a p-type semiconductor layer. When the first semiconductor layer 110 is an n-type semiconductor layer, the second semiconductor layer 130 is a p-type semiconductor layer. When the first semiconductor layer 110 is a p-type semiconductor layer, the second semiconductor layer 130 is an n-type semiconductor layer. It is a semiconductor layer. The n-type semiconductor layer provides electrons, and the p-type semiconductor layer provides holes. The n-type semiconductor layer is made of one or several types of n-type gallium nitride, n-type gallium arsenide, and n-type copper phosphate. The p-type semiconductor layer is made of one or several kinds of p-type gallium nitride, p-type gallium arsenide, and p-type copper phosphate. The thickness of the first semiconductor layer 110 is 1 μm to 5 μm. In the present embodiment, the first semiconductor layer 110 is n-type gallium nitride.

  In this embodiment, the first semiconductor layer 110 has a first surface (not shown) and a second surface (not shown) that face each other. The first surface is in contact with the first electrode 112. An active layer 120 and a second semiconductor layer 130 are stacked on the second surface.

  Referring to FIGS. 1 and 2, the second surface of the first semiconductor layer 110 has a three-dimensional nanostructure array, and the three-dimensional nanostructure array is disposed in a first area of the second surface. The three-dimensional nanostructure array includes a plurality of three-dimensional nanostructures 113. The three-dimensional nanostructure array may be provided alone on the surface of the first semiconductor layer 110 in contact with the active layer 120, or may have an integral structure with the first semiconductor layer 110. Preferably, the three-dimensional nanostructure array may be formed integrally with the first semiconductor layer 110. Here, the integrated structure means that the three-dimensional nanostructure 113 is integrated with the first semiconductor layer 110 without a gap between the surface of the first semiconductor layer 110. When the three-dimensional nanostructure array is installed alone on the surface of the first semiconductor layer 110, the material may or may not be the same as the material of the first semiconductor layer 110. In this embodiment, the three-dimensional nanostructure array has an integral structure with the first semiconductor layer 110.

  Referring to FIGS. 2 and 3, each three-dimensional nanostructure 113 in the three-dimensional nanostructure array is a protruding structure, and from the main body surface of the first semiconductor layer 110, the main body of the first semiconductor layer 110. Projects in the direction away from the surface. On the main body surface of the first semiconductor layer 110, the extending directions of the plurality of three-dimensional nanostructures 113 are the same. Moreover, the cross section in the extending direction of each three-dimensional nanostructure 113 is M-type, but the cross-section in each extending direction of the plurality of three-dimensional nanostructures 113 is also M-type, The shape and area are preferably the same.

  Each of the three-dimensional nanostructures 113 extends on the main body surface of the first semiconductor layer 110 by a straight line, a broken line, or a curved line, and is parallel to each other. In the plurality of three-dimensional nanostructures 113, the distance between two adjacent three-dimensional nanostructures 113 is 0 nm to 200 nm. The stretching direction of the three-dimensional nanostructure 113 may or may not change. When the stretching direction does not change, the stretching direction is a straight line. In this case, the plurality of three-dimensional nanostructures 113 are straight and extend in parallel to each other. When the stretching direction changes, the stretching direction is a polygonal line or a curved line. In this case, the plurality of three-dimensional nanostructures 113 are each a polygonal line or a curved line and extend in parallel with each other. The stretching direction may or may not change. However, it is preferable that an arbitrary point is selected in the stretching direction, and the cross sections of the plurality of three-dimensional nanostructures 113 at the arbitrary points are each M-shaped.

  The plurality of three-dimensional nanostructures 113 are distributed on the surface of the main body of the first semiconductor layer 110 by a one-dimensional array to form a three-dimensional nanostructure array. Here, the one-dimensional array means that a plurality of three-dimensional nanostructures 113 are arranged on the surface of the main body of the first semiconductor layer 110 along one direction in the form of a one-dimensional array. Further, the arrangement in the form of a one-dimensional array means that, for example, as shown in FIG. 2, strip-like protrusion structures are arranged at equal intervals along one direction Y direction or concentric protrusions. This means that the partial structure and the concentric quadrangular protrusion structure are arranged concentrically along one direction away from the circular center.

  Referring to FIG. 2, in the present embodiment, the three-dimensional nanostructure 113 is a strip-shaped protrusion structure. The strip-shaped protrusion structure is straight and extends along the same direction. Here, the extending direction of the strip-shaped protruding structure is defined as the X direction, and the direction perpendicular to the extending direction of the strip-shaped protruding structure is defined as the Y direction. In the X direction, one end of the strip-like protruding structure extends to the opposite other end along the X direction, and in the Y direction, the strip is composed of two protruding structures along the Y direction. A plurality of three-dimensional nanostructures 113 are arranged in parallel with each other. At this time, the cross section in the X direction of each three-dimensional nanostructure 113 is M-shaped. Therefore, the three-dimensional nanostructure 113 is an M-type three-dimensional nanostructure.

  Referring to FIG. 4, each M-type three-dimensional nanostructure 113 includes a first protrusion 1132 and a second protrusion 1134. The extending directions of the first protrusion 1132 and the second protrusion 1134 are the same, and they are all parallel to each other and extend along the X direction. The first protrusion 1132 has two intersecting surfaces, which are a first surface 1132a and a second surface 1132b, respectively. The first surface 1132a and the second surface 1132b may each be a flat surface, a curved surface, or a folded surface. In the present embodiment, the first surface 1132a and the second surface 1132b are flat surfaces. The first surface 1132a extends in a direction away from the surface of the main body of the first semiconductor layer 110 and intersects the second surface 1132b at an angle θ to form a tip (not shown) of the first protrusion 1132. . The first surface 1132a extends the surface of the main body of the first semiconductor layer 110 and intersects the surface of the main body of the first semiconductor layer 110 at an angle α. The angle θ is 0 ° (not including 0 °) to 180 ° (not including 180 °), but is preferably 30 ° to 60 °. The angle α is 0 ° (not including 0 °) to 90 °, and preferably 80 ° to 90 °.

  The structure of the second protrusion 1134 is basically the same as the structure of the first protrusion 1132. The second protrusion 1134 has two intersecting surfaces, and the two surfaces are a first surface 1134a and a second surface 1134b, respectively. The first surface 1134a extends in a direction away from the surface of the main body of the first semiconductor layer 110 and intersects the second surface 1134b at an angle θ to form the tip of the second protrusion 1134. The first surface 1134a extends the surface of the main body of the first semiconductor layer 110 and intersects the surface of the main body of the first semiconductor layer 110 at an angle α. Furthermore, the second surface 1134b of the second protrusion 1134 intersects the second surface 1132b of the first protrusion 1132 at a portion close to the surface of the main body of the first semiconductor layer 110, and the three-dimensional nanostructure 113. The first groove 1136 is formed. A surface of the second surface 1132b of the first protrusion 1132 extending the surface of the main body of the first semiconductor layer 110 intersects with a surface parallel to the surface of the main body of the first semiconductor layer 110 at an angle β. The angle β is 0 ° (not including 0 °) to 90 °, but may or may not be the same as the angle α.

  A second groove 1138 is formed between two adjacent three-dimensional nanostructures 113. Specifically, the first surface 1134a of the second protrusion 1134 of one three-dimensional nanostructure 113 and the first surface 1132a of the first protrusion 1132 of another adjacent three-dimensional nanostructure 113 are: The second groove 1138 is formed by crossing the surface of the main body of the first semiconductor layer 110. That is, an intersection line between the first surface 1134a of the second protrusion 1134 of one three-dimensional nanostructure 113 and the first surface 1132a of the first protrusion 1132 of another adjacent three-dimensional nanostructure 113. Exists on the surface of the main body of the first semiconductor layer 110.

  With respect to the first protrusion 1132 and the second protrusion 1134, there is no restriction on the height of the first protrusion 1132 and the second protrusion 1134 protruding from the surface of the main body of the first semiconductor layer 110 in a direction away from the surface. Here, the height of the first protrusion 1132 and the second protrusion 1134 is the first protrusion 1132 or the second protrusion from the surface of the main body of the first semiconductor layer 110, as indicated by h2 in FIG. 1134 is the distance to the highest point. The height of the first protrusion 1132 and the height of the second protrusion 1134 may or may not be the same. The height of the first protrusion 1132 and the height of the second protrusion 1134 are 150 nm to 200 nm, respectively. Further, the aggregate of the highest points of the first protrusion 1132 or the second protrusion 1134 may be a straight line, a broken line, or a curved line. That is, the intersecting line formed by intersecting the first surface 1132a and the second surface 1132b of the first protrusion 1132 is a straight line, a broken line, or a curved line. Similarly, the intersection line formed by intersecting the first surface 1134a and the second surface 1134b of the second protrusion 1134 is also a straight line, a broken line, or a curved line. In each three-dimensional nanostructure 113, the distance between the highest point of the first protrusion 1132 and the highest point of the second protrusion 1134 is 20 nm to 100 nm. In the present embodiment, the height of the first protrusion 1132 and the height of the second protrusion 1134 are the same, and the height is 180 nm. The aggregate of the highest point of the first protrusion 1132 and the highest point of the second protrusion 1134 is a straight line.

  The cross section of the first protrusion 1132 and the second protrusion 1134 in the X direction is trapezoidal or triangular. In the present embodiment, the first protrusion 1132 and the second protrusion 1134 have a triangular cross section in the X direction. The first protrusion 1132 and the second protrusion 1134 form a pair of peaks, and the first protrusion 1132 and the second protrusion 1134 come into contact with each other to form a contact line. Moreover, the cross section of the 1st protrusion 1132 and the 2nd protrusion 1134 may mutually be the same, or may not be the same. When the cross section of the 1st protrusion 1132 and the 2nd protrusion 1134 is the same, the 1st protrusion 1132 and the 2nd protrusion 1134 exhibit a symmetrical structure. Here, the “symmetrical structure” indicates that the cross section of the first protrusion 1132 and the second protrusion 1134 is symmetric with respect to the contact line. Further, the first protrusion 1132 and the second protrusion 1134 may have an asymmetric structure. In the present embodiment, the first protrusion 1132 and the second protrusion 1134 have a symmetrical structure.

  There is a gap between the first protrusion 1132 and the second protrusion 1134, or there may be no gap. The first surface 1132a and the second surface 1132b of the first protrusion 1132 are not flat due to the limitations in manufacturing and other conditions, and for example, a part of the surface may be an arc surface or a bent surface. In this case, the angle θ formed so as to intersect the first surface 1132a and the second surface 1132b is not a sharp corner but another shape such as an arc angle. However, the specific shape of the corner may not affect the overall structure of the first protrusion 1132. In addition, when the surface of a part of the second protrusion 1134 is an arc surface or a bent surface, the angle θ formed by intersecting the second surface 1134b and the second surface 1134a is not a sharp angle. That is, it is another shape such as an arc angle, and the specific shape of the angle may not affect the entire structure of the first protrusion 1134.

  In the three-dimensional nanostructure 113 having each M shape, a first groove 1136 is formed between the first protrusion 1132 and the second protrusion 1134. The direction in which the first groove 1136 extends is the same as the direction in which the first protrusion 1132 and the second protrusion 1134 extend. The cross-sectional shape of the first groove 1136 is V-shaped. The V-shaped groove is located on the surface of the three-dimensional nanostructure 113 and extends along the extending direction of the three-dimensional nanostructure 113. The depth h1 of the first groove 1136 indicates the shortest distance between the surface where the highest point of the first protrusion 1132 or the second protrusion 1134 is located and the surface where the lowest point of the first groove 1136 is located. That is, the depth h <b> 1 of the first groove 1136 is the minimum distance at which the first groove 1136 is recessed in the direction of the first semiconductor layer 110. The depth h1 of the first groove 1136 of each M-type three-dimensional nanostructure 113 is the same. The depth h1 of the first groove 1136 is smaller than the height h2 of the first protrusion 1132 or the second protrusion 1134.

  The second groove 1138 is formed between the adjacent M-type three-dimensional nanostructures 113. The extending direction of the second groove 1138 is the same as the extending direction of the three-dimensional nanostructure 113. The cross section in the extending direction of the second groove 1138 is V-shaped or an inverted trapezoid.

  In the X direction, the shape and area of the cross section of the second groove 1138 at each point are basically the same, but an error occurs due to restrictions in manufacturing and the influence of other conditions. However, it is preferable that the error does not affect the overall shape of the cross section. The first groove 1136 and the second groove 1138 are all different in cross-sectional shape, area, and depth. The depth h2 of the second groove 1138 is the minimum distance from the surface where the highest point of the first protrusion 1132 or the second protrusion 1134 is located to the surface of the main body of the first semiconductor layer 110. The depth h2 of the second groove 1138 is different from the depth h1 of the first groove 1136. The depth h2 of the second groove 1138 is deeper than the depth h1 of the first groove 1136. Preferably, the ratio between the depth h1 of the first groove 1136 and the depth h2 of the second groove 1138 is 1: 1.2 ≦ h1: h2 ≦ 1: 3. The depth h1 of the first groove 1136 is 30 nm to 120 nm, and the depth h2 of the second groove 1138 is 100 nm to 200 nm. In the present embodiment, the depth h1 of the first groove 1136 is 80 nm, and the depth h2 of the second groove 1138 is 180 nm. The distance between the first protrusion 1132 and the second protrusion 1134 and the ratio of the depth h1 of the first groove 1136 and the depth h2 of the second groove 1138 can be selected according to the specific conditions of the product. .

  The width of each three-dimensional nanostructure 113 is the maximum length in which the three-dimensional nanostructure 113 extends in the Y direction. The maximum width λ of the three-dimensional nanostructure 113 in the present embodiment is a length extending along the Y direction on the surface of the main body of the first semiconductor layer 110 in a cross section viewed from the X direction of the three-dimensional nanostructure 113. Point to. The maximum width λ of the M-type three-dimensional nanostructure 113 is 100 nm to 300 nm. The width of the three-dimensional nanostructure 113 decreases along the direction away from the surface of the main body of the first semiconductor layer 110. That is, in each three-dimensional nanostructure 113, the distance between the highest point of the first protrusion 1132 and the highest point of the second protrusion 1134 is shorter than the maximum width of the three-dimensional nanostructure 113.

The distance between two adjacent second grooves 1138 is close to the second groove 1138 from the bottom point of the second groove 1138 that is recessed toward the surface of the main body of the first semiconductor layer 110. It is the distance to the lowest point of the second groove 1138 that is recessed in the direction of the surface of the main body of the first semiconductor layer 110. That is, the distance between two adjacent second grooves 1138 is the maximum width of the three-dimensional nanostructure 113. Further, the distance λ ₀ between two adjacent three-dimensional nanostructures 113 may or may not be the same. The distance λ ₀ increases as the height of the first protrusion 1132 or the second protrusion 1134 increases. When the height decreases, the distance λ ₀ also decreases.

In the Y direction, the distance λ ₀ between two adjacent three-dimensional nanostructures 113 is ₀ nm to 200 nm. When λ ₀ is 0, the cross section of the second groove 1138 is V-shaped. However, when λ ₀ > 0, the cross section of the second groove 1138 is an inverted trapezoid. In the Y direction, the plurality of three-dimensional nanostructures 113 are arranged in parallel with each other with periodicity in the second semiconductor layer 130. The period P of the three-dimensional nanostructure 113 is 100 nm to 500 nm. Further, a circumferential phase P, a maximum width of three-dimensional nano-structures 113 lambda, and the distance lambda ₀ of the two three-dimensional nano-structures 113 adjacent, satisfies the following formula (1).

(Formula 1)
P = λ + λ ₀ (1)

The units of P and λ and λ ₀ are nanometers. When the period P is a fixed value, λ decreases as λ ₀ increases. Conversely, as λ ₀ decreases, λ increases. In addition, the plurality of three-dimensional nanostructures 113 may be formed on the surface of the main body of the first semiconductor layer 110 by a plurality of periodicities. That is, some three-dimensional nanostructures 113 may be arranged with a period P, and some other three-dimensional nanostructures 113 may be arranged with a period P1 (P ≠ P1). When the three-dimensional nanostructures 113 are arranged with a plurality of periodicities, the applicable area can be expanded. In this embodiment, the period P is about 200 nm, and the width λ of the three-dimensional nanostructure 113 is about 190 nm. The distance λ ₀ between two adjacent three-dimensional nanostructures 113 is about 10 nm.

  The active layer 120 is disposed on the second surface of the first semiconductor layer 110. Specifically, the active layer 120 covers a surface having a plurality of three-dimensional nanostructures 113. The surface where the active layer 120 contacts the first semiconductor layer 110 is a patterned surface. The patterned surface of the active layer 120 has a plurality of protrusions and a plurality of grooves, and the pattern formed on the patterned surface of the active layer 120 is a three-dimensional structure in which a plurality of three-dimensional nanostructures 113 are formed. Interdigitate with the pattern of the nanostructure array. Engaging here means that the plurality of grooves on the surface of the active layer 120 correspond to the plurality of protrusions of the three-dimensional nanostructure 113, and the plurality of protrusions on the surface of the active layer 120 correspond to the three-dimensional nanostructure 113. It corresponds to a plurality of grooves.

  The active layer 120 is a single quantum well layer or a multiple quantum well layer and provides photons. The active layer 120 includes gallium nitride, gallium nitride indium (GaInN), aluminum nitride gallium indium (AlGaInN), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium phosphide indium (GaInP), and It consists of one kind or several kinds of aluminum gallium arsenide (GaInAs). The thickness of the active layer 120 is 0.01 μm to 0.6 μm. In this embodiment, the active layer 120 has a thickness of 0.3 μm and is composed of a stacked GaInN layer and GaN layer.

  The second semiconductor layer 130 is disposed on the surface of the active layer 120 opposite to the surface in contact with the first semiconductor layer 110, and covers the entire surface. The surface of the second semiconductor layer 130 that is away from the active layer 120 is the light emitting surface of the light emitting diode 10. The thickness of the second semiconductor layer 130 is 0.1 μm to 3 μm. In the present embodiment, the second semiconductor layer 130 is P-type GaN doped with magnesium, and the thickness thereof is 0.3 μm.

  The first electrode 112 is electrically connected to the first semiconductor layer 110 and completely covers the surface of the first semiconductor layer 110. The first electrode 112 is a p-type electrode or an n-type electrode, but needs to be the same as the type of the first semiconductor layer 110. The first electrode 112 has at least one layered structure. The first electrode 112 is made of one or several of silver, titanium, aluminum, nickel, and gold. In the present embodiment, the first electrode 112 is an n-type electrode having a two-layer structure, and includes a laminated titanium layer having a thickness of 15 nm and a gold layer having a thickness of 200 nm.

  The second electrode 132 is a p-type electrode or an n-type electrode, but needs to be the same as the type of the second semiconductor layer 130. The second electrode 132 is placed in contact with a part of the surface of the second semiconductor layer 130 opposite to the surface in contact with the active layer 120. That is, the second electrode 132 is installed on the light emitting surface of the light emitting diode 10. The shape and position of the second electrode 132 have almost no influence on the light emission rate of the light emitting diode 10. When the second electrode 132 is a transparent electrode, the second electrode 132 is disposed so as to cover the entire surface of the second semiconductor layer 130 opposite to the surface in contact with the active layer 120, thereby emitting light. The current of the diode 10 can be dispersed and the generation of heat can be reduced. The second electrode 132 has at least one layered structure. The second electrode 132 can be made of any one or several of titanium, silver, aluminum, nickel, and gold, or can be made of carbon nanotubes or ITO. In the present embodiment, the second electrode 132 is a p-type electrode and is disposed at one end of the surface of the second semiconductor layer 130. The second electrode 132 is a titanium / gold electrode having a double structure composed of one titanium layer having a thickness of 15 nm and one gold layer having a thickness of 100 nm.

  Further, a reflective layer (not shown) is provided between the first semiconductor layer 110 and the first electrode 112. The reflective layer covers the surface of the first semiconductor layer 110. The reflective layer is made of one or several of titanium, silver, aluminum, nickel, and gold. When the photons formed in the active layer 120 reach the reflection layer, the reflection layer reflects the photons and emits them from the light emitting surface of the light emitting diode 10, so that the light emission rate of the light emitting diode 10 can be increased. .

  The active layer 120 is disposed in the first region of the first semiconductor layer 110 having a plurality of three-dimensional nanostructures 113. Thereby, the area which contacts the active layer 120 and the 1st semiconductor layer 110 can be increased. In addition, since electrons and holes can move to the active layer 120 and be bonded to each other, the number of photons generated can be increased, and the light emission efficiency of the light emitting diode 10 can be increased.

  Referring to FIG. 5, the method for manufacturing the light emitting diode 10 according to the first embodiment provides a substrate 100, a step (S 11) in which the substrate 100 includes a growth surface 101, and a first semiconductor layer on the surface of the growth surface 101. 110 is grown (S12), a three-dimensional nanostructure 113 is formed on the surface of the first semiconductor layer 110 (S13), and a three-dimensional nanostructure 113 of the first semiconductor layer 110 is activated on the surface. The step of growing the layer 120 and the second semiconductor layer 130 in order (S14), the step of removing the substrate 100 and exposing the first semiconductor layer 110 (S15), and the exposed surface of the first semiconductor layer 110 In addition, the step of installing the first electrode 112 (S15), and forming the second electrode 132 on the surface of the second semiconductor layer 130 opposite to the surface in contact with the active layer 120, Comprising a step (S16) which is electrically connected to the second semiconductor layer 130.

In step (S11), the thickness of the substrate 100 is 300 μm to 500 μm. The substrate 100 includes SOI (silicon on insulator), LiGaO ₂ , LiAlO ₂ , Al ₂ O ₃ , Si, GaAs, GaN, GaSb, InN, InP, InAs, InSb, AlP, AlAs, AlSb, AlN, GaP, SiC, SiGe, GaMnAs, GaAlAs, GaInAs, GaAlN, GaInN, AlInN, GaAsP, InGaN, AlGaInN, AlGaInP, GaP: Zn, and GaP: N can be made of one or several kinds.

  The substrate 100 has a growth surface 101 for growing crystals on the first semiconductor layer 110, and the growth surface 101 supports the crystal growth of the first semiconductor layer 110. The material of the substrate 100 can be selected according to the material of the first semiconductor layer 110 to be manufactured, but preferably has a lattice constant and a thermal expansion coefficient similar to those of the material of the first semiconductor layer 110. In this embodiment, the substrate 100 is a sapphire substrate, and its thickness is 400 μm.

  The light emitting diode 10 further includes a buffer layer (not shown). The buffer layer is formed on the growth surface 101. The buffer layer can reduce the lattice mismatch phenomenon between the first semiconductor layers 110 and improve the quality of epitaxial growth between the first semiconductor layers 110. The buffer layer is made of gallium nitride (GaN) or aluminum nitride (AlN) and has a thickness of 10 nm to 300 nm.

  The substrate 100 provides a growth surface 101 on which the first semiconductor layer 110 is grown. The growth surface 101 is a smooth surface from which oxygen and carbon have been removed. The substrate 100 is a single layer or a multilayer. When the substrate 100 is a single layer, the substrate 100 has a single crystal structure. When the substrate 100 is a multilayer, the substrate 100 has at least one single crystal structure, and the single crystal structure has a crystal plane as the growth surface 101.

  In step (S12), the first semiconductor layer 110 is formed by molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), low pressure epitaxial growth, low temperature epitaxy, liquid phase epitaxy (LPE), selective epitaxy, Crystals can be produced by one or several methods such as metal organic chemical vapor deposition (MOVPE), ultrahigh vacuum chemical vapor deposition (UHVCVD), hydride vapor deposition (HVPE), and metal organic chemical vapor deposition (MOCVD). Can be grown.

In this embodiment, the first semiconductor layer 110 is n-type GaN doped with silicon (Si). The first semiconductor layer 110 is grown by metal organic vapor phase epitaxy. Here, high purity ammonia (NH ₃ ) is used as a nitrogen source gas, hydrogen is used as a carrier gas, trimethyl gallium (TMGa) or triethyl gallium (TEGa) is used as a gallium source gas, and silane (SiH ₄ ) is used as a silicon source gas. Used as

  In this embodiment, the first semiconductor layer 110 is grown by placing a sapphire substrate in a vacuum reaction chamber, heating the reaction chamber to 1100 ° C. to 1200 ° C., and introducing a carrier gas and a nitrogen source gas into the reaction chamber. The step of firing the sapphire substrate for 200 seconds to 1000 seconds (S121), the temperature of the reaction chamber is lowered to 500 ° C. to 650 ° C. in the atmosphere of the carrier gas, and at the same time, the source gas of gallium and the nitrogen source gas are supplied Introducing and growing a GaN buffer layer (not shown) at a low temperature (S122), stopping the introduction of the gallium source gas, maintaining the introduction of the carrier gas and the nitrogen source gas, and increasing the temperature of the reaction chamber The temperature is raised to 1110 ° C. to 1200 ° C. and annealing is performed for 30 seconds to 300 seconds (S123), and the temperature of the reaction chamber is set to 100. ° C. and maintained at C. to 1100 ° C., at the same time introducing a raw material gas of gallium again by introducing a silicon source gas, including a step (S124) of growing a first semiconductor layer 110 at a high temperature, the.

  In step (S122), since the first semiconductor layer 110 and the substrate 100 have different lattice constants, the low temperature GaN buffer layer can further reduce the lattice mismatch of the first semiconductor layer 110.

  After step (S123), the temperature of the reaction chamber is maintained at 1110 ° C. to 1200 ° C., and a gallium source gas is introduced into the reaction chamber to grow an undoped conductor layer, and then a silicon source gas And the first semiconductor layer 110 is grown. The undoped conductor layer can further reduce the lattice mismatch of the first semiconductor layer 110.

  Referring to FIG. 6 together, the step (S13) includes a step (S131) of placing the mask layer 103 on the surface of the first semiconductor layer 110, and a step of patterning the mask layer 103 by nanoprinting and etching ( S132), etching the first semiconductor layer 110, patterning the surface of the first semiconductor layer 110, forming a three-dimensional nanostructure preform 1131 (S133), and removing the mask layer 103. Forming a plurality of three-dimensional nanostructures 113 (S134).

  In step (S131), the mask layer 103 has a single layer structure or a composite structure. When the mask layer 103 has a single-layer structure, the material of the mask layer 103 is ZEP520A, HSQ (Hydrogen Silsesquioxane), PMMA (polymethyl methacrylate), PS (polystyrene), SOG (Silicon on Glass), or other organosilicon The mask layer 103 protects the portion of the first semiconductor layer 110 that is covered. In this embodiment, the mask layer 103 is a composite mask layer. The mask layer 103 includes a first mask layer 1032 and a second mask layer 1034. The first mask layer 1032 and the second mask layer 1034 are stacked on the first semiconductor layer 110, and the first mask layer 1032 is covered with the second mask layer 1034. The first semiconductor layer 110 is adjacent to one surface of the first mask layer 1032, and the second mask layer 1034 is adjacent to the surface of the first mask layer 1032 opposite to the surface adjacent to the first semiconductor layer 110. And the first mask layer 1032 is covered. The materials of the first mask layer 1032 and the second mask layer 1034 are not limited, and can be selected according to the required etching depth and etching gas. The first mask layer 1032 is made of ZEP520A, PMMA, PS, SAL601, ARZ720, etc., and the second mask layer 1034 is made of HSQ, SOG (Spin On Glass), or other organosilicon oligomers. In this embodiment, the material of the first mask layer 1032 is ZEP520A, and the material of the second mask layer 1034 is HSQ. The first mask layer 1032 and the second mask layer 1034 are deposited on the surface of the first semiconductor layer 110 by screen printing or spin coating.

  Step (S131) includes a step (S131a) for forming the first mask layer 1032 and a step (S131b) for forming the second mask layer 1034.

  In the step (S131a), in the first stage, the surface of the first semiconductor layer 110 is washed, and the surface of the first semiconductor layer 110 is spin-coated with ZEP520A. The rotation speed of the spin coating is 500 rotations / minute to 6000 rotations / minute, and the time is 0.5 minutes to 1.5 minutes. In the second step, the first mask layer 1032 is formed on the surface of the first semiconductor layer 110 by drying at a temperature of 140 ° C. to 180 ° C. The drying time is 3 minutes to 5 minutes. At this time, the thickness of the first mask layer 1032 reaches 100 nm to 500 nm.

  In step (S131b), in the first stage, HSQ is spin-coated on the surface of the first mask layer 1032 under a high pressure condition. The rotation speed of the spin coating is 2500 rpm to 7000 rpm, and the time is 0.5 minutes to 2 minutes. In the second stage, HSQ is solidified to form a second mask layer 1034. At this time, the thickness of the second mask layer 1034 is 100 nm to 500 nm, preferably 300 nm to 500 nm. The second mask layer 1034 has excellent structural stability, can be pressed at room temperature, and the pressing resolution reaches 10 nm or less.

  Further, one step (S131c) can be included between step (S131a) and step (S131b). In this step (S131c), one transient layer (not shown) is formed on the surface of the first mask layer 1032. In this embodiment, the transient layer is made of silica and is used to protect the first mask layer 1032 when the second mask layer 1034 is etched.

  Step (S132) includes providing a mold 200 having a nanopatterned surface (S132a), pasting the nanopatterned surface of the mold 200 onto the second mask layer 1034, pressing at room temperature, and separating Step (S132b), removing the second mask layer 1034 at the bottom of the formed groove and exposing the first mask layer 1032 (S132c), and the first mask layer corresponding to the lower part of the groove 1032 is removed, the first semiconductor layer 110 is exposed, and a patterned mask layer 103 is formed (S132d).

  In step (S132a), the mold 200 is made of a hard material or a soft material. When the mold 200 is made of a hard material, the material of the mold 200 is, for example, nickel, silicon, or silica. When the mold 200 is made of a soft material, the material of the mold 200 is PET, PMMA, PS (polystyrene), or PDMS (polydimethylsiloxane). A nano pattern is formed on the surface of the mold 200. The nano pattern is a plurality of strip-like protrusions in which a plurality of protrusions are arranged at intervals, or a plurality of concentric protrusion structures arranged at intervals, or a concentric square-like protrusion. An array of structures. In this embodiment, the nano pattern formed on the surface of the mold 200 is an array in which a plurality of protrusions are arranged at intervals. The plurality of protrusions have a strip-like protrusion structure and extend along the same direction. A concave groove is formed between two adjacent strip-shaped protrusion structures. The cross-sections of the strip-shaped protrusion structure and the concave groove viewed from the extending direction thereof are each rectangular. The width of the strip-like protrusion structure along the direction perpendicular to the extending direction of the plurality of protrusions is not limited, and can be selected as necessary. In this embodiment, the material of the mold 200 is silica, the width of the strip-shaped protrusion structure is 50 nm to 200 nm, and the width of the concave groove is 50 nm to 200 nm. Further, the width of the strip-shaped protrusion structure and the width of the groove may or may not be the same.

In step (S132b), the nano pattern on the surface of the mold 200 is transferred to the second mask layer 1034 by applying pressure to the first semiconductor layer 110 through the mold 200 at room temperature. Specifically, first, the surface having the nano pattern of the mold 200 is bonded to the second mask layer 1034, and then the degree of vacuum is 1 × 10 ⁻¹ mbar to ¹ × 10 ⁻⁵ mbar, A pressure of 2 pounds / square foot to 100 pounds / square foot is applied to keep the mold 200 and the second mask layer 1034 pasted together, and this state is maintained for 2 to 30 minutes. And the second mask layer 1034 are separated. As a result, the nano pattern on the surface of the mold 200 is transferred to the second mask layer 1034.

  The nano pattern transferred to the surface of the second mask layer 1034 includes a plurality of strip-shaped protrusion structures extending in parallel, and a concave groove is formed between adjacent strip-shaped protrusion structures, and The size and shape of the concave groove of the second mask layer 1034 correspond to the size and shape of the protrusion of the mold 200, and the size and shape of the strip-shaped protrusion of the second mask layer 1034 are determined by the mold. Corresponds to the size and shape of 200 concave grooves. In the process of applying pressure, the second mask layer 1034 is compressed and thinned by the protrusions of the mold 200, thereby forming concave grooves in the second mask layer 1034. As a result, the second mask layer 1034 at the bottom of the concave groove becomes a thin layer and adheres to the surface of the first mask layer 1032.

In step (S132c), the second mask layer 1034 at the bottom of the groove is removed by plasma etching. In this embodiment, the second mask layer 1034 remaining at the bottom of the groove is removed by a reactive plasma etching method to expose the first mask layer 1032. Specifically, the first semiconductor layer 110 on which the patterned second mask layer 1034 is formed is installed in a reactive plasma etching system, and carbon tetrafluoride (CF) is formed by the reactive plasma etching system. ₄ ) Plasma is formed. Thereafter, the formed carbon tetrafluoride plasma diffuses and moves to the second mask layer 1034. At this time, the second mask layer 1034 at the bottom of the groove is etched by carbon tetrafluoride plasma. The carbon tetrafluoride plasma etching system has a power of 10 W to 150 W, the introduction rate of the carbon tetrafluoride plasma is 2 sccm to 100 sccm, and the atmospheric pressure is 0.5 Pa to 15 Pa. Etching time with carbon plasma is 2 seconds to 4 minutes. In this embodiment, the work rate of the carbon tetrafluoride plasma etching system is 40 W, the introduction flow rate of the carbon tetrafluoride plasma is 26 sccm, the atmospheric pressure is 2 Pa, and the etching time is 10 seconds. By the above method, the second mask layer 1034 at the bottom of the groove is etched by carbon tetrafluoride plasma to expose the first mask layer 1032. At the same time, the protrusion structure of the second mask layer 1034 is etched and thinned. However, at this time, the nano pattern of the second mask layer 1034 can maintain the complete shape.

  In step (S132d), the first mask layer 1032 at the bottom of the groove is etched with oxygen plasma in an oxygen plasma etching system to expose the first semiconductor layer 110. The oxygen plasma etching system has a power of 10 W to 150 W, an oxygen plasma introduction rate of 2 sccm to 100 sccm, a pressure of 0.5 Pa to 15 Pa, and a time of etching with oxygen plasma of 5 Seconds to 5 minutes. In this embodiment, the power of the oxygen plasma etching system is 40 W, the introduction flow rate of the oxygen plasma is 40 sccm, the atmospheric pressure is 2 Pa, and the etching time is 120 seconds. By the above method, the first mask layer 1032 corresponding to the concave groove is etched by oxygen plasma, and the second mask layer 1034 covers a region not corresponding to the concave groove. Keep resolution effective. Thus, the nanopattern of the second mask layer 1034 can be replicated on the first mask layer 1032, thereby patterning the mask layer 103 entirely.

  The mask layer 103 includes a plurality of protrusion structures 1031 formed on the surface of the first semiconductor layer 110. A groove 1033 is formed between the adjacent protrusion structures 1031. The surface of the first semiconductor layer 110 in the region corresponding to the groove 1033 is exposed, and the protrusion structure 1031 covers a region other than the region corresponding to the groove 1033. Further, by suppressing the flow rate and etching direction of the entire etching gas, the side wall of the protruding structure 1031 formed after the etching is almost perpendicular to the first semiconductor layer 110. Thereby, the conformity and uniformity of the shape of the three-dimensional nanostructure preform 1131 formed during the subsequent etching of the first semiconductor layer 110 can be ensured. In the process of etching the first mask layer 1032, the protruding structure of the second mask layer 1034 is slightly etched. However, the rate at which the second mask layer 1034 is etched is slower than the rate at which the first mask layer 1032 is etched. Accordingly, the nanopattern of the second mask layer 1034 is basically retained.

  In step (S133), after the first semiconductor layer 110 is installed in an inductively coupled plasma etching system, the first semiconductor layer 110 is etched using an etching gas. In the etching process, the portion of the first semiconductor layer 110 corresponding to the groove 1033 is removed by the gas, and a concave groove is formed on the surface of the first semiconductor layer 110.

  Further, in the etching process, the surface of the first semiconductor layer 110 not covered with the mask layer 103 is etched to form a plurality of grooves on the surface of the first semiconductor layer 110, and the depth of the plurality of grooves is All of the two protrusion structures 1031 adjacent to each other in the mask layer 103 are gradually inclined relative to each other by the step (S133a), which is basically the same, and the plasma collision action. A step (S133b) in which two ends of the semiconductor layer 110 approach each other and finally come into contact with each other (S133b).

  In the step (S133a), the gas employed in the etching in the course of etching reacts with the first semiconductor layer 110 not covered with the mask layer 103 to form a protective layer. Since the protective layer can prevent the first semiconductor layer 110 from being further etched, the area of the first semiconductor layer 110 to be etched gradually decreases. That is, the width of the groove formed in the first semiconductor layer 110 decreases along the etching direction of the first semiconductor layer 110, and the wall of the groove is substantially perpendicular to the surface of the first semiconductor layer 110. Become. At the same time, the etching gas gradually reduces the width of the top of the protrusion structure 1031 by etching the top of the protrusion structure 1031 of the mask layer 103. In the etching process, the etching gas also etches the mask layer 103. However, the rate at which the mask layer 103 is etched is slower than the rate at which the surface of the first semiconductor layer 110 is etched. Accordingly, the shape and distribution of the mask layer 103 can be maintained in the process in which the first semiconductor layer 110 is etched to form a plurality of concave grooves.

  Step (S133b) includes the following three sub-steps.

  In the first sub-step, during the process of etching with gas, the two adjacent projecting structures 1031 gradually tilt relative to each other due to the impact of plasma, and the tops of the projecting structures 1031 (the first semiconductor layer 110 and The two one ends are approaching each other, and finally touching each other.

  In the second sub-step, the tops of the two adjacent protrusion structures 1031 gradually come close to each other and come into contact with each other, so that the portion of the first semiconductor layer 110 corresponding to the contact portion of the top of the protrusion structure 1031 is etched. Will slow down. That is, the width of the concave groove formed at the position corresponding to the portion where the top portion of the protrusion structure 1031 contacts is narrowed with the depth of etching, and further, the concave groove of the V-shaped structure is formed. However, at this time, the depth of the groove is relatively shallow. Therefore, the first semiconductor layer 110 is etched between the protruding structures 1031 that are not yet in contact with the etching gas at the same etching rate. Thereby, the depth of the groove | channel formed between the protrusion structures 1031 which have not yet contacted is deeper than the concave groove formed in the part which the top part of the protrusion structure 1031 contacts.

  In the third sub-step, after the tops of the protrusion structures 1031 are in contact with each other, the gas cannot continue to etch the first semiconductor layer 110 covered with the contacted parts. Accordingly, the first groove 1136 is formed on the surface of the first semiconductor layer 110. At the same time, the gas continues to etch the first semiconductor layer 110 between the two protruding structures 1031 that are not in contact with each other, forming a second groove 1138. As a result, the depth of the second groove 1138 becomes deeper than the depth of the first groove 1136, and the three-dimensional nanostructure preform 1131 is formed.

In this embodiment, the gas is a mixed gas, and the mixed gas contains Cl ₂ , BCl ₃ , O ₂ , and Ar ₂ . The power of the plasma etching system is 10 W to 150 W, the introduction speed of the mixed gas is 8 sccm to 150 sccm, the atmospheric pressure formed is 0.5 Pa to 15 Pa, and the etching time is 5 seconds to 5 minutes. Among them, the introduction rate of Cl ₂ is ₂ sccm to 60 sccm, the introduction rate of BCl ₃ is ₂ sccm to 30 sccm, the introduction rate of O ₂ is 3 sccm to 40 sccm, and the introduction rate of Ar ₂ is 1 sccm to ₂₀ sccm. is there. In this embodiment, the power of the plasma etching system is 70 W, the plasma introduction flow is 40 sccm, the atmospheric pressure formed is 2 Pa, and the etching time is 120 seconds. Among them, the introduction rate of Cl ₂ is 26 sccm, the introduction rate of BCl ₃ is 16 sccm, the introduction rate of O ₂ is 20 sccm, and the introduction rate of Ar ₂ is 10 sccm.

  The mask layer 103 and the etching gas are not limited and can be selected as necessary. In the process of etching, a pure gas or a mixed gas may be used as long as the protrusion structures 1031 in the mask layer 103 can contact each other. Further, the gas introduction speed, the atmospheric pressure, the etching time, the gas ratio, and the like can be selected depending on the size and dimensions of the required three-dimensional nanostructure 113.

  In step (S134), the mask layer 103 is dissolved and removed with an organic solvent, and then a three-dimensional nanostructure preform 1131 is formed. The organic solvent is, for example, tetrahydrofuran (THF), acetone, butanone, cyclohexane, hexane, methanol or ethanol. In this example, the organic solvent is butanone. The mask layer 103 is dissolved in butanone and detached from the first semiconductor layer 110. After removing the mask layer 103, the first semiconductor layer 110 is formed. That is, a plurality of three-dimensional nanostructures 113 are formed in the first semiconductor layer 110. The three-dimensional nanostructure 113 and the first semiconductor layer 110 are integrally formed.

  Further, after the patterned mask layer 103 is formed on another medium or substrate, the mask layer 103 may be placed on the surface of the first semiconductor layer 110.

  In step (S <b> 14), the growth method of the active layer 120 and the second semiconductor layer 130 is essentially the same as the growth method of the first semiconductor layer 110. In this embodiment, the active layer 120 and the second semiconductor layer 130 are grown by introducing ammonia, hydrogen, and gallium source gases until the first semiconductor layer 110 is grown, and the temperature of the reaction chamber is set to 700 ° C. to 900 ° C. Maintaining the gas pressure in the reaction chamber at 50 to 500 torr (S141), and further introducing indium source gas into the reaction chamber to form a multilayer quantum well structure by the InGaN / GaN system. Growing to form the active layer 120 (S142), the introduction of the indium source gas is stopped, the temperature of the reaction chamber is maintained at 1000 ° C. to 1100 ° C., and the gas pressure of the reaction chamber is set at 76 torr to 200 torr. In step (S143), and further introducing a magnesium source gas into the reaction chamber to form a P-type GaN epitaxial layer doped with magnesium. Let me long, including a step (S144) of forming the second semiconductor layer 130.

  In step (S15), the substrate 100 is removed by a method such as a laser radiation method or a chemical corrosion method. The method for removing the substrate 100 can be selected depending on the material of the first semiconductor layer 110. In this embodiment, the substrate 100 is removed by a laser radiation method.

  The substrate 100 is removed by polishing and cleaning the surface of the substrate 100 on which the first semiconductor layer 110 is grown (S151), placing the cleaned substrate 100 on a platform, and using a laser to form the first substrate 100 and the first semiconductor layer 110. A step (S152) of processing the semiconductor layer 110, and a step of removing the substrate 100 (S153) by placing the laser-treated substrate 100 in a solution.

  In step (S151), by polishing the substrate 100, the surface of the substrate 100 becomes smooth. Therefore, the dispersion of the laser is reduced in the process of processing by the laser. Next, the surface of the substrate 100 is cleaned with hydrochloric acid or sulfuric acid.

In step (S152), a laser is incident on the polished surface of the substrate 100. At this time, the incident direction is a direction perpendicular to the surface of the substrate 100 polished. The wavelength of the laser can be selected depending on the material of the substrate 100 and the first semiconductor layer 110. Specifically, the energy of the laser is smaller than the energy gap of the substrate 100 and larger than the energy gap of the first semiconductor layer 110. Thus, the laser passes through the substrate 100 and reaches the first semiconductor 110 body layer, and the laser is peeled off at a portion where the semiconductor layer 110 and the substrate 100 are in contact with each other. In addition, the buffer layer of the first semiconductor layer 110 where the semiconductor layer 110 and the substrate 100 are in contact with each other has high laser absorptivity, so that the temperature of the buffer layer rises quickly and then decomposes. In this embodiment, the first semiconductor layer 110 is gallium nitride and the energy gap is 3.3 ev. The substrate 100 is a sapphire substrate, and the energy gap is 9.9 ev. The laser is KrK, the laser wavelength is 248 nm, the energy is 5 ev, the pulse width is 20 to 40 ns, the energy density is 400 to 600 mj / cm ² , the spot shape is square, and the focus size Is 0.5 mm × 0.5 mm, and scanning starts from the edge of the substrate 100. The scanning length is 0.5 mm / s. In the scanning process, gallium nitride is decomposed into gallium and nitrogen. The first semiconductor layer 110 of this embodiment has a high absorption rate for a specific laser wavelength. Accordingly, the corresponding laser wavelength can be selected.

  Process with laser in vacuum or protective gas environment. Thereby, it can prevent that a nanocarbon tube is oxidized and destroyed. The protective gas here is an inert gas such as nitrogen gas, helium or argon.

  In step (S153), the substrate 100 processed by the laser is left in an acidic solution, gallium is removed by an oxidation process, and the substrate 100 and the first semiconductor layer 110 are separated. The solution is hydrochloric acid, sulfuric acid, nitric acid or the like that can dissolve gallium.

  In step (S16), the first electrode 112 is formed by physical vapor deposition such as electron beam evaporation, vacuum evaporation, or ion sputtering. Alternatively, the first electrode 112 is formed by using a conductive substrate and attaching it to a part of the exposed surface of the first semiconductor layer 110 with a conductive paste or the like. In the present embodiment, the first electrode 112 is formed on the exposed surface of the first semiconductor layer 110 by electron beam evaporation.

  In step (S17), the manufacturing method of the second electrode 132 is the same as the manufacturing method of the first electrode 112. In the present embodiment, the second electrode 132 is formed by an electron beam evaporation method and is provided on a part of the surface of the second semiconductor layer 130.

(Example 2)
Referring to FIG. 7, the light emitting diode 20 according to the second embodiment includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120. In addition, a plurality of three-dimensional nanostructures 123 are installed on the surface of the active layer 120 away from the first semiconductor layer 110.

  The structure of the light emitting diode 20 according to the second embodiment is basically the same as the structure of the light emitting diode 10 according to the first embodiment. The difference is that in the light emitting diode 20, a plurality of three-dimensional nanostructures 123 are also formed on the surface of the active layer 120 away from the first semiconductor layer 110. Referring to FIG. 8, the three-dimensional nanostructure 123 includes a first protrusion 1232 and a second protrusion 1234, and a first groove 1236 is provided between the first protrusion 1232 and the second protrusion 1234. A second groove 1238 is formed between two adjacent three-dimensional nanostructures 123 formed. The three-dimensional nanostructure 123 and the three-dimensional nanostructure 113 have the same structure and are installed correspondingly. The plurality of three-dimensional nanostructures 123 on the surface of the active layer 120 and the plurality of three-dimensional nanostructures 113 on the surface of the first semiconductor layer 110 have the same undulation tendency. It points to something. Specifically, the first protrusion 1232 and the first protrusion 1132 are coaxial, the second protrusion 1234 and the second protrusion 1134 are coaxial, and the first groove 1236 and the first groove 1136 are The second groove 1238 and the second groove 1138 are coaxial.

  The second semiconductor layer 130 is disposed on the surface of the plurality of three-dimensional nanostructures 123. Further, since the plurality of three-dimensional nanostructures 123 have a plurality of grooves and protrusions, a plurality of three-dimensional nanostructures (not shown) are formed on the surface of the second semiconductor layer 130. Specifically, the plurality of grooves of the second semiconductor layer 130 correspond to the plurality of protrusions of the three-dimensional nanostructure 123, and the plurality of protrusions of the second semiconductor layer 130 correspond to the three-dimensional nanostructure 123. Corresponds to a plurality of grooves.

  Referring to FIG. 9, the method of manufacturing the light emitting diode 20 according to the second embodiment provides a substrate 100, the substrate 100 including a growth surface 101 (S <b> 21), and a first semiconductor layer on the surface of the growth surface 101. 110 is grown (S22), a three-dimensional nanostructure 113 is formed on the surface of the first semiconductor layer 110 (S23), and the three-dimensional nanostructure 113 of the first semiconductor layer 110 is activated on the surface. The step of growing a layer 120 and forming a plurality of three-dimensional nanostructures 123 on the surface of the active layer 120 away from the first semiconductor layer 110 (S24), and forming a second on the surfaces of the plurality of three-dimensional nanostructures 123 A step of forming the semiconductor layer 130 (S25), a step of removing the substrate 100 and exposing the first semiconductor layer 110 (S26), and a table of the exposed first semiconductor layer 110. The second electrode 132 is formed on the surface opposite to the surface in contact with the active layer 120 of the second semiconductor layer 130 by installing the first electrode 112 (S27). (S28).

  The manufacturing method of the light emitting diode 20 of the second embodiment is basically the same as the manufacturing method of the light emitting diode 10 of the first embodiment. The difference is that, in the process of growing the active layer 120, the substrate 100 on which the first semiconductor layer 110 is formed is placed in a vertical growth reaction chamber to control the reaction conditions (for example, the gas introduction speed and the flow direction). That is. Accordingly, the growth direction and thickness of the active layer 120 can be controlled, and the active layer 120 can be grown with an undulating tendency corresponding to the plurality of three-dimensional nanostructures 113. That is, the first protrusion 1132 and the second protrusion 1134 correspond to each other to form a protrusion, and the first groove 1136 and the second groove 1138 also correspond to each other to form a groove. Accordingly, a plurality of three-dimensional nanostructures 123 can be formed on the surface of the active layer 120 away from the first semiconductor layer 110.

(Example 3)
Referring to FIG. 10, the light emitting diode 30 according to the third embodiment includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120. The plurality of three-dimensional nanostructures 133 are installed on the surface of the second semiconductor layer 130 that is separated from the first semiconductor layer 110.

  The structure of the light emitting diode 30 according to the third embodiment is basically the same as the structure of the light emitting diode 10 according to the first embodiment, except that the first semiconductor layer of the second semiconductor layer 130 in the light emitting diode 30 is different. That is, a plurality of three-dimensional nanostructures 133 are formed on the surface away from 110. Referring to FIG. 11, the three-dimensional nanostructure 133 has a first protrusion 1332 and a second protrusion 1334, and a first groove 1336 is formed between the first protrusion 1332 and the second protrusion 1334. A second groove 1338 is formed between two adjacent three-dimensional nanostructures 133 formed. The three-dimensional nanostructure 133 and the three-dimensional nanostructure 113 have the same structure.

  The method for manufacturing the light emitting diode 30 according to the third embodiment provides the substrate 100, the step of the substrate 100 including the growth surface 101 (S31), and the step of growing the first semiconductor layer 110 on the surface of the growth surface 101 (S32). ), Forming the three-dimensional nanostructure 113 on the surface of the first semiconductor layer 110 (S33), forming the active layer 120 on the surface of the three-dimensional nanostructure 113 of the first semiconductor layer 110, and the second semiconductor The step of growing the layer 130 in order (S34), the step of forming a plurality of three-dimensional nanostructures 133 on the surface of the second semiconductor layer 130 away from the first semiconductor layer 110 (S35), and the substrate 100. Removing and exposing the first semiconductor layer 110 (S36); and placing the first electrode 112 on the exposed surface of the first semiconductor layer 110 (S37). Includes the surface in contact with the active layer 120 of the second semiconductor layer 130 to form the second electrode 132 on the opposite surface, a step (S38) for electrically connecting the second semiconductor layer 130.

Example 4
Referring to FIG. 12, the light emitting diode 40 according to the fourth embodiment includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120. The plurality of three-dimensional nanostructures 123 are installed on the surface of the active layer 120 away from the first semiconductor layer 110. The plurality of three-dimensional nanostructures 133 are installed on the surface of the second semiconductor layer 130 away from the first semiconductor layer 110.

  The structure of the light emitting diode 40 according to the fourth embodiment is basically the same as the structure of the light emitting diode 20 according to the second embodiment, except that the first semiconductor layer of the second semiconductor layer 130 is different from the light emitting diode 40. That is, a plurality of three-dimensional nanostructures 133 are formed on the surface away from 110. The three-dimensional nanostructure 133 has a first protrusion 1332 and a second protrusion 1334, a first groove 1336 is formed between the first protrusion 1332 and the second protrusion 1334, and the adjacent two A second groove 1338 is formed between the three three-dimensional nanostructures 133. The three-dimensional nanostructure 133 and the three-dimensional nanostructure 113 have the same structure.

  The manufacturing method of the light emitting diode 40 according to the fourth embodiment includes providing the substrate 100, the substrate 100 including the growth surface 101 (S41), and growing the first semiconductor layer 110 on the surface of the growth surface 101 ( S42), forming a three-dimensional nanostructure 113 on the surface of the first semiconductor layer 110 (S43), and growing the active layer 120 on the surface of the three-dimensional nanostructure 113 of the first semiconductor layer 110, Forming a plurality of three-dimensional nanostructures 123 on the surface of the active layer 120 away from the first semiconductor layer 110 (S44), and forming a second semiconductor layer 130 on the surfaces of the plurality of three-dimensional nanostructures 123; (S45), forming a plurality of three-dimensional nanostructures 133 on the surface of the second semiconductor layer 130 away from the first semiconductor layer 110 (S46), and the substrate 100 Removing and exposing the first semiconductor layer 110 (S47); placing the first electrode 112 on the exposed surface of the first semiconductor layer 110 (S48); and the active layer 120 of the second semiconductor layer 130. Forming a second electrode 132 on a surface opposite to the surface in contact with the first semiconductor layer 130 and electrically connecting the second electrode 132 to the second semiconductor layer 130 (S49).

(Example 5)
Referring to FIG. 13, the light emitting diode 50 according to the fifth embodiment includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120. The plurality of three-dimensional nanostructures 115 are disposed on the surface of the first semiconductor layer 110 away from the active layer 120.

  The structure of the light emitting diode 50 according to the fifth embodiment is basically the same as the structure of the light emitting diode 10 according to the first embodiment, except that the light emitting diode 50 is different from the active layer 120 of the first semiconductor layer 110 in the light emitting diode 50. That is, a plurality of three-dimensional nanostructures 115 are formed on the surface to be separated. The three-dimensional nanostructure 115 and the three-dimensional nanostructure 113 have the same structure, and the cross section is M-shaped. The first electrode 112 covers a plurality of three-dimensional nanostructures 115.

  The method of manufacturing the light emitting diode 50 according to the fifth embodiment provides the substrate 100, the step of including the growth surface 101 (S51), and the step of growing the first semiconductor layer 110 on the surface of the growth surface 101 ( S52) and a step of forming a three-dimensional nanostructure 113 on the surface of the first semiconductor layer 110 (S53) an active layer 120 and a second semiconductor layer on the surface of the three-dimensional nanostructure 113 of the first semiconductor layer 110 130 in order (S54), removing the substrate 100 and exposing the first semiconductor layer 110 (S55), and exposing a plurality of three-dimensional nanostructures on the exposed surface of the first semiconductor layer 110. A step of forming the body 115 (S56), a step of covering the plurality of three-dimensional nanostructures 115 with the first electrode 112 (S57), and an activity of the second semiconductor layer 130 The surface in contact with the layer 120 to form a second electrode 132 on the opposite surface, comprising the steps (S58) to electrically connect the second semiconductor layer 130.

(Example 6)
Referring to FIG. 14, the light emitting diode 60 according to Example 6 includes a first semiconductor layer 110, an active layer 120, a second semiconductor layer 130, a first electrode 112, and a second electrode 132. The first semiconductor layer 110, the active layer 120, the second semiconductor layer 130, and the second electrode 132 are sequentially stacked on one side of the first electrode 112 in a direction away from the one side. The first electrode 112 is electrically connected to the first semiconductor layer 110. The second electrode 132 is electrically connected to the second semiconductor layer 130. The plurality of three-dimensional nanostructures 113 are installed on the surface of the first semiconductor layer 110 that is in contact with the active layer 120. The plurality of three-dimensional nanostructures 115 are disposed on the surface of the first semiconductor layer 110 away from the active layer 120. The plurality of three-dimensional nanostructures 123 are installed on the surface of the active layer 120 away from the first semiconductor layer 110.

  The structure of the light emitting diode 60 according to the sixth embodiment is basically the same as the structure of the light emitting diode 20 according to the second embodiment, except that the light emitting diode 60 is different from the active layer 120 of the first semiconductor layer 110 in the light emitting diode 60. That is, a plurality of three-dimensional nanostructures 115 are formed on the surface to be separated. The three-dimensional nanostructure 115 and the three-dimensional nanostructure 113 have the same structure.

  The method for manufacturing the light-emitting diode 60 according to the sixth embodiment provides a substrate 100, the substrate 100 including the growth surface 101 (S61), and the step of growing the first semiconductor layer 110 on the surface of the growth surface 101 ( S62), forming a three-dimensional nanostructure 113 on the surface of the first semiconductor layer 110 (S63), growing the active layer 120 on the surface of the three-dimensional nanostructure 113 of the first semiconductor layer 110, Forming a plurality of three-dimensional nanostructures 123 on the surface of the active layer 120 away from the first semiconductor layer 110 (S64), and forming a second semiconductor layer 130 on the surfaces of the plurality of three-dimensional nanostructures 123; (S65), forming a plurality of three-dimensional nanostructures 133 on the surface of the second semiconductor layer 130 away from the first semiconductor layer 110 (S66), and the substrate 100 Removing and exposing the first semiconductor layer 110 (S67); forming a plurality of three-dimensional nanostructures 115 on the exposed surface of the first semiconductor layer 110; A step of covering the structure 115 (S68) and a second electrode 132 is formed on the surface of the second semiconductor layer 130 opposite to the surface in contact with the active layer 120, and is electrically connected to the second semiconductor layer 130. Step (S69).

10, 20, 30, 40, 50, 60 Light emitting diode 100 Substrate 101 Growth surface 103 Mask layer 110 First semiconductor layer 112 First electrode 113, 123, 133, 115 Three-dimensional nanostructure 120 Active layer 130 Second semiconductor layer 132 Second electrode 1031 Protrusion structure 1032 First mask layer 1033 Groove 1034 Second mask layer 1131 Three-dimensional nanostructure preform 1132, 1232, 1332 First protrusion 1134, 1234, 1334 Second protrusion 1136, 1236 1336 1st groove 1138, 1238, 1338 2nd groove 1132a, 1134a, 1st surface 1132b, 1134b, 2nd surface 200 Mold

Claims (1)

A light emitting diode comprising a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode,
The first semiconductor layer has opposing first and second surfaces;
The first semiconductor layer, the active layer, and the second semiconductor layer are sequentially stacked on the first electrode along a direction away from the first electrode,
The first electrode covers the first surface of the first semiconductor layer, the second electrode is electrically connected to the second semiconductor layer,
The surface away from the active layer of the second semiconductor layer is the light emitting surface of the light emitting diode,
Two or more layers of the first semiconductor layer, the active layer, and the second semiconductor layer so that the plurality of three-dimensional nanostructures are disposed at least between the active layer and the first semiconductor layer or the second semiconductor layer. Alternatively, it is installed on the surface of the three layers in the form of a one-dimensional array,
Each of the three-dimensional nanostructures is an M-shaped strip-shaped protruding structure, and a plurality of M-shaped strip-shaped protruding structures are formed by any one of the first semiconductor layer, the active layer, and the second semiconductor layer, Extend continuously on the surface of two or three layers,
Each three-dimensional nanostructure includes one first protrusion and one second protrusion, and the first protrusion and the second protrusion are parallel to each other and extend in the same direction, A first groove is formed between the first protrusion and the second protrusion of the three-dimensional nanostructure, and one first groove is formed between each two adjacent three-dimensional nanostructures. A light emitting diode, wherein two grooves are formed and a depth of the second groove is deeper than a depth of the first groove.