JP5978956B2 - Nonvolatile memory device, integrated circuit device, and electronic apparatus - Google Patents

Description

  The present invention relates to a nonvolatile memory device, an integrated circuit device, an electronic device, and the like.

  In recent years, it is possible to use a large-capacity nonvolatile storage device such as a flash memory. On the other hand, there is a demand for an OTP (One Time Programmable) memory with a small capacity and low cost for calibration of an analog circuit that may vary depending on the individual.

  The OTP memory is a nonvolatile memory that can be written only once. For example, a floating gate avalanche injection metal oxide semiconductor (FAMOS) is a kind of non-volatile memory and can erase written information by ultraviolet rays. However, after being covered with a commonly used IC package having no window for ultraviolet irradiation, it can be used as a small-capacity OTP memory.

  Here, in the nonvolatile memory device, if the voltage applied to the memory cell is not limited to an appropriate range, there is a possibility that data disturb that data is rewritten unintentionally occurs. For example, the amount of charge accumulated in the gate electrode at the time of reading may change, and erroneous writing may occur.

  The invention of Patent Document 1 uses a regulator to drive a nonvolatile memory device with a power supply voltage (hereinafter, internal voltage) generated from a power supply voltage supplied from the outside of the nonvolatile memory device. Therefore, the voltage applied to the memory cell can be limited. For example, the invention of Patent Document 2 discloses a limiter circuit that limits a boosted voltage used at the time of writing.

JP 2005-122832 A JP-A 61-269299

  However, in the invention of Patent Document 1, data cannot be read from the nonvolatile storage device until the internal voltage is stabilized after the start-up. For example, when the nonvolatile memory device stores calibration data of an analog circuit or the like, the calibration data cannot be read immediately at the start-up, and it is necessary to wait until the internal voltage becomes stable.

  In the invention of Patent Document 2, the occurrence of data disturbance at the time of writing (hereinafter referred to as writing) can be suppressed, but the occurrence of data disturbance at the time of reading operation (hereinafter referred to as reading) cannot be suppressed. For example, in the OTP memory, writing is performed only once and thereafter only reading is performed. Therefore, it is particularly important to suppress the occurrence of data disturb (hereinafter referred to as read disturb) in reading.

  The present invention has been made in view of such problems. According to some embodiments of the present invention, it is possible to provide a nonvolatile memory device, an integrated circuit device, an electronic device, and the like that can read data from a memory cell in a short time after power-on and can suppress the occurrence of read disturb. .

(1) The present invention is a nonvolatile memory device to which a first voltage and a second voltage lower than the first voltage are supplied from the outside, storing data in a nonvolatile manner and A memory cell including a first transistor to which the first voltage or the second voltage is supplied, and a second transistor used to select the first transistor; and the data from the memory cell. A limiter circuit that applies a gate voltage to the gate of the second transistor when reading, and the gate voltage of the second transistor supplied by the limiter circuit is relative to the source voltage of the first transistor And a predetermined voltage difference based on a threshold voltage of the second transistor.

  The nonvolatile memory device of the present invention includes a memory cell and a limiter circuit. The memory cell includes a first transistor that is a non-volatile storage element and a second transistor for selecting the first transistor. For example, the first transistor may be a FAMOS (Floating gate Avalanche injection Metal Oxide Semiconductor) structure transistor, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure transistor, or the like. The memory transistor may be used. For example, the second transistor is a MOS structure transistor, and may be connected in series with the first transistor.

  The limiter circuit is a voltage limiter circuit, and may be composed of, for example, a diode-connected transistor, a diode, a resistor, or the like. The nonvolatile memory device of the present invention includes a limiter circuit, so that a gate voltage having a predetermined voltage difference with respect to the source voltage of the first transistor (the first voltage or the second voltage is supplied) is obtained. To the second transistor. Here, the predetermined voltage difference is determined based on the threshold voltage of the second transistor. For example, the data of the first transistor is read to determine whether it is “0” or “1”. It may be a necessary and sufficient value.

  Note that “0” and “1” are notations indicating binary numbers and logic, but in the following, they are also associated with the voltage level of the digital circuit, with the low level set to “0” and the high level set to “1”. It shall correspond.

Here, it is assumed that a first voltage V _DD (for example, 3.3 V) and a second voltage GND (a ground voltage, for example, 0 V) are supplied to the nonvolatile memory device from the outside. In the conventional nonvolatile memory device, when data is read, for example, the gate voltage of the second transistor is applied so that an equal voltage difference is generated between V _{DD and} GND with respect to the source voltage of the first transistor. At this time, since a gate voltage having a large voltage difference is used, the possibility that charges are accumulated in the insulating film of the first transistor is increased, and erroneous writing (read disturb) is likely to occur.

However, in the nonvolatile memory device of the present invention, a gate voltage having a predetermined voltage difference with respect to the source voltage of the first transistor is applied to the second transistor at the time of reading. This predetermined voltage difference is determined based on the threshold voltage of the second transistor, and is sufficiently smaller than between V _{DD and} GND. Therefore, the occurrence of read disturb can be suppressed.

In addition, the nonvolatile memory device of the present invention uses a predetermined voltage based on the threshold voltage of the second transistor from V _DD (first voltage) and GND (second voltage) received from the outside by an internal limiter circuit. Differences can be generated.

On the other hand, even in a conventional nonvolatile memory device, a voltage lower than V _DD (eg, 1.8 V) generated by a regulator external to the nonvolatile memory device is used as the first voltage, so that read disturb can be reduced. Occurrence could be suppressed. However, it takes some time from when the power is turned on (for example, when V _DD is supplied) until the regulator stably supplies a voltage lower than V _DD . Since the nonvolatile memory device of the present invention operates with V _DD (first voltage) and GND (second voltage), the time from power-on to read operation compared to the case of receiving the voltage from the regulator. Is early.

  As described above, the nonvolatile memory device of the present invention can read data from the memory cell in a short time after the power is turned on, and can suppress the occurrence of read disturb.

(2) In this nonvolatile memory device, the limiter circuit includes a plurality of circuit elements connected in multiple stages between a first node and a second node, and the voltage of the first node is When the data is read from the memory cell, the voltage of the second node may be the gate voltage of the second transistor.

(3) In this nonvolatile memory device, the circuit element may be a diode-connected transistor.

(4) In this nonvolatile memory device, the limiter circuit may include a resistor having one end electrically connected to the second node when the data is read from the memory cell.

The limiter circuit of the nonvolatile memory device of these inventions includes a plurality of circuit elements connected in multiple stages. To be connected in multiple stages may be connected in series, may be connected in parallel, or may be a combination of series and parallel to connect a plurality of circuit elements. Further, both ends of a plurality of circuit elements connected in multiple stages are defined as a first node and a second node, and the voltage of the first node is V _DD (first voltage) or GND (second voltage). ). The voltage of the second node is a value determined according to the connection of the circuit elements.

Here, the circuit element may be a diode-connected transistor. The transistor at this time may be the same size as the second transistor having a MOS structure, for example. One diode-connected transistor causes a voltage drop of the threshold voltage V _th . If the limiter circuit includes two such transistors connected in series and the voltage at the first node is V _DD , the voltage at the second node is given by V _DD -2 × V _th . At this time, the limiter circuit can generate a voltage value related to the threshold voltage V _th of the second transistor as the voltage of the second node. If the threshold voltage V _th is known in advance, a diode or resistor having characteristics that cause a voltage drop corresponding to V _th may be used as the circuit element.

The limiter circuit may include an adjustment element or circuit so that the voltage of the second node is automatically adjusted to a desired value. For example, the adjustment element may include a resistor (high resistance) having one end connected to the second node. At this time, the other end is connected to V _DD (first voltage) or GND (second voltage), and when the voltage of the second node is higher or lower than a desired value, the resistor is connected to this resistor. The voltage of the second node may be adjusted by passing a current. Note that the adjustment based on the current flowing through the resistor may be performed only when data is read.

As described above, the limiter circuit of the nonvolatile memory device according to these inventions has a plurality of circuit elements connected in multiple stages and a desired value in which the voltage of the second node is associated with the threshold voltage of the second transistor. can do. And the non-volatile memory | storage device of these invention can make the voltage of a 2nd node the gate voltage of a 2nd transistor, and can suppress generation | occurrence | production of a read disturbance.

(5) In this nonvolatile memory device, the memory cell may include the first transistor having a floating gate structure.

(6) In this nonvolatile memory device, the memory cell may include the first transistor having a MONOS structure.

Specifically, the nonvolatile memory device of the present invention may have the following memory cell structure. First, the memory cell may include a first transistor having a floating gate structure. The source voltage of the first transistor may be V _DD (first voltage) during reading. That is, a P-type FAMOS transistor may be used as the first transistor. At this time, the second transistor may be a P-type MOS transistor.

  The memory cell may include a first transistor having a MONOS structure. The source voltage of the first transistor may be GND (second voltage) at the time of reading. That is, an N-type MONOS transistor may be used as the first transistor. At this time, the second transistor may be an N-type MOS transistor.

  Thus, the nonvolatile memory device of the present invention may include a FAMOS transistor or a MONOS transistor. In addition, the nonvolatile memory device of the present invention can be configured using a P-type transistor or can be configured using an N-type transistor. Therefore, there is no restriction on the type of transistor, and for example, it can be used without particular limitation in applications such as replacing an existing nonvolatile memory device in order to suppress the occurrence of read disturb.

(7) The present invention is an integrated circuit device including the nonvolatile memory device described above.

(8) The present invention is an electronic device including the nonvolatile memory device.

(9) The present invention is an integrated circuit device, including the nonvolatile memory device and a regulator, wherein the nonvolatile memory device stores a set value of the regulator, and the regulator A third voltage that is an intermediate voltage between the first voltage and the second voltage is generated, and the set value is received from the nonvolatile memory device before the third voltage is generated.

  Since these inventions include the nonvolatile memory device described above, it is possible to realize an integrated circuit device (IC), an electronic device, and the like that can read data from the nonvolatile memory device in a short time after power-on. In addition, since the nonvolatile memory device can suppress the occurrence of read disturb, a highly reliable integrated circuit device, electronic device, or the like can be realized.

  At this time, the integrated circuit device may include a regulator that generates an intermediate voltage (third voltage) between the first voltage and the second voltage. The nonvolatile memory device included in the integrated circuit device may include a set value of the regulator. Since the data can be read from the memory cell in a short time after the power is turned on, the regulator can receive this set value before generating the third voltage. Therefore, it is possible to realize an integrated circuit device that can flexibly adjust settings at startup.

Explanatory drawing of the non-volatile storage device of 1st Embodiment. The figure explaining the structure of the limiter circuit of 1st Embodiment. The figure explaining the output of the limiter circuit of 1st Embodiment. FIG. 3 is a diagram for explaining a read operation of the memory cell according to the first embodiment. The figure which shows the relationship between the operation mode of 1st Embodiment, and the voltage to apply. Explanatory drawing of the non-volatile storage device of 2nd Embodiment. The figure explaining the structure of the limiter circuit of 2nd Embodiment. The figure explaining the output of the limiter circuit of 2nd Embodiment. FIG. 6 is a diagram for explaining a read operation of a memory cell according to a second embodiment. The figure which shows the relationship between the operation mode of 2nd Embodiment, and the voltage to apply. The block diagram of the integrated circuit device containing the non-volatile memory device of a comparative example. FIG. 12 is a timing chart showing set value stabilization time in the integrated circuit device of FIG. 11. The block diagram of the integrated circuit device containing the non-volatile memory device of the said embodiment. FIG. 14 is a timing chart showing a set value stabilization time in the integrated circuit device of FIG. 13. The block diagram of the electronic device containing the non-volatile storage device of the said embodiment. FIG. 16A to FIG. 16B are diagrams illustrating the appearance of electronic devices.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Nonvolatile storage device (first embodiment)
1.1. Configuration of Nonvolatile Storage Device FIG. 1 is a diagram illustrating a configuration of a nonvolatile storage device 10 according to the present embodiment. The nonvolatile memory device 10 includes a plurality of memory cells MC including a transistor (FAMOS transistor FTr) having a floating gate avalanche injection metal oxide semiconductor (FAMOS) structure which is a nonvolatile memory element.

  In the nonvolatile memory device 10, memory cells MC are arranged in an array in the Y direction (hereinafter referred to as the row direction) in FIG. 1 and the X direction (hereinafter referred to as the column direction) in FIG. The nonvolatile memory device 10 of this embodiment has a structure in which m (m is a natural number) memory cells MC in the row direction and n (n is a natural number) in the column direction.

The memory cell MC is connected to the source line SL, the word lines WL _{1 to} WL _m , and the bit lines BL _{1 to} BL _n as shown in FIG. Whether the word lines WL _{1 to} WL _m are active or inactive is determined based on word line control signals WI _{1 to} WI _m from a control unit (not shown). The word line control signals WI _{1 to} WI _m are active high signals.

Here, the word line adjustment unit CT adjusts the voltages of the word lines WL _{1 to} WL _m . Word lines adjusting section CT includes an inverter IV ₁ to IV _m of the word line control signal WI ₁ ~WI _m each is input. Inverter IV ₁ to IV _m are respectively connected to the word line WL ₁ to WL _m. The word line adjustment unit CT includes a common limiter circuit LC. The limiter circuit LC can adjust the output voltage of the inverters IV _{1 to} IV _m .

FIG. 1 shows a part of the nonvolatile memory device 10 and does not show all the components of the nonvolatile memory device 10. In the following description, regarding the structure and control common to all the memory cells MC, the memory cell MC in i rows (1 ≦ i ≦ m, i is a natural number) and j columns (1 ≦ j ≦ n, j is a natural number). Only _ij will be described and illustrated. Also, the word line adjustment unit CT is a part of the word line adjustment unit C, which is a part of the structure and control.
Only _Ti will be described and illustrated.

The memory cell MC _ij is selected by the word line WL _i and the bit line BL _j and is written and read. Note that the voltage of the bit line BL _j is also controlled by a control unit (not shown).

Memory cell MC _ij is (corresponding to the second transistor of the present invention) FAMOS transistors FTr (corresponding to the first transistor of the present invention) the selection is selected by the word line WL _i transistor CTr including floating gate FG series It has a structure connected to.

Here, in the state in which charges are injected into the floating gate FG, a current flows when read out. This is detected and the value of the memory cell MC _ij is assumed to be “0”. Further, in a state in which no electric charge is injected into the floating gate FG, no current flows when read out, so this is detected and the value of the memory is “1”. For example, the expected value when reading the initial memory cell MC _ij that has not been written (that is, injection of charge into the floating gate FG) is “1”.

As shown in FIG. 1, in the memory cell MC _ij , the FAMOS transistor FTr and the selection transistor CTr are P-type transistors, but they may be configured by N-type transistors instead of P-type transistors. The source line SL is common and is connected to the sources of the FAMOS transistors FTr of all the memory cells MC.

1.2. Configuration of Limiter Circuit FIG. 2 is a diagram showing a detailed configuration of the limiter circuit LC. Since the structure of the word line adjustment unit CT shown in FIG. 1 is common to each word line, only the word line adjustment unit CT _i which is a part including the limiter circuit LC will be illustrated and described. Note that the memory cells MC other than the memory cell MC _ij connected to the word line WL _i have the same structure and control as the memory cell MC _ij, and therefore illustration and description thereof are omitted. Further, the same elements as those in FIG.

The word line adjuster CT _i of FIG. 2, (corresponding to the second voltage of the present invention, a ground voltage) (first corresponding to the voltage of the present invention) and GND V _DD is supplied externally. The word line adjustment unit CT _i includes an inverter IV _i to which the word line control signal WI _i is input and whose output is connected to the word line WL _i .

Here, when the word line control signal WI _i that is active high is set to “0” (low level) by the control unit (not shown), it is connected to the gate of the P-type selection transistor CTr of the memory cell MC _ij. The voltage of the word line WL _i to be set becomes V _DD . Therefore, the selection transistor CTr is turned off. That is, when the word line control signal WI _i is “0” (low level), the memory cell MC _ij is not selected and the word line WL _i is inactive.

On the other hand, when the word line control signal WI _i is “1” (high level), the voltage of the word line WL _i becomes the voltage of the node N ₃ . The voltage at the node N ₃ is the output voltage of the limiter circuit LC. Therefore, the configuration of the limiter circuit LC will be described below, and the voltage at the node N ₃ is obtained assuming that the operation mode of the nonvolatile memory device is “read”.

The limiter circuit LC includes a plurality of circuit elements (hereinafter, circuit element group L ₁ ) connected in multiple stages, and a resistor R having one end connected to the node N ₃ . Limiter circuit LC receives a signal RD and a signal WR whose values change depending on the operation mode from a control unit (not shown). If the operation mode is read (when data is read from the memory cell MC _ij ), the signal RD is “1” (high level) and the signal WR is “0” (low level). If the operation mode is write (when data is written to the memory cell MC _ij ), the signal RD is “0” and the signal WR is “1”. If the operation mode is neither read nor write, the signal RD and the signal WR are both “0”.

If the operation mode is read, the signal RD is “1”, and therefore the other end of the resistor R is grounded. Here, the voltage of the node N ₁ (corresponding to the first node of the present invention) at one end of the circuit element group L ₁ is V _DD . The node N ₂ (corresponding to the second node of the present invention) at the other end of the circuit element group L ₁ is electrically connected to the node N ₃ because the operation mode is read and the signal WR is “0”. Connected. That is, when the operation mode is read, the voltage at the node N ₃ becomes the voltage at the node N ₂ .

As shown in FIG. 2, the circuit element group L ₁ includes two diode-connected P-type transistors (transistor L ₁₀ and transistor L ₁₁ ) as circuit elements. Then, they are connected in series to the transistor L ₁₀ and transistor L _11. Therefore, _assuming that the threshold voltage of the P-type transistor is V _thp , the voltage at the node N ₂ finally becomes approximately V _DD −2 × | V _thp |. Therefore, when the operation mode is read and the word line control signal WI _i is “1”, the voltage of the word line WL _i can be considered to be V _DD −2 × | V _thp |.

Here, the resistance R is a high resistance having a weaker current capability than the transistors L ₁₀ and L ₁₁ . When the operation mode is read, the resistor R included in the limiter circuit LC has a function of stabilizing the voltage at the node N ₃ (here, the same as the voltage at the node N ₂ ) to approximately V _DD −2 × | V _thp |.

Figure 3 is a node for voltages N _3, a current I _L1 flowing through the transistor L ₁₀ and transistor L _11, illustrates the current I _R flowing through the resistor R. Consider a case where the voltage at the node N ₃ becomes V _x1 higher than, for example, V _DD −2 × | V _thp |. At this time, no current flows through the transistors L ₁₀ and L ₁₁ (current I _L1 ), but a current flows through the resistor R (current I _R ). Therefore, the voltage at the node N ₃ changes from V _{x1 in} the direction of the arrow a _{1 in} FIG. That is, the voltage at the node N ₃ gradually decreases.

Next, consider a case where the voltage at the node N ₃ becomes V _x0 lower than, for example, V _DD −2 × | V _thp |. At this time, a current flows through the transistor L ₁₀ and the transistor L ₁₁ (current I _L1 ), and a current also flows through the resistor R (current I _R ). Since the resistor R is a high resistance having a weaker current capability than the transistors L ₁₀ and L ₁₁ , the voltage at the node N ₃ changes from V _{x0 in} the direction of the arrow a _{0 in} FIG. That is, the voltage at the node N ₃ gradually increases.

When the voltage at the node N ₃ changes in the direction of the arrow a ₀ or the arrow a ₁ in FIG. 3 and reaches the intersection B _{0 of the} current I _L1 and the current I _R , the current flowing through the transistors L ₁₀ and L ₁₁ And the current flowing through the resistor R are equal, so that it is stable. Here, the voltage of the node N ₃ corresponding to the intersection B ₀ is approximately V _DD −2 × | V _thp |. Therefore, the limiter circuit LC can finally generate a voltage of approximately V _DD −2 × | V _thp | by including the resistor R. Therefore, when the operation mode is read and the word line control signal WI _i is “1”, the nonvolatile memory device 10 stably supplies the voltage of the word line WL _i to V _DD −2 × | V. _thp |

1.3. Details of Read Operation Here, it will be described with reference to FIG. 4 that the occurrence of read disturb can be suppressed by limiting the voltage of the word line WL _i to V _DD −2 × | V _thp |. FIG. 4 shows a state in which the data of the memory cell MC _ij is read with respect to the memory cell MC _{ij with} the voltage of the source line SL as V _DD and the voltage of the bit line BL _j as GND. At this time, the current IR _P of the read signal flowing through the bit line BL _j, determines whether the data in the memory cell MC _ij is "0" or "1".

Since the voltage of the word line WL _i connected to the gate of the selection transistor CTr is V _DD −2 × | V _thp |, the voltage of the node N _{p in} FIG. 4 is read if it is not equal to or higher than V _DD − | V _thp |. Can not. That is, the voltage of the node N _p is V _DD - | If lower, the selection transistor _{CTr | | V thp V gs |} <| V thp | , and the selection transistor CTr is turned off. V _gs is a gate-source voltage. V _thp is a threshold voltage of the P-type transistor, and is the same as the threshold voltage of the transistor L ₁₀ and the transistor L ₁₁ .

Then, the condition for reading the data in the memory cell MC _ij is that the voltage at the node N _p is equal to or higher than V _DD − | V _thp |. This condition is the voltage between the drain and the source applied to the FAMOS transistor FTr. _Means that | V _ds | is limited to | V _thp |.

For example, in the conventional nonvolatile memory device, when data is read, for example, a gate voltage (GND) that causes an equal voltage difference between V _{DD and} GND with respect to the source voltage (V _DD ) of the first transistor. Is applied to the second transistor. At this time, the magnitude | V _ds | of the drain-source voltage applied to the FAMOS transistor FTr can be | V _DD −V _thp |, so that read disturb is likely to occur.

The drain applied to FAMOS transistor FTr - the magnitude of the voltage between the source | V _ds | is | V _thp | this embodiment the non-volatile memory device 10, which is limited to the, | V _thp | is | V _DD -V _{Since this} value is smaller than _thp |, the occurrence of read disturb can be suppressed.

Thus, the nonvolatile memory device 10 sets the voltage applied to the FAMOS transistor FTr by _setting the voltage at the time of reading of the word line WL _i connected to the gate of the selection transistor CTr to V _DD −2 × | V _thp |. The generation of read disturb can be suppressed by restricting the magnitude of | V _thp |.

Here, the limiter circuit LC of the nonvolatile memory device 10 can change the configuration of the circuit element group L ₁ so that the voltage at the time of reading the word line WL _i is other than V _DD −2 × | V _thp |. Is possible. For example, by connecting M diode-connected P-type transistors in the circuit element group L ₁ in series, the voltage at the time of reading the word line WL _i can be _expressed as V _DD −M × | V _thp | (where M is It can be changed to an integer of 2 or more. However, considering that the voltage applied to the FAMOS transistor FTr can be (M−1) × | V _thp |, the configuration of the present embodiment (M = 2) is preferable.

  The circuit element of the limiter circuit LC is not limited to the transistor as in this embodiment, and may be a diode, for example. For example, the limiter circuit LC may be a resistance dividing circuit using a resistance element.

1.4. Other Operation Modes FIG. 5 summarizes the relationship between the operation mode and the applied voltage in the nonvolatile memory device 10 of the present embodiment. As described above, when the operation mode is read, a voltage of V _DD -2 × | V _thp | is obtained as an output of the limiter circuit LC. This voltage is applied to the word line WL _i , and the data of the memory cell MC _ij can be read by setting the voltage of the source line SL to V _DD and the voltage of the bit line BL _j to GND.

When the operation mode is write, the signal RD is “0” and the signal WR is “1”. Therefore, the voltage at the node N ₃ becomes GND (see FIG. 2). Therefore, the voltage of the word line WL _i is GND, the data is written to the memory cell MC _ij by setting the voltage of the source line SL to GND and the voltage of the bit line BL _{j to} a write voltage higher than V _DD. Can do. Incidentally, if GND voltage of the bit line BL _j, data write is not performed.

When the operation mode is neither read nor write (in this example, the standby state), both the signal RD and the signal WR are “0”. At this time, no current flows through the resistor R, and the voltage of the output (node N ₃ ) of the limiter circuit LC becomes V _DD −2 × | V _thp | or more (see FIG. 2). Further, the voltage of the word line WL _i is V _DD (inactive). By setting the voltage of the source line SL to V _DD and the voltage of the bit line BL _j to V _DD , the memory cell MC _ij enters the standby state. .

As described above, the nonvolatile memory device 10 has operation modes of read, write, and standby states as in the conventional nonvolatile memory device. As described above, the voltage applied to the FAMOS transistor FTr can be _{increased by setting} the voltage at the time of reading of the word line WL _i connected to the gate of the selection transistor CTr to V _DD −2 × | V _thp |. The occurrence of read disturb can be suppressed by limiting to | V _thp |.

At this time, the nonvolatile memory device 10 limits the voltage of the word line WL _i to V _DD −2 × | V _thp |, but does not require a voltage generated by a regulator external to the nonvolatile memory device. Absent. The nonvolatile memory device 10 can adjust the voltage of the word line WL _i based on V _DD and GND from the outside by an internal limiter circuit. Therefore, since a regulator that requires a certain amount of time to stably supply the internal voltage is not required, the nonvolatile memory device 10 can read the data in the memory cell MC _{ij in} a short time after the power is turned on.

It should be noted that the memory cell MC _ij of only FAMOS transistor FTr not including the selected transistor CTr is also conceivable. At this time, the gate voltage of the selection transistor of the data line (wiring different from the source line SL) to which the FAMOS transistor FTr is connected may be limited. However, since the device for the precharge means is also required, the circuit configuration of the nonvolatile memory device 10 of this embodiment can be simplified.

2. Nonvolatile storage device (second embodiment)
2.1. Configuration of Nonvolatile Storage Device FIG. 6 is a diagram illustrating a configuration of the nonvolatile storage device 10 of the present embodiment. The nonvolatile memory device 10 includes a plurality of memory cells MC including a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) transistor (MONOS transistor MTr) that is a nonvolatile memory element. In addition, the same code | symbol is attached | subjected to the same element as FIGS. Further, only matters different from the first embodiment will be described to avoid duplication.

The memory cell MC is connected to the source line SL, the word lines WL _{1 to} WL _m , the write word lines WL _{1w to} WL _mw , and the bit lines BL _{1 to} BL _n as shown in FIG. Whether word lines WL _{1 to} WL _m and write word lines WL _{1w to} WL _mw are active or inactive, word line control signals nWI _{1 to} nWI _m and write word line control signals from a control unit (not shown), respectively. nWI _{1w to} nWI _mw are determined. The word line control signals nWI _{1 to} nWI _m and the write word line control signals nWI _{1w to} nWI _mw are active low signals.

The word line adjustment unit CT adjusts the voltages of the word lines WL _{1 to} WL _m , and the write word line adjustment unit CT _w adjusts the voltages of the write word lines WL _{1w to} WL _mw , respectively. Here, the word line adjustment section CT includes an inverter IV ₁ to IV _m of the word line control signal nWI ₁ ~nWI _m each is input. Inverter IV ₁ to IV _m are respectively connected to the word line WL ₁ to WL _m. The word line adjustment unit CT includes a common limiter circuit LC. The limiter circuit LC can adjust the output voltage of the inverters IV _{1 to} IV _m .

Here, the structure of the write word line adjustment unit CT is the same as that of the word line adjustment unit CT, and a description thereof will be omitted. Further, the word lines WL _{1 to} WL _m and the write word lines WL _{1w to} WL _mw may be controlled independently, but in the nonvolatile memory device 10 of this embodiment used as an OTP memory, the word line WL _{1 to} WL _m and write word lines WL _{1w to} WL _mw can be handled like the same signal (see FIG. 10). Therefore, the display of the write word line adjustment unit CT is omitted from FIG. A configuration in which independent write word lines WL _{1w to} WL _mw are not provided and shared by the word lines WL _{1 to} WL _m is also possible.

The memory cell MC _ij includes a MONOS transistor MTr (corresponding to the first transistor of the present invention) including the charge storage layer FN and a selection transistor CTr (corresponding to the second transistor of the present invention) selected by the word line WL _i . It has a structure connected in series.

Here, in a state where no charge is injected into the charge storage layer FN, a current flows when read out, and this is detected and the value of the memory cell MC _ij is assumed to be “1”. Further, in the state where charges are injected into the charge storage layer FN, no current flows when read out, so this is detected and the value of the memory is “0”.

As shown in FIG. 6, in the memory cell MC _ij , the MONOS transistor MTr and the selection transistor CTr are N-type transistors. The source line SL is common and is connected to the sources of the MONOS transistors MTr of all the memory cells MC.

2.2. Configuration of Limiter Circuit FIG. 7 is a diagram showing a detailed configuration of the limiter circuit LC. Since the word line adjustment unit CT and the write word line adjustment unit CT shown in FIG. 6 have the same structure, only the word line adjustment unit CT _i including the limiter circuit LC will be illustrated and described. Note that the memory cells MC other than the memory cell MC _ij connected to the word line WL _i have the same structure and control as the memory cell MC _ij, and therefore illustration and description thereof are omitted. Moreover, the same code | symbol is attached | subjected to the same element as FIGS. 1-6 and description is abbreviate | omitted.

When the word line control signal nWI _i that is active low is set to “1” (high level) by a control unit (not shown), the word connected to the gate of the N-type selection transistor CTr of the memory cell MC _ij The voltage on the line WL _i is GND. Therefore, the selection transistor CTr is turned off. That is, when the word line control signal nWI _i is “1” (high level), the memory cell MC _ij is not selected and the word line WL _i is inactive.

On the other hand, when the word line control signal nWI _i is “0” (low level), the voltage of the word line WL _i becomes the voltage of the node N ₃ . The voltage at the node N ₃ is the output voltage of the limiter circuit LC.

The limiter circuit LC includes a plurality of circuit elements connected in multiple stages (hereinafter, a circuit element group L ₂ ) and a resistor R having one end connected to the node N ₃ . The limiter circuit LC receives a signal nRD and a signal nWR whose values change depending on the operation mode from a control unit (not shown). When the operation mode is read (when data is read from the memory cell MC _ij ), the signal nRD is “0” (low level) and the signal nWR is “1” (high level). If the operation mode is write, the signal nRD is “1” and the signal nWR is “0”. If the operation mode is neither read nor write, the signal nRD and the signal nWR are both “1”.

If the operation mode is read, since the signal nRD is “0”, the voltage at the other end of the resistor R becomes V _DD . Here, the voltage of the node N ₁ (corresponding to the first node of the present invention) at one end of the circuit element group L ₂ is GND. And, for the node N ₂ of the other end of the circuit element group L ₂ (corresponding to a second node of the present invention), since the operation mode is the signal nWR is "1" in the lead, the node N ₃ and electrically Connected. That is, when the operation mode is read, the voltage at the node N ₃ becomes the voltage at the node N ₂ .

As shown in FIG. 7, the circuit element group L ₂ includes two diode-connected N-type transistors (transistor L ₂₀ and transistor L ₂₁ ) as circuit elements. The transistor L ₂₀ and the transistor L ₂₁ are connected in series. Therefore, _assuming that the threshold voltage of this N-type transistor is V _thn , the voltage at the node N ₂ finally becomes approximately 2 × V _thn . Therefore, when the operation mode is read and the word line control signal nWI _i is “0”, the voltage of the word line WL _i can be considered to be 2 × V _thn .

Here, the resistance R is a high resistance having a weaker current capability than the transistors L ₂₀ and L ₂₁ . When the operation mode is read, the resistor R included in the limiter circuit LC has a function of stabilizing the voltage at the node N ₃ (here, the same as the voltage at the node N ₂ ) at about 2 × V _thn .

Figure 8 is a node for voltages N _3, the current I _L2 flowing through the transistor L ₂₀ and transistor L _21, illustrates the current I _R flowing through the resistor R. Consider a case where the voltage at the node N ₃ becomes V _x0 lower than 2 × V _thn, for example. At this time, no current flows through the transistor L ₂₀ and the transistor L ₂₁ (current I _L2 ), but a current flows through the resistor R (current I _R ). Therefore, the voltage at the node N ₃ changes from V _{x0 in} the direction of the arrow a _{0 in} FIG. That is, the voltage at the node N ₃ gradually increases.

Next, consider a case where the voltage at the node N ₃ becomes V _x1 higher than 2 × V _thn, for example. At this time, a current flows through the transistor L ₂₀ and the transistor L ₂₁ (current I _L2 ), and a current also flows through the resistor R (current I _R ). Since the resistor R is a high resistance having a weaker current capability than the transistors L ₂₀ and L ₂₁ , the voltage at the node N ₃ changes from V _{x1 in} the direction of the arrow a _{1 in} FIG. That is, the voltage at the node N ₃ gradually decreases.

When the voltage at the node N ₃ changes in the direction of the arrow a ₀ or the arrow a ₁ in FIG. 8 and reaches the intersection B _{0 of the} current I _L2 and the current I _R , the current flowing through the transistors L ₂₀ and L ₂₁ And the current flowing through the resistor R are equal, so that it is stable. Here, the voltage at the node N ₃ corresponding to the intersection B ₀ is approximately 2 × V _thn . Therefore, the limiter circuit LC can finally generate a voltage of approximately 2 × V _thn by including the resistor R. Therefore, the nonvolatile memory device 10 stably sets the voltage of the word line WL _i to 2 × V _thn when the operation mode is read and the word line control signal nWI _i is “0”. Can do.

Here, also for the write word line WL _iw, control by the write word line adjuster CT _w of As (not shown) is given the same voltage as the word line WL _i is performed.

2.3. Details of Read Operation Here, it will be described with reference to FIG. 9 that the occurrence of read disturb can be suppressed by limiting the voltage of the word line WL _i to 2 × V _thn . FIG. 9 shows a state in which the data of the memory cell MC _ij is read with respect to the memory cell MC _{ij with} the voltage of the source line SL as GND and the voltage of the bit line BL _j as V _DD . At this time, the current IR _P of the read signal flowing through the bit line BL _j, determines whether the data in the memory cell MC _ij is "0" or "1".

Since the voltage of the word line WL _i connected to the gate of the selection transistor CTr is a 2 × V _thn, the voltage of the node N _n in Figure 9 can not be read unless the following V _thn. That is, when the voltage of the node N _n is higher than V _thn, V _gs <V _thn next for the selected transistor CTr, selection transistor CTr is turned off. V _gs is a gate-source voltage. V _thn is the threshold voltage of the N-type transistor, and is the same as the threshold voltage for the transistors L ₂₀ and L ₂₁ . At this time, the voltage of the write word line WL _iw connected to the gate of the MONOS transistor MTr is also 2 × V _thn .

Then, the condition for reading the data in the memory cell MC _ij is that the voltage at the node N _n is equal to or lower than V _thn , and this condition is that the voltage V _ds between the drain and the source applied to the MONOS transistor MTr. _Is limited to V _thn .

As described above, the nonvolatile memory device 10 sets the voltage applied to the MONOS transistor MTr to 2 × V _thn by reading the voltage of the word line WL _i connected to the gate of the selection transistor CTr to 2 × V _thn . By limiting to V _thn which is a relatively small value, the occurrence of read disturb can be suppressed.

2.4. Other Operation Modes FIG. 10 summarizes the relationship between the operation mode and the applied voltage in the nonvolatile memory device 10 of the present embodiment. When the operation mode is read as described above, a voltage of 2 × V _thn is obtained as the output of the limiter circuit LC. This voltage is applied to the word line WL _i , and the data of the memory cell MC _ij can be read by setting the voltage of the source line SL to GND and the voltage of the bit line BL _j to V _DD . The write word line WL _iw is also set to the same voltage 2 × V _thn as the word line WL _i .

When the operation mode is write, the signal nRD is “1” and the signal nWR is “0”. Therefore, the voltage at the node N ₃ becomes V _DD (see FIG. 7). Therefore, the voltage of the word line WL _i (and the write word line WL _iw) is V _DD, the voltage of the source line SL V _DD, the voltage of the bit line BL _j by to GND, the the memory cell MC _ij Data can be written. However, V _DD here is a sufficiently high voltage that can be written. If the voltage of the bit line BL _j is V _DD , data is not written.

When the operation mode is neither read nor write (in this example, the standby state), both the signal nRD and the signal nWR are “1”. At this time, no current flows through the resistor R, and the output voltage (node N ₃ ) of the limiter circuit LC is 2 × V _thn or less (see FIG. 7). The voltage of the word line WL _i and the write word line WL _iw is GND (inactive). By setting the voltage of the source line SL to GND and the voltage of the bit line BL _j to GND, the memory cell MC _ij It will be in a standby state.

As described above, the nonvolatile memory device 10 has operation modes of read, write, and standby states as in the conventional nonvolatile memory device. As described above, the voltage applied to the MONOS transistor _MTr is limited to V _thn by setting the voltage at the time of reading the word line WL _i connected to the gate of the selection transistor CTr to 2 × V _thn. Thus, occurrence of read disturb can be suppressed.

At this time, the nonvolatile memory device 10 limits the voltage of the word line WL _i to 2 × V _thn , but does not require a voltage generated by a regulator external to the nonvolatile memory device. The nonvolatile memory device 10 can adjust the voltage of the word line WL _i based on V _DD and GND from the outside by an internal limiter circuit. Therefore, since a regulator that requires a certain amount of time to stably supply the internal voltage is not required, the nonvolatile memory device 10 can read the data in the memory cell MC _{ij in} a short time after the power is turned on.

3. Integrated Circuit Device The nonvolatile memory device 10 of the first and second embodiments may be a part of the integrated circuit device 1 (see FIG. 13). At this time, since the operation can be performed not by the internal voltage from the regulator but by the external voltage (V _DD , GND), the nonvolatile memory device 10 can read data in a short time after the integrated circuit device 1 is powered on. Therefore, it is possible to realize the integrated circuit device 1 in which the setting value of the regulator included in the integrated circuit device 1 is stored in the nonvolatile storage device 10 and the setting at the time of starting can be adjusted flexibly. In addition, since the nonvolatile memory device 10 can suppress the occurrence of read disturb, the integrated circuit device 1 with high reliability can be realized.

  Hereinafter, the integrated circuit device 1 including the nonvolatile memory device 10 will be described in comparison with a conventional integrated circuit device 501 as a comparative example.

3.1. FIG. 11 is a block diagram of an integrated circuit device 501 of a comparative example. The integrated circuit device 501 includes a conventional nonvolatile memory device 510 that operates at an internal voltage V _INT (eg, 1.8 V). In addition to the nonvolatile memory device 510, the integrated circuit device 501 includes a regulator 3 that generates an internal voltage V _INT based on V _DD (eg, 3.3V) and GND (eg, 0V) from the outside, and an internal voltage V _INT An operating data processing unit 9 is included.

The data processing unit 9 includes, for example, an analog unit 5 and a logic unit 7. The analog unit 5 receives analog input data D _ai from the outside of the integrated circuit device 501, executes predetermined processing, and outputs analog output data D _ao . The analog output data D _ao may be data not directly related to the analog input data D _ai . The logic unit 7 receives the digital input data D _di from the outside of the integrated circuit device 501, executes a predetermined process, and outputs the digital output data D _do . The digital output data D _do may be data not directly related to the digital input data D _di . The analog unit 5 and the logic unit 7 may exchange data with each other.

Here, the integrated circuit device 501 is intended to include the setting value P _d setting P _a and logic unit 7 of the analog portion 5. Set value P _a, P _d each analog section 5, a value that affects the processing of the logic unit 7, an analog unit 5, the logic unit 7, as soon as possible setting value P _a after power on, need to read P _d There shall be.

FIG. 12 is a diagram illustrating the timing at which the setting values P _a and P _d are read in the integrated circuit device 501 of the comparative example. Here, it is assumed that time t ₀ is the time when the power is turned on when V _DD from the outside (corresponding to the first voltage of the present invention) is stabilized. It is assumed that time t ₁ is the time when V _INT (corresponding to the third voltage of the present invention) generated by the regulator 3 is stabilized.

The nonvolatile memory device 510 included in the integrated circuit device 501 of the comparative example operates with V _INT that is an internal voltage, similarly to the analog unit 5 and the logic unit 7. Therefore, the time t _{S0 at which} the set value P _a of the analog unit 5 (P _{a0 in} FIG. 12) and the set value P _d of the logic unit 7 (P _{d0 in} FIG. 12) can be read is later than the time t _1. .

3.2. On the other hand, FIG. 13 is a block diagram of an integrated circuit device 1 including the nonvolatile memory device 10 of the first embodiment and the second embodiment. The same reference numerals are given to the same elements as those in FIG.

The nonvolatile memory device 10 can be operated by V _DD and GND from the outside. Since the occurrence of read disturb can be suppressed as described above, the reliability is not inferior to that of the conventional nonvolatile memory device 510.

FIG. 14 is a diagram illustrating the timing at which the setting values P _a and P _d are read in the integrated circuit device 1 including the nonvolatile memory device 10. The same elements as those in FIG. 12 are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 14, the non-volatile memory device 10 is operated by V _DD and GND from the outside. Therefore, before V _INT stabilizes (time t ₁ ) after power-on (time t ₀ ), the analog storage device 10 set value P _a and the logic unit 7 set value P _d of lead parts 5 are possible (time t _S). Therefore, the analog unit 5 and the logic unit 7 can receive the set values P _a0 and P _d0 of FIG. 14 at the same time (time t ₁ ) when the internal voltage V _INT is stabilized. Therefore, the integrated circuit device 1 can advance the operation start of the analog unit 5 and the logic unit 7 by the time from time t ₁ to time t _S0 in FIG. 12 as compared with the integrated circuit device 501 of the comparative example.

Further, the integrated circuit device 1, the nonvolatile memory device 10 may include a setting value P _r regulator 3 (Pr in Fig. 13). To operate by V _DD, GND from the non-volatile storage device 10, and is a power-on (time t ₀₎ earlier timing after (time t _S), the set value P _r regulator 3 becomes possible lead. Therefore, the regulator 3 can receive the set value P _r0 of FIG. 14 at the time t _S before generating the internal voltage V _INT and can flexibly adjust the setting at the time of startup.

As described above, since the integrated circuit device 1 includes the nonvolatile memory device 10, data in the nonvolatile memory device can be read in a short time after the power is turned on. Further, since the nonvolatile memory device 10 can suppress the occurrence of read disturb, the reliability of the integrated circuit device 1 can be improved. Then, the integrated circuit device 1 may include the set value of the regulator 3 in the nonvolatile memory device 10. Since the integrated circuit device 1 reads the setting value of the regulator 3 before generating the internal voltage V _INT , the setting at the time of startup can be adjusted flexibly.

Further, the regulator 3 of the integrated circuit device 501 of the comparative example generates an internal voltage V _INT that drives the whole including the nonvolatile memory device 510. For this reason, the regulator 3 of the integrated circuit device 501 of the comparative example stably generates the internal voltage V _INT in consideration of, for example, a large transient current at the time of address selection of the nonvolatile memory device 510 and a steady current at the time of signal amplification. There is a need. Therefore, the integrated circuit device 501 of the comparative example also has a problem that the circuit scale of the regulator 3 becomes large.

However, the integrated circuit device 1 including the nonvolatile memory device 10 of the first embodiment and the second embodiment does not need to supply the internal voltage V _INT to the nonvolatile memory device 10. Therefore, the circuit scale of the regulator 3 can be reduced. At this time, the circuit scale of the limiter circuit LC (see FIGS. 1 and 6) increases, but the limiter circuit LC is only connected to the word lines WL _{1 to} WL _m , and the load capacity is small and steady. Since no current flows, a small circuit can be obtained. Therefore, the integrated circuit device 1 includes the integrated circuit device 50 of the comparative example.
Compared to 1, the overall circuit scale can be reduced.

4). Electronic Device The nonvolatile memory device 10 of the first embodiment or the second embodiment, or the integrated circuit device 1 may be a part of the electronic device 300. The electronic device 300 will be described with reference to FIGS. In addition, the same code | symbol is attached | subjected about the same element as FIGS. 1-4, and description is abbreviate | omitted.

  FIG. 15 is a functional block diagram of the electronic device 300. The electronic device 300 includes an integrated circuit device 1 including a nonvolatile storage device 10, a CPU (Central Processing Unit) 320, an operation unit 330, a ROM (Read Only Memory) 340, a RAM (Random Access Memory) 350, a communication unit 360, a display A unit 370 and a sound output unit 380. Note that the electronic apparatus 300 may be configured such that some of the components (each unit) in FIG. 15 are omitted or changed, or other components may be added.

  The integrated circuit device 1 includes the nonvolatile memory device 10 and performs various processes in response to commands from the CPU 320. For example, the obtained data may be corrected or the data format may be converted based on the parameters stored in the nonvolatile storage device 10.

  The CPU 320 performs various calculations using, for example, data from the integrated circuit device 1 according to a program stored in the ROM 340 or the like. Further, the CPU 320 performs various control processes. For example, the CPU 320 transmits various processes according to operation signals from the operation unit 330, processes for controlling the communication unit 360 to perform data communication with the outside, and display signals for causing the display unit 370 to display various types of information. And a process for causing the sound output unit 380 to output various sounds.

  The operation unit 330 is an input device including operation keys, button switches, and the like, and outputs an operation signal corresponding to an operation by the user to the CPU 320.

  The ROM 340 stores programs, data, and the like for the CPU 320 to perform various calculation processes and control processes.

  The RAM 350 is used as a work area of the CPU 320, and temporarily stores programs and data read from the ROM 340, data input from the operation unit 330, calculation results executed by the CPU 320 according to various programs, and the like.

  The communication unit 360 performs various controls for establishing data communication between the CPU 320 and an external device.

  The display unit 370 is a display device configured by an LCD (Liquid Crystal Display) or the like, and displays various types of information based on a display signal input from the CPU 320.

  The sound output unit 380 is a device that outputs sound such as a speaker.

  The electronic device 300 uses the integrated circuit device 1 including the nonvolatile memory device 10 described above. Therefore, the data in the nonvolatile memory device 10 can be read in a short time after the power is turned on. Further, since the nonvolatile memory device 10 can suppress the occurrence of read disturb, it has high reliability. Therefore, it can be said that the electronic device 300 operates in a short time after the power is turned on and has high reliability in quality.

Various electronic devices can be considered as the electronic device 300. For example, personal computers (for example, mobile personal computers, laptop personal computers, tablet personal computers), mobile terminals such as mobile phones, digital still cameras, inkjet discharge devices (for example, inkjet printers), routers, switches, etc. Storage area network devices, local area network devices, televisions, video cameras, video tape recorders, car navigation devices, pagers, electronic notebooks (including those with communication functions), electronic dictionaries, calculators, electronic game devices, game controllers, word processors , Workstations, videophones, security TV monitors, electronic binoculars, POS terminals, medical equipment (eg electronic thermometers, blood pressure monitors, blood Meter, electrocardiogram measuring device, ultrasonic diagnostic device, electronic endoscope), fish detector, various measuring instruments, instruments (eg, vehicle, aircraft, ship instruments), flight simulator, head mounted display, motion trace, Examples include motion tracking, motion controller, PDR (pedestrian position and orientation measurement), and the like.

  FIG. 16A illustrates an example of the appearance of a smartphone that is an example of the electronic apparatus 300. A smartphone that is the electronic device 300 includes a button as the operation unit 330 and an LCD as the display unit 370. The smart phone as the electronic device 300 uses the integrated circuit device 1 including the non-volatile storage device 10 so that the set value and other data can be read from the memory cell in a short time after the power is turned on. . In addition, since the nonvolatile storage device 10 can suppress the occurrence of data disturbance at the time of reading, the reliability of the smartphone that is the electronic device 300 is also increased.

  FIG. 16B is a diagram illustrating a drive recorder (an example of a vehicle instrument) that is an example of the electronic apparatus 300. The drive recorder is mounted on the automobile 400 and is a device that processes necessary images of the front camera 201 and the rear camera 203 attached to the automobile 400 and stores necessary information, for example.

  The drive recorder which is the electronic device 300 can read the set value and other data from the memory cell in a short time after the power is turned on by using the integrated circuit device 1 including the nonvolatile memory device 10. Therefore, it is possible to operate immediately after the engine of the automobile 400 is started. Further, since the nonvolatile memory device 10 can suppress the occurrence of data disturbance at the time of reading, the nonvolatile memory device 10 has high reliability and can be used in applications such as automobiles that require high safety.

5. Others The present invention includes substantially the same configuration (for example, a configuration having the same function, method, and result, or a configuration having the same object and effect) as the configurations described in the embodiments and modifications. In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. In addition, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 Integrated circuit device, 3 Regulator, 5 Analog part, 7 Logic part, 9 Data processing part, 10 Non-volatile storage device, 201 Front camera, 203 Rear camera, 300 Electronic device, 330 Operation part, 360 Communication part, 370 Display part 380 sound output unit, 400 automobile, 501 integrated circuit device, 510 nonvolatile memory device, BL _{1 to} BL _n , BL _j
Bit line, CT, CT _i word line adjustment unit, CT, CT _w write word line adjustment unit, CTr
Selection transistor, Dai analog input data, Dao analog output data, Ddi digital input data, Ddo digital output data, FG floating gate, FN charge storage layer, FTr FAMOS transistor, L ₁ circuit element group, L ₁₀ transistor, L ₁₁ transistor, L ₂ circuit element group, L ₂₀ transistor, L ₂₁
Transistor, LC limiter circuit, MC memory cell, MC _ij memory cell, MTr MONOS transistor, N1 node, N2 node, N3 node, Nn node, Np node, R resistor, SL source line, WI _{1 to} WI _m , WI _i word Line control signal, WL _{1 to} WL _m , WL _i word line, WL _{1w to} WL _mw , WL _iw write word line, nWI _{1 to} nWI _m , nWI _i word line control signal, nWI _{1w to} nWI _mw write word line Control signal

Claims (9)

A nonvolatile memory device to which a first voltage and a second voltage lower than the first voltage are supplied from the outside,
A memory that stores data in a nonvolatile manner and includes a first transistor to which the first voltage or the second voltage is supplied to a source, and a second transistor that is used to select the first transistor Cell,
A limiter circuit that applies a gate voltage to the gate of the second transistor when reading the data from the memory cell;
The non-volatile memory, wherein a gate voltage of the second transistor supplied by the limiter circuit has a predetermined voltage difference based on a threshold voltage of the second transistor with respect to a source voltage of the first transistor. apparatus. The nonvolatile memory device according to claim 1,
The limiter circuit is
A plurality of circuit elements connected in multiple stages between the first node and the second node;
The voltage of the first node is the first voltage or the second voltage;
When reading the data from the memory cell,
A nonvolatile memory device in which the voltage of the second node is a gate voltage of the second transistor. The nonvolatile memory device according to claim 2,
The circuit element is:
A non-volatile memory device that is a diode-connected transistor. The non-volatile memory device according to claim 2,
The limiter circuit is
When reading the data from the memory cell,
A nonvolatile memory device including a resistor having one end electrically connected to the second node. The non-volatile memory device according to claim 1,
The memory cell is
A nonvolatile memory device including the first transistor having a floating gate structure. The non-volatile memory device according to claim 1,
The memory cell is
A nonvolatile memory device including the first transistor having a MONOS structure.   An integrated circuit device comprising the nonvolatile memory device according to claim 1.   An electronic device including the nonvolatile memory device according to claim 1. The nonvolatile memory device according to any one of claims 1 to 6,
Regulator,
Including
The nonvolatile memory device is
Store the set value of the regulator,
The regulator is
Generating a third voltage that is an intermediate voltage between the first voltage and the second voltage;
An integrated circuit device that receives the set value from the nonvolatile memory device before generating the third voltage.

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