JP5978814B2 - Memory device, arithmetic processing device, and cache memory control method - Google Patents

Description

  The present disclosure relates to a memory device, an arithmetic processing device, and a cache memory control method.

  In a multi-core processor in which a plurality of processor cores are mounted on the same chip, the difference between the processor processing speed, main memory access latency, and memory access throughput becomes a problem. In order to alleviate this problem, processors typically have a multi-level memory system. A small-capacity and high-speed memory that is between the main memory and the arithmetic unit of the processor and temporarily copies and holds the data in the main memory is called a cache memory. As long as the processor refers to the data on the cache memory, memory access with low latency and high throughput is possible.

  The cache memory mainly includes an LRU (Last Recently Used) array, a tag array, and a data array. Data is copied from the main memory to each array element of the data array. Copying data from the main memory to the data array is executed in units of cache lines. The memory space of the main memory is divided in units of cache lines, and the divided memory areas are sequentially assigned to the cache lines. Since the capacity of the cache memory is smaller than the capacity of the main memory, the memory area of the main memory is repeatedly assigned to the same cache line.

  In general, among all bits of an address, a predetermined number of middle bits serve as an index of the cache memory, and the remaining bits positioned higher than that serve as a cache memory tag. A tag array of the cache memory stores a tag corresponding to each index. However, a plurality of tags are generally stored for each index, and these plurality of tags are called ways. When accessing data, tags of a plurality of ways with corresponding indexes in the tag array are read using the index portion in the address indicating the access destination. It is determined whether or not the read tag matches the bit pattern of the tag portion in the address. If any tag of the read multiple ways matches, the access becomes a cache hit. If none of the tags of the plurality of read ways match, the access is a cache miss.

  In the case of a cache hit, the cache data (data of a predetermined number of bits for one cache line) corresponding to the corresponding way (the way with the matching tag) of the corresponding index is accessed in the cache RAM. In the case of a cache miss, the access target data stored in the main memory is transferred to the corresponding cache line in the cache RAM. At this time, if valid cache data exists in all the ways of the corresponding index, the least necessary data (for example, data that has passed the most time since the last access) is used as the data to be accessed. The replacement process is executed. During this replacement process, a write-back operation is executed, and before the data to be replaced is overwritten and disappears, the data is written into the main memory, and the contents of the cache memory are reflected in the main memory. The LRU (Last Recently Used) array of the cache memory is an area for storing the way of the data that has passed the most time since the last access.

  It is conceivable to improve throughput of read / write processing by collectively accessing a DRAM (Dynamic Random Access Memory), which is an element of a DIMM (Dual Inline Memory Module) used as a main memory, in a large data unit. The DRAM includes a cell array in which memory elements that store 1-bit information are arranged in a matrix, and a circuit that controls read / write access to the memory elements. In accessing the DRAM, first, one word line corresponding to a row address in the cell array is selectively activated to designate a row direction position, and then a column direction position designated by a column address is selected. Read and write data. When accessing consecutive column addresses with the same row address, the access time can be shortened by continuously accessing multiple data in the column direction while the word line remains selectively activated. Can do. Such an access method is called continuous access here.

  In a multi-level memory system, access to the main memory occurs when reading data to be copied from the main memory to the cache memory or when writing data evicted from the cache memory to the main memory. . Among these, the operation of copying data from the main memory to the cache memory (cache fill operation) is executed when the data is needed (or predicted to be needed in the near future) in the arithmetic unit of the processor. Therefore, access to the main memory by cache fill can be basically controlled by a program, and access control can be performed so as to access continuous addresses of the main memory. On the other hand, the operation of expelling data from the cache memory (write-back operation) is an operation that is performed secondaryly during the cache fill process, and the way to be expelled is seemingly random regardless of program control. is there. Therefore, in write back, access control cannot be performed so as to access continuous addresses of the main memory.

  Although the write-back write address cannot be freely controlled, if the cache line size is increased, it is possible to realize writing to a certain continuous address at the time of write-back. In other words, by increasing the cache line size, the access unit for main memory access increases, and continuous access of a certain length is always performed. However, the cache line size is determined by considering the cache memory hit rate and the processor physical capacity in consideration of the spatial locality that the reference address is concentrated in a predetermined address range and the temporal locality that the reference address is concentrated in a predetermined time range. The implementation cost is determined to be optimal. A smaller cache line size is desired for processors that are generally capable of running a myriad of applications. That is, if the total capacity of the cache memory is constant, there is a trade-off relationship between spatial locality and temporal locality. If attention is focused on only one cache line, the increase in the cache line size increases the utilization efficiency of spatial locality. However, considering the references to multiple cache lines, the cache to be referenced by referring to other cache lines Since the probability that a line is evicted increases, the utilization efficiency of temporal locality decreases. Generally, the disadvantage when the utilization efficiency of the spatial locality due to the reduction in the line size is reduced can be reduced by predicting which cache line is referred to. Specifically, the cache line data around the referenced cache line may be copied together. However, reducing the line size is effective in increasing the temporal locality utilization efficiency, so it is difficult to achieve both the spatial locality utilization efficiency and the temporal locality utilization efficiency.

JP-A-7-160577 JP 2011-164948 A JP 2008-310465 A

  In view of the above, a memory device, an arithmetic processing device, and a cache memory control method in which the size of data for continuous access to the main memory is variable are desired.

A memory device includes: a data array that stores cache data for each index; a management data array that stores management data indicating either the first state or the second state for each cache data of the data array; When a single line is stored in the data array in response to a cache fill request on a line, the corresponding management data in the management data array is set to the first state and continuously in response to a cache fill request on consecutive multiple lines. When storing a plurality of lines in the data array, a write control circuit that sets the management data corresponding to the management data array to the second state, and the management data array When the management data indicates the first state, the eviction target cache data is set as a single line. When a write request is generated and the corresponding management data in the management data array indicates the second state, the cache data of the data array and the eviction target cache data that are grouped together with the eviction target cache data are An access control circuit for generating a request to write as a continuous plurality of lines; a tag array for storing a plurality of tags corresponding to a plurality of ways for each index; and a buffer for storing cache data to be written back; A plurality of cache data corresponding to the plurality of ways is stored for each index, and when the management data corresponding to the management data array indicates a second state at the time of write back of the cache data to be purged, the eviction is performed. Index of target cache data Of the adjacent index, the cache data having the tag and same tag of the eviction target cache data selected from the data array, and stores the target cache data eviction the said selected cache data in the buffer.

The method of the cache memory, set the corresponding management data of the management data array in the case of storing a single line data array in a first state in response to the cache fill request in a single line, multiple consecutive When storing a plurality of continuous lines in the data array in response to a cache fill request on a line, the management data corresponding to the management data array is set to the second state, and when the cache data to be evicted is written back, When the management data corresponding to the management data array indicates the first state, a request to write the eviction cache data as a single line is generated, and the management data corresponding to the management data array indicates the second state In this case, the cache data of the data array that is bundled with the cache data to be evicted Generates a request to write said eviction target cache data as a continuous plurality of lines, a plurality of each index Way there are multiple tags corresponding said data array a plurality of corresponding to said plurality of ways for each index When cache data is stored and the management data corresponding to the management data array indicates the second state at the time of write-back of the eviction target cache data, in the adjacent index of the index of the eviction target cache data, Each step includes selecting cache data having the same tag as the tag of the eviction target cache data from the data array, and storing the selected cache data and the eviction target cache data in a write-back buffer .

The arithmetic processing unit includes an arithmetic unit, a cache memory, and a memory access controller, and the cache memory has a data array for storing cache data for each index, and a first state or for each cache data of the data array. A management data array that stores management data indicating any of the second states, and a corresponding one of the management data array when storing a single line in the data array in response to a cache fill request on a single line A document in which management data is set to the first state, and the management data array corresponding to the management data array is set to the second state when consecutive lines are stored in the data array in response to a cache fill request for continuous lines. Write control circuit and the write-out target cache data at the write back of the management data array When the corresponding management data indicates the first state, a request for writing the eviction target cache data as a single line is transmitted to the memory access controller, and the corresponding management data in the management data array indicates the second state. An access control circuit that transmits a request to write the cache data of the data array and the cache data to be evicted as a plurality of continuous lines to the memory access controller together with the cache data to be evicted, and for each index. Includes a tag array for storing a plurality of tags corresponding to a plurality of ways and a buffer for storing cache data to be written back, and the data array stores a plurality of cache data corresponding to the plurality of ways for each index. The chasing When the corresponding management data in the management data array indicates the second state at the time of write back of the target cache data, the same index as the tag of the target cache data is set in the adjacent index of the index of the target cache data. Cache data having the tag is selected from the data array, and the selected cache data and the eviction target cache data are stored in the buffer .

  According to at least one embodiment of the present disclosure, there are provided a memory device, an arithmetic processing device, and a cache memory control method in which the size of data for continuous access to a main memory is variable.

1 is a diagram of a system including a CPU module and a main memory. It is a figure which shows an example of a structure of the lowest cache memory. It is a flowchart which shows an example of operation | movement of the lowest-order cache memory at the time of 1 line data request | requirement, or 1 line cache fill request | requirement. It is a flowchart which shows an example of a cache fill process. It is a flowchart which shows an example of operation | movement of the lowest cache memory at the time of 2 line cache fill request | requirement. It is a flowchart which shows an example of a miss side fill process. It is a flowchart which shows an example of a fill process. It is a flowchart which shows an example of a fill process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a diagram of a system including a CPU module and a main memory. The system of FIG. 1 includes a central processing unit (CPU) module 10 and a plurality of DIMMs 11 that are main memories. The CPU module 10 includes a calculation unit 12, an uppermost cache memory 13, a lowermost cache memory 14, and a memory access controller (MAC) 15. The arithmetic unit 12 executes a program stored in the DIMM 11 and executes arithmetic processing on the data stored in the DIMM 11. The program and data stored in the DIMM 11 are accessed by the memory access controller 15 and supplied to the arithmetic unit 12 via the memory access controller 15, the lowest cache memory 14, and the highest cache memory 13. The uppermost cache memory 13 and the lowermost cache memory 14 have a smaller storage capacity than the DIMM 11 and can access data at a higher speed than the DIMM 11, and include, for example, an SRAM (Static Random Access Memory) as a memory device. In general, a copy of a part of data stored in the lowest cache memory 14 is held in the highest cache memory 13. A copy of a part of the data stored in the DIMM 11 is held in the lowest cache memory 14. Although FIG. 1 shows a two-level cache memory of the highest cache memory 13 and the lowest cache memory 14, the number of cache memory layers is not limited to two. For example, a one-layer configuration in which only the lowest cache memory 14 is provided may be used.

  FIG. 2 is a diagram illustrating an example of the configuration of the lowest cache memory 14. 2 includes a command buffer 20, an address buffer 21, an even index generation circuit (EIG) 22-1, an odd index generation circuit (OIG) 22-2, an even bank 23-1, and an odd bank. 23-2. The lowest level cache memory 14 further includes merge flag control circuits (MFC) 24-1 and 24-2, LRU control circuits (LC) 25-1 and 25-2, and valid flag control circuits (VFC) 26-1 and 26. -2. The lowest-order cache memory 14 further includes data bus selection circuits 27-1 to 30-1 and 27-2 to 30-2, tag comparison circuits 31-1 and 31-2, 35-1 and 35-2, and empty ways. Check circuits 32-1 and 32-2 are included. The lowest level cache memory 14 further includes eviction way selection circuits 33-1 and 33-2, address restoration circuits 34-1 and 34-2, tag generation circuits 36-1 to 38-1 and 36-2 to 38-2, It includes selectors 39-1 through 42-1 and 39-2 through 42-2. The lowest level cache memory 14 further includes a hit determination circuit 43, a merge flag check circuit 44, an index comparison circuit 45, and an arbitration circuit 46. The lowest level cache memory 14 further includes a cache fill address buffer 47, a cache fill data buffer 48, a data response buffer 49, and a write back address & data buffer 50. The lowest level cache memory 14 further includes an SRAM access control circuit 51, an LRU update control circuit 52, a cache write control circuit 53, a cache response control circuit 54, a MAC access control circuit 55, and a selector 56.

  The even bank 23-1 includes a decoder 60-1, a merge flag array 61-1, an LRU flag array 62-1, a valid flag array 63-1, a tag array 64-1, a data array 65-1, and buffers 66-1 to 66-1. 70-1 included. The odd bank 23-2 includes a decoder 60-2, a merge flag array 61-2, an LRU flag array 62-2, a valid flag array 63-2, a tag array 64-2, a data array 65-2, and buffers 66-2 to 70-2 included.

  In FIG. 2, a signal line indicated by a solid line indicates a flow of a control signal, a signal line indicated by a dotted line indicates a flow of an address signal, and a signal line indicated by a double line indicates a flow of a data signal. In addition, the boundary between each functional block shown in each box and other functional blocks basically indicates a functional boundary, and separation of physical position, separation of electrical signal, control logic It does not always correspond to the separation. In the case of hardware, each functional block may be one hardware module physically separated from other blocks to some extent, or in a hardware module physically integrated with other blocks. One function may be shown. In the case of software, each functional block may be one software module logically separated from other blocks to some extent, or one function in a software module logically integrated with another block. May be shown.

  The even bank 23-1 stores the cache data on the even index side, and the odd bank 23-2 stores the cache data on the odd index side. In the example shown in FIG. 2, two ways are provided in each of the even-numbered bank 23-1 and the odd-numbered bank 23-2, but the number of ways is not limited to two, and any number including one is included. It may be. In the example shown in FIG. 2, in a cache fill operation and a write back operation, data access to the main memory with a single cache line or data access to the main memory in which two consecutive cache lines are grouped is possible. is there. This is an example not intended to be limited, and the cache memory may be designed so as to execute data access to the main memory in which three or more continuous plural cache lines are grouped. For example, in order to enable read / write access to the main memory in which four consecutive plural cache lines are grouped, four banks are provided, and each of these four banks has modulo 4 of 1, 2, 3 , And 4 may be stored.

  The basic operation of the cache memory will be described below taking the even bank 23-1 as an example. A similar cache memory operation is executed for the odd bank 23-2.

  Data copied from the main memory is stored in each array element of the data array 65-1 of the even bank 23-1. Copying data from the main memory to the data array is executed in units of cache lines. The memory space of the main memory is divided in units of cache lines, and the divided memory areas are sequentially assigned to the cache lines. Since the capacity of the cache memory is smaller than the capacity of the main memory, the memory area of the main memory is repeatedly assigned to the same cache line. Among all the bits of the address, a predetermined number of middle bits serve as an index of the cache memory, and bits positioned higher than that serve as a tag of the cache memory.

  The tag array 64-1 stores cache data for each index. More specifically, the tag array 64-1 stores a plurality of tags (two tags in the example of FIG. 2) corresponding to a plurality of ways for each index. When accessing data, an address (request address) indicating an access destination is supplied to the address buffer 21 from a higher-level cache or arithmetic unit. An index part in the request address is extracted by the even index generation circuit 22-1, the extracted index part is decoded by the decoder 60-1, and one index corresponding to the access destination is designated. The tags of the plurality of ways with the specified index are read from the tag array 64-1 via the buffer 69-1, and sent to the tag comparison circuit 31-1 via the data bus selection circuits 27-1 and 28-1. Supplied. The data of a plurality of ways with the designated index is read out from the data array 65-1 through the buffer 70-1, and is selected through the data bus selection circuits 29-1 and 30-1 into the selector 39-1. To be supplied.

  From the access destination address supplied from the address buffer 21, the tag generation circuit 37-1 extracts the tag of the request address. The tag comparison circuit 31-1 compares the extracted access destination tag with a plurality of tags read from the tag array 64-1, and determines whether the bit patterns match. When any tag of the plurality of ways read from the tag array 64-1 matches, the access is a cache hit. If none of the tags of the plurality of read ways match, the access is a cache miss.

  In the case of a cache hit, the selector 39-1 selects cache data (data of a predetermined number of bits for one cache line) corresponding to the corresponding way (the way with the matching tag) of the corresponding index. This selection operation is performed based on information indicating the matched tag supplied from the tag comparison circuit 31-1 to the selector 39-1. The cache data is output to a higher-level cache or arithmetic unit via the data response buffer 49.

  In the case of a cache miss, the access target data stored in the main memory is transferred to the corresponding cache line of the data array 65-1. At this time, if valid cache data exists in all the ways of the corresponding index, the least necessary data (for example, data that has passed the most time since the last access) is used as the data to be accessed. The replacement process is executed. During this replacement process, a write-back operation is executed, and before the data to be replaced is overwritten and disappears, the data is written into the main memory, and the contents of the cache memory are reflected in the main memory. The LRU array 62-1 is an area for storing the way of data for which the most time has elapsed since the last access. The valid flag array 63-1 is an area for storing a flag indicating whether or not the data is valid for each data of the data array 65-1.

  The specific operation in the case of a cache miss is roughly as follows. The empty way check circuit 32-1 checks whether or not there is an empty way (that is, an available way indicating that the valid flag indicates an invalid state) based on the valid flag data from the valid flag array 63-1. To do. If there is an empty way, data is read from the designated address (request address) of the main memory, and the read data is stored in the empty way of the data array 65-1. When there is no empty way, the eviction way selection circuit 33-1 selects a eviction target way based on the LRU information from the LRU array 62-1. Although details will be described later, among the plurality of cache data corresponding to the plurality of ways read from the data array 65-1, the cache data corresponding to the eviction target way is selected by the selector 41-1. The selected data is written into the main memory via the write back address & data buffer 50 and the memory access controller 15. Thereafter, data is read from the designated address (request address) of the main memory, and the read data is stored in the evicted way in the data array 65-1.

  In the lowest level cache memory 14 shown in FIG. 2, as a cache fill operation, data can be read from the main memory with a single cache line, or data can be read from the main memory with a group of two consecutive cache lines. is there. Similarly, in the write back operation, data can be written to the main memory using a single cache line, or data can be written to the main memory in which two consecutive cache lines are grouped. In this way, continuous access to the main memory on a single cache line and continuous access to the main memory on the continuous cache line are executed, and the size of data for continuous access to the main memory becomes variable. In the following description, the cache line is simply called a line. As described above, the unit to be bundled is not limited to two lines, and may be three lines or more.

  Whether the cache fill operation is performed in units of a single line or in units of two continuous lines is specified by an access command from a higher-level device (for example, a higher-level cache). The host device requests a cache fill operation in one line when data of a size smaller than one line is required, and requests data in a continuous two lines when data of a size larger than one line is required. Request a cache fill operation. In the write-back operation, whether to perform a write operation in units of single lines or a write operation in units of two continuous lines depends on whether the data of the line to be written (data expelled by cache fill) is bundled with other lines. Depends on whether or not. When the data of one line to be written is grouped with another line, the write back operation is executed by grouping these two lines. When the data of one line to be written is not grouped with other lines, the write-back operation is executed with this one line alone.

  Whether or not data of a certain line is grouped with data of other lines is designated by management data stored in the management data array. The merge flag array 61-1 is an example of a management data array, and stores a merge flag (an example of management data) indicating either the first state or the second state for each cache data of the data array 65-1. To do. The first state indicates that the target cache data is in a single line state, and the second state indicates that the target cache data is in a continuous line state that is bundled with other lines. The first state may correspond to, for example, a flag value of 0, and the second state may correspond to a flag value of 1. In the following description, when the merge flag is in the second state, the merge flag may be expressed as “set”, “set”, “exists”, or the like. When the merge flag is in the first state, the merge flag may be expressed as “not set”, “not set”, “not present”, or the like.

  When the cache write control circuit 53 stores a single line in the data array 65-1 in response to a cache fill request for a single line, the cache write control circuit 53 sets the corresponding merge flag in the merge flag array 61-1 to the first state. And The cache write control circuit 53 further sets the second merge flag corresponding to the merge flag array 61-1 in the second flag when the continuous multiple lines are stored in the data array 65-1 in response to the cache fill request for the continuous multiple lines. State. The MAC access control circuit 55 issues a request to write the eviction target cache data as a single line if the merge flag corresponding to the merge flag array 61-1 indicates the first state during write back of the eviction target cache data. Generate. The MAC access control circuit 55 further generates a request for writing a plurality of continuous lines when the corresponding merge flag in the merge flag array 61-1 indicates the second state. Specifically, the MAC access control circuit 55 generates a request to write the cache data of the data array 65-1 and the cache data to be evicted together with the eviction target cache data as a continuous plurality of lines.

  The above operation is for the even bank 23-1 side, but the same operation is also performed for the odd bank 23-2 side. In the above description, a group of data includes one even index cache data and one adjacent odd index cache data. For example, when cache data of an even index is a target to be evicted and the cache data of the even index is in the second state by the merge flag, the corresponding cache data of adjacent odd indexes is a group of partner data. . Similarly, when cache data of a certain odd index is a target to be evicted and the cache data of the odd index is in the second state by the merge flag, the counterpart data in which the corresponding cache data of adjacent even indexes are grouped together It is. As a method for specifying the partner data to be grouped, cache data having the same tag as the tag of the eviction target cache data in the adjacent index of the eviction target cache data index may be selected from the data array 65-1.

  The above selection operation is performed by the address restoration circuits 34-1 and 34-2, the tag generation circuits 38-1 and 38-2, the selectors 42-1 and 42-2, the tag comparison circuit 35-1 and the value 35-2. Realized. More specifically, if there is cache data that has been subject to eviction on the even index side, a tag corresponding to that data is supplied to the address restoration circuit 34-1, and the address of the eviction target data is determined by the address restoration circuit 34-1. Restore. That is, the address of the eviction target data is restored by combining the address signal from the address buffer 21 and the tag corresponding to the eviction target data. This restoration address is supplied to the tag generation circuit 38-2 via the selector 42-2, and the tag generation circuit 38-2 generates a tag for the data to be purged. The tag comparison circuit 35-2 compares a plurality of tags read from the tag array 64-2 of the odd bank 23-2 with the tags generated by the tag generation circuit 38-2, and identifies the way where the tags match. To do. Information for specifying the matching way is supplied to the selector 41-2, and the other party's cache data is selected by the selector 41-2 and stored in the write-back address & data buffer 50. Even on the even index side, the tag comparison circuit 35-1 compares a plurality of tags read from the tag array 64-1 of the even bank 23-1 with the tags generated by the tag generation circuit 38-2, and tags Identify ways that match. Information for specifying the matching way is supplied to the selector 41-1, and the cache data to be evicted is selected by the selector 41-1 and stored in the write-back address & data buffer 50. The restored address restored on the even index side and the restored address restored on the odd index side are both supplied to the write back address & data buffer 50. If there is cache data to be evicted on the odd index side, the same operation as described above is executed except that the above operation is reversed between the even side and the odd side.

  The hit determination circuit 43 generates information indicating the hit bank and the missed bank based on the tag comparison results from the tag comparison circuits 31-1 and 31-2. At this time, as will be described later, the hit determination circuit 43 detects only the true hit by referring to the least significant bit of the index which is a part of the request address. The hit determination circuit 43 uses the arbitration circuit 46, the selector 56, the LRU update control circuit 52, the cache write control circuit 53, the cache response control circuit 54, and the MAC access control circuit 55 as information indicating the hit bank and the missed bank. To supply. The merge flag check circuit 44 checks whether or not the merge flag is set for the eviction target way based on the information indicating the eviction way supplied from the eviction way selection circuits 33-1 and 33-2. The check result is supplied to the arbitration circuit 46. The index comparison circuit 45 compares the indexes. The comparison result is supplied to the arbitration circuit 46. The arbitration circuit 46 supplies a selection signal to the selectors 42-1 and 42-2 based on information indicating the hit bank and the missed bank, information on the presence / absence of the merge flag of the eviction target way, and the like.

  The SRAM access control circuit 51 controls reading / writing of the merge flag array, the LRU array, the valid flag array, the tag array, and the data array with respect to the even bank 23-1 and the odd bank 23-2. When a request is generated from an upper storage hierarchy (cache), the SRAM access control circuit 51 reads data from each array to a buffer. Further, when a response is returned from the memory access controller 15 and data is set in the buffer of the bank, the SRAM access control circuit 51 writes the data into the corresponding array.

  The LRU update control circuit 52 stores the hit bank and way when a request is hit when a request is made for one line data or a request for one line cache fill. Remember. The LRU update control circuit 52 further stores a hit way for the bank for which the request is hit and a free way or a eviction way for the missed bank when a two-line cache fill request is made. If there is a vacant way and there is a eviction, priority is given to the vacant way. The LRU update control circuit 52 also updates the LRU array based on the stored bank and way number when data read from the main memory is written to the array.

  The cache write control circuit 53 stores an empty way or a eviction way for a missed bank if a miss occurs at the time of one-line data request or one-line cache fill request. When eviction occurs due to the merge flag factor for the other bank, the cache write control circuit 53 stores the eviction way. When a two-line cache fill request is made, the cache write control circuit 53 stores the hit way for the hit bank, and also stores the eviction way when eviction occurs due to a merge flag factor. For the missed bank, the cache write control circuit 53 stores an empty way or a eviction way.

  The cache write control circuit 53 stores a tag, data, and valid flag in a buffer that matches a stored empty way or eviction way for a bank where a cache fill occurs when a one-line data request or a one-line cache fill request occurs. Set. If eviction has occurred in the other bank, the cache write control circuit 53 sets an invalid flag in the buffer that matches the evacuated way. The cache write control circuit 53 sets a merge flag in a buffer matching the way if a hit way is stored when a two-line cache fill request is stored. However, when the eviction way due to the merge flag factor is stored, the cache write control circuit 53 sets an invalid flag in the buffer matching the way. If an empty way or a eviction way is stored for the missed bank, the cache write control circuit 53 sets a tag, data, a valid flag, and a merge flag in a buffer that matches the way. The buffers referred to here are buffers 66-1 to 70-1 and buffers 66-2 to 70-2. The flags set for the buffer are merge flag control circuits (MFC) 24-1 and 24-2, LRU control circuits (LC) 25-1 and 25-2, and valid flag control circuits (VFC) 26-1 and 26-. 2 is performed.

  The cache response control circuit 54 returns a response to the upper storage hierarchy when a cache hit occurs when one line data is requested, and returns a response when data is returned from the memory access controller 15 when a cache miss occurs.

  The MAC access control circuit 55 sends a normal data read request for one line to the memory access controller 15 when a cache miss occurs when one line data is requested or one line cache fill is requested. When a data request is made, the MAC access control circuit 55 further instructs the data response buffer 49 to return data. Further, when there is no merge flag in the eviction target data, the MAC access control circuit 55 sends a normal data write request for one line to the memory access controller 15. If there is a merge flag in the eviction target data, the MAC access control circuit 55 sends a data write request for two lines to the memory access controller 15 as merge access.

  The MAC access control circuit 55 sends a read request for two lines to the memory access controller 15 as merge access if a miss occurs in both banks at the time of a two-line cache fill request. When a miss occurs in only one bank, the MAC access control circuit 55 sends a read request for one line to the memory access controller 15 as normal access only for the data on the bank that has been missed. Further, the MAC access control circuit 55 issues a normal data write request for one line to the memory access controller 15 when the two-line cache fill request causes eviction only in one of the banks and there is no merge flag in the eviction target data. send. If there is a merge flag in the eviction target data of any bank, the MAC access control circuit 55 sends a data write request for two lines to the memory access controller 15 as merge access. If eviction occurs in both banks and there is no merge flag in the eviction target data, the MAC access control circuit 55 sends a data write request for two independent lines to the memory access controller 15 as normal access.

  FIG. 3 is a flowchart showing an example of the operation of the least significant cache memory 14 at the time of requesting one line data or requesting one line cache fill. In step S1, a one-line data request or a one-line cache fill request comes from an upper storage hierarchy. In step S2, the even bank 23-1 and the odd bank 23-2 are accessed simultaneously, and the merge flag, LRU information, valid flag, tag, and cache data are read from each bank. The even index may be generated by truncating the request address, and the odd index may be generated by rounding up the request address. In step S3, the read tag is compared with the tag generated from the request address. This comparison is executed by the tag comparison circuits 31-1 and 31-2.

  In step S4, the hit determination circuit 43 determines whether or not the tags match in the bank indicated by the least significant bit of the index that is a part of the request address (the bit that determines even or odd). For example, when the request address is an even number, if the tags match in the even bank, a true hit is obtained. Even if the request address is an even number and the tag matches in the odd bank, it is a hit at the position where the address is incremented by 1, not a true hit.

  If there is a cache hit, the LRU of the hit bank is updated in step S5. If the request from the upper layer is a data request, the hit data is written into the data response buffer 49 in step S6. In step S7, a completion response is returned to the upper storage hierarchy (it is not necessary to execute at the time of the fill request).

  If there is a cache miss, an empty way is determined in step S8. If there is an empty way, fill processing A-1 described later is executed. If there is no empty way, the eviction way is selected in step S9. Although an empty way is selected in both banks, the correct operation is executed only in the bank that matches the request address.

  In step S10, it is checked whether or not the selected way has a merge flag. If there is no merge flag, the data corresponding to the eviction way of the bank that matches the odd or even number of the request address is written to the write-back address & data buffer 50 in step S11. At this time, when there is no merge flag, the arbitration circuit 46 selects the multiplexers 42-1 and 42-2 to output data from the address restoration circuit of the bank with the odd or even number of request addresses matching. Give a signal. The arbitration circuit 46 further notifies the MAC access control circuit 55 that only one line is being written back. In step S12, the MAC access control circuit 55 notifies the memory access controller 15 that the eviction of write-back data for one line has been completed. Thereafter, fill processing A-1 described later is executed.

  If there is a merge flag, in step S13, the data corresponding to the eviction way of the bank that matches the odd number or even number of the request address and the data of the other bank paired therewith are written back to the write back address & data buffer 50. Write to. That is, since there are lines in the other bank that have addresses that are continuous with the eviction target line, the data paired with the other bank is also stored in the write back address & data buffer 50 as a write back target. At this time, when there is a merge flag, the arbitration circuit 46 outputs a selection signal to the multiplexers 42-1 and 42-2 so as to output data from the address restoration circuit of the bank with the odd or even number of request addresses matching. Put out. For example, when the request address is an even number, the address of the address restorer 34-1 in the even bank is supplied to both the tag comparison circuits 35-1 and 35-2. Furthermore, the arbitration circuit 46 notifies the MAC access control circuit 55 that it is a write back subject to merge access for two continuous lines. In step S14, the MAC access control circuit 55 notifies the memory access controller 15 that the continuation of write-back data for two continuous lines has been completed. Thereafter, fill processing A-2, which will be described later, is executed.

  FIG. 4 is a flowchart illustrating an example of the cache fill process. In the case of the fill process A-1, in step S15, the data read from the memory access controller 15 is stored in the empty way of the corresponding bank, and the LRU is updated. In the case of the fill process A-2, in step S16, the data read from the memory access controller 15 is stored in the empty way of the relevant bank, and the invalid flag array of the empty way is invalidated on the other bank side. Write the indicated data. Further, the LRU is updated. Thereafter, in step S17, in the case of a data request, data is also written into the data response buffer 49, and a completion response is returned to the upper storage hierarchy.

  FIG. 5 is a flowchart showing an example of the operation of the least significant cache memory 14 when a two-line cache fill request is made. In step S21, a continuous two-line cache fill request is received from the upper storage hierarchy. In step S22, the even bank 23-1 and the odd bank 23-2 are accessed simultaneously, and the merge flag, LRU information, valid flag, tag, and cache data are read from each bank. In the case of a 2-line cache fill request, the request address is always an even address. In step S23, the read tag is compared with the tag generated from the request address. This comparison is executed by the tag comparison circuits 31-1 and 31-2.

  In step S24, the hit determination circuit 43 determines whether or not the tags match in both banks. If there is a cache hit in both banks, the LRU is updated in both banks in step S25.

  If the tags do not match in at least one bank, it is determined in step S26 whether the tags do not match in both banks. If there is a mistake in only one bank, a miss side fill process C-1 described later is executed. If there is a mistake in both banks, an empty way is checked in both banks in step S27. If both banks are free, fill processing B-1 described later is executed.

  If there is no vacancy in at least one of the banks, it is determined in step S28 whether eviction is necessary in both banks. That is, it is determined whether both banks have no empty way or only one of them has no empty way. When eviction is necessary only in one bank, fill processing C-2 described later is executed.

  If eviction is required in both banks, the eviction way is selected in each of both banks in step S29. Thereafter, in step S30, the state of the merge flag is determined. As the state of the merge flag, there are cases where the merge flag exists in both banks, the merge flag exists only in one bank, and the merge flag does not exist in both banks.

  If there is a merge flag in both banks, the data of the eviction way selected from the even bank is written in the write-back address & data buffer 50 in step S31. Further, paired data is evicted from the odd bank and written to the write back address & data buffer 50. Note that there are lines in one bank where addresses are continuous with respect to the lines in one bank. However, when the expelling way is selected based on the LRU in both banks, the ways corresponding to the continuous two lines that are paired with each other are selected. Is not necessarily selected as a target for eviction. For this reason, the result of the even bank is preferentially used here. Alternatively, the odd bank results may be prioritized rather than the even banks. In other words, when there is a merge flag for at least two eviction target cache data selected in response to a cache fill request on a plurality of continuous lines, one of the at least two eviction target cache data is eviction target cache data. Select. At this time, the arbitration circuit 46 supplies a selection signal to the selectors 42-1 and 42-2 so as to output the data from the address restoration circuit 34-1 of the even bank. As a result, the cache data having the same tag as the tag of the selected one eviction target cache data in the adjacent index of the index of one selected eviction target cache data is specified in the data array. Then, the specified cache data and the one selected eviction target cache data are stored in the write-back address & data buffer 50 for write-back. The arbitration circuit 46 further notifies the MAC access control circuit 55 that it is a write back subject to merge access for two continuous lines.

  If the merge flag exists only in one bank, the data of the eviction way selected from the bank having the merge flag is written in the write-back address & data buffer 50 in step S33. Further, paired data is evicted from the other bank and written to the write back address & data buffer 50. The selection result of the eviction way by the LRU in the other bank is ignored. At this time, the arbitration circuit 46 supplies a selection signal to the selectors 42-1 and 42-2 so as to output data from the address restoration circuit of the bank having the merge flag. The arbitration circuit 46 further notifies the MAC access control circuit 55 that it is a write back subject to merge access for two continuous lines.

  Subsequent to steps S31 and S33, in step S32, the MAC access control circuit 55 notifies the memory access controller 15 that the continuation of write-back data of two continuous lines has been completed.

  If the merge flag does not exist in both banks, the data of the eviction target way selected by the LRU is written in the write-back address & data buffer 50 in each bank in step S34. At this time, the arbitration circuit 46 supplies selection signals to the selectors 42-1 and 42-2 so that the data from the respective address restoration circuits 34-1 and 34-2 are output in both banks. The arbitration circuit 46 further notifies the MAC access control circuit 55 that the write back is for two lines.

  Subsequent to step S34, in step S35, the MAC access control circuit 55 notifies the memory access controller 15 that the two lines of write-back data to be written to the main memory have been evicted independently.

  FIG. 6 is a flowchart illustrating an example of the miss-side fill process C-1. If only one of the even bank side and the odd bank side misses, the cache fill process is executed on the missed side.

  In step S41, it is checked whether there is an empty way. If there is an empty way, fill processing B-2 described later is executed. If there is no empty way, in step S42, the eviction way is selected according to the LRU in the missed bank. In step S43, it is checked whether the selected way has a merge flag. If there is no merge flag, the data corresponding to the eviction way of the bank that has made a mistake is written in the write-back address & data buffer 50 in step S44. At this time, when there is no merge flag, the arbitration circuit 46 outputs a selection signal to the multiplexers 42-1 and 42-2 so as to output the data from the address restoration circuit of the bank that has missed. The arbitration circuit 46 further notifies the MAC access control circuit 55 that the write back is for only one line and the bank to be written back. In step S45, the MAC access control circuit 55 notifies the memory access controller 15 that one line of write-back data has been evicted. Thereafter, fill processing B-2, which will be described later, is executed.

  If there is a merge flag, the data corresponding to the eviction way of the bank that has made a mistake and the data of the other bank paired therewith are written in the write-back address & data buffer 50 in step S46. That is, since there are lines in the other bank that have addresses that are continuous with the eviction target line, the data paired with the other bank is also stored in the write back address & data buffer 50 as a write back target. At this time, when there is a merge flag, the arbitration circuit 46 outputs a selection signal to the multiplexers 42-1 and 42-2 so as to output data from the address restoration circuit of the bank that has missed. Furthermore, the arbitration circuit 46 notifies the MAC access control circuit 55 that it is a write back subject to merge access for two continuous lines. In step S47, the MAC access control circuit 55 notifies the memory access controller 15 that the continuation of write-back data for two continuous lines has been completed. Thereafter, fill processing B-3, which will be described later, is executed.

  FIG. 7 is a flowchart showing an example of the fill process C-2. When only one of the even bank side and the odd bank side needs to be evicted (when there is no empty way), the cache fill process is executed in the bank requiring evict.

  In step S51, the eviction way is selected according to the LRU in the bank that needs eviction. In step S52, it is checked whether the selected way has a merge flag. If there is no merge flag, the data corresponding to the eviction way of the bank requiring eviction is written into the write-back address & data buffer 50 in step S53. At this time, if there is no merge flag, the arbitration circuit 46 outputs a selection signal to the multiplexers 42-1 and 42-2 so as to output the data from the address restoration circuit of the bank that needs to be evicted. The arbitration circuit 46 further notifies the MAC access control circuit 55 that the write back is for only one line and the bank to be written back. In step S54, the MAC access control circuit 55 notifies the memory access controller 15 that the eviction of write-back data for one line has been completed. Thereafter, fill processing B-2, which will be described later, is executed.

  If there is a merge flag, in step S55, the data corresponding to the eviction way of the bank requiring eviction and the data of the other bank paired therewith are written into the write-back address & data buffer 50. That is, since there are lines in the other bank that have addresses that are continuous with the eviction target line, the data paired with the other bank is also stored in the write back address & data buffer 50 as a write back target. At this time, if there is a merge flag, the arbitration circuit 46 outputs a selection signal to the multiplexers 42-1 and 42-2 so as to output data from the address restoration circuit of the bank that needs to be evicted. Furthermore, the arbitration circuit 46 notifies the MAC access control circuit 55 that it is a write back subject to merge access for two continuous lines. In step S56, the MAC access control circuit 55 notifies the memory access controller 15 that the continuous two-line write-back data has been evicted. Thereafter, fill processing B-4 described later is executed.

  FIG. 8 is a flowchart illustrating an example of the fill processes B-1 to B-4. In the fill process B-1 shown in FIG. 8A, the data for two lines read from the memory access controller 15 is stored and the LRU is updated in the corresponding empty way of the corresponding bank. Furthermore, data indicating validity is set in the valid flag, and a merge flag is set. In the fill process B-2 shown in FIG. 8B, the data for one line read from the memory access controller 15 is stored and the LRU is updated in the corresponding empty way of the corresponding bank. Furthermore, data indicating validity is set in the valid flag, and a merge flag is set. Further, since the hit bank data is paired with the filled data, a merge flag is also set in the merge flag array of the hit bank. In the fill process B-3 shown in FIG. 8C, the data for one line read from the memory access controller 15 is stored and the LRU is updated in the corresponding empty way of the corresponding bank. Furthermore, data indicating validity is set in the valid flag, and a merge flag is set. Further, since the hit bank data is paired with the filled data, a merge flag is also set in the merge flag array of the hit bank. Furthermore, the valid flag is set to invalid in the empty way of the vacant bank. In the fill process B-4 shown in FIG. 8D, the data for two lines read from the memory access controller 15 are stored and the LRU is updated in the corresponding empty way of the corresponding bank. Furthermore, data indicating validity is set in the valid flag, and a merge flag is set.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

10 CPU
11 DIMM
12 arithmetic unit 13 uppermost cache memory 14 lowermost cache memory 15 memory access controller 43 hit determination circuit 44 merge flag check circuit 45 index comparison circuit 46 arbitration circuit 51 SRAM access control circuit 52 LRU update control circuit 53 cache write control circuit 54 Cache response control circuit 55 MAC access control circuit

Claims (8)

A data array for storing cache data for each index; and
A management data array for storing management data indicating either the first state or the second state for each cache data of the data array;
When a single line is stored in the data array in response to a cache fill request on a single line, the corresponding management data in the management data array is set to the first state, and a cache fill request on consecutive multiple lines is met. A write control circuit for setting the corresponding management data in the management data array to the second state when storing a plurality of continuous lines in the data array;
If the management data corresponding to the management data array indicates the first state at the time of write-back of the cache data to be evicted, a request for writing the cache data to be evicted as a single line is generated, and the management data array An access control circuit for generating a request to write the cache data of the data array and the eviction target cache data as a plurality of continuous lines together with the eviction target cache data when the management data to be indicated indicates a second state and,
A tag array for storing a plurality of tags corresponding to a plurality of ways for each index;
A buffer for storing cache data to be written back;
Only including,
A plurality of cache data corresponding to the plurality of ways is stored for each index in the data array, and the management data corresponding to the management data array indicates a second state at the time of write back of the eviction target cache data Selecting cache data having the same tag as the tag of the eviction target cache data in the adjacent index of the index of the eviction target cache data from the data array, and selecting the selected cache data and the eviction target cache data. Is stored in the buffer . The write control circuit according to claim 1 in the case of storing a single line to the data array in response to the cache fill request in continuous plural lines to corresponding management data second state of the control data array serial mounting of the memory device. When the management data indicates the second state with respect to at least two eviction target cache data selected in response to the cache fill request in the continuous multiple lines, one of the at least two eviction target cache data Select cache data to be evicted, and in the data array, cache data having the same tag as the tag of the selected cache data to be evicted in the adjacent index of the selected cache data to be evicted in the data array. 3. The memory device according to claim 1, wherein the memory device is specified, and the specified cache data and the selected one eviction target cache data are stored in the buffer. The continuous multi-line memory device according to claim 1 to 3 any one of claims a continuous two lines. Set the corresponding management data of the management data array in the case of storing a single line data array in a first state in response to the cache fill request in a single line,
When storing a plurality of continuous lines in the data array in response to a cache fill request in a plurality of continuous lines, the management data corresponding to the management data array is set to the second state,
A request to write the eviction target cache data as a single line when the management data corresponding to the management data array indicates a first state during write back of the eviction target cache data;
When the management data corresponding to the management data array indicates the second state, a request to write the cache data of the data array and the cache data to be purged as a plurality of continuous lines together with the cache data to be purged to generate,
There are a plurality of tags corresponding to a plurality of ways for each index, and a plurality of cache data corresponding to the plurality of ways is stored for each index in the data array, and when the cache data to be evicted is written back When the management data corresponding to the management data array indicates the second state, the cache data having the same tag as the tag of the eviction target cache data in the adjacent index of the index of the eviction target cache data is A cache memory control method including each step of selecting from a data array and storing the selected cache data and the eviction target cache data in a write-back buffer . 6. The method of controlling a cache memory according to claim 5, wherein when a single line is stored in the data array in response to a cache fill request in a plurality of continuous lines, the management data corresponding to the management data array is set to the second state. . When the management data indicates the second state with respect to at least two eviction target cache data selected in response to the cache fill request in the continuous multiple lines, one of the at least two eviction target cache data Select cache data to be evicted, and in the data array, cache data having the same tag as the tag of the selected cache data to be evicted in the adjacent index of the selected cache data to be evicted in the data array. identified, the control method of the cache memory according to claim 5 or 6, wherein storing the one eviction target cache data wherein is the selected and specified cache data to the write-back buffer. An arithmetic unit;
Cache memory,
A memory access controller, wherein the cache memory is
A data array for storing cache data for each index; and
A management data array for storing management data indicating either the first state or the second state for each cache data of the data array;
When a single line is stored in the data array in response to a cache fill request on a single line, the corresponding management data in the management data array is set to the first state, and a cache fill request on consecutive multiple lines is met. A write control circuit for setting the corresponding management data in the management data array to the second state when storing a plurality of continuous lines in the data array;
When the management data corresponding to the management data array indicates the first state during write-back of the eviction target cache data, a request to write the eviction target cache data as a single line is transmitted to the memory access controller, When the management data corresponding to the management data array indicates the second state, a request to write the cache data of the data array and the cache data to be purged together with the eviction target cache data as a plurality of continuous lines is issued. An access control circuit for transmitting to the memory access controller ;
A tag array for storing a plurality of tags corresponding to a plurality of ways for each index;
A buffer for storing cache data to be written back;
Only including,
A plurality of cache data corresponding to the plurality of ways is stored for each index in the data array, and the management data corresponding to the management data array indicates a second state at the time of write back of the eviction target cache data Selecting cache data having the same tag as the tag of the eviction target cache data in the adjacent index of the index of the eviction target cache data from the data array, and selecting the selected cache data and the eviction target cache data. Is stored in the buffer .

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