JP5975114B2 - Wireless communication apparatus, wireless communication system, and control method of wireless communication apparatus - Google Patents

Description

  The present invention relates to a radio communication device, a radio communication system, and a control method for the radio communication device.

  A wireless communication device used in a mobile phone, a wireless LAN, or the like installs a plurality of overhanging wireless devices connected to the base station device (including a baseband processing device) by an optical cable or the like at a location away from the base station device (including a baseband processing device). As a result, the communication area is expanded. Furthermore, in recent years, an overhanging wireless device has to be added in order to cope with a rapid increase in traffic. For this reason, there is a demand for low power consumption of the entire wireless communication device and miniaturization of each overhanging wireless device.

  By the way, it is known that a power amplifier provided in the final stage of the transmission unit of the wireless communication apparatus consumes a great amount of power. Therefore, reducing the power consumption of the power amplifier is very effective in reducing the power consumption of the entire wireless communication apparatus.

  Therefore, for example, a switching amplifier that is expected to have high power efficiency is employed as the power amplifier. The switching amplifier amplifies power of an input signal having a pulse waveform while maintaining the waveform. Here, since the pulse waveform signal can transmit only 1 bit per pulse, the input signal of the switching amplifier needs to be converted into 1-bit information in advance. For example, a ΔΣ modulation circuit is used as a circuit that converts multi-bit information into 1-bit information.

  Related techniques are disclosed in Patent Document 1 and Patent Document 2. Both Patent Document 1 and Patent Document 2 disclose a wireless communication device including a ΔΣ modulator and a switching amplifier that amplifies an output signal of the ΔΣ modulator. In addition, Patent Document 3 also discloses a wireless communication device including a ΔΣ modulator.

US Pat. No. 6,977,546 B2 European Patent Application No. 2180610 JP 2007-88618 A

  However, in the related technology, since the change timing of the high-frequency signal waveform and the change timing of the pulse waveform input to the switching amplifier do not coincide with each other, a current is supplied to the switch element at the on-off transition of the switch element constituting the switching amplifier. There is a problem that power consumption increases. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The present invention has been made to solve such problems, and provides a wireless communication device, a wireless communication system, and a control method for the wireless communication device that can reduce power consumption. Objective.

  According to one embodiment, a wireless communication device includes a baseband processing unit that modulates a baseband signal to generate a high-frequency signal, and a phase-synchronized ΔΣ modulation that outputs the high-frequency signal as a ΔΣ-modulated signal by ΔΣ-modulating the high-frequency signal And an overhanging radio unit that is formed separately from the baseband processing unit and amplifies the ΔΣ modulation signal and wirelessly transmits the signal, and the phase-locked ΔΣ modulator detects the amplitude of the high-frequency signal. An amplitude detector that outputs an amplitude signal, a phase detector that detects a phase of the high-frequency signal and outputs a phase signal, and a pulse phase signal generator that generates a pulse phase signal of a pulse waveform based on the phase signal A ΔΣ modulator that ΔΣ modulates the amplitude signal in synchronization with the pulse phase signal, an output signal of the ΔΣ modulator, and the pulse phase signal to generate the ΔΣ modulation signal If, having said overhanging radio unit includes a switching amplifier which amplifies the ΔΣ modulated signal.

  According to the embodiment, it is possible to provide a wireless communication apparatus, a wireless communication system, and a control method for the wireless communication apparatus that can reduce power consumption.

1 is a block diagram illustrating an outline of a wireless communication apparatus according to a first embodiment; It is a figure which shows an example of the specific structure of an amplitude detector. It is a figure which shows an example of the specific structure of a phase comparator. It is a figure which shows an example of the specific structure of a mixer. It is a figure which shows an example of the specific structure of switching amplifier. 3 is a timing chart illustrating an operation of the wireless communication apparatus according to the first exemplary embodiment. 1 is a block diagram showing details of a wireless communication device according to a first exemplary embodiment; FIG. 6 is a block diagram showing a first modification example of the wireless communication apparatus according to the first exemplary embodiment; 6 is a block diagram illustrating a third modification of the wireless communication apparatus according to the first embodiment; FIG. FIG. 6 is a block diagram showing a fourth modification example of the wireless communication apparatus according to the first exemplary embodiment; It is a figure which shows the 1st modification of switching amplifier. It is a figure for demonstrating operation | movement of the switching amplifier shown in FIG. It is a figure for demonstrating operation | movement of the switching amplifier shown in FIG. It is a figure which shows the 2nd modification of switching amplifier. It is a figure for demonstrating operation | movement of the switching amplifier shown in FIG. It is a figure for demonstrating operation | movement of the switching amplifier shown in FIG. It is a figure which shows the 3rd modification of switching amplifier. It is a figure which shows the 4th modification of switching amplifier. 3 is a block diagram illustrating a configuration example of a wireless communication apparatus according to a second embodiment; FIG. FIG. 10 is a block diagram illustrating a modification of the wireless communication device according to the second exemplary embodiment. FIG. 6 is a block diagram illustrating a configuration example of a wireless communication system according to a third exemplary embodiment. FIG. 6 is a diagram schematically illustrating a wireless communication system according to a third embodiment. FIG. 9 is a block diagram illustrating a specific example of a wireless communication device used in a wireless communication system according to a third embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a block diagram of an outline of the wireless communication apparatus according to the first embodiment. The wireless communication apparatus according to the present embodiment includes a phase-synchronous ΔΣ modulator that ΔΣ modulates the amplitude signal γ included in the high-frequency signal in synchronization with the phase signal θ included in the high-frequency signal. Thereby, the radio communication apparatus 1 according to the present embodiment can reduce the output current at the time of on / off transition of the switch element provided in the switching amplifier 121, and thus can reduce power consumption. This will be specifically described below.

  The wireless communication device 1 illustrated in FIG. 1 includes a baseband processing unit 11, an overhanging radio unit 12, an optical cable 13 that connects the baseband processing unit 11 and the overhanging radio unit 12, and an antenna 14. Note that the baseband processing unit 11 and the overhanging radio unit 12 are formed separately, and signals are transferred via the optical cable 13.

(Baseband processing unit 11)
The baseband processing unit 11 includes a phase synchronization type ΔΣ modulator 111. The phase-synchronous ΔΣ modulator 111 performs ΔΣ modulation on the high-frequency signal generated by modulating the baseband signal and outputs it as a ΔΣ modulation signal.

(Phase-locked ΔΣ modulator 111)
The phase-locked ΔΣ modulator 111 includes an amplitude detector 1111, a phase detector 1112, a pulse phase signal generator 1113, a ΔΣ modulator 1114, and a mixer (mixer) 1115.

(Amplitude detector 1111)
The amplitude detector 1111 detects the amplitude signal γ included in the high-frequency signal generated by the baseband processing unit 11. Hereinafter, it demonstrates in detail using a specific example.

  FIG. 2 is a diagram illustrating an example of a specific configuration of the amplitude detector 1111. The amplitude detector 1111 illustrated in FIG. 2 includes a diode D1, a resistance element R1, and a capacitor C1. The diode D1 outputs a current proportional to the square of the input voltage. Therefore, the diode D1 outputs a current having a larger time average value as the amplitude value of the high-frequency signal is larger. The resistor element R1 and the capacitor C1 provided at the subsequent stage of the diode D1 constitute a filter circuit, and extract only the DC component included in the output current of the diode D1. This DC component is equal to the time average value of the output current of the diode D1. Accordingly, the DC component increases as the amplitude value of the high-frequency signal increases. In other words, the amplitude value of the high-frequency signal input to the diode D1 and the DC component of the output current of the diode D1 are in a monotonically increasing relationship and in a one-to-one relationship. For this reason, it is possible to extract information on the amplitude value of the high-frequency signal from the DC component of the output current of the diode D1.

(Phase detector 1112)
The phase detector 1112 detects the phase signal θ included in the high-frequency signal generated by the baseband processing unit 11. Hereinafter, it demonstrates in detail using a specific example.

  FIG. 3 is a diagram illustrating an example of a specific configuration of the phase detector 1112. The phase detector 1112 illustrated in FIG. 3 includes a comparator CMP1. The comparator CMP1 generates an H level output signal when the input signal is a positive value, and generates an L level output signal when the input signal is a negative value. Here, the high-frequency signal shows a positive value when the phase is 0 ° to 180 °, and shows a negative value when the phase is 180 ° to 360 °. Therefore, the comparator CMP1 generates an H-level output signal when the phase of the high-frequency signal is 0 ° to 180 °, and generates an L-level output signal when the phase of the high-frequency signal is 180 ° to 360 °.

(Pulse phase signal generator 1113)
The pulse phase signal generator 1113 generates a pulse phase signal having a pulse waveform based on the phase signal θ. Details will be described below.

  The output waveform of the comparator CMP1 provided in the phase detector 1112 is ideally a rectangular wave. However, in practice, since there are parasitic resistance and capacitance on the output side of the comparator CMP1, the output waveform of the comparator approaches a sine wave. Therefore, the pulse phase signal generator 1113 again shapes the phase signal θ approaching a sine wave into a rectangular wave signal.

  The pulse phase signal generator 1113 may have a configuration having only a comparator, similar to the phase detector 1112, but in order to avoid a rectangular wave from returning to a sine wave due to parasitic parameters, a high gain is provided after the comparator. It is preferable to further include an amplifier. As a result, the pulse phase signal generator 1113 can reshape the phase signal θ approaching a sine wave into a rectangular wave signal.

(ΔΣ modulator 1114)
The ΔΣ modulator 1114 modulates the amplitude signal γ in synchronization with the pulse phase signal. Details will be described below.

  The ΔΣ modulator 1114 performs a sampling operation with the signal period from the pulse phase signal generator 1113. Therefore, the ΔΣ modulator 1114 performs a sampling operation at a frequency higher than the frequency component included in the amplitude information from the amplitude detector 1111, converts multi-bit information included in the input signal into 1-bit information, and outputs it. Note that the quantization noise generated by the ΔΣ modulator 1114 is highest at the Nyquist frequency and becomes smaller as the frequency is lower.

  By operating the ΔΣ modulator 1114 at a frequency higher than the frequency of the input signal, the input signal can be pushed into a frequency region sufficiently lower than the Nyquist frequency. As described above, by operating the ΔΣ modulator 1114 at a frequency higher than the frequency of the input signal, the input signal is hardly affected by the quantization noise.

(Mixer 1115)
The mixer 1115 mixes the output signal of the ΔΣ modulator 1114 and the pulse phase signal to generate a ΔΣ modulation signal. Hereinafter, it demonstrates in detail using a specific example.

  FIG. 4 is a diagram illustrating an example of a specific configuration of the mixer 1115. The mixer 1115 shown in FIG. 4 has an AND circuit AND1. The AND circuit AND1 outputs the pulse phase signal as it is as a ΔΣ modulation signal when the output signal of the Σ modulator 1114 is H level, and regardless of the pulse phase signal when the output signal of the ΔΣ modulator 1114 is L level. An L level ΔΣ modulation signal is output.

  The baseband processing unit 11 converts the ΔΣ modulation signal output from the phase synchronization type ΔΣ modulator 111 into an optical signal, and then transmits the optical signal to the overhanging radio unit 12 via the optical cable 13.

(Overhang radio section 12)
The overhanging radio unit 12 converts the optical signal transmitted from the baseband processing unit 11 via the optical cable 13 into a ΔΣ modulation signal, amplifies the ΔΣ modulation signal, and wirelessly transmits the signal from the antenna 14. The overhanging radio unit 12 includes a switching amplifier 121 that amplifies the ΔΣ modulation signal.

(Switching amplifier 121)
FIG. 5 is a diagram illustrating an example of a specific configuration of the switching amplifier 121. The switching amplifier 121 shown in FIG. 5 is a so-called class D amplifier, and is a high side gate (switch element) 100-1, a low side gate (switch element) 100-2, and a high side that drives the high side gate 100-1. A side driver (high side amplifier) 200-1 and a low side driver (low side amplifier) 200-2 for driving the low side gate 100-2 are provided. In this embodiment, the case where both the high-side gate 100-1 and the low-side gate 100-2 are depletion type N-channel field effect transistors will be described as an example.

  In the high side gate 100-1, the drain is connected to the power source 101-1, the source is connected to the output terminal (external output terminal) OUT, and the output (first control signal) of the high side driver 200-1 is supplied to the gate. Is done. In the present embodiment, a case where the power supply 101-1 generates a power supply voltage of 30V will be described as an example. In the low-side gate 100-2, the drain is connected to the output terminal OUT, the source is connected to the ground (0 V), and the output (second control signal) of the low-side driver 200-2 is supplied to the gate.

  The high side gate 100-1 is turned on / off based on the first control signal output from the high side driver 200-1. The low side gate 100-2 is turned on / off complementarily with the high side gate 100-1 based on the second control signal output from the low side driver 200-2. The switching amplifier 121a outputs an amplified signal having a voltage level (30V or 0V) corresponding to the value of the ΔΣ modulation signal from a node (output terminal OUT) between the high side gate 100-1 and the low side gate 100-2. Output. That is, the switching amplifier 121 amplifies power while maintaining the pulse waveform of the ΔΣ modulation signal.

(Timing chart)
FIG. 6 is a timing chart showing the operation of the wireless communication device 1. Specifically, FIG. 6 shows the phase signal θ output from the phase detector 1112, the pulse phase signal output from the pulse phase signal generator 1113, the output signal (pulse amplitude signal) of the ΔΣ modulator 1114, the mixing The output signal of the device 1115 and the output current of the switching amplifier 121 are shown.

  The state transition points (that is, the rising edge and the falling edge) of the output signal (ΔΣ modulation signal) of the mixer 1115 coincide with the state transition points of the pulse phase signal. Further, the rising edge and falling edge of the pulse phase signal coincide with 0 ° and 180 ° of the phase signal θ, respectively. Therefore, the rising edge and falling edge of the output signal (ΔΣ modulation signal) of the mixer 1115 coincide with the phases of 0 ° and 180 ° of the high-frequency signal.

  The switching amplifier 121 generates an output signal having a pulse waveform equal to the input signal. Here, the current supplied from the switching amplifier 121 to the filter (not shown) approximates a value obtained by dividing the high-frequency signal component (voltage) included in the output signal of the switching amplifier 121 by the resistance value of the load (antenna 14). Are equal. That is, the waveform of the current supplied from the switching amplifier 121 to the filter (not shown) is equal to the waveform of the high-frequency signal. In other words, the phase of the output current of the switching amplifier 121 matches the phase of the high-frequency signal.

  Considering that the on / off transition points of the high-side gate 100-1 and the low-side gate 100-2 constituting the switching amplifier 121 coincide with the state transition point of the output signal (ΔΣ modulation signal) of the mixer 1115, the high-side gate The phase of the output current of the switching amplifier 121 at the on / off transition point of 100-1 and the low-side gate 100-2 is 0 ° or 180 °. That is, the output current instantaneously becomes zero at the on / off transition point of the high side gate 100-1 and the low side gate 100-2.

  As described above, the wireless communication apparatus 1 according to the present embodiment includes the phase synchronization type ΔΣ modulator that ΔΣ modulates the amplitude signal γ included in the high frequency signal in synchronization with the phase signal θ included in the high frequency signal. Thereby, the radio communication apparatus 1 according to the present embodiment can reduce the output current at the time of on / off transition of the switch element provided in the switching amplifier 121, and thus can reduce power consumption.

  Furthermore, the wireless communication apparatus 1 according to the present embodiment includes the phase-locked ΔΣ modulator 111 in the baseband processing unit 11 instead of the protruding wireless unit 12. Thereby, the wireless communication apparatus 1 according to the present embodiment can reduce the overhanging wireless unit 12 in size.

  In the present embodiment, the case where the ΔΣ modulator 1114 generates an output signal having two output values (H, L) is described as an example, but the present invention is not limited to this. The ΔΣ modulator 1114 can be appropriately changed to a configuration that generates an output signal having three or more output values. In addition, the ΔΣ modulator 1114 can be appropriately changed to a configuration for generating output signals having a number of output values corresponding to the external control signal. In this case, the switching amplifier 121 outputs an amplified signal having a voltage level corresponding to the value of the ΔΣ modulation signal.

(Specific configuration example of the wireless communication device 1)
FIG. 7 is a block diagram showing details of the wireless communication device 1. Note that the wireless communication device 1 illustrated in FIG. 7 is merely an example, and may be changed as appropriate without departing from the spirit of the present invention. As already described in FIG. 1, the wireless communication device 1 shown in FIG. 7 includes a baseband processing unit 11, an overhanging radio unit 12, an optical cable 13 that connects the baseband processing unit 11 and the overhanging radio unit 12, And an antenna 14. Note that the baseband processing unit 11 and the overhanging radio unit 12 are formed separately, and signals are transferred via the optical cable 13.

  The baseband processing unit 11 includes a baseband control unit (BB) 112, a modulator (MOD) 113, a multiplexer (MUX) 114, a filter (Filter) 115, and a peak suppressor (Peak Red) 116. A phase-locked ΔΣ modulator (PMC DMS) 111, a SerDes unit 117, an OE conversion unit (first OE conversion unit) 118, and a demodulator (DEM) 119.

  The overhanging radio unit 12 includes an OE conversion unit (second OE conversion unit) 122, a SerDes unit 123, a switching amplifier (SW AMP) 121, a filter (bandpass filter) 124, a low noise amplifier (LNA) 125, A mixer 126, an AD converter (ADC) 127, an automatic gain control filter (Filter AGC) 128, and a separator (DEMUX) 129 are provided.

First, the transmission operation of the wireless communication device 1 shown in FIG. 7 will be briefly described.
In the baseband processing unit 11, the baseband control unit 112 generates a baseband signal. The modulator 113 modulates the baseband signal and outputs it as a high frequency signal. The multiplexer 114 multiplexes and outputs the high frequency signal. The filter 115 passes only a desired frequency band from the output of the multiplexer 114. The peak suppressor 116 suppresses and outputs the output of the filter 115 that exceeds the threshold voltage. The phase-locked ΔΣ modulator 111 converts the high-frequency signal supplied from the modulator 113 via the multiplexer 114, the filter 115, and the peak suppressor 116 into a ΔΣ modulation signal and outputs it. The SerDes unit 117 serializes the ΔΣ modulation signal. The OE converter 118 converts the ΔΣ modulation signal (electric signal) output from the SerDes unit 117 into an optical signal. This optical signal is transmitted to the overhanging radio unit 12 via the optical cable 13. Since the optical signal in this case is the above-described phase-locked ΔΣ modulation wave, the sampling frequency matches the high-frequency signal frequency.

  In the overhang radio unit 12, the OE conversion unit 122 converts the optical signal transmitted from the baseband processing unit 11 through the optical cable 13 into a ΔΣ modulation signal (electric signal). The SerDes unit 123 deserializes the ΔΣ modulation signal. The switching amplifier 121 amplifies power while maintaining the pulse waveform of the ΔΣ modulation signal output from the SerDes unit 123. The filter 124 has a pass band that matches the frequency band of the high-frequency signal, and selectively passes only the high-frequency signal component included in the output signal of the switching amplifier 121. An antenna (load) 14 is connected to the subsequent stage of the filter 124, thereby reproducing a high frequency signal. The reproduced high-frequency signal is radiated from the antenna 14 into the air (that is, wirelessly transmitted).

Next, the reception operation of the wireless communication device 1 shown in FIG. 7 will be briefly described.
In the overhanging radio unit 12, the low noise amplifier 125 amplifies the high frequency signal received by the antenna 14 with low noise. The mixer 126 down-converts (frequency conversion) the output signal of the low noise amplifier 125. The AD converter 127 converts the output signal (analog signal) of the mixer 126 into a digital signal. The automatic gain control filter 128 performs filtering processing such as interpolation and decimation on the output signal of the AD converter 127. The separator 129 separates and outputs the output signal of the automatic gain control filter 128. The SerDes unit 123 serializes the output signal of the separator 129. The OE converter 122 converts the output signal (electric signal) of the SerDes unit 123 into an optical signal. This optical signal is transmitted to the baseband processing unit 11 via the optical cable 13.

  In the baseband processing unit 11, the OE conversion unit 118 converts the optical signal transmitted from the overhanging radio unit 12 via the optical cable 13 into an electrical signal. The SerDes unit 117 deserializes this electric signal. The demodulator 119 demodulates the output signal of the SerDes unit 117 and outputs it as a baseband signal. The baseband signal output from the demodulator 119 is supplied to the baseband control unit 112.

  Next, a modification of the wireless communication device 1 shown in FIG. 7 will be described with reference to FIGS.

(First Modification of Wireless Communication Device 1)
FIG. 8 is a diagram illustrating a first modification of the wireless communication device 1 illustrated in FIG. 7 as a wireless communication device 1a. Compared with the wireless communication device 1 shown in FIG. 7, the wireless communication device 1 a shown in FIG. 8 includes a phase-locked ΔΣ modulator 111 in the overhanging wireless unit 12 instead of the baseband processing unit 11. Specifically, the phase-locked ΔΣ modulator 111 is provided immediately before the switching amplifier 121. The other configuration and operation of the wireless communication device 1a illustrated in FIG. 8 are the same as those of the wireless communication device 1 illustrated in FIG.

  Thus, even when the phase-locked ΔΣ modulator 111 is provided in the overhanging radio unit 12, the power consumption is reduced. However, the case where the phase-locked ΔΣ modulator 111 is provided in the baseband processing unit 11 is more advantageous for downsizing the overhanging radio unit 12.

(Second Modification of Wireless Communication Device 1)
As a second modification of the wireless communication device 1, the filter 124 may be replaced with a variable filter. The variable filter 124 is a filter that can be switched to any one of the plurality of pass bands, or a filter that can change the pass band.

  As the sampling frequency of the phase-locked ΔΣ modulator 111 provided in the baseband processing unit 11 is changed, the frequency of the pass band of the variable filter 124 provided in the overhanging radio unit 12 can be changed. The baseband processing unit 11 can directly generate and control a radio frequency.

(Third Modification of Wireless Communication Device 1)
FIG. 9 is a diagram illustrating a third modification of the wireless communication device 1 illustrated in FIG. 7 as a wireless communication device 1b. Compared with the wireless communication device 1 shown in FIG. 7, the wireless communication device 1 b shown in FIG. 9 does not include the OE conversion units 118 and 122, and includes an Ethernet cable 13 a instead of the optical cable 13. Other configurations and operations of the wireless communication device 1b illustrated in FIG. 9 are the same as those of the wireless communication device 1 illustrated in FIG.

  The Ethernet cable 13a projects the ΔΣ modulation signal output from the baseband processing unit 11 to the wireless unit 12 by the Ethernet (registered trademark) standard. The wireless communication device 1b illustrated in FIG. 9 can achieve the same effects as the wireless communication device 1 illustrated in FIG.

(Fourth Modification of Wireless Communication Device 1)
FIG. 10 is a diagram showing a fourth modification of the wireless communication device 1 shown in FIG. 7 as a wireless communication device 1c. Compared with the wireless communication device 1 shown in FIG. 7, the wireless communication device 1 c shown in FIG. 10 wirelessly transmits a ΔΣ modulation signal from the baseband processing unit 11 to the overhanging wireless unit 12 instead of the optical cable 13.

  The baseband processing unit 11 replaces the OE conversion unit 118 with a circuit for wireless transmission / reception (a modulator 211, an up converter 212, a power amplifier 213, a filter 214, a low noise amplifier 215, a down converter 216, and a demodulator 217). ). The overhanging radio unit 12 includes a radio transmission / reception circuit (a filter 221, a low noise amplifier 222, a down converter 223, a demodulator 224, a modulator 225, an up converter 226, and a power amplifier 227) instead of the OE conversion unit 122. . Since a general method is used for a wireless transmission / reception method between the baseband processing unit 11 and the overhanging wireless unit 12, a detailed description thereof is omitted.

  The wireless communication device 1c illustrated in FIG. 10 can achieve the same effects as the wireless communication device 1 illustrated in FIG.

  Next, a modification of the switching amplifier 121 will be described with reference to FIGS.

(First Modification of Switching Amplifier 121)
FIG. 11 is a diagram illustrating a first modification of the switching amplifier 121 as a switching amplifier 121a. FIG. 11 also shows the filter 124 and the load (antenna) 14.

  The switching amplifier 121a includes a high side gate (switch element) 100-1, a low side gate (switch element) 100-2, a high side driver (high side amplifier) 200-1 that drives the high side gate 100-1, And a low-side driver (low-side amplifier) 200-2 for driving the low-side gate 100-2. In this embodiment, the case where both the high-side gate 100-1 and the low-side gate 100-2 are depletion type N-channel field effect transistors will be described as an example.

  In the high side gate 100-1, the drain is connected to the power source 101-1, the source is connected to the output terminal (external output terminal) OUT, and the output (first control signal) of the high side driver 200-1 is supplied to the gate. Is done. In the present embodiment, a case where the power supply 101-1 generates a power supply voltage of 30V will be described as an example. In the low-side gate 100-2, the drain is connected to the output terminal OUT, the source is connected to the ground (0 V), and the output (second control signal) of the low-side driver 200-2 is supplied to the gate.

  The high-side driver 200-1 includes a resistance element (first resistance element) 203-1 and an N-channel field effect transistor (first transistor; hereinafter simply referred to as a transistor) 201-1 as a switch element. The resistance element 203-1 and the transistor 201-1 constitute an input switching amplifier. One end of the resistance element 203-1 is connected to the output terminal OUT, and the other end of the resistance element 203-1 is connected to the drain of the transistor 201-1. In the transistor 201-1, the source (voltage supply terminal) is connected to the power source 202-1, and the ΔΣ modulation signal is supplied to the gate. Then, the high side driver 200-1 outputs a first control signal from a node between the resistance element 203-1 and the transistor 201-1. In the present embodiment, a case where the power supply 202-1 generates a power supply voltage of −5V will be described as an example. In this embodiment, a case where the resistance value of the resistance element 203-1 is 2Ω will be described as an example.

  The low-side driver 200-2 includes a resistance element 203-2 and an N-channel field effect transistor (hereinafter simply referred to as a transistor) 201-2 as a switch element. The resistance element 203-2 and the transistor 201-2 constitute an input switching amplifier. One end of the resistance element 203-2 is connected to the power source 204-2, and the other end of the resistance element 203-2 is connected to the drain of the transistor 201-2. In the transistor 201-2, the source is connected to the power source 202-2, and the inverted signal of the ΔΣ modulation signal is supplied to the gate. The low-side driver 200-3 outputs a second control signal from a node between the resistance element 203-2 and the transistor 201-2. Note that in this embodiment, the case where the power supply 204-2 generates a power supply voltage of 0V and the power supply 202-2 generates a power supply voltage of -5V will be described as an example. In the present embodiment, a case where the resistance value of the resistance element 203-2 is 2Ω will be described as an example.

  The high side gate 100-1 is turned on / off based on the first control signal output from the high side driver 200-1. The low side gate 100-2 is turned on / off complementarily with the high side gate 100-1 based on the second control signal output from the low side driver 200-2. Then, the switching amplifier 121a outputs an amplified signal having a voltage level corresponding to the value of the ΔΣ modulation signal from a node (output terminal OUT) between the high side gate 100-1 and the low side gate 100-2.

  Note that, as described above, in this embodiment, the case where both the high-side gate 100-1 and the low-side gate 100-2 are depletion type N-channel field effect transistors is described as an example. Therefore, for example, the high-side gate 100-1 and the low-side gate 100-2 are turned on when the gate-source is at the same potential, and turned off when the gate-source is −5V. Specifically, the high side gate 100-1 is turned on when the first control signal is 30V and turned off when the first control signal is -5V. The low side gate 100-2 is turned on when the second control signal is 0V, and turned off when the second control signal is -5V.

  Next, the operation of the switching amplifier 121a will be described with reference to FIGS. 12A and 12B.

  First, an operation when the switching amplifier 121a outputs a high-side voltage (power supply voltage 30V of the power supply 101-1) will be described with reference to FIG. 12A.

  When the switching amplifier 121a outputs a high-side voltage, it is necessary to turn on the high-side gate 100-1 and turn off the low-side gate 100-2. Therefore, the high-side driver 200-1 turns on the high-side gate 100-1 by turning off the transistor 201-1 and setting the gate-source of the high-side gate 100-1 to the same potential. In this state, since no current flows through the resistance element 203-1, the power consumption in the high side driver 200-1 is ideally zero. On the other hand, the low-side driver 200-2 turns off the low-side gate 100-2 by turning on the transistor 201-2 and setting the gate-source between the low-side gate 100-2 to -5V. In this state, a current flows through the resistance element 203-2. At this time, the voltage drop at the resistance element 203-2 is 5V, and the current value is 2.5A. Therefore, power consumption that occurs instantaneously can be suppressed to about 12.5 W.

  Next, an operation when the switching amplifier 121a outputs a low-side voltage (ground ground voltage 0 V) will be described with reference to FIG. 12B.

  When the switching amplifier 121a outputs a low side voltage, it is necessary to turn on the low side gate 100-2 and turn off the high side gate 100-1. Therefore, the low-side driver 200-2 turns on the low-side gate 100-2 by turning off the transistor 201-2 to make the gate-source of the low-side gate 100-2 have the same potential. In this state, since no current flows through the resistance element 203-2, the power consumption in the low-side driver 200-2 is ideally zero. On the other hand, the high side driver 200-1 turns off the high side gate 100-1 by turning on the transistor 201-1 and setting the gate-source between the high side gate 100-1 to -5V. In this state, a current flows through the resistance element 203-1. However, at this time, since the output terminal OUT connected to one end of the resistance element 203-1 is 0 V, the voltage drop at the resistance element 203-1 is 5 V and the current value is 2.5 V. Therefore, power consumption that occurs instantaneously can be suppressed to about 12.5 W.

  As described above, the switching amplifier 121a shown in FIG. 11 uses the source (output terminal OUT) of the high-side gate 100-1 as a power source, thereby reducing the voltage drop in the resistance element 203-1, and reducing power consumption. Can be reduced.

(Second Modification of Switching Amplifier 121)
FIG. 13 is a diagram illustrating a second modification of the switching amplifier 121 as a switching amplifier 121b. FIG. 13 also shows a filter 124 and a load (antenna) 14.

  In the switching amplifier 121b illustrated in FIG. 13, the configurations of the high-side driver 200-1 and the low-side driver 200-2 are different from those of the switching amplifier 121a illustrated in FIG.

  Specifically, the high side driver 200-1 illustrated in FIG. 13 includes an inverter array (relay amplifier) 205-1 in which a plurality of inverters are cascade-connected in addition to the configuration of the high side driver 200-1 illustrated in FIG. , A diode 206-1 and a capacitor 207-1. In the present embodiment, an example in which the charged amount of capacitor 207-1 is 5V will be described.

  The inverter train 205-1 amplifies the voltage at the node between the resistance element 203-1 and the transistor 201-1 and outputs the amplified voltage as a first control signal. Note that the high-potential side power supply terminal of the inverter train 205-1 is connected to the source (output terminal OUT) of the high-side gate 100-1, and the low-potential side power supply terminal of the inverter train 205-1 is connected to the diode 206-1. Connected to the anode. The cathode of the diode 206-1 is connected to a node between the resistance element 203-1 and the transistor 201-1. One end of the capacitor 207-1 is connected to the high potential side power supply terminal of the inverter row 205-1 and the other end of the capacitor 207-1 is connected to the low potential side power supply terminal of the inverter row 205-1.

  Here, the high-side driver 200-1 shown in FIG. 13 increases the resistance value of the resistance element 203-1 while maintaining high-speed operation by reducing the size of the first stage inverter of the inverter row 205-1. Can do. If the resistance value of the resistance element 203-1 is increased, the amount of current flowing through the resistance element 203-1 is reduced when the transistor 201-1 is on, so that an increase in power consumption is further suppressed.

  Further, the high-side driver 200-1 shown in FIG. 13 includes the diode 206-1, so that the voltage of the input terminal of the high-side driver 200-1 (that is, the gate of the transistor 201-1) is lower than the ground voltage 0V. You can avoid that.

  Note that in the high-side driver 200-1 illustrated in FIG. 13, when the transistor 201-1 is turned on, the capacitor 207-1 is charged by the diode 206-1 and the transistor 201-1 is turned off. In this case, electric power is supplied to the inverter train 205-1 by the electric charge stored in the capacitor 207-1.

  On the other hand, the low-side driver 200-2 shown in FIG. 13 further includes an inverter array (relay amplifier) 205-2 in which a plurality of inverters are cascade-connected in addition to the configuration of the low-side driver 200-2 shown in FIG. FIG. 13 further shows a power supply 206-2 that generates a power supply voltage of −5V.

  The inverter row 205-2 amplifies the voltage at the node between the resistance element 203-2 and the transistor 201-2 and outputs the amplified voltage as a second control signal. Note that the high potential side power supply terminal of the inverter array 205-2 is connected to the ground, and the low potential side power supply terminal of the inverter array 205-2 is connected to the power supply 206-2 that generates a power supply voltage of −5V. .

  Here, the low-side driver 200-2 shown in FIG. 13 can increase the resistance value of the resistance element 203-2 while maintaining high-speed operation by reducing the size of the first stage inverter of the inverter row 205-2. it can. If the resistance value of the resistance element 203-2 is increased, the amount of current flowing through the resistance element 203-2 is reduced when the transistor 201-2 is turned on, so that an increase in power consumption is further suppressed.

  Next, the operation of the switching amplifier 121b will be described with reference to FIGS. 14A and 14B.

  First, the operation when the switching amplifier 121b outputs the high-side voltage (power supply voltage 30V of the power supply 101-1) will be described with reference to FIG. 14A.

  When the switching amplifier 121b outputs a high-side voltage, it is necessary to turn on the high-side gate 100-1 and turn off the low-side gate 100-2. Therefore, the high-side driver 200-1 turns on the high-side gate 100-1 by turning off the transistor 201-1 and setting the gate-source of the high-side gate 100-1 to the same potential. At this time, electric power is supplied to the inverter train 205-1 by the electric charge of 5V stored in the capacitor 207-1. In this state, no current flows through the resistance element 203-1 and the diode 206-1, and the power consumption in the inverter train 205-1 is as low as about the state transition loss (fCV ^ 2). Therefore, the power consumption in the high side driver 200-1 can be kept low. On the other hand, the low-side driver 200-2 turns off the low-side gate 100-2 by turning on the transistor 201-2 and setting the gate-source between the low-side gate 100-2 to -5V. In this state, as described with reference to FIG. 12A, the power consumption of the resistance element 203-2 is kept low. Further, as described above, the power consumption of the resistance element 203-2 can be further reduced by reducing the initial stage inverter size of the inverter row 205-2 and increasing the resistance value of the resistance element 203-2.

  Next, with reference to FIG. 14B, an operation when the switching amplifier 121b outputs a low-side voltage (ground ground voltage 0 V) will be described.

  When the switching amplifier 121b outputs a low side voltage, it is necessary to turn on the low side gate 100-2 and turn off the high side gate 100-1. Therefore, the low-side driver 200-2 turns on the low-side gate 100-2 by turning off the transistor 201-2 to make the gate-source of the low-side gate 100-2 have the same potential. In this state, no current flows through the resistance element 203-2, and power consumption in the inverter train 205-2 is as low as about the state transition loss (fCV ^ 2). Therefore, the power consumption in the low side driver 200-2 can be kept low. On the other hand, the high side driver 200-1 turns off the high side gate 100-1 by turning on the transistor 201-1 and setting the gate-source between the high side gate 100-1 to -5V. In this state, a current flows through the resistance element 203-1. However, at this time, as described with reference to FIG. 12B, the power consumption of the resistance element 203-1 can be kept low. Further, as described above, the power consumption of the resistance element 203-1 can be further reduced by reducing the size of the first stage inverter of the inverter row 205-1 and increasing the resistance value of the resistance element 203-1.

  As described above, the switching amplifier 121b shown in FIG. 13 uses the source (output terminal OUT) of the high-side gate 100-1 as a power source, thereby reducing the voltage drop in the resistance element 203-1, and reducing the power consumption. Can be reduced. Furthermore, since the switching amplifier 121b shown in FIG. 13 includes the inverter arrays 205-1 and 205-2, the resistance values of the resistance elements 203-1 and 203-2 can be increased, thereby further reducing power consumption. can do.

(Third Modification of Switching Amplifier 121)
FIG. 15 is a diagram illustrating a third modification of the switching amplifier 121 as a switching amplifier 121c. FIG. 15 also shows the filter 124 and the load (antenna) 14.

  In the switching amplifier 121c illustrated in FIG. 15, the configurations of the high-side driver 200-1 and the low-side driver 200-2 are different from those of the switching amplifier 121a illustrated in FIG.

  Specifically, the high side driver 200-1 shown in FIG. 15 includes an inverter array (relay amplifier) 205-1 in which a plurality of inverters are cascade-connected in addition to the configuration of the high side driver 200-1 shown in FIG. Further prepare. A DC-DC converter 400 is provided outside the switching amplifier 121. In the present embodiment, a case where the DC-DC converter 400 generates an output voltage of 5 V will be described as an example.

  The inverter train 205-1 amplifies the voltage at the node between the resistance element 203-1 and the transistor 201-1 and outputs the amplified voltage as a first control signal. The high potential side power supply terminal of the inverter row 205 is connected to the source (output terminal OUT) of the high side gate 100-1 and one output terminal of the DC-DC converter 400, and the low potential side of the inverter row 205-1. The power supply terminal is connected to the other output terminal of the DC-DC converter 400.

  The high side driver 200-1 shown in FIG. 15 can improve the stability of the power supply by supplying power from the DC-DC converter 400. In addition, about DC-DC converter 400, since a well-known structure can be utilized, the description is abbreviate | omitted.

  Here, the high-side driver 200-1 shown in FIG. 15 increases the resistance value of the resistance element 203-1 while maintaining high-speed operation by reducing the size of the first stage inverter of the inverter row 205-1. Can do. If the resistance value of the resistance element 203-1 is increased, the amount of current flowing through the resistance element 203-1 is reduced when the transistor 201-1 is on, so that an increase in power consumption is further suppressed.

  The low-side driver 200-2 illustrated in FIG. 15 is the same as the low-side driver 200-2 illustrated in FIG.

(Fourth modification of the switching amplifier 121)
FIG. 16 is a diagram illustrating a fourth modification of the switching amplifier 121 as a switching amplifier 121d. FIG. 16 also shows a filter 124 and a load (antenna) 14.

  The switching amplifier 121d illustrated in FIG. 16 includes, as compared with the switching amplifier 121c illustrated in FIG. 15, a low-potential-side power supply terminal of the inverter array 205-1 and a node between the resistance element 203-1 and the transistor 201-1. In addition, a diode 206-1 is further provided. Since the other configuration and operation of the switching amplifier 121d are the same as those of the switching amplifier 121c, description thereof is omitted.

  The switching amplifier 121d shown in FIG. 16 can achieve the same effect as the switching amplifier 121c shown in FIG. Further, the switching amplifier 121d shown in FIG. 16 includes the diode 206-1, thereby avoiding that the voltage of the input terminal of the high-side driver 200-1 (that is, the gate of the transistor 201-1) is lower than the ground voltage 0V. can do.

  The low-side driver 200-2 provided in the above-described switching amplifiers 121a to 121d may or may not include the inverter row 205-2. In the switching amplifiers 121a to 121d, general amplifiers may be used instead of the inverter arrays 205-1 and 205-2.

<Embodiment 2>
FIG. 17 is a block diagram illustrating details of the wireless communication device 1d according to the second embodiment. The wireless communication device 1d illustrated in FIG. 17 further includes a power source 218 that generates a DC signal, as compared with the wireless communication device 1 illustrated in FIG.

  In the baseband processing unit 11, the OE conversion unit 118 superimposes the ΔΣ modulation signal and the DC signal from the power supply 218 and converts the signal into an optical signal. In the overhanging radio unit 12, the OE conversion unit 122 converts the optical signal transmitted from the baseband processing unit 11 through the optical cable 13 into a ΔΣ modulation signal and a DC signal. The overhanging radio unit 12 operates using the DC signal converted by the OE conversion unit 122 as a power source.

  As a result, the wireless communication device 1d does not need to provide a power source for the overhanging radio unit 12, so that the overhanging radio unit 12 can be further downsized.

(Modification of wireless communication device 1d)
FIG. 18 is a diagram illustrating a modification example of the wireless communication device 1d illustrated in FIG. 17 as a wireless communication device 1e. Compared with the wireless communication device 1d shown in FIG. 17, the wireless communication device 1e shown in FIG. 18 includes bias tees 219 and 220 instead of the OE conversion units 118 and 122, and an Ethernet cable 13a instead of the optical cable 13. Is provided.

  In the baseband processing unit 11, the bias tee (superimposing unit) 219 superimposes the ΔΣ modulation signal and the DC signal from the power supply 218 and outputs the superimposed signal. In the overhanging radio unit 12, the bias tee (separating unit) 220 separates the superimposed signal transmitted from the baseband processing unit 11 via the Ethernet cable 13a into a ΔΣ modulation signal and a DC signal and outputs them. The overhanging radio unit 12 operates using the DC signal separated by the bias tee 220 as a power source.

  Accordingly, the wireless communication device 1e does not need to provide a power source for the overhanging radio unit 12, and thus the overhanging radio unit 12 can be further downsized.

  As described above, the wireless communication apparatus according to the above embodiment uses the phase-synchronized ΔΣ modulator to modulate the amplitude signal γ included in the high-frequency signal in synchronization with the phase signal θ included in the high-frequency signal. doing. Thereby, the radio communication apparatus 1 according to the present embodiment can reduce the output current at the time of on / off transition of the switch element provided in the switching amplifier 121, and thus can reduce power consumption.

  Furthermore, the wireless communication apparatus 1 according to the present embodiment includes the phase-locked ΔΣ modulator 111 in the baseband processing unit 11 instead of the protruding wireless unit 12. Thereby, the wireless communication apparatus 1 according to the present embodiment can reduce the overhanging wireless unit 12 in size.

  In the related technology, in order to obtain a desired modulation accuracy, it is necessary to sufficiently increase the sampling frequency of the ΔΣ modulator with respect to the high-frequency signal. For example, in the configuration disclosed in Patent Document 3, it is necessary to set the sampling frequency of the ΔΣ modulator to about 10 times, preferably at least twice as high as the high frequency signal. As a result, the signal frequency transmitted by the means (for example, an optical module) for connecting the overhanging radio unit (12) and the baseband processing unit (11) has increased. As a result, there are problems such as an increase in the cost of the optical module and an increase in power consumption. On the other hand, such a problem does not occur in the wireless communication device 1 according to the present embodiment.

<Embodiment 3>
FIG. 19 is a block diagram of a configuration example of the wireless communication system 2 according to the third embodiment. As described above, since the wireless communication device 1 operates in synchronization with the clock signal having the frequency corresponding to the carrier frequency (the output signal of the pulse phase signal generator 1113), the baseband processing is performed on the carrier frequency of the overhanging radio unit 12. It is possible to determine by controlling directly from the unit 11. Therefore, the radio communication system 2 according to the present embodiment has a plurality of radio frequencies (frequency of high-frequency signals) assigned to each of the plurality of radio communication devices 1 and each of the plurality of radio communication devices 1. The average traffic capacity is improved by controlling at least one of a plurality of bandwidths (band resources) allocated. This will be specifically described below.

  The wireless communication system 2 illustrated in FIG. 19 includes n (n is an integer of 2 or more) wireless communication devices 1 (hereinafter also referred to as wireless communication devices 1_1 to 1_n) and a control unit 21. Each of the wireless communication devices 1_1 to 1_n includes baseband processing units 11_1 to 11_n and overhanging wireless units 12_1 to 12_n.

  The wireless communication system 2 employs a C-RAN (Cloud Radio Access Network or Centralized Radio Access Network) wireless communication technique. Specifically, the control unit 21 and the baseband processing units 11_1 to 11_n are arranged in the vicinity (concentrated arrangement). Thereby, in the wireless communication system 2, since some components are shared by the plurality of baseband processing units, the cost can be reduced as compared with the case where the plurality of baseband processing units are arranged in a distributed manner. In addition, since the radio communication system 2 can control baseband resources across cells, a plurality of baseband processing units are arranged in a distributed manner in a cell where baseband processing units and overhanging radio units exist. Thus, the traffic capacity can be improved and the load on the core network (not shown) can be reduced as compared with the case where the resource control is closed. That is, the radio communication system 2 according to the present embodiment can exert a general advantageous effect in the C-RAN system. Hereinafter, the control unit 21 and the baseband processing units 11_1 to 11_n are collectively referred to as a centralized arrangement baseband processing unit 20.

  The control unit 21 uses a plurality of radio frequencies assigned to each of the radio communication devices 1_1 to 1_n and radio communication based on the data communication amount of each of the radio communication devices 1_1 to 1_n, information on the frequency usage status, and the like It controls at least one of a plurality of bandwidths allocated to each of the devices 1_1 to 1_n.

  For example, the control unit 21 sets a radio frequency assigned to a wireless communication device (for example, a wireless communication device that is frequently accessed from a mobile phone) having a data communication amount of a predetermined value or more among the wireless communication devices 1_1 to 1_n. The wireless communication apparatus switches to a wireless frequency assigned to a wireless communication apparatus whose data communication amount is less than a predetermined value (for example, a wireless communication apparatus with little access from a mobile phone). Alternatively, the control unit 21 assigns a radio frequency assigned to a radio communication device having a data communication amount equal to or greater than a predetermined value among the radio communication devices 1_1 to 1_n to any of the plurality of radio communication devices 1_1 to 1_n. Switch to an unassigned radio frequency. As a result, the radio communication system 2 can switch the radio frequency of the radio communication device where access is concentrated to a radio frequency that is rarely used by other radio communication devices. Can be improved.

  In addition, the control unit 21 widens the bandwidth allocated to the wireless communication devices having a data communication amount equal to or greater than a predetermined value among the wireless communication devices 1_1 to 1_n, and performs data communication among the wireless communication devices 1_1 to 1_n. A bandwidth allocated to a wireless communication apparatus whose amount is less than a predetermined value is reduced. As a result, the wireless communication system 2 can use the bandwidth efficiently, so that the average traffic capacity can be improved. Furthermore, since the wireless communication system 2 reduces the bandwidth when the amount of data communication is small, an increase in power consumption can be suppressed.

  FIG. 20 is a diagram schematically showing the radio communication system 2 shown in FIG. In the example of FIG. 20, the overhang radio units 12_1 and 12_2 are provided in the area of the cell A, and the overhang radio units 12_3 and 12_4 are provided in the area of the cell B. Each of the cells A and B may be an outdoor area or an indoor area (for example, each floor in a building). As shown in FIG. 20, in the radio communication system 2 according to the present embodiment, not only the radio frequency and bandwidth control between radio communication devices belonging to the same cell, but also the radio frequency between radio communication devices belonging to different cells. It can be seen that bandwidth control is performed.

  Each wireless communication device 1 provided in the wireless communication system 2 may make the filter 124 provided in the overhanging radio unit 12 a variable filter in consideration of switching of assigned radio frequency and bandwidth. preferable. The variable filter is, for example, a filter that can be switched or changed using any one of a plurality of radio frequencies as a pass band. Or a variable filter is a filter which can change or change a pass bandwidth, for example. Furthermore, the variable filter is a filter that can switch or change both the radio frequency and the pass bandwidth.

  FIG. 21 is a diagram illustrating a specific example of each wireless communication device 1 provided in the wireless communication system 2 as a wireless communication device 1f. The wireless communication device 1f shown in FIG. 21 includes selection circuits 130 and 131 and filters 124a and 124b as variable filters, instead of the filter 124, as compared with the wireless communication device 1 shown in FIG.

  The selection circuit 130 and the filter 124 a are provided in the subsequent stage of the switching amplifier 121. The filter 124a is an aggregate of a plurality of filters having different pass bands. The selection circuit 130 selects a filter corresponding to the assigned radio frequency and bandwidth from among a plurality of filters included in the filter 124a. Further, the selection circuit 131 and the filter 124b are provided at the subsequent stage of the low noise amplifier 125. The filter 124b is an aggregate of a plurality of filters having different pass bands. The selection circuit 131 selects a filter corresponding to the assigned radio frequency and bandwidth from the plurality of filters included in the filter 124b.

  The other configuration and operation of the wireless communication device 1f shown in FIG. 21 are the same as those of the wireless communication device 1 shown in FIG.

  As described above, the radio communication system 2 according to the present embodiment includes a plurality of radio frequencies (frequency of high-frequency signals) assigned to each of the plurality of radio communication devices 1 and each of the plurality of radio communication devices 1. By controlling at least one of a plurality of bandwidths (band resources) allocated to the average traffic capacity, it is possible to improve the average traffic capacity or suppress the increase in power consumption.

  Moreover, the radio | wireless communications system 2 concerning this Embodiment is provided with the some radio | wireless communication apparatus 1 which operate | moves synchronizing with the clock signal of the frequency according to the carrier frequency as mentioned above. Thereby, the radio communication system 2 according to the present embodiment can quickly change the radio frequency and bandwidth allocated to each radio communication device 1 simply by changing the carrier frequency. Such control is performed by wireless communication provided with a plurality of radio communication devices that have a high-frequency circuit limited in frequency (for example, an amplifier configured by an analog circuit such as a distributed constant line, a capacitive element, an inductor, etc.) and has a radio unit. Not possible with the system. Even if a plurality of amplifiers limited in frequency are provided in each overhanging radio unit and the radio frequency is made variable, circuit reconfiguration (for example, in order to reconfigure the band-limiting filter characteristics in the baseband, The service must be temporarily interrupted due to reconfiguration with the restart of Field Programmable Gate Array (FPGA).

  Although the case where the wireless communication system 2 includes a plurality of wireless communication devices 1 has been described as an example in the present embodiment, the present invention is not limited to this. The wireless communication system 2 can be appropriately changed to a configuration including a plurality of wireless communication devices 1a to 1e instead of the wireless communication device 1. In addition, even when any one of the wireless communication devices 1a to 1e is used, each overhanging wireless unit is considered in consideration of switching of the assigned radio frequency and bandwidth as in the case where the wireless communication device 1 is used. 12 is preferably a variable filter.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2012-281150 for which it applied on December 25, 2012, and takes in those the indications of all here.

1, 1a, 1b, 1c, 1d, 1e, 1f Wireless communication device 1_1 to 1_n Wireless communication device 2 Wireless communication system 11 Baseband processing unit 11_1 to 11_n Baseband processing unit 12 Overhang radio unit 12_1 to 12_n Overhang radio unit 13 Optical cable 13a Ethernet cable 14 Antenna 20 Centrally arranged baseband processing unit 21 Control unit 100-1 High side gate 100-2 Low side gate 101-1 202-1, 202-2, 204-2 Power supply 111 Phase-synchronous ΔΣ modulator 112 Baseband control unit 113, 211, 225 Modulator 114 Multiplexer 115 Filter 116 Peak suppressor 117, 123 SerDes unit 118, 122 OE conversion unit 119, 217, 224 Demodulator 121, 121a, 121b, 121c , 121d switching amplifier 124, 124a, 124b filter 125 low noise amplifier 126 mixer 127 AD converter 128 automatic gain control filter 129 separator 130, 131 selection circuit 200-1 high side driver 200-2 low side driver 201-1, 201- 2 Transistors 203-1 and 203-2 Resistance elements 205-1 and 205-2 Inverter train 206-1 Diode 207-1 Capacitor 212, 226 Up-converter 213, 227 Power amplifier 214, 221 Filter 215, 222 Low noise amplifier 216 223 Down converter 218 Power source 219, 220 Bias tee 400 DC-DC converter 1111 Amplitude detector 1112 Phase detector 1113 Pulse phase signal generator 11 14 ΔΣ modulator 1115 Mixer D1 Diode R1 Resistance element C1 Capacitor CMP1 Comparator AND1 AND circuit

Claims (29)

Baseband processing means for generating a high-frequency signal by modulating the baseband signal;
Phase-synchronous ΔΣ modulation means for ΔΣ modulating the high-frequency signal and outputting it as a ΔΣ modulation signal;
An overhanging radio unit that is formed separately from the baseband processing unit, amplifies the ΔΣ modulation signal, and wirelessly transmits the signal;
The phase-locked ΔΣ modulation means is
Amplitude detecting means for detecting the amplitude of the high-frequency signal and outputting the amplitude signal;
Phase detection means for detecting a phase of the high-frequency signal and outputting a phase signal;
Pulse phase signal generation means for generating a pulse phase signal of a pulse waveform based on the phase signal;
ΔΣ modulation means for ΔΣ modulating the amplitude signal in synchronization with the pulse phase signal;
Mixing means for mixing the output signal of the ΔΣ modulation means and the pulse phase signal to generate the ΔΣ modulation signal;
The overhanging radio means is
Have a switching amplifier that amplifies the ΔΣ modulation signal,
The switching amplifier is
A high-side amplifier and a low-side amplifier that respectively output first and second control signals corresponding to the ΔΣ modulation signal;
A high-side gate provided between a high-potential-side power supply and an external output terminal and controlled to be turned on / off based on the first control signal;
A low-side gate provided between a low-potential-side power supply and the external output terminal and controlled to be turned on and off complementarily with the high-side gate based on the second control signal,
The high-side amplifier is a wireless communication device having an input switching amplifier that uses the external output terminal as a power source . The overhanging radio means is
The wireless communication apparatus according to claim 1, further comprising a band-pass filter that extracts a desired high-frequency signal from the output of the switching amplifier.   The wireless communication apparatus according to claim 2, wherein the band pass filter is a filter capable of changing a pass band.   The radio communication apparatus according to claim 1, wherein the phase-synchronous ΔΣ modulation unit is provided in the baseband processing unit. The phase-synchronous ΔΣ modulation means is provided in the baseband processing means,
The wireless communication apparatus according to any one of claims 1 to 3, further comprising an optical cable that transmits the ΔΣ modulation signal output from the baseband processing means to the overhanging wireless means. The baseband processing means includes
First OE conversion means for converting the ΔΣ modulation signal output from the phase-synchronous ΔΣ modulation means into an optical signal;
The overhanging radio means is
6. The wireless communication apparatus according to claim 5, further comprising second OE conversion means for converting the optical signal transmitted from the baseband processing means via the optical cable into the ΔΣ modulation signal. The baseband processing means includes
A power supply for generating a DC signal;
The first OE conversion means superimposes the ΔΣ modulation signal and the direct current signal to convert them into an optical signal,
The second OE conversion means converts the optical signal transmitted from the baseband processing means via the optical cable into the ΔΣ modulation signal and the DC signal,
The wireless communication apparatus according to claim 6, wherein the overhanging radio unit operates using the DC signal converted by the second OE conversion unit as a power source. The phase-synchronous ΔΣ modulation means is provided in the baseband processing means,
The wireless communication apparatus according to any one of claims 1 to 3, further comprising an Ethernet cable that transmits the ΔΣ modulation signal output from the baseband processing means to the overhanging wireless means according to an Ethernet standard. The baseband processing means includes
A power supply for generating a DC signal;
Superimposing means that superimposes the ΔΣ modulation signal and the DC signal and outputs a superimposed signal; and
The overhanging radio means is
Separating means for separating and outputting the superimposed signal transmitted from the baseband processing means via the Ethernet cable into the ΔΣ modulation signal and the DC signal,
9. The wireless communication apparatus according to claim 8, wherein the overhanging radio unit operates using the DC signal separated by the separation unit as a power source. The ΔΣ modulation means generates an output signal having three or more output values,
The wireless communication apparatus according to claim 1, wherein the switching amplifier amplifies the ΔΣ modulation signal to a voltage level corresponding to a value of the ΔΣ modulation signal. The ΔΣ modulation means generates an output signal having a number of output values according to an external control signal,
The wireless communication apparatus according to claim 1, wherein the switching amplifier amplifies the ΔΣ modulation signal to a voltage level corresponding to a value of the ΔΣ modulation signal. The high side amplifier is
Further comprising a wireless communication apparatus according to any one of claims 1 to 11 a relay amplifier for amplifying and outputting the output of the input switching amplifier as the first control signal. The wireless communication device according to claim 12 , wherein the relay amplifier is an inverter train in which a plurality of inverters are cascade-connected. The high side amplifier is
A diode having an anode connected to the low-potential-side power supply terminal of the relay amplifier and a cathode connected to the output of the input switching amplifier;
14. The wireless communication device according to claim 12 , further comprising a capacitor provided between a low potential side power supply terminal of the relay amplifier and the external output terminal. A DC-DC converter;
The wireless communication device according to claim 12 or 13 , wherein a high potential side power supply terminal and a low potential side power supply terminal of the relay amplifier are respectively connected to two output terminals of the DC-DC converter. The high side amplifier is
The wireless communication device according to claim 15 , further comprising a diode having an anode connected to a low potential power supply terminal of the relay amplifier and a cathode connected to an output of the input switching amplifier. The input switching amplifier is
A first resistance element provided between the external output terminal and a control terminal of the high-side gate;
A first transistor provided between a voltage supply terminal to which a voltage for turning off the high-side gate is supplied and a control terminal of the high-side gate and controlled to be turned on / off based on the ΔΣ modulation signal; The wireless communication device according to any one of claims 1 to 16 , further comprising: A plurality of the wireless communication devices according to any one of claims 1 to 17 ,
Control means for controlling at least one of a plurality of high-frequency signal frequencies assigned to each of the plurality of wireless communication devices and a plurality of bandwidths assigned to each of the plurality of wireless communication devices. A wireless communication system further comprising: 19. The control unit according to claim 18 , wherein the control unit controls at least one of a frequency of the plurality of high-frequency signals and a plurality of bandwidths based on a data communication amount of each of the plurality of wireless communication devices. Wireless communication system. The control means determines the frequency of the high-frequency signal assigned to a wireless communication device having a data communication amount of a predetermined value or more among the plurality of wireless communication devices, and determines the data communication amount of the plurality of wireless communication devices. The wireless communication system according to claim 18 or 19 , wherein the frequency is switched to the frequency of the high-frequency signal assigned to a wireless communication device less than a predetermined value. The control means assigns the frequency of the high-frequency signal assigned to a wireless communication device having a data communication amount of a predetermined value or more among the plurality of wireless communication devices to any of the plurality of wireless communication devices. The wireless communication system according to claim 18 , wherein the wireless communication system is switched to a frequency that is not. The control means widens a bandwidth allocated to a wireless communication device having a data communication amount of a predetermined value or more among the plurality of wireless communication devices, and a data communication amount of the plurality of wireless communication devices is The radio | wireless communications system as described in any one of Claims 18-21 which narrows the bandwidth allocated with respect to the radio | wireless communication apparatus less than predetermined value. The radio communication system according to any one of claims 18 to 22 , wherein the control unit and the plurality of baseband processing units are arranged in the vicinity. In the baseband processing means,
Modulate baseband signal to generate high frequency signal,
Detecting the amplitude of the high-frequency signal to generate an amplitude signal;
Detecting a phase of the high-frequency signal to generate a phase signal;
Generate a pulse phase signal of a pulse waveform based on the phase signal,
ΔΣ modulation of the amplitude signal in synchronization with the pulse phase signal,
The result of ΔΣ modulation and the pulse phase signal are mixed to generate a ΔΣ modulation signal,
In the overhanging wireless means formed separately from the baseband processing means,
Amplifying the ΔΣ modulation signal;
A method of controlling a wireless communication device for wirelessly transmitting the amplified ΔΣ modulation signal ,
The switching amplifier that amplifies the ΔΣ modulation signal is
A high-side amplifier and a low-side amplifier that respectively output first and second control signals corresponding to the ΔΣ modulation signal;
A high-side gate provided between a high-potential-side power supply and an external output terminal and controlled to be turned on / off based on the first control signal;
A low-side gate provided between a low-potential-side power supply and the external output terminal and controlled to be turned on and off complementarily with the high-side gate based on the second control signal,
The wireless communication device control method , wherein the high-side amplifier includes an input switching amplifier that uses the external output terminal as a power source . Controlling at least one of a plurality of high-frequency signal frequencies allocated to each of the plurality of radio communication devices and a plurality of bandwidths allocated to each of the plurality of radio communication devices. Item 25. A method for controlling a wireless communication device according to Item 24 . 26. The wireless communication device according to claim 25 , wherein at least one of a frequency of the plurality of high-frequency signals and a plurality of bandwidths are controlled based on a data communication amount of each of the plurality of wireless communication devices. Control method. The frequency of the high-frequency signal assigned to a wireless communication device having a data communication amount greater than or equal to a predetermined value among the plurality of wireless communication devices, and a wireless having a data communication amount less than a predetermined value among the plurality of wireless communication devices 27. The method of controlling a wireless communication apparatus according to claim 25 or 26 , wherein the frequency of the high-frequency signal assigned to the communication apparatus is switched. Switching the frequency of the high frequency signal data traffic among the plurality of wireless communication devices is allocated to a predetermined value or more wireless communication devices, the Tei no frequency assigned to any of said plurality of wireless communication devices 27. A method of controlling a wireless communication apparatus according to claim 25 or 26 . Widening the bandwidth allocated to a wireless communication device having a data communication amount greater than or equal to a predetermined value among the plurality of wireless communication devices, and wireless communication having a data communication amount less than a predetermined value among the plurality of wireless communication devices The method for controlling a wireless communication apparatus according to any one of claims 25 to 28 , wherein a bandwidth allocated to the communication apparatus is narrowed.

Images