JP5974792B2 - Electromagnetic circuit cooperation analysis program, electromagnetic circuit cooperation analysis apparatus, and electromagnetic circuit cooperation analysis method - Google Patents

Description

  The present invention relates to an electromagnetic field circuit linkage analysis program, an electromagnetic field circuit linkage analysis apparatus, and an electromagnetic field circuit for causing a computer to execute a linkage analysis combining an electromagnetic wave analysis method in a finite difference time domain and a circuit analysis method based on a transient electrical circuit analysis. It is related to the linkage analysis method.

  Conventionally, as a simulation method for analyzing an electromagnetic field of an electronic circuit, an FDTD (Finite-difference time-domain) method using an electromagnetic wave analysis simulator and a SPICE (Simulation Program with Integrated Circuit Emphasis) using a circuit analysis simulator There is known a method of linking with circuit simulation such as a simulation program with an emphasis on.

  The FDTD method is a method of electromagnetic field analysis that simulates the transient behavior of electromagnetic waves. The Maxwell differential equation, which is the basic equation of electromagnetic waves, is differentiated between time and space, and the electromagnetic field in the analysis space is updated temporally. In this way, the time response of the output point is obtained. SPICE is a transient electric circuit analysis tool developed by the University of California, Berkeley, and analyzes the operation of circuit elements such as integrated circuits arranged on a printed circuit board simultaneously with electromagnetic field analysis.

  The FDTD method using an electromagnetic wave analysis simulator can obtain a wave source, obtain an electric field and a magnetic field alternately while advancing the time, and assign a circuit to the differentiated cell for analysis. Then, a magnetic field is applied to a circuit analysis simulator such as SPICE. The circuit analysis simulator receives this magnetic field as a current value and performs circuit analysis. Then, the result of the circuit analysis is returned as a voltage value to the electromagnetic wave analysis simulator using the FDTD method. The electromagnetic wave analysis simulator further analyzes the magnetic field based on the electric field.

By repeating these processes in cooperation, the behavior of the electromagnetic wave is required.
FIG. 1 is a diagram showing an example of the first prior art.
In FIG. 1, (A) is an example of a three-terminal electromagnetic field equivalent circuit of a base [B], a collector [C], and an emitter [E], and (B) is an electromagnetic field equivalent circuit of (A). (C) shows the electromagnetic field equivalent circuit of (A) with a SPICE solver.

  Here, the circuit branch as shown in FIG. 1B is a kind of branch of the electric field lattice of the FDTD model, and the electric field calculated by the SPICE solver is set. The electromagnetic field equivalent circuit is a SPICE netlist, in which a current calculated by the FDTD method is set. With such a three-terminal electromagnetic field equivalent circuit, a complex circuit element unit is calculated with a SPICE solver, and the result is taken into the FDTD solver to calculate the FDTD-SPICE linkage analysis of the entire circuit. (For example, refer nonpatent literature 1.).

FIG. 2 is a diagram showing an example of the second prior art.
In FIG. 2, (A) is an example of an N-terminal network in which a ground plane exists, (B) is an N-terminal network of (A) represented by an FDTD solver, and (C) is The N terminal network of (A) is represented by a SPICE solver.

  When an electronic device to be analyzed has a PCB (Printed Circuit Board) ground plane, a linkage method using N two-terminal Thomas equivalent circuits for an N-terminal network is known. (For example, see Non-Patent Document 2). In the case of an N-terminal network as shown in FIG. 2A, the potential difference between the terminal of the network and the ground plane directly below is set as the reference voltage at this terminal.

A. Thomas, et al .: The use of SPICE lumped circuits as sub-grid models for FDTD analysis, IEEE Microwave and Guided Wave Letters, vol.4, pp141-143 (1994) Hideki Asai, et al .: Electronic circuit simulation technique, Science and Technology Publishing, pp255-257

FIG. 3 is a diagram showing a case where the first prior art is extended to an N-terminal electromagnetic field equivalent circuit.
In the case of the first prior art, as shown in FIG. 3A, the three-terminal electromagnetic field equivalent circuit can be expanded to an N-terminal electromagnetic field equivalent circuit. Here, N is a natural number of 4 or more. At that time, the circuit branch on the FDTD lattice may be connected to one reference lattice point (reference lattice point: reference terminal).

However, the maximum number of circuit branches that can be connected to one lattice point is five as shown in FIG. 3B, considering the conductors connected to the terminals in the positive and negative directions of the xyz axis.
FIG. 4 is a diagram showing an FDTD model (A) and a SPICE model (B) of a six-terminal electromagnetic field equivalent circuit.

Since the number of terminals that can be connected to one reference lattice point is five, an FDTD model of a six-terminal electromagnetic field equivalent circuit can be configured as shown in FIG.
However, there is a problem that it is not possible to perform a cooperative analysis of a general N-terminal network exceeding the 6-terminal network.

FIG. 5 is a diagram showing an FDTD model (A) and a SPICE model (B) of an 8-terminal electromagnetic field equivalent circuit.
Since the number of terminals that can be connected to one reference lattice point is five, as shown in FIG. 5A, an FDTD model of an 8-terminal electromagnetic field equivalent circuit cannot be configured.

FIG. 6 is a diagram illustrating an example of a circuit network having no ground plane.
As shown in FIG. 6, since there is no ground plane directly under the device, the potential difference between the terminal of the network and the ground plane directly below cannot be set as a reference voltage at the terminal, and there is no ground plane. There was a problem that the N terminal network could not be linked and analyzed.

  The present invention has been made in view of the actual situation as described above. When performing electromagnetic field circuit linkage analysis, the electric field grid point corresponding to the reference terminal is connected by a conductor and expanded to a plurality of electric field grid points. An object of the present invention is to provide an electromagnetic field circuit cooperation analysis program, an electromagnetic field circuit cooperation analysis apparatus, and an electromagnetic field circuit cooperation analysis method that can perform cooperation analysis of multi-terminal circuits even when there is no ground plane.

  In one plan, a circuit corresponding to the position of the terminal based on the device position information indicating the position of the device model corresponding to the electronic circuit to be analyzed and the terminal position information indicating the position of the terminal of the device model. A circuit based on electromagnetic field analysis and circuit information based on electromagnetic field information including the circuit branch and the reference conductor is generated by generating a branch on a lattice and connecting the circuit branch based on a predetermined rule. It is characterized by executing a linkage analysis with the analysis.

  According to the present invention, since there is no need to connect the electric field grid branch corresponding to the equivalent circuit to the ground plane, there is an effect that the cooperative analysis is possible even in an N-terminal network without a ground plane.

It is a figure which shows the example of a 1st prior art. It is a figure which shows the example of the 2nd prior art. It is a figure which shows the case where the 1st prior art is extended to the electromagnetic field equivalent circuit of N terminal. It is a figure which shows the FDTD model (A) and SPICE model (B) of a 6 terminal electromagnetic field equivalent circuit. It is a figure which shows the FDTD model (A) and SPICE model (B) of an electromagnetic equivalent circuit of 8 terminals. It is a figure which shows the example of the network without a ground plane. It is a figure which shows the FDTD model of an electromagnetic field equivalent circuit of 8 terminals. It is a figure which shows the FDTD model (A) and SPICE model (B) of the network without a ground plane. It is a figure explaining an example of functional composition of an electromagnetic field circuit cooperation analysis device to which this embodiment is applied. It is a flowchart which shows the flow of the cooperation data generation process performed in the electromagnetic field circuit cooperation analysis apparatus to which this Embodiment is applied. 6 is a diagram for explaining a configuration of a linkage information storage unit 901. FIG. 6 is a diagram illustrating a configuration example of a cooperation information storage unit 901. FIG. It is a figure for demonstrating the flow of the specific example 1 of a cooperation data generation process. It is a figure for demonstrating the flow of the specific example 2 of a cooperation data generation process. It is a figure for demonstrating the flow of the specific example 3 of a cooperation data generation process. It is a figure for demonstrating the flow of the specific example 4 of a cooperation data generation process. It is a figure for demonstrating the flow of the specific example 5 of a cooperation data generation process. It is a figure for demonstrating the flow of the specific example 6 of a cooperation data generation process. It is a figure which shows the structural example of the electromagnetic field information added to the cooperation electromagnetic field information storage part 905. FIG. It is a figure which shows the structural example of the circuit information added to the cooperation circuit information storage part 906. FIG. It is a figure for demonstrating making a virtual terminal into a reference | standard. It is a figure which shows the device area definition example 1. FIG. 6 is a diagram illustrating a wiring example 1 of a device region definition example 1. FIG. It is a figure which shows the example 2 of a wiring of the device area definition example 1. FIG. FIG. 10 is a diagram illustrating a wiring example 3 of the device region definition example 1; It is a figure which shows the device area definition example 2. FIG. 10 is a diagram illustrating a wiring example 1 of a device region definition example 2. FIG. It is a figure which shows the example 2 of wiring of the device area definition example 2. FIG. It is a figure which shows the wiring example 3 of the device area definition example 2. FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
This embodiment is realized by incorporating an electromagnetic field circuit cooperation analysis program in an information processing apparatus such as a personal computer, and the information processing apparatus executes the electromagnetic field circuit cooperation analysis program as an electromagnetic field circuit cooperation analysis apparatus. The

FIG. 7 is a diagram showing an FDTD model of an 8-terminal electromagnetic field equivalent circuit.
The concept of the present invention will be described with reference to FIG.
In order to develop the reference grid point into a plurality of grid points, a virtual conductor is developed at the device position by a predetermined algorithm described later. The electric field branch that should share the reference grid point is connected to one of the developed reference grid points.

  Since the potentials at the plurality of reference lattice points are short-circuited by the conductor developed at the device position, the potentials can be approximately regarded as a single potential at a single lattice point. Since the current flowing from the device terminal to the device portion flows in a closed manner in the conductor portion developed at the device position, it can be regarded as a current that flows approximately to a single lattice point.

FIG. 8 is a diagram showing an FDTD model (A) and a SPICE model (B) of a network without a ground plane.
As shown in FIG. 8, since it is not necessary to connect the electric field grid branch corresponding to the equivalent circuit to the ground plane, it is possible to perform a collaborative analysis even in an N-terminal network without a ground plane. Therefore, it is possible to simulate a device having 7 terminals or more even if the device has no ground plane.

FIG. 9 is a diagram illustrating an example of a functional configuration of an electromagnetic field circuit cooperation analysis apparatus to which the present embodiment is applied.
In FIG. 9, the electromagnetic field circuit cooperation analysis apparatus 900 includes a cooperation data generation unit 910, a control unit 920, an FDTD solver 930, and a circuit simulator 940. Further, the electromagnetic field circuit cooperation analysis apparatus 900 can refer to the cooperation information storage unit 901, the electromagnetic field information storage unit 902, the circuit information storage unit 903, and the control information storage unit 904.

  The linkage data generation unit 910 generates a reference conductor for short-circuiting the electromagnetic field equivalent circuit, the electric field branch (circuit branch) corresponding to the equivalent circuit, and the reference lattice point from the correspondence information between the electric field grid point and the network terminal. And it adds to the circuit information memorize | stored in the circuit information memory | storage part 903, It memorize | stores in the cooperation circuit information memory | storage part 906, It adds to the electromagnetic field information memorize | stored in the electromagnetic field information memory | storage part 902, and cooperates electromagnetic field information memory | storage part Store in 905. Details of the generation of the reference conductor by the cooperation data generation unit 910 will be described later.

  The cooperation information storage unit 901 stores cooperation information such as device position information, terminal position information, and terminal name information. The electromagnetic field information storage unit 902 stores electromagnetic field information such as electric field grid definition, dielectric definition, conductor definition, and circuit branch definition. The circuit information storage unit 903 stores a SPICE netlist that is connection information of circuit elements to be subjected to circuit analysis by the circuit simulator 940. The control information storage unit 904 starts a time when the analysis of the electronic circuit by the electromagnetic field circuit cooperation analysis apparatus 900 is started, an end time when the analysis of the electronic circuit by the electromagnetic field circuit cooperation analysis apparatus 900 ends, and an output Control information such as information is stored.

  The FDTD solver 930 provides a wave source to alternately obtain an electric field E and a magnetic field H, and provides a magnetic field as an analysis result to the circuit simulator 940 via the control unit 920. The circuit simulator 940 performs circuit analysis with the applied magnetic field H as the current value I, and returns the electric field E as the voltage value V to the FDTD solver 930. While repeating this processing between the FDTD solver 930 and the circuit simulator 940, the behavior of the electromagnetic wave of the electronic circuit is obtained. Thus, for example, analysis of a printed board is performed by linking two simulations.

  The control unit 920 includes an input unit 921, a data exchange unit 922, and an output unit 923, and controls analysis processing by the electromagnetic field circuit cooperation analysis apparatus 900. The input unit 921 reads the electromagnetic field information and the circuit information from the cooperative electromagnetic field information storage unit 905 and the cooperative circuit information storage unit 906 as appropriate, and inputs them to the FDTD solver 930 and the circuit simulator 940. The data exchange unit 922 transfers each data between the FDTD solver 930 and the circuit simulator 940. Then, the output unit 923 outputs the analysis result 907 by the electromagnetic field circuit cooperation analysis apparatus 900.

  With the above configuration, the electromagnetic field circuit linkage analysis apparatus 900 has an abnormal analysis result (waveform) 907 when there is no ground plane in a four-terminal network, and is automatically generated when there is no ground plane in a circuit network of five terminals or more. It is possible to eliminate problems in analysis processing in the conventional cooperative analysis device such as error termination due to inability.

FIG. 10 is a flowchart showing the flow of the linkage data generation process executed in the electromagnetic field circuit linkage analysis apparatus to which the present embodiment is applied.
First, in step S1001, the cooperation data generation unit 910 generates and arranges circuit branches based on the device position and terminal position information stored in the cooperation information storage unit 901, generates a reference conductor, and performs wiring. Specific examples of circuit branch generation, placement, reference conductor generation, and wiring will be described later with reference to FIGS.

  Next, in step S1002, the cooperation data generation unit 910 adds the circuit branch and the conductor generated by the placement and routing processing in step S1001 to the electromagnetic field information stored in the electromagnetic field information storage unit 902, and the cooperation electromagnetic field information. The data is output to the storage unit 905. A specific example will be described later with reference to FIG.

  In step S1003, the cooperation data generation unit 910 adds an electric field equivalent circuit to the circuit information stored in the circuit information storage unit 903 based on the terminal name information stored in the cooperation information storage unit 901, and the cooperation circuit The information is output to the information storage unit 906. A specific example will be described later with reference to FIG.

Here, the cooperation information storage unit 901 will be described.
FIG. 11 is a diagram for explaining the configuration of the cooperation information storage unit 901.
As shown in FIG. 11, the cooperation information stored in the cooperation information storage unit 901 is defined as a device region whose device position is a rectangular parallelepiped on the electric field grid. In the device region, circuit branches and reference conductors for cooperative analysis are arranged.

  In the terminal position information of the netlist terminal (see FIG. 11B) of the device circuit network, the terminal positions are specified by the number of terminals, and the terminal positions are defined on the surface excluding the sides of the device area (FIG. 11). (See (A)). In the terminal name information, terminal names (node names on the net list) are defined for the number of terminals. Note that terminal positions and terminal names correspond in the specified order.

FIG. 12 is a diagram illustrating a configuration example of the cooperation information storage unit 901.
In FIG. 12, (A) is an example of the configuration of linkage information defined in the linkage information storage unit 901, (B) is an example of linkage information defined as a device area, and (C) is ( The linkage information of A) is represented by a SPICE solver.

As illustrated in FIG. 12, device position information, terminal position information, and terminal name information are defined in the cooperation information storage unit 901.
That is, the device position information is defined by its start point (100 100 100) and end point (110 110 102). The terminal position information is defined by four points (100 102 101), (100 108 101), (110 102 101), and (110 108 101). The terminal name information is defined by n1, n2, n3, and n4.

Next, specific examples 1 to 6 will be described as specific examples of the cooperative data generation processing described with reference to FIG.
FIG. 13 is a diagram for explaining the flow of the specific example 1 of the cooperative data generation process.

FIG. 13A is a flowchart illustrating the flow of specific example 1 of the cooperative data generation process.
First, in step S1301, the cooperation data generation unit 910 acquires the number n of terminals based on the terminal position information stored in the cooperation information storage unit 901.

  In step S1302, the linkage data generation unit 910 adds the device position region from the terminal position pk to the device position region for k = 1 to 1 (k = 1, 2, 3,..., N−1). A circuit branch having a length of one lattice is arranged in the inner direction of the circuit, and the other end of the circuit branch is set to a position pk ′ (dash). In the example shown in FIG. 13B, “p1 ′ (dash)”, “p2 ′ (dash)”, and “p3 ′ (dash)”.

  Next, in step S1303, the cooperative data generation unit 910 arranges a one-grid-length conductor branch from the terminal position pn which is a reference terminal toward the inside of the device position region, and sets the other end of the conductor branch to the position pn ′ (dash ). In the example shown in FIG. 13B, “p4 ′ (dash)”.

  Next, in step S1304, as shown in FIG. 13C, the linkage data generation unit 910 adds the position pk ′ (dash) and the position pn ′ ( Between the dashes) along the electric field grid by the maze method. The maze method is a method of searching for wiring routes in all directions by labeling the wiring grid in the order in which ripples spread from the starting point. If there is a wiring route, the shortest one is always found. It has the feature that it can.

  In step S1305, the cooperation data generation unit 910 merges the n-1 wiring results to obtain a reference conductor.

FIG. 14 is a diagram for explaining the flow of the specific example 2 of the cooperative data generation process.
FIG. 14A is a flowchart showing the flow of specific example 2 of the linkage data generation process.
First, in step S1401, the cooperation data generation unit 910 acquires the number n of terminals based on the terminal position information stored in the cooperation information storage unit 901.

  In step S1402, the linkage data generation unit 910 adds k to 1 and increments n by 1 (k = 1, 2, 3,..., N) from the terminal position pk to the inside of the device position area. A circuit branch having one lattice length is arranged, and the other end of the circuit branch is set to a position pk ′ (dash). In the example shown in FIG. 14B, “p1 ′ (dash)”, “p2 ′ (dash)”, “p3 ′ (dash)”, and “p4 ′ (dash)”.

Next, in step S1403, the cooperation data generation unit 910 calculates the center point “(start point position + end point position) / 2” of the device region and sets it as the position pr (see FIG. 14B).
Next, in step S1404, as shown in FIG. 14C, the cooperative data generation unit 910 adds an electric field between the position pk ′ (dash) and the position pr until k is incremented by 1 and reaches n. Route along the grid by the maze method.

  In step S1405, the cooperation data generation unit 910 merges the n wiring results and sets the result as a reference conductor.

FIG. 15 is a diagram for explaining the flow of the specific example 3 of the cooperative data generation process.
FIG. 15A is a flowchart showing the flow of specific example 3 of the cooperative data generation process.
First, in step S1501, the cooperation data generation unit 910 acquires the number n of terminals based on the terminal position information stored in the cooperation information storage unit 901.

  In step S1502, as shown in FIG. 15B, the cooperative data generation unit 910 adds 1 from k = 1 to n−1 and increments 1 from the terminal position pk to the inner side of the device position area. A circuit branch having a lattice length is arranged.

Next, in step S1503, as illustrated in FIG. 15B, the cooperative data generation unit 910 arranges a conductor branch having a length of one grid from the terminal position pn to the inner side of the device position area.
Next, in step S1504, as shown in FIG. 15C, the cooperative data generation unit 910 fills the entire area of the device position area one lattice length away with conductor branches in the xyz direction, To do.

FIG. 16 is a diagram for explaining the flow of the specific example 4 of the cooperative data generation process.
FIG. 16A is a flowchart illustrating the flow of specific example 4 of the cooperative data generation process.

First, in step S1601, the cooperation data generation unit 910 acquires the number n of terminals based on the terminal position information stored in the cooperation information storage unit 901.
Then, in step S1602, for k = 1 to 1 and up to n, as shown in FIG. 16 (B), the cooperative data generation unit 910 performs one grid length from the terminal position pk to the inside of the device position area. The circuit branches are arranged.

  Next, in step S1603, as shown in FIG. 16C, the cooperative data generation unit 910 fills the entire area of the device position area one lattice length away with conductor branches in the xyz direction, To do.

FIG. 17 is a diagram for explaining the flow of the specific example 5 of the cooperative data generation process.
FIG. 17A is a flowchart illustrating the flow of specific example 5 of the cooperative data generation process.

First, in step S1701, steps S1301 to S1305 in FIG. 13 are executed.
In step S1702, the cooperative data generation unit 910 traces the wiring connected to the position pk ′ (dash) and adds the position where the reference conductor branches to pk ′ from k = 1 to n−1. '(Two dash). In the example shown in FIG. 17B, “p1 ″ (two dash)”, “p2 ″ (two dash)”, and “p3 ″ (two dash)”.

  Next, in step S1703, the cooperative data generation unit 910 uses one lattice length on the pk ″ (two dash) side of the wiring between the positions pk ′ (dash) and pk ″ (two dash) as a circuit branch. replace. In the example shown in FIG. 17C, between “p1 ′ (dash)” and “p1 ″ (two dash)”, between “p2 ′ (dash)” and “p2 ″ (two dash)” and “p3 ′” Between (dash) and “p3 ″ (two dash)”. Also, the cooperation data generation unit 910 replaces the circuit branch between the positions pk and pk ′ (dash) with a conductor branch. In the example shown in FIG. 17C, “p1” “p1 ′ (dash)”, “p2” “p2 ′ (dash)”, and “p3” “p3 ′ (dash)”.

FIG. 18 is a diagram for explaining the flow of the specific example 6 of the cooperative data generation process.
FIG. 18A is a flowchart showing the flow of specific example 6 of the cooperative data generation process.

First, in step S1801, steps S1401 to S1405 in FIG. 14 are executed.
In step S1802, for k = 1 to n, the cooperative data generation unit 910 traces the wiring connected to the position pk ′ (dash) and determines the position where the reference conductor branches pk ″ ( 2 dash). In the example shown in FIG. 18B, “p1 ″ (two dash)”, “p2 ″ (two dash)”, “p3 ″ (two dash)”, and “p4 ″ (two dash)”.

  Next, in step S1803, the cooperative data generation unit 910 uses one lattice length on the pk ″ (two dash) side of the wiring between the positions pk ′ (dash) and pk ″ (two dash) as a circuit branch. replace. In the example shown in FIG. 18C, “p1 ′ (dash)” “p1 ″ (two dash)”, “p2 ′ (dash)” “p2 ″ (two dash)”, “p3 ′” Between (dash), “p3 ″ (two dash)” and between “p4 ′ (dash)”, “p4 ″ (two dash)”. Also, the cooperation data generation unit 910 replaces the circuit branch between the positions pk and pk ′ (dash) with a conductor branch. In the example shown in FIG. 18C, “p1” “p1 ′ (dash)”, “p2” “p2 ′ (dash)”, “p3” “p3 ′ (dash)”, and “p4” Between "p4 '(dash)".

FIG. 19 is a diagram illustrating a configuration example of electromagnetic field information added to the cooperative electromagnetic field information storage unit 905.
As described with reference to FIG. 10, in step S <b> 1002, the cooperation data generation unit 910 converts the circuit branch and the conductor generated by the placement and routing process in step S <b> 1001 into the electromagnetic field information stored in the electromagnetic field information storage unit 902. And output to the cooperative electromagnetic field information storage unit 905.

  For example, in the case of a circuit network as shown in FIG. 19C, a reference conductor as shown in FIG. 19A and a circuit branch as shown in FIG. The information is output to the information storage unit 905.

FIG. 20 is a diagram illustrating a configuration example of circuit information added to the cooperation circuit information storage unit 906.
As described with reference to FIG. 10, in step S <b> 1003, the cooperation data generation unit 910 adds the electric field to the circuit information stored in the circuit information storage unit 903 based on the terminal name information stored in the cooperation information storage unit 901. An equivalent circuit is added and output to the linked circuit information storage unit 906.

For example, in the case of a circuit network as shown in FIG. 20B, an electromagnetic field equivalent circuit as shown in FIG. 20A is generated and output to the linked circuit information storage unit 906.
The present embodiment has been described above with reference to FIGS. 7 to 20.

Next, a definition example and wiring example of a device area different from the device area shown in FIG. 11 will be described with reference to FIGS.
In the device region definition example 1 and the device region definition example 2 to be described below, including the example shown in FIG. 11, the reference lattice points of the circuit branch that should be shared by a single lattice point are conventionally expanded to a plurality of points by conductors. When the actual terminal is used as a reference, the reference conductor has no direct connection with a terminal (conductor outside the device area) other than one terminal, and when the virtual terminal is used as a reference The reference conductor has no connection with a direct terminal (external conductor). Using the virtual terminal as a reference means that the reference lattice point is a virtual terminal to which no terminal conductor is connected as shown in FIG.

FIG. 22 is a diagram illustrating a device area definition example 1.
As shown in FIG. 22, the device position is defined as a device region which is a rectangular parallelepiped on the electric field grid, and six terminals are defined on the side surface.

FIG. 23 is a diagram illustrating a wiring example 1 of the device region definition example 1.
As shown in FIG. 23, the wiring is radiated from the center so as to be the shortest line. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

FIG. 24 is a diagram illustrating a wiring example 2 of the device region definition example 1.
As shown in FIG. 24, the reference conductor is laid down so as to reduce the impedance. However, the capacitance component of the reference conductor increases. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

FIG. 25 is a diagram illustrating a wiring example 3 of the device region definition example 1.
As shown in FIG. 25, the reference conductor portion is wired as small as possible. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

FIG. 26 is a diagram illustrating a device area definition example 2. In FIG.
As shown in FIG. 26, the device position is defined as a device region which is a rectangular parallelepiped on the electric field grid, and nine terminals are defined on the lower surface thereof.

FIG. 27 is a diagram illustrating a wiring example 1 of the device region definition example 2.
As shown in FIG. 27, wiring is performed so as to be the shortest line radially from the center. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

FIG. 28 is a diagram illustrating a wiring example 2 of the device region definition example 2.
As shown in FIG. 28, the reference conductor is laid down so as to reduce the impedance. However, the capacitance component of the reference conductor increases. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

FIG. 29 is a diagram illustrating a wiring example 3 of the device region definition example 2.
As shown in FIG. 29, wiring is performed so that the reference conductor portion is as small as possible. In addition, (A) is an example wired based on a real terminal, and (B) is an example wired based on a virtual terminal.

  As described above, the embodiments of the present invention have been described with reference to the drawings. However, the above-described embodiments of the present invention are not limited to hardware or a DSP (Digital Signal Processor) as a function of the electromagnetic field circuit cooperation analysis apparatus. It can be realized by firmware or software on a board or CPU board.

  Further, the electromagnetic field circuit cooperation analysis apparatus to which the present invention is applied is not limited to the above-described embodiment as long as the function is executed. Needless to say, the system or the integrated device may be a system that performs processing via a network such as a LAN or a WAN.

  The electromagnetic field circuit cooperation analysis apparatus to which the present invention is applied includes a CPU connected to a bus, a ROM or RAM memory, an input device, an output device, an external recording device, a medium drive device, and a network connection device. It can also be realized with a system. That is, the ROM, RAM memory, external recording device, and portable recording medium in which the software program that realizes the system of the above-described embodiment is recorded are supplied to the electromagnetic field circuit cooperation analysis device, and the electromagnetic field circuit cooperation is performed. Needless to say, this can also be achieved by the computer of the analysis apparatus reading and executing the program.

  In this case, the program itself read from the portable recording medium or the like realizes the novel function of the present invention, and the portable recording medium or the like on which the program is recorded constitutes the present invention.

  Examples of portable recording media for supplying the program include flexible disks, hard disks, optical disks, magneto-optical disks, CD-ROMs, CD-Rs, DVD-ROMs, DVD-RAMs, magnetic tapes, and nonvolatile memory cards. Various recording media recorded via a network connection device (in other words, a communication line) such as a ROM card, electronic mail or personal computer communication can be used.

  The computer (information processing apparatus) executes the program read out on the memory, thereby realizing the functions of the above-described embodiment, and an OS running on the computer based on the instructions of the program. Performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

  Furthermore, a program read from a portable recording medium or a program (data) provided by a program (data) provider is stored in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After being written, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing based on the instructions of the program, and the functions of the above-described embodiments are also realized by the processing. obtain.

  That is, the present invention is not limited to the embodiment described above, and can take various configurations or shapes without departing from the gist of the present invention.

900 Electromagnetic circuit cooperation analysis device 901 Cooperation information storage unit 902 Electromagnetic field information storage unit 903 Circuit information storage unit 904 Control information storage unit 905 Cooperation electromagnetic field information storage unit 906 Cooperation circuit information storage unit 907 Analysis result 910 Cooperation data generation unit 920 Control unit 921 Input unit 922 Data exchange unit 923 Output unit 930 FDTD solver 940 Circuit simulator

Claims (5)

On the computer,
Based on the device position information indicating the position of the device model corresponding to the electronic circuit to be analyzed and the terminal position information indicating the position of the terminal of the device model, a circuit branch corresponding to the position of the terminal is generated on the lattice,
Generating a reference conductor by connecting the circuit branches based on a predetermined rule;
Executing a linkage analysis between an electromagnetic field analysis based on electromagnetic field information including the circuit branch and the reference conductor and a circuit analysis based on the circuit information;
Electromagnetic circuit cooperation analysis program characterized by this.   2. The electromagnetic circuit coupling analysis according to claim 1, wherein the reference conductor is obtained by extending a reference lattice point to a plurality of lattice points by connecting a plurality of circuit branches based on a predetermined rule. program.   The electromagnetic field circuit linkage analysis program according to claim 1, wherein the predetermined rule is a maze method. An electromagnetic field circuit linkage analysis apparatus for performing linkage analysis between electromagnetic field analysis and circuit analysis,
A circuit that generates a circuit branch corresponding to the position of the terminal on the lattice based on device position information indicating the position of the device model corresponding to the electronic circuit to be analyzed and terminal position information indicating the position of the terminal of the device model Branch generation means;
Reference conductor generating means for generating a reference conductor by connecting the circuit branches based on a predetermined rule;
A collaborative analysis means for performing a collaborative analysis between an electromagnetic field analysis based on electromagnetic field information including the circuit branch and the reference conductor, and a circuit analysis based on the circuit information;
An electromagnetic field circuit cooperative analysis device characterized by comprising: Computer
Based on the device position information indicating the position of the device model corresponding to the electronic circuit to be analyzed and the terminal position information indicating the position of the terminal of the device model, a circuit branch corresponding to the position of the terminal is generated on the grid,
A reference conductor is generated by connecting the circuit branches based on a predetermined rule,
Performing a linkage analysis between an electromagnetic field analysis based on electromagnetic field information including the circuit branch and the reference conductor and a circuit analysis based on the circuit information;
An electronic circuit analysis method characterized by the above.

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