JP5972614B2 - Doping apparatus, doping method, and manufacturing method of semiconductor device - Google Patents

Description

One embodiment of the disclosed invention relates to a doping apparatus and a doping method.

An ion doping apparatus (also referred to as a doping apparatus) has a doping chamber connected to an ion source. In the doping apparatus, a substrate is placed in a doping chamber in a vacuum state, and ions generated by an ion source are accelerated by an electric field and added to the extreme surface layer of the substrate. In this specification, a substrate is one of objects to be doped. The ion source consists of a plasma chamber, an extraction acceleration electrode system (extraction electrode and acceleration electrode) that extracts ions generated in the plasma chamber, and a deceleration electrode system (deceleration electrode and ground electrode) that controls the inflow of secondary electrons. Yes. A porous electrode is generally used as the electrode, and ions pass through this hole and reach the doping chamber. Such a flow of ions is referred to as an ion flow.

As a plasma generation method of the ion source, there are a DC discharge method, a high frequency discharge method, a microwave discharge method, and the like (see Patent Document 1). Further, it is possible to confine the plasma inside the ion source by applying a magnetic field, and a cusp magnetic field may be formed by disposing a permanent magnet around the plasma chamber.

By the way, in recent years, attention has been focused on metal oxides exhibiting semiconductor characteristics called oxide semiconductors as constituent materials of transistors. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, and zinc oxide. Transistors in which channels are formed in such metal oxides that exhibit semiconductor characteristics are already known. (Patent Document 2 and Patent Document 3).

JP 2009-21066 A JP 2007-123861 A JP 2007-96055 A

In an oxide semiconductor, part of hydrogen and oxygen vacancies serves as a donor and generates electrons as carriers. In the oxide semiconductor film, when the carrier density is increased, a channel is formed in the transistor without application of voltage to the gate. As a result, the threshold voltage shifts in the negative direction.

Therefore, oxygen is added to the oxide semiconductor film, or excess oxygen is added to the insulating film in contact with the oxide semiconductor film to form an oxygen-excess region, and oxygen is supplied from the oxygen-excess region to the oxide semiconductor film. Then, oxygen deficiency can be suppressed, which is preferable. By adding oxygen to the oxide semiconductor film or forming an oxygen-excess region in the insulating film in contact with the oxide semiconductor film, the electrical characteristics of the transistor can be improved.

When the above doping apparatus is used to add oxygen to the oxide semiconductor film or the insulating film in contact with the oxide semiconductor film, oxygen can be added to a wide region of the oxide semiconductor film or the insulating film surface. This is preferable.

However, when oxygen is added by a doping apparatus, there is a risk that the filament that generates thermoelectrons and the electrode that accelerates or decelerates the generated ions are oxidized by oxygen. If the filament oxidizes, it becomes impossible to generate plasma. Further, when the electrode is oxidized, a plurality of holes provided in the electrode may be clogged with oxide, which may block the ion flow.

In view of the above, an object of one embodiment of the disclosed invention is to provide a doping apparatus to which oxygen can be added.

Another object of one embodiment of the disclosed invention is to provide a semiconductor device with improved electrical characteristics.

In one embodiment of the disclosed invention, first, thermoelectrons are generated by passing an electric current through a filament provided in the first chamber.

Further, an inert gas is introduced into the first chamber from the gas introduction unit. The introduced inert gas collides with the thermoelectrons, whereby ions of the inert gas are generated, and plasma of the inert gas is generated. Thus, since the filament is exposed to an inert gas, the filament is not oxidized.

The generated inert gas ions are extracted by the extraction electrode installed in the second chamber and accelerated by the acceleration electrode. The extraction electrode and the acceleration electrode are porous, and if the extraction electrode and the acceleration electrode are oxidized, there is a possibility that a plurality of provided holes may be clogged with oxide. However, since the inert gas ions pass through the extraction electrode and the acceleration electrode, there is no possibility that the extraction electrode and the acceleration electrode are oxidized.

The accelerated inert gas ions reach the third chamber. Oxygen ions are supplied to the third chamber by an oxygen ion supply unit. More specifically, the oxygen ion supply unit has an oxygen introduction device, a tube connecting the oxygen introduction device and the oxygen plasma chamber, and a coil wound around the tube. Oxygen is introduced into the chamber. When a high voltage is applied by a coil wound around the tube, oxygen passing through the tube is turned into plasma (inductively coupled plasma). That is, oxygen ions are generated by applying a voltage with the coil. When oxygen is turned into plasma, not only oxygen ions but also oxygen radicals may be generated. In that case, in this specification, “oxygen ion” includes “oxygen radical” even if not described. In addition, the said pipe | tube uses the pipe | tube comprised with insulators, such as a quartz glass tube, for example. In this way, oxygen plasma is generated in the third chamber.

In the third chamber, oxygen ions generated as described above are supplied to a region through which inert gas ions pass. Thereby, ions of the inert gas collide with oxygen ions. The colliding inert gas ions and oxygen ions are irradiated to the object installed in the fourth chamber by the kinetic energy of the inert gas ions.

As described above, the target is irradiated with oxygen ions. The object is also irradiated with ions of an inert gas simultaneously with oxygen ions, but there is no particular problem because of the inert gas.

According to one aspect of the disclosed invention, an arc chamber having a gas introduction unit into which an inert gas is introduced, a filament that generates thermoelectrons, and a first ion that extracts ions of the inert gas ionized in the arc chamber. Oxygen ions are supplied to the first electrode, the second electrode for accelerating the ions of the inert gas extracted by the first electrode, and the region through which the inert gas ions accelerated by the second electrode pass And a sample chamber into which ions of the inert gas and oxygen ions are introduced.

In one embodiment of the disclosed invention, the oxygen ion supply unit is characterized in that oxygen ions are generated by inductively coupled plasma to generate oxygen ions.

In one embodiment of the disclosed invention, the oxygen ion supply unit includes an oxygen introduction device, a tube connected to the oxygen introduction device, and a coil wound around the tube.

In one embodiment of the disclosed invention, the material of the tube is quartz glass.

In one embodiment of the disclosed invention, the material of the filament is tungsten.

In one embodiment of the disclosed invention, each of the first electrode and the second electrode is a porous electrode, and a material of the first electrode and the second electrode is tungsten. And

In one embodiment of the disclosed invention, a current is passed through a filament to generate thermoelectrons, the thermoelectrons collide with an inert gas to generate ions of the inert gas, and the generated inert gas By applying a voltage to the ions of the electrode by an electrode, the ions of the inert gas are accelerated, and by applying a voltage to the oxygen, oxygen plasma is generated to generate oxygen ions, and the oxygen ions are The present invention relates to a doping method characterized in that ions of accelerated inert gas collide with each other and an object is irradiated with the oxygen ions.

One embodiment of the disclosed invention is characterized in that an insulating layer is formed over a substrate and the insulating layer is irradiated with the oxygen ions.

In one embodiment of the disclosed invention, the oxide semiconductor layer is irradiated with the oxygen ions.

According to one embodiment of the disclosed invention, a doping apparatus to which oxygen can be added can be provided.

According to one embodiment of the disclosed invention, a semiconductor device with improved electrical characteristics can be provided.

Schematic of a doping apparatus. Schematic of a doping apparatus. 2A and 2B are a plan view and a cross-sectional view of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device. FIG. 14 is a cross-sectional view of a semiconductor device.

Hereinafter, embodiments of the invention disclosed in this specification will be described with reference to the drawings. However, the invention disclosed in this specification can be implemented in many different modes, and various changes can be made in form and details without departing from the spirit and scope of the invention disclosed in this specification. It will be readily understood by those skilled in the art. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in the drawings described below, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

Note that in the invention disclosed in this specification, a semiconductor device refers to all elements and devices that function by utilizing a semiconductor, and includes an electric device including an electronic circuit, a display device, a light-emitting device, and the like. The category is the electronic equipment.

Note that the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.

Note that ordinal numbers such as “first”, “second”, and “third” in this specification and the like are added to avoid confusion between components and are not limited numerically. To do.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In addition, the functions of “source” and “drain” may be switched when transistors having different polarities are employed or when the direction of current changes in circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

Note that in this specification and the like, “electrically connected” includes a case of being connected via “something having an electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. For example, “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

In this specification and the like, the term “substantially equal” with respect to thickness is used not only for being completely equal but also for including substantially equal cases. For example, “substantially equal” means that the influence on the characteristics of the semiconductor device is negligible (the influence on the characteristics is 5% or less) compared to the case where it is completely equal, or is slightly unintentionally. And the like (when the polishing amount is less than about 5 nm).

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the constituent elements is “directly above” or “directly below”. For example, the expression “a gate electrode over a gate insulating film” does not exclude an element including another component between the gate insulating film and the gate electrode.

[Embodiment 1]
A doping apparatus of the present embodiment is shown in FIG. The doping apparatus shown in FIG. 1 includes an arc chamber 101 that is a first chamber, an ion acceleration chamber 103 that is a second chamber, an oxygen plasma chamber 104 that is a third chamber, and a sample chamber 102 that is a fourth chamber. Have. In FIG. 1, the arc chamber 101, the ion acceleration chamber 103, and the oxygen plasma chamber 104 are connected without any clear separation, so that all these chambers can be regarded as one chamber and are used for doping. It can also be said that it is an ion source that generates ions.

The arc chamber 101 is provided with a filament 111 serving as a cathode, an anode 116, and a gas introduction unit 134 for introducing an inert gas such as argon. Note that the anode 116 is not necessarily provided if not necessary.

The inert gas is introduced into the arc chamber 101 from the gas introduction unit 134.

Thermal electrons are generated by passing a current through the filament 111. In the present embodiment, tungsten (W) is used as the material of the filament 111.

A cross section A1-A2 of the arc chamber 101 provided with the filament 111 in FIG. 1 is shown in FIG. 2A, four filaments 111 are provided at equal intervals in an arc chamber 101 having a circular cross section.

An inert gas is introduced from the gas introduction unit 134 into the arc chamber 101. The introduced inert gas collides with the thermoelectrons, whereby ions of the inert gas are generated, and an inert gas plasma 138 is generated (arc discharge). Thus, since the filament is exposed to an inert gas and not exposed to oxygen, the filament 111 is not oxidized.

In the ion acceleration chamber 103, an extraction electrode 112, an acceleration electrode 113, a deceleration electrode 114, and a ground electrode 115 are provided. The extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115 are porous electrodes each having a plurality of through holes. The extraction electrode 112 and the anode 116 are at the same potential, and are electrically connected to the positive electrode of the extraction power supply 131. The acceleration electrode 113 is electrically connected to the negative electrode of the extraction power supply 131 and the positive electrode of the acceleration power supply 132. The deceleration electrode 114 is electrically connected to the negative electrode of the deceleration power supply 133. The ground electrode 115 is grounded. As described above, voltages having different voltage values are applied to the extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115. In this embodiment, tungsten (W) is used as a material for the extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115.

Ions generated in the arc chamber 101 are extracted by applying a voltage having a predetermined voltage value to the extraction electrode 112 and accelerated to a desired speed by applying a voltage having another voltage value to the acceleration electrode 113. Is done. The decelerating electrode 114 and the ground electrode 115 collect diverging ions to improve the directionality of the ion flow.

FIG. 2B shows a cross section taken along B1-B2 of the ion acceleration chamber 103 provided with the extraction electrode 112 in FIG. As shown in FIG. 2B, an extraction electrode 112 which is a porous electrode having a plurality of through holes is provided in an ion acceleration chamber 103 having a circular cross section.

Note that the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115 also have the same structure as the extraction electrode 112 shown in FIG.

The deceleration electrode 114 has a function of suppressing the progress of ions that have passed through the extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115, but are reflected back to the wall of the doping apparatus. Accordingly, it is possible to suppress oxygen ions (described later) from traveling toward the arc chamber 101 as well as ions of the inert gas that are reflected back to the wall of the doping apparatus.

The extraction power supply 131, the acceleration power supply 132, and the deceleration power supply 133 are provided outside the doping apparatus. The negative electrode of the acceleration power supply 132 and the positive electrode of the deceleration power supply 133 are grounded.

The generated inert gas ions are extracted by the extraction electrode 112 and accelerated by the acceleration electrode 113. The extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115 are porous electrodes. If these porous electrodes are oxidized, there is a possibility that a plurality of provided holes are clogged with oxide. However, since the inert gas ions pass through the extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115, there is no possibility that these porous electrodes are oxidized.

The generated inert gas ions pass through the extraction electrode 112, the acceleration electrode 113, the deceleration electrode 114, and the ground electrode 115 and reach the oxygen plasma chamber 104.

The oxygen plasma chamber 104 is provided with an oxygen ion supply unit 145 and an exhaust device 136. The oxygen ion supply unit 145 includes an oxygen introduction device 135 that introduces oxygen, a tube 141 that connects the oxygen introduction device 135 and the oxygen plasma chamber 104, and a coil 142 that is wound around the tube 141. The tube 141 is, for example, a quartz glass tube or the like, and is a tube made of an insulator. Further, as the material of the inner wall of the oxygen plasma chamber 104, it is preferable to use a material that is not oxidized, for example, an oxide material, more specifically molybdenum oxide.

In the oxygen plasma chamber 104, oxygen is introduced from the oxygen introduction device 135. Further, the oxygen supplied to the oxygen plasma chamber 104 is exhausted by the exhaust device 136. As a result, an oxygen air flow is generated from the oxygen introduction device 135 toward the exhaust device 136 in the oxygen plasma chamber 104.

When a high voltage is applied from the power source 143 to the coil 142 wound around the tube 141, a high voltage is applied from the coil 142 to oxygen. Thereby, oxygen passing through the tube 141 is turned into plasma (inductively coupled plasma). Thereby, oxygen ions are generated while oxygen moves from the oxygen introduction device 135 to the oxygen plasma chamber 104.

In this way, oxygen plasma 139 is generated in the oxygen plasma chamber 104.

In the oxygen plasma chamber 104, oxygen ions generated as described above are supplied to a region through which inert gas ions pass. Thereby, ions of the inert gas collide with oxygen ions. The colliding inert gas ions and oxygen ions are irradiated onto the object 120 provided in the sample chamber 102 by the kinetic energy of the inert gas ions.

Note that a diffusion prevention plate 144 for preventing diffusion of oxygen ions and inert gas ions may be provided between the oxygen plasma chamber 104 and the sample chamber 102. The diffusion preventing plate 144 may be formed from a porous material having a plurality of through holes.

As described above, the target object 120 is irradiated with oxygen ions. The object 120 is irradiated with ions of an inert gas simultaneously with oxygen ions, but there is no particular problem because of the inert gas.

In the sample chamber 102, a stage 107 and an exhaust device 108 are provided. The object 120 to be irradiated with oxygen ions is disposed on the stage 107. Note that the stage 107 may be configured to be able to move the wall (or floor) of the sample chamber in which the stage 107 is provided. By moving the stage 107, the object 120 is also moved, and the object 120 can be irradiated with ions uniformly.

When the sample chamber 102 processes the object 120 having a larger area than the cross-sectional area of the ion flow, the entire surface of the object 120 can be doped by scanning the stage 107. In such a case, the object 120 is irradiated with a cross-sectional shape of the ion flow that is rectangular or linear. 1 shows a configuration in which the object 120 is arranged horizontally and the ion flow is irradiated in the vertical direction with respect to the object 120. However, in order to reduce particles on the object 120, the object The structure may be such that 120 is arranged perpendicular to the ground and the ion flow is irradiated in a direction perpendicular to the object 120.

In the present embodiment, the object 120 is held on the stage 107 by the holding means 121a and the holding means 121b. Alternatively, the object 120 may be held on the stage 107 with a vacuum chuck or the like.

FIG. 2C shows a cross section of C1-C2 of the sample chamber 102 provided with the object 120, the stage 107, the holding means 121a, and the holding means 121b in FIG. As shown in FIG. 2C, a stage 107 is provided in a sample chamber 102 having a circular cross section. Further, the object 120 is held on the stage 107 by holding the end of the object 120 with the holding means 121 a and the holding means 121 b.

In FIG. 2C, the object 120 having a smaller area than the cross-sectional area of the ion flow is described. When processing the object 120 having a larger area than the cross-sectional area of the ion flow, the entire surface of the object 120 can be doped by scanning the stage 107 as described above. In such a case, the cross-sectional shape of the ion flow may be rectangular or linear, and the object 120 may be irradiated.

The object 120 is, for example, a substrate on which an oxide semiconductor layer or an insulating film in contact with the oxide semiconductor layer is formed.

Note that an exhaust device 108 is provided in the sample chamber 102, and the arc chamber 101, the sample chamber 102, the ion acceleration chamber 103, and the oxygen plasma chamber 104 are evacuated before the target 120 is irradiated with ions. A high vacuum state is established by the device 108.

In the doping apparatus shown in FIG. 1, what is generated using the filament 111 is plasma of an inert gas. In addition, the ions introduced into the acceleration electrode 113 by the extraction electrode 112, and the distribution of ions by the acceleration electrode 113 and the acceleration / deceleration electrode 114 and the ground electrode 115 are adjusted by the inert gas ions.

On the other hand, no filament or electrode is installed inside the oxygen plasma chamber where oxygen plasma is generated and oxygen ions are generated. Thereby, it can prevent that a filament and an electrode are oxidized.

As described above, in the doping apparatus of the present embodiment, oxygen can be added to the object 120 (irradiation with oxygen ions), and oxidation of the filament and the porous electrode can be prevented. .

Each of the exhaust device 136 and the exhaust device 108 may be a dry pump, a mechanical booster pump, a turbo molecular pump, or the like as appropriate.

If necessary, a mass separator may be provided between the oxygen plasma chamber 104 as the third chamber and the sample chamber 102 as the fourth chamber. By installing the mass separator, it is possible to irradiate the target with ion species having a specific mass.

As described above, according to this embodiment, a doping apparatus to which oxygen can be added can be provided.

[Embodiment 2]
In this embodiment, one embodiment of a method for manufacturing a semiconductor device using the doping apparatus described in Embodiment 1 will be described. In this embodiment, a transistor including an oxide semiconductor layer is described as an example of a semiconductor device.

The transistor may have a single gate structure in which one channel formation region is formed, a double gate structure in which two channel formation regions are formed, or a triple gate structure in which three channel formation regions are formed. Alternatively, a dual gate type having two gate electrode layers arranged above and below the channel region with a gate insulating layer interposed therebetween may be used.

A transistor 440a illustrated in FIGS. 3A to 3C is an example of a top-gate transistor. FIG. 3A is a plan view, and a cross section taken along one-dot chain line X1-X2 in FIG. 3A corresponds to FIG. 3B, and one-dot chain line Y1-Y2 in FIG. The cut section corresponds to FIG.

As shown in FIG. 3B, which is a cross-sectional view in the channel length direction, and FIG. 3C, which is a cross-sectional view in the channel width direction, the semiconductor device including the transistor 440a includes an insulating surface provided with a base insulating layer 436. Over the substrate 400 having the oxide semiconductor layer 403, the source electrode layer 405a, the drain electrode layer 405b, the gate insulating layer 402, the gate electrode layer 401, the side wall insulating layer 412 provided on the side surface of the gate electrode layer 401, and the gate electrode An insulating layer 413 provided over the layer 401, an interlayer insulating layer 417 provided over the source electrode layer 405a and the drain electrode layer 405b, an interlayer insulating layer 415 provided over the interlayer insulating layer 417, and an insulating layer covering the transistor 440a 407. Note that some components are not illustrated in FIG. 3A for easy understanding of the drawing.

In addition, the base insulating layer 436 described in this embodiment is an example in which the first base insulating layer 436a and the second base insulating layer 436b are stacked. In addition, the gate insulating layer 402 described in this embodiment is an example in which the first gate insulating layer 402a and the second gate insulating layer 402b are stacked. The first base insulating layer 436a, the second gate insulating layer 402b, and the interlayer insulating layer 417 are preferably formed using an impurity such as hydrogen, moisture, hydride, or hydroxide, or a material having a barrier property against oxygen. . By applying a material having a barrier property to the insulating layer, entry of impurities from the outside is prevented, and oxygen from the oxide semiconductor layer 403, the second base insulating layer 436b, and the first gate insulating layer 402a is prevented. Desorption can be prevented.

The interlayer insulating layer 415 is provided to planarize unevenness due to the transistor 440a, and the height of the upper surface (vertical distance from the surface of the substrate 400) is substantially the same as that of the sidewall insulating layer 412 and the insulating layer 413. The heights of the upper surfaces of the source electrode layer 405a and the drain electrode layer 405b are lower than the heights of the upper surfaces of the interlayer insulating layer 415, the sidewall insulating layer 412, and the insulating layer 413, and higher than the height of the upper surface of the gate electrode layer 401.

In FIG. 3, the insulating layer 407 is provided in contact with the interlayer insulating layer 415, the interlayer insulating layer 417, the source electrode layer 405a, the drain electrode layer 405b, the sidewall insulating layer 412, and the insulating layer 413.

Note that in this specification, a region overlapping with the gate electrode layer 401 in the oxide semiconductor layer 403 is referred to as a channel formation region, and a region in contact with the source electrode layer 405a in the oxide semiconductor layer 403 is referred to as a source region. A region in the oxide semiconductor layer 403 that is in contact with the drain electrode layer 405b is referred to as a drain region. In addition, a region between the channel formation region and the source region in the oxide semiconductor layer 403 is referred to as an offset region 406a, and a region between the channel formation region and the drain region is referred to as an offset region 406b. The offset region 406a and the offset region 406b are formed in positions overlapping with the sidewall insulating layer 412 in the oxide semiconductor layer 403.

That is, the channel formation region, the source region, the drain region, the offset region 406a, and the offset region 406b are formed by self-alignment. Note that by providing the offset region, parasitic capacitance generated between the gate electrode layer 401 and the source electrode layer 405a can be reduced. In addition, parasitic capacitance generated between the gate electrode layer 401 and the drain electrode layer 405b can be reduced.

In addition, since a channel formation region is formed by self-alignment, miniaturization of a transistor is easily realized, on-state characteristics (eg, on-current and field-effect mobility) are high, and high-speed operation is possible.

On the other hand, in the manufacturing process described later, in the case where an impurity element that changes conductivity of the oxide semiconductor is added to the oxide semiconductor layer 403 using the gate electrode layer 401 as a mask, the oxide semiconductor layer 403 is formed between the source region and the channel formation region. In addition, a low resistance region is formed in a self-aligned manner between the drain region and the channel formation region. When the low-resistance region is formed, the on-resistance of the transistor 440a can be reduced and the operation speed can be improved.

An oxide semiconductor used for the oxide semiconductor layer 403 preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. In addition, it is preferable to include gallium (Ga) in addition to the stabilizer for reducing variation in electrical characteristics of the transistor including the oxide. Moreover, it is preferable to have tin (Sn) as a stabilizer. Moreover, it is preferable to have hafnium (Hf) as a stabilizer. Moreover, it is preferable to have aluminum (Al) as a stabilizer. Moreover, it is preferable to have a zirconium (Zr) as a stabilizer.

Other stabilizers include lanthanoids such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), and terbium (Tb). , Dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu).

For example, as the oxide semiconductor layer 403, indium oxide, tin oxide, zinc oxide, a binary metal oxide In—Zn-based oxide, Sn—Zn-based oxide, Al—Zn-based oxide, Zn— Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides (also referred to as IGZO) that are ternary metal oxides, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide, Sn-Al-Zn-based oxide, In-Hf-Zn Oxide, In—La—Zn oxide, In—Ce—Zn oxide, In—Pr—Zn oxide, In—Nd—Zn oxide, In—Sm—Zn oxide, In -Eu-Zn-based oxide, In-Gd-Zn-based oxide, In-Tb-Zn-based , In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In-Lu -Zn-based oxides, In-Sn-Ga-Zn-based oxides that are quaternary metal oxides, In-Hf-Ga-Zn-based oxides, In-Al-Ga-Zn-based oxides, In- Sn-Al-Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides can be used.

Note that here, for example, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.

Alternatively, a material represented by InMO ₃ (ZnO) _m (m> 0) may be used as the oxide semiconductor. Note that M represents one metal element or a plurality of metal elements selected from Ga, Fe, Mn, and Co. Alternatively, a material represented by In ₂ SnO ₅ (ZnO) _n (n> 0) may be used as the oxide semiconductor.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5: 1) / 5), or an In—Ga—Zn-based oxide having an atomic ratio of In: Ga: Zn = 3: 1: 2 (= 1/2: 1/6: 1/3) and oxidation in the vicinity of the composition. Can be used. Alternatively, In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1) / 2) or In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) atomic ratio In—Sn—Zn-based oxide or oxide in the vicinity of the composition Should be used.

However, the composition is not limited thereto, and a material having an appropriate composition may be used depending on required semiconductor characteristics (mobility, threshold value, variation, etc.). In order to obtain the required semiconductor characteristics, it is preferable that the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic bond distance, density, and the like are appropriate.

For example, high mobility can be obtained relatively easily with an In—Sn—Zn-based oxide. However, mobility can be increased by reducing the defect density in the bulk also in the case of using an In—Ga—Zn-based oxide.

Note that for example, the composition of an oxide in which the atomic ratio of In, Ga, and Zn is In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: B: C (A + B + C = 1) is in the vicinity of the oxide composition, a, b, c are (a−A) ² + (b−B) ² + (c−C) ² ≦ r ² Satisfying. For example, r may be 0.05. The same applies to other oxides.

In addition to a single crystal oxide semiconductor, a polycrystalline (also referred to as polycrystal) oxide semiconductor, or an amorphous oxide semiconductor, an oxide semiconductor disclosed in this embodiment includes a CAAC-OS (C Axis Aligned). Crystalline Oxide Semiconductor) can be used.

The CAAC-OS is not completely single crystal nor completely amorphous. The CAAC-OS is an oxide semiconductor with a crystal-amorphous mixed phase structure where crystal parts are included in an amorphous phase. Note that the crystal part is often large enough to fit in a cube whose one side is less than 100 nm. Further, in an observation image obtained by a transmission electron microscope (TEM), a boundary between an amorphous part and a crystal part included in the CAAC-OS is not clear. Further, a grain boundary (also referred to as a grain boundary) cannot be confirmed in the CAAC-OS by TEM. Therefore, in CAAC-OS, reduction in electron mobility due to grain boundaries is suppressed.

The crystal part included in the CAAC-OS has a c-axis aligned in a direction perpendicular to the formation surface or surface of the CAAC-OS and a triangular or hexagonal atomic arrangement when viewed from the direction perpendicular to the ab plane. , When viewed from the direction perpendicular to the c-axis, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. Note that the directions of the a-axis and the b-axis may be different between different crystal parts. In this specification, a simple term “perpendicular” includes a range from 85 ° to 95 °.

Note that in the CAAC-OS, the distribution of crystal parts may not be uniform. For example, in the formation process of the CAAC-OS, in the case where crystal growth is performed from the surface side of the oxide semiconductor layer, the ratio of crystal parts in the vicinity of the surface may be higher in the vicinity of the formation surface. Further, when an impurity is added to the CAAC-OS, the crystal part in a region to which the impurity is added becomes amorphous in some cases.

Since the c-axis of the crystal part included in the CAAC-OS is aligned in a direction perpendicular to the formation surface or the surface of the CAAC-OS, depending on the shape of the CAAC-OS (the cross-sectional shape of the formation surface or the cross-sectional shape of the surface) May face different directions. Note that the c-axis direction of the crystal part is a direction perpendicular to a surface or a surface where the CAAC-OS is formed. The crystal part is formed by film formation or by performing crystallization treatment such as heat treatment after film formation.

A transistor using a CAAC-OS can reduce variation in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor has high reliability.

Note that part of oxygen included in the oxide semiconductor layer may be replaced with nitrogen.

Further, in an oxide semiconductor having a crystal part such as a CAAC-OS, defects in a bulk can be further reduced, and mobility higher than that of an oxide semiconductor in an amorphous state can be obtained by increasing surface flatness. . In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on the flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, more preferably Is preferably formed on a surface of 0.1 nm or less.

Ra is a three-dimensional extension of the centerline average roughness defined in JIS B0601 so that it can be applied to a surface. “A value obtained by averaging the absolute values of deviations from a reference surface to a specified surface” Can be expressed. In addition, Ra can be evaluated with an atomic force microscope (AFM: Atomic Force Microscope).

The thickness of the oxide semiconductor layer is 1 nm or more and 30 nm or less (preferably 5 nm or more and 10 nm or less). Can be used as appropriate. The oxide semiconductor layer 403 is formed using a sputtering apparatus that performs film formation in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target, that is, a so-called CP sputtering apparatus (Columner Plasma Sputtering system). May be.

4A to 4E and FIGS. 5A to 5D illustrate an example of a method for manufacturing a semiconductor device including the transistor 440a.

First, the base insulating layer 436 is formed over the substrate 400.

There is no particular limitation on a substrate that can be used as the substrate 400 as long as it has heat resistance enough to withstand heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate such as silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, or the like can be applied, and a semiconductor element provided on these substrates, The substrate 400 may be used.

Alternatively, a semiconductor device may be manufactured using a flexible substrate as the substrate 400. In order to manufacture a semiconductor device having flexibility, the transistor 440a including the oxide semiconductor layer 403 may be directly formed over a flexible substrate, or the transistor including the oxide semiconductor layer 403 over another manufacturing substrate. 440a may be manufactured and then peeled off and transferred to the flexible substrate. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor 440a including the oxide semiconductor layer.

As the base insulating layer 436, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, plasma CVD, sputtering, or the like can be used. Or it can form using these mixed materials. Note that in this specification, oxynitridation refers to a composition having a higher oxygen content than nitrogen, and nitridation oxidation refers to a composition having a higher nitrogen content than oxygen. Shall. Here, the oxygen and nitrogen contents are measured using Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering Spectroscopy (HFS).

Further, a thermal oxide film may be used as the base insulating layer 436. The thermal oxide film can be formed by oxidizing the substrate surface by heat-treating the substrate in an oxidizing atmosphere. For example, a thermal oxide film is formed on the surface of the substrate 400 by performing heat treatment at 900 ° C. to 1200 ° C. for several hours in an atmosphere containing oxygen or water vapor using a single crystal silicon substrate as the substrate 400. can do.

The base insulating layer 436 may be a single layer or a stacked layer, but is an insulating layer in which oxygen in an amount exceeding the stoichiometric ratio exists in the layer (in the bulk) in order from the side closer to the oxide semiconductor layer 403 described later. When the insulating layer has a barrier property against impurities and oxygen such as hydrogen, moisture, hydride, or hydroxide, oxygen is supplied to the oxide semiconductor layer 403 and the oxide semiconductor layer This is preferable because release of oxygen from 403 can be suppressed. In this embodiment, as the base insulating layer 436, a stack of a first base insulating layer 436a and a second base insulating layer 436b is used. The first base insulating layer 436a formed over the substrate 400 is formed using a material such as silicon nitride or aluminum oxide that has a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, or oxygen. It is preferable. In addition, since the second base insulating layer 436b formed over the first base insulating layer 436a is in contact with the oxide semiconductor layer 403, an amount of oxygen exceeding at least the stoichiometric ratio exists in the layer (in the bulk). It is preferable. For example, when silicon oxide is used for the second base insulating layer 436b, SiO _{2 + α} (where α> 0) is set. With the use of such the second base insulating layer 436b, oxygen can be supplied to the oxide semiconductor layer 403, so that characteristics can be improved. By supplying oxygen to the oxide semiconductor layer 403, oxygen vacancies in the oxide semiconductor layer 403 can be filled.

In order to form the second base insulating layer 436b in which oxygen exceeding the stoichiometric ratio exists in the layer (in the bulk), after forming the second base insulating layer 436b, Oxygen may be added using the doping apparatus described. As for the method for adding oxygen using the doping apparatus described in Embodiment 1, the substrate 400 in which the first base insulating layer 436a and the second base insulating layer 436b are stacked is described in Embodiment 1. As the object 120, oxygen is added to the second base insulating layer 436b.

In this embodiment, a single crystal silicon substrate is used as the substrate 400, silicon nitride with a thickness of 50 nm is formed as the first base insulating layer 436a over the substrate 400 by a plasma CVD method, and the first base insulating layer 436a is formed. Next, silicon oxide with a thickness of 300 nm is formed as the second base insulating layer 436b.

The temperature at which the base insulating layer 436 is formed is preferably equal to or lower than the temperature that the substrate 400 can withstand. For example, the base insulating layer 436 is formed while the substrate 400 is heated to a temperature of 350 ° C to 450 ° C. Note that the temperature at which the base insulating layer 436 is formed is preferably constant. For example, the base insulating layer 436 is formed by heating the substrate 400 to 350 ° C.

Further, after the base insulating layer 436 is formed, heat treatment may be performed under reduced pressure, a nitrogen atmosphere, a rare gas atmosphere, or an ultra-dry air nitrogen atmosphere. The concentration of hydrogen, moisture, hydride, hydroxide, or the like contained in the base insulating layer 436 can be reduced by heat treatment. The degree of heat treatment is preferably equal to or lower than a temperature that the substrate 400 can withstand and higher. Specifically, the temperature is preferably higher than the deposition temperature of the base insulating layer 436 and lower than the strain point of the substrate 400.

Note that the hydrogen concentration of the base insulating layer 436 is less than 5 × 10 ¹⁸ atoms / cm ³ , preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, and further preferably 1 It is desirable to set it as x10 ¹⁶ atoms / cm ³ or less.

After the second base insulating layer 436b is formed, oxygen is added using the doping apparatus described in Embodiment 1. Accordingly, the second base insulating layer 436b in which oxygen in an amount exceeding at least the stoichiometric ratio exists in the layer (in the bulk) can be formed.

As for the method for adding oxygen to the second base insulating layer 436b, as described above, the substrate 400 in which the first base insulating layer 436a and the second base insulating layer 436b are stacked is described in Embodiment Mode 1. As the object 120, oxygen is added to the second base insulating layer 436b (see FIG. 4A).

By supplying oxygen, a bond between an element constituting the second base insulating layer 436b and hydrogen, or a bond between the element and a hydroxyl group is cut, and the hydrogen or the hydroxyl group reacts with oxygen to cause water. Therefore, when heat treatment is performed after supplying oxygen, impurities such as hydrogen or a hydroxyl group are easily released as water. Therefore, heat treatment may be performed after oxygen is supplied to the second base insulating layer 436b. After that, oxygen may be further supplied to the second base insulating layer 436b so that the second base insulating layer 436b is in an oxygen-excess state. Further, the supply of oxygen to the second base insulating layer 436b and the heat treatment may be alternately performed a plurality of times. Further, heat treatment and oxygen supply may be performed at the same time.

Next, the oxide semiconductor layer 403 is formed over the base insulating layer 436 by a sputtering method.

In the formation process of the oxide semiconductor layer 403, in order to prevent the oxide semiconductor layer 403 from containing hydrogen or water as much as possible, as a pretreatment for forming the oxide semiconductor layer 403, a preheating chamber of a sputtering apparatus is used. The substrate over which the base insulating layer 436 is formed is preferably preheated, and impurities such as hydrogen and moisture adsorbed on the substrate and the base insulating layer 436 are released and exhausted. Note that a cryopump is preferable as an exhaustion unit provided in the preheating chamber.

Planarization treatment may be performed on a region where the oxide semiconductor layer 403 is in contact with the base insulating layer 436. Although it does not specifically limit as planarization processing, Polishing processing (for example, chemical mechanical polishing method), dry etching processing, and plasma processing can be used.

As the plasma treatment, for example, reverse sputtering in which an argon gas is introduced to generate plasma can be performed. Inverse sputtering is a method in which a surface is modified by forming a plasma near the substrate by applying a voltage to the substrate side using an RF power source in an argon atmosphere. Note that nitrogen, helium, oxygen, or the like may be used instead of the argon atmosphere. When reverse sputtering is performed, powdery substances (also referred to as particles or dust) attached to the surface of the base insulating layer 436 can be removed.

As the planarization treatment, the polishing treatment, the dry etching treatment, and the plasma treatment may be performed a plurality of times or in combination. In the case where the steps are performed in combination, the order of steps is not particularly limited, and may be set as appropriate depending on the unevenness state of the surface of the base insulating layer 436.

For example, the surface of the silicon oxide layer used as the base insulating layer 436 is polished by a chemical mechanical polishing method (polishing conditions: polyurethane-based polishing cloth, silica-based slurry, slurry temperature at room temperature, polishing pressure 0.001 MPa, polishing) The rotation speed (table / spindle) 60 rpm / 56 rpm, polishing time 0.5 minutes) is performed, and the average surface roughness (Ra) on the surface of the silicon oxide layer may be about 0.15 nm.

Note that as a sputtering gas for forming the oxide semiconductor layer 403, a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed gas of a rare gas and oxygen is used as appropriate. As the sputtering gas, it is preferable to use a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed.

Note that the oxide semiconductor layer 403 is formed under a condition in which a large amount of oxygen is contained (for example, film formation is performed by a sputtering method in an atmosphere containing 100% oxygen), which contains a large amount of oxygen or oxygen is supersaturated. It is preferable to be in a state (preferably a state in which the oxide semiconductor includes a region where the oxygen content is excessive with respect to the stoichiometric composition ratio in the crystalline state).

For example, in the case where an oxide semiconductor layer is formed by a sputtering method, the sputtering gas is preferably used under a condition where the proportion of oxygen in the sputtering gas is large and the sputtering gas is preferably used as 100% oxygen gas. When a film is formed under a condition where the proportion of oxygen gas in the sputtering gas is large, particularly 100% oxygen gas, release of Zn from the oxide semiconductor layer can be suppressed even when the formation temperature is 300 ° C. or higher, for example.

The oxide semiconductor layer 403 is preferably a highly purified layer that hardly contains impurities such as copper, aluminum, and chlorine. In the manufacturing process of the transistor, it is preferable to select as appropriate a process in which these impurities are not mixed or attached to the surface of the oxide semiconductor layer. Specifically, the copper concentration of the oxide semiconductor layer 403 is 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less. The aluminum concentration of the oxide semiconductor layer 403 is 1 × 10 ¹⁸ atoms / cm ³ or less. The chlorine concentration of the oxide semiconductor layer 403 is 2 × 10 ¹⁸ atoms / cm ³ or less.

The concentration of alkali metal such as sodium (Na), lithium (Li), or potassium (K) in the oxide semiconductor layer 403 is 5 × 10 ¹⁶ cm ⁻³ or less, preferably 1 × 10 ¹⁶ cm ^{− in} Na. ³ or less, more preferably 1 × 10 ¹⁵ cm ⁻³ or less, Li is 5 × 10 ¹⁵ cm ⁻³ or less, preferably 1 × 10 ¹⁵ cm ⁻³ or less, and K is 5 × 10 ¹⁵ cm ⁻³ or less, preferably It is preferable to set it as 1 * 10 < ¹⁵ > cm <^-3> or less.

In this embodiment, as the oxide semiconductor layer 403, an In—Ga—Zn-based oxide (IGZO) with a thickness of 35 nm is formed by a sputtering method using a sputtering apparatus having an AC power supply device. As a target for manufacturing by a sputtering method, a metal oxide target having a composition ratio of In: Ga: Zn = 3: 1: 2 [atomic ratio] is used.

The relative density (filling rate) of the metal oxide target is 90% to 100%, preferably 95% to 99.9%. By using a metal oxide target with a high relative density, the formed oxide semiconductor layer 403 can be a dense film.

As a sputtering gas used for forming the oxide semiconductor layer 403, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

First, a substrate is held in a film formation chamber held in a reduced pressure state. Then, a sputtering gas from which hydrogen and moisture are removed is introduced while moisture remaining in the deposition chamber is removed, and the oxide semiconductor layer 403 is formed over the substrate 400 using the above target. In order to remove moisture remaining in the deposition chamber, it is preferable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. Further, the exhaust means may be a turbo molecular pump provided with a cold trap. In the film formation chamber evacuated using a cryopump, for example, a compound containing a hydrogen atom (more preferably a compound containing a carbon atom) such as a hydrogen atom or water (H ₂ O) is exhausted. The concentration of impurities contained in the oxide semiconductor layer 403 formed in the chamber can be reduced.

Alternatively, the base insulating layer 436 and the oxide semiconductor layer 403 may be formed successively without being released to the atmosphere. When the base insulating layer 436 and the oxide semiconductor layer 403 are successively formed without being exposed to the air, impurities such as hydrogen and moisture can be prevented from attaching to the surface of the base insulating layer 436.

Further, after the oxide semiconductor layer 403 is formed, heat treatment for removing (dehydrating or dehydrogenating) excess hydrogen (including water and a hydroxyl group) in the oxide semiconductor layer 403 may be performed. The temperature of the heat treatment is 300 ° C. or higher and 700 ° C. or lower, or lower than the strain point of the substrate. The heat treatment can be performed under reduced pressure or a nitrogen atmosphere. For example, the substrate is introduced into an electric furnace which is one of heat treatment apparatuses, and the oxide semiconductor layer 403 is subjected to heat treatment at 450 ° C. for 1 hour in a nitrogen atmosphere.

Note that the heat treatment apparatus is not limited to an electric furnace, and an apparatus for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, a rapid thermal annealing (RTA) device such as a GRTA (Gas Rapid Thermal Anneal) device or an LRTA (Lamp Rapid Thermal Anneal) device can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the high-temperature gas, an inert gas that does not react with an object to be processed by heat treatment, such as nitrogen or a rare gas such as argon, is used.

For example, as the heat treatment, GRTA may be performed in which the substrate is placed in an inert gas heated to a high temperature of 650 ° C. to 700 ° C., heated for several minutes, and then the substrate is taken out of the inert gas.

Note that in the heat treatment, it is preferable that water, hydrogen, or the like be not contained in nitrogen or a rare gas such as helium, neon, or argon. Alternatively, the purity of nitrogen or a rare gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably Is preferably 0.1 ppm or less).

In addition, after heating the oxide semiconductor layer 403 by heat treatment, a dew point of high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (CRDS (cavity ring-down laser spectroscopy) method) is supplied to the same furnace. The amount of water when measured using a meter may be 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or the dinitrogen monoxide gas. Alternatively, the purity of the oxygen gas or nitrous oxide introduced into the heat treatment apparatus is 6N or more, preferably 7N or more (that is, the impurity concentration in the oxygen gas or nitrous oxide is 1 ppm or less, preferably 0.1 ppm or less. ) Is preferable. Oxygen is supplied by supplying oxygen, which is a main component material of the oxide semiconductor, which has been reduced by the process of removing impurities by dehydration or dehydrogenation treatment by the action of oxygen gas or dinitrogen monoxide gas. Oxygen vacancies in the physical semiconductor are reduced, so that the oxide semiconductor layer 403 can be i-type (intrinsic) or substantially i-type. In this respect, since it is not i-type by adding an impurity element such as silicon, it can be said that i-type oxide semiconductor includes an unprecedented technical idea.

The heat treatment for dehydration or dehydrogenation may be performed before or after the formation of the island-shaped oxide semiconductor layer 403 as long as it is after the formation of the oxide semiconductor layer. Further, the heat treatment for dehydration or dehydrogenation may be performed a plurality of times or may be combined with other heat treatments.

Further, oxygen that is a main component material of the oxide semiconductor may be desorbed and reduced at the same time by dehydration or dehydrogenation treatment. In the oxide semiconductor layer, oxygen vacancies exist at locations where oxygen is released, and donor levels that cause fluctuations in electrical characteristics of the transistor are generated due to the oxygen vacancies.

Therefore, oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) may be supplied to the oxide semiconductor layer 403 subjected to dehydration or dehydrogenation treatment.

By supplying oxygen to the oxide semiconductor layer 403 that has been subjected to dehydration or dehydrogenation treatment, oxygen vacancies in the oxide semiconductor that are generated by the step of removing impurities by the dehydration or dehydrogenation treatment are reduced. The oxide semiconductor layer 403 can be electrically i-type (intrinsic). A transistor including the oxide semiconductor layer 403 that is electrically i-type (intrinsic) is electrically stable because variation in electrical characteristics is suppressed.

As a method for supplying oxygen, oxygen may be added using the doping apparatus described in Embodiment 1. The substrate 400 in which the oxide semiconductor layer 403 is formed over the base insulating layer 436 is added to the oxide semiconductor layer 403 as the object 120 described in Embodiment 1 (see FIG. 4B).

By supplying oxygen, a bond between an element constituting the oxide semiconductor layer 403 and hydrogen, or a bond between the element and a hydroxyl group is cut, and water is generated by the reaction of the hydrogen or the hydroxyl group with oxygen. Therefore, when heat treatment is performed after supplying oxygen, hydrogen or a hydroxyl group that is an impurity is easily released as water. Therefore, heat treatment may be performed after oxygen is supplied to the oxide semiconductor layer 403. After that, oxygen may be further supplied to the oxide semiconductor layer 403 so that the oxide semiconductor layer 403 is in an oxygen-excess state. Further, supply of oxygen to the oxide semiconductor layer 403 and heat treatment may be alternately performed a plurality of times. Further, heat treatment and oxygen supply may be performed at the same time.

In this manner, the oxide semiconductor layer 403 is highly purified by sufficiently removing impurities such as hydrogen, and sufficient oxygen is supplied to reduce oxygen vacancies in the oxide semiconductor layer 403. Therefore, it is desirable that the material is i-type (intrinsic) or substantially i-type (intrinsic).

An oxide semiconductor (purified OS), which is purified by reducing impurities such as moisture or hydrogen, which serves as an electron donor (donor), supplies oxygen to the oxide semiconductor, and then oxygen in the oxide semiconductor. By reducing defects, an i-type (intrinsic) oxide semiconductor or an oxide semiconductor that is almost as close to i-type (substantially i-type) can be obtained. A transistor using an i-type or substantially i-type oxide semiconductor for a semiconductor layer in which a channel is formed has a characteristic of extremely low off-state current.

Specifically, the hydrogen concentration of the highly purified oxide semiconductor layer is such that a measured value of hydrogen concentration by secondary ion mass spectrometry (SIMS) is 5 × 10 ¹⁹ atoms / cm ³ or less, Preferably it is 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less. In addition, since sufficient oxygen is supplied to the oxide semiconductor layer 403 so that the oxygen is supersaturated, an insulating layer containing much oxygen (such as silicon oxide) is provided in contact with the oxide semiconductor layer 403 so as to be interposed therebetween. preferable.

Further, the hydrogen concentration in the insulating layer containing a large amount of oxygen is also important because it affects the characteristics of the transistor. When the hydrogen concentration of the insulating layer containing a large amount of oxygen is 7.2 × 10 ²⁰ atoms / cm ³ or more, the variation in the initial characteristics of the transistor is increased, the dependency on the L length is increased, and in the BT stress test, Because of deterioration, the hydrogen concentration of the insulating layer containing a large amount of oxygen is set to be less than 7.2 × 10 ²⁰ atoms / cm ³ . That is, the hydrogen concentration of the oxide semiconductor layer is preferably 5 × 10 ¹⁹ atoms / cm ³ or less, and the hydrogen concentration of the insulating layer containing a large amount of oxygen is preferably less than 7.2 × 10 ²⁰ atoms / cm ³ .

Here, the SIMS analysis of the hydrogen concentration is mentioned. In SIMS analysis, it is known that, based on the principle, it is difficult to accurately obtain data in the vicinity of the sample surface and in the vicinity of the laminated interface with films of different materials. Therefore, when analyzing the distribution of the hydrogen concentration in the layer in the thickness direction by SIMS, the average value in a region where there is no extreme variation in the value and an almost constant value can be obtained in the range where the target layer exists. Adopted as hydrogen concentration. In addition, when the thickness of the layer to be measured is small, there may be a case where an area where a substantially constant value is obtained cannot be found due to the influence of the hydrogen concentration in the adjacent film. In this case, the maximum value or the minimum value of the hydrogen concentration in the region where the film exists is adopted as the hydrogen concentration in the film. Further, in the region where the film is present, when there is no peak peak having the maximum value and no valley peak having the minimum value, the value of the inflection point is adopted as the hydrogen concentration.

Next, the oxide semiconductor layer 403 is processed into an island shape, so that the gate insulating layer 442 covering the island-shaped oxide semiconductor layer 403 is formed.

Note that the planarization treatment may be performed on the surface of the oxide semiconductor layer 403 in order to improve the coverage with the gate insulating layer 442. In particular, when a thin insulating layer is used as the gate insulating layer 442, the surface of the oxide semiconductor layer 403 is preferably flat.

The thickness of the gate insulating layer 442 is 1 nm to 20 nm, and can be formed using a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like as appropriate. Alternatively, the gate insulating layer 442 may be formed using a so-called CP sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the surface of the sputtering target.

Note that when a silicon oxide film or silicon oxynitride is formed by a CVD method as the gate insulating layer 442, glow discharge plasma is generated in an HF band of 3 MHz to 30 MHz, typically 13.56 MHz and 27.12 MHz. It is preferable to apply high-frequency power or high-frequency power in a VHF band from 30 MHz to about 300 MHz, typically 60 MHz. Moreover, it can also carry out by applying the microwave high frequency electric power of 1 GHz or more. Note that pulse oscillation in which high-frequency power is applied in a pulsed manner or continuous oscillation in which high-frequency power is continuously applied can be employed. A silicon oxide film or silicon oxynitride formed using a microwave of 1 GHz or higher is an oxide film in which fixed charges in the gate insulating layer 442 and the interface with the oxide semiconductor layer 403 are formed by normal plasma CVD. Less than silicon film or silicon oxynitride. Therefore, reliability of electrical characteristics such as a threshold voltage of the transistor can be increased.

Although the gate insulating layer 442 may be a single layer or a stacked layer, an insulating layer in which oxygen in an amount exceeding at least the stoichiometric ratio exists in the layer (in the bulk) in order from the side closer to the oxide semiconductor layer 403; In addition, when the insulating layer has a barrier property against impurities such as hydrogen, moisture, hydride, or hydroxide, and oxygen, oxygen is supplied to the oxide semiconductor layer 403 and the oxide semiconductor layer 403 This is preferable because the desorption of oxygen can be suppressed. In this embodiment, a stack of a first gate insulating layer 442a and a second gate insulating layer 442b is used as the gate insulating layer 442. As a material of the gate insulating layer 442, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, hafnium oxide, gallium oxide, or a mixed material thereof is used. Can be formed. In this embodiment, as the gate insulating layer 442, a first gate insulating layer 442a and a second gate insulating layer 442b are stacked.

In general, the capacitive element has a configuration in which a dielectric is sandwiched between two opposing electrodes. The thinner the dielectric (the shorter the distance between the two opposing electrodes), the more the dielectric As the dielectric constant increases, the capacitance value increases. However, if the dielectric is made thin in order to increase the capacitance value of the capacitive element, the leakage current generated between the two electrodes tends to increase, and the withstand voltage of the capacitive element tends to decrease.

A portion where the gate electrode, the gate insulating layer, and the semiconductor layer of the transistor overlap functions as the above-described capacitor (hereinafter also referred to as “gate capacitor”). Note that a channel is formed in the semiconductor layer in a region overlapping with the gate electrode with the gate insulating layer interposed therebetween. That is, the gate electrode and the channel formation region function as two electrodes of the capacitor, and the gate insulating layer functions as a dielectric of the capacitor. Although it is preferable that the capacitance value of the gate capacitance is large, if the gate insulating layer is thinned in order to increase the capacitance value, problems such as an increase in the leakage current and a decrease in the withstand voltage are likely to occur.

Therefore, as the gate insulating layer 442, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate added with nitrogen (HfSi _x O _y N _z (x> 0, y> 0, z) > 0)), high-k materials such as hafnium aluminate to which nitrogen is added (HfAl _x O _y N _z (x> 0, y> 0, z> 0)), hafnium oxide, yttrium oxide, Even when the gate insulating layer 442 is thick, a sufficient capacitance value between the gate electrode layer 401 and the oxide semiconductor layer 403 can be secured.

For example, when a high-k material having a high dielectric constant is used for the gate insulating layer 442, a capacitance value equivalent to that obtained when silicon oxide is used for the gate insulating layer 442 can be realized even when the gate insulating layer 442 is thick. Leakage current generated between the gate electrode layer 401 and the oxide semiconductor layer 403 can be reduced. In addition, leakage current generated between a wiring formed using the same layer as the gate electrode layer 401 and another wiring overlapping with the wiring can be reduced. Note that the gate insulating layer 442 may have a stacked structure of a high-k material and the above material.

The gate insulating layer 442 preferably contains oxygen in a portion in contact with the oxide semiconductor layer 403. In this embodiment, the first gate insulating layer 442a in contact with the oxide semiconductor layer 403 preferably contains oxygen in the film (in the bulk) at least in excess of the stoichiometric ratio. For example, when a silicon oxide film is used as the first gate insulating layer 442a, SiO _{2 + α} (where α> 0) is set. In this embodiment, a silicon oxide film with SiO _{2 + α} (α> 0) is used as the first gate insulating layer 442a. By using this silicon oxide film as the first gate insulating layer 442a, oxygen can be supplied to the oxide semiconductor layer 403, and the characteristics can be improved. Further, the first gate insulating layer 442a is preferably formed in consideration of the size of a transistor to be manufactured and the step coverage with the first gate insulating layer 442a.

After the formation of the first gate insulating layer 442a, when oxygen is supplied to the first gate insulating layer 442a so that the first gate insulating layer 442a is in an oxygen-excess state, an oxide semiconductor is formed from the first gate insulating layer 442a. This is preferable because oxygen can be supplied to the layer 403.

As a method for supplying oxygen, oxygen may be added using the doping apparatus described in Embodiment 1. As the object 120 described in Embodiment 1, the substrate 400 in which the first gate insulating layer 442a is formed over the oxide semiconductor layer 403 is added with oxygen to the first gate insulating layer 442a (FIG. C)).

By supplying oxygen, the bond between the element constituting the first gate insulating layer 442a and hydrogen, or the bond between the element and the hydroxyl group is cut, and the hydrogen or the hydroxyl group reacts with oxygen. Thus, water is generated, so that heat treatment is performed after supplying oxygen, whereby hydrogen or a hydroxyl group that is an impurity can be easily removed as water. That is, the impurity concentration in the first gate insulating layer 442a can be further reduced. Therefore, heat treatment may be performed after oxygen is supplied to the first gate insulating layer 442a. After that, oxygen may be further supplied to the first gate insulating layer 442a so that the gate insulating layer 442 is in an oxygen-excess state. Further, the supply of oxygen to the first gate insulating layer 442a and the heat treatment may be alternately performed a plurality of times. Further, heat treatment and oxygen supply may be performed at the same time.

Next, a second gate insulating layer 442b is formed over the first gate insulating layer 442a. Accordingly, the gate insulating layer 442 which is a stack of the first gate insulating layer 442a and the second gate insulating layer 442b is formed over the oxide semiconductor layer 403. (See FIG. 4D). The second gate insulating layer 442b is preferably formed using a material having a barrier property against oxygen and impurities such as hydrogen, moisture, hydride, or hydroxide, such as silicon nitride and aluminum oxide.

Further, before the gate insulating layer 442 is formed, moisture or organic substances attached to the surface of the oxide semiconductor layer 403 by plasma treatment using oxygen, dinitrogen monoxide, a rare gas (typically argon), or the like. It is preferable to remove impurities such as.

Next, a stack of a conductive layer 404 (not shown) for forming the gate electrode layer 401 and an insulating layer 408 (not shown) for forming the insulating layer 413 is formed over the gate insulating layer 442. Then, part of the conductive layer 404 and the insulating layer 408 is selectively etched by a first photolithography step, so that a stack of the gate electrode layer 401 and the insulating layer 413 is formed (see FIG. 4E).

Note that unless otherwise specified, the photolithography process in this specification includes a resist mask forming process, a conductive layer or insulating layer etching process, and a resist mask peeling process. .

In this embodiment, as the conductive layer 404, tantalum nitride with a thickness of 30 nm is formed over the gate insulating layer 442 by a sputtering method, and tungsten with a thickness of 135 nm is formed over the tantalum nitride. As the insulating layer 408, silicon oxynitride with a thickness of 200 nm is formed by a plasma CVD method.

A resist mask for forming the gate electrode layer 401 and the insulating layer 413 by selectively etching part of the conductive layer 404 and the insulating layer 408 may be formed by a printing method or an inkjet method. When the resist mask is formed by an ink-jet method, a manufacturing cost can be reduced because a photomask is not used.

In addition, the etching for forming the gate electrode layer 401 and the insulating layer 413 may be a dry etching method or a wet etching method, or both may be used. In order to form a fine pattern, it is preferable to use a dry etching method capable of anisotropic etching.

In the case where the conductive layer 404 and the insulating layer 408 are etched by a dry etching method, a gas containing a halogen element can be used as an etching gas. As an example of a gas containing a halogen element, a chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like is used. Fluorine gas such as carbon fluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ) or trifluoromethane (CHF ₃ ), hydrogen bromide (HBr), or oxygen as appropriate Can be used. Further, an inert gas may be added to the etching gas used. As the dry etching method, a parallel plate RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching conditions (such as the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the substrate-side electrode temperature, etc.) are adjusted as appropriate so that the desired processed shape can be etched.

The conductive layer 404 to be the gate electrode layer 401 later is formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloy material containing any of these materials as a main component. Can do. As the conductive layer 404, a semiconductor layer typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. The conductive layer 404 may have a single-layer structure or a stacked structure.

The material of the conductive layer 404 is indium oxide tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide. A conductive material such as zinc oxide or indium tin oxide to which silicon oxide is added can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

As the conductive layer 404 in contact with the gate insulating layer 442, a metal oxide containing nitrogen, specifically, an In—Ga—Zn-based metal oxide containing nitrogen, an In—Sn-based metal oxide containing nitrogen, In-Ga-based metal oxide containing nitrogen, In-Zn-based metal oxide containing nitrogen, tin oxide containing nitrogen, indium oxide containing nitrogen, or a metal nitride film (InN, SnN, or the like) is used. be able to. These materials have a work function of 5 eV (electron volt) or more, and when used as a gate electrode layer, the threshold voltage of the electrical characteristics of the transistor can be made positive, and so-called normally-off switching elements can be obtained. realizable.

As a material for the insulating layer 413, an inorganic insulating material such as silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, silicon nitride, aluminum nitride, silicon nitride oxide, or aluminum nitride oxide can be typically used. The insulating layer 413 can be formed by a CVD method, a sputtering method, or the like.

Next, an insulating layer 411 (not shown) is formed over the gate electrode layer 401 and the insulating layer 413, and the sidewall insulating layer 412 is formed by etching the insulating layer 411. Further, the gate insulating layer 442 is etched using the gate electrode layer 401 and the sidewall insulating layer 412 as a mask, so that the gate insulating layer 402 (first gate insulating layer 402a and second gate insulating layer 402b) is formed (FIG. 5). (See (A)).

The insulating layer 411 can be formed using a material and a method similar to those of the insulating layer 413. In this embodiment, a silicon oxynitride film formed by a CVD method is used.

Next, over the oxide semiconductor layer 403, the gate insulating layer 402, the gate electrode layer 401, the sidewall insulating layer 412, and the insulating layer 413, a source electrode layer and a drain electrode layer (including wirings formed using the same layer as the source electrode layer and the drain electrode layer later) are included. Is formed (see FIG. 5B).

The conductive layer 445 is formed using a material that can withstand heat treatment performed later. For example, selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), scandium (Sc), etc. Alternatively, a metal film containing any of the above elements or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing any of the above elements as a component can be used. Moreover, high or low such as titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta) or the like on one or both of the lower side or upper side of a low resistance metal film such as aluminum (Al), copper (Cu), etc. A structure in which a melting point metal film or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is stacked may be employed. It is preferable to stack a refractory metal film or a metal nitride film thereof on one or both of the lower resistance metal film and the lower resistance metal film, because the metal migration (diffusion) of the low resistance metal film can be inhibited. . That is, the conductive layer 445 is a stack of a first conductive layer, a metal film which is a second conductive layer, and a third conductive layer, and a low-resistance conductive layer is used as the second conductive layer. A material capable of inhibiting the movement of the metal of the second conductive layer is used for at least one of the first conductive layer and the third conductive layer. Further, when the third conductive layer on the second conductive layer covers the end portion of the second conductive layer, the movement of the metal from the end portion of the second conductive layer can be suppressed. Therefore, it is preferable.

For example, as the conductive layer 445, a layer of tungsten (W), copper (Cu), and tantalum nitride is used, and low resistance copper (Cu) is sandwiched between tungsten (W) and tantalum nitride that inhibit the movement of copper. Good.

Further, the conductive layer 445 may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide containing silicon oxide can be used.

In this embodiment, as the conductive layer 445, tungsten with a thickness of 30 nm is formed by a sputtering method.

The conductive layer 445 is formed by a second photolithography process. Specifically, a resist mask is formed over the conductive layer 445 and part of the conductive layer 445 is selectively etched, and then the resist mask is removed to form an island-shaped conductive layer 445. Note that in the etching step, the conductive layer 445 which overlaps with the gate electrode layer 401 is not removed.

When a tungsten layer with a thickness of 30 nm is used as the conductive layer 445, the conductive layer is etched by, for example, selectively etching a part of the tungsten layer by dry etching ((etching condition: etching gas (CF ₄ : Cl ₂ : O ₂ = 55 sccm: 45 sccm: 55 sccm, power source power 3000 W, bias power 140 W, pressure 0.67 Pa) to form an island-shaped tungsten layer.

At this time, on the surface of the oxide semiconductor layer 403 exposed by the formation of the conductive layer 445, an element included in the conductive layer 445, an element present in the treatment chamber, and an element included in the etching gas used for etching are impurities. May adhere.

When the impurities are attached, the off-state current of the transistor is increased or the electrical characteristics of the transistor are easily deteriorated. In addition, a parasitic channel is easily generated in the oxide semiconductor layer 403, and an electrode or a wiring to be electrically isolated is easily electrically connected through the oxide semiconductor layer 403.

Further, depending on impurities, the oxide semiconductor layer 403 is mixed in the vicinity of the surface of the oxide semiconductor layer 403 (in the bulk), oxygen in the oxide semiconductor layer 403 is extracted, and oxygen vacancies exist in the surface of the oxide semiconductor layer 403 and in the vicinity of the surface. Sometimes formed. For example, chlorine and boron contained in the above-described etching gas and aluminum which is a constituent material of the etching chamber can be one of the factors that cause the oxide semiconductor layer 403 to have low resistance (n-type).

Therefore, after the etching for forming the conductive layer 445 is completed, it is preferable to perform a cleaning process (impurity removing process) for removing impurities attached to the surface of the oxide semiconductor layer 403.

The impurity removal treatment can be performed by plasma treatment or solution treatment. As the plasma treatment, oxygen plasma treatment, dinitrogen monoxide plasma treatment, or the like can be used. Further, a rare gas (typically argon) may be used for the plasma treatment.

In addition, the washing treatment with a solution can be performed using an alkaline solution such as a TMAH (Tetramethylammonium Hydroxide) solution, an acidic solution such as dilute hydrofluoric acid or oxalic acid, water, or the like. For example, when dilute hydrofluoric acid is used, dilute hydrofluoric acid obtained by diluting 50 wt% hydrofluoric acid with water to about 1/10 ^{2 to} 1/10 ⁵ , preferably about 1/10 ^{3 to} 1/10 ⁵ is used. That is, dilute hydrofluoric acid having a concentration of 0.5 wt% to 5 × 10 ⁻⁴ wt%, preferably 5 × 10 ⁻² wt% to 5 × 10 ⁻⁴ wt% is used for the cleaning treatment. desirable. By the cleaning treatment, the impurity attached to the surface of the oxide semiconductor layer 403 can be removed.

In addition, when the impurity removal treatment is performed using a diluted hydrofluoric acid solution, the surface of the oxide semiconductor layer 403 can be etched. That is, impurities attached to the surface of the oxide semiconductor layer 403 and impurities mixed in the vicinity of the surface of the oxide semiconductor layer 403 can be removed together with part of the oxide semiconductor layer 403. Accordingly, the thickness of the oxide semiconductor layer 403 in the region overlapping with the conductive layer 445 may be larger than the thickness of the region not overlapping. That is, the thickness of a region of the oxide semiconductor layer 403 that overlaps with the source electrode layer 405a and the drain electrode layer 405b may be larger than the thickness of a region that does not overlap. For example, when an IGZO film is treated with 1/10 ³ diluted hydrofluoric acid (0.05% hydrofluoric acid), the film thickness decreases by 1 to 3 nm per second, and 2/10 ⁵ diluted hydrofluoric acid (0.0025% hydrofluoric acid). When the IGZO film is treated with (acid), the film thickness decreases by about 0.1 nm per second.

By performing the impurity removal treatment, the chlorine concentration on the surface of the semiconductor layer is 1 × 10 ¹⁹ / cm ³ or less (preferably 5 × 10 ¹⁸ / cm ³ or less at the peak value of the concentration obtained by analysis using SIMS, Preferably, it can be 1 × 10 ¹⁸ / cm ³ or less. Further, the boron concentration on the surface of the semiconductor layer can be set to 1 × 10 ¹⁹ / cm ³ or less (preferably 5 × 10 ¹⁸ / cm ³ or less, more preferably 1 × 10 ¹⁸ / cm ³ or less). In addition, the aluminum concentration on the surface of the semiconductor layer can be set to 1 × 10 ¹⁹ / cm ³ or less (preferably 5 × 10 ¹⁸ / cm ³ or less, more preferably 1 × 10 ¹⁸ / cm ³ or less).

By performing the impurity removal treatment, a highly reliable transistor having stable electric characteristics can be realized. Note that the impurity removal treatment may be performed after the gate insulating layer 402 is formed.

Next, the insulating layer 447 is formed over the island-shaped conductive layer 445 and the insulating layer 446 is formed over the insulating layer 447.

The insulating layer 447 can be formed using a material and a method similar to those of the second gate insulating layer 402b and the first base insulating layer 436a. The insulating layer 447 can be formed using a material and a method similar to those of the insulating layer 413. The insulating layer 447 is preferably formed using a material having a barrier property against oxygen, such as hydrogen, moisture, hydride, or hydroxide, such as silicon nitride or aluminum oxide. In this embodiment, aluminum oxide is formed to a thickness of 10 nm as the insulating layer 447 by a sputtering method. By making aluminum oxide have a high density (a density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistors 440a and 440b. The film density can be measured by Rutherford Backscattering Spectrometry (RBS) or X-ray reflectance measurement (XRR: X-Ray Reflection).

Further, the insulating layer 446 is formed with a thickness that can planarize unevenness generated by the layers that have been formed over the substrate 400 so far. In this embodiment, silicon oxynitride is formed to a thickness of 300 nm as the insulating layer 446 by a CVD method.

After the formation of the insulating layer 447, oxygen is supplied to the insulating layer 447 so that the insulating layer 447 is in an oxygen-excess state because oxygen can be supplied from the insulating layer 447 to the oxide semiconductor layer 403.

As a method for supplying oxygen, oxygen may be added using the doping apparatus described in Embodiment 1. As the object 120 described in Embodiment 1, the substrate 400 over which the insulating layer 447 is formed is added with oxygen to the insulating layer 447 (see FIG. 5C).

Further, after the insulating layer 446 is formed, oxygen may be added to the insulating layer 446 using the doping apparatus described in Embodiment 1. In that case, oxygen may be added to the insulating layer 446 using the substrate 400 over which the insulating layer 446 is formed as the object 120 described in Embodiment 1.

Supplying oxygen breaks the bond between the elements that make up the insulating layer and hydrogen, or the bond between the element and the hydroxyl group, and the hydrogen or hydroxyl group reacts with oxygen to produce water. Therefore, by performing heat treatment after supplying oxygen, hydrogen or a hydroxyl group that is an impurity can be easily removed as water. That is, the impurity concentration in the insulating layer 447 and / or the insulating layer 446 can be further reduced. Therefore, heat treatment may be performed after oxygen is supplied to the insulating layer 447, the insulating layer 446, or both. After that, oxygen may be further supplied to the insulating layer 447 and / or the insulating layer 446 so that the insulating layer 447 and / or the both are in an oxygen-excess state. Further, the supply of oxygen and the heat treatment to the insulating layer 447 and / or the insulating layer 446 may be alternately performed a plurality of times. Further, heat treatment and oxygen supply may be performed at the same time.

Next, the insulating layer 447, the insulating layer 446, and the conductive layer 445 are polished by a chemical mechanical polishing method, and the insulating layer 447, the insulating layer 446, and the conductive layer 445 are partially removed so that the insulating layer 413 is exposed.

By the polishing treatment, the insulating layer 446 is processed into the interlayer insulating layer 415, the insulating layer 447 is processed into the interlayer insulating layer 417, the conductive layer 445 over the gate electrode layer 401 is removed, and the source electrode layer 405a and the drain electrode layer 405b is formed.

In this embodiment mode, the chemical mechanical polishing method is used to remove the insulating layer 446, the insulating layer 447, and the conductive layer 445. However, other cutting (grinding and polishing) methods may be used. Further, in the step of removing the conductive layer 445 over the gate electrode layer 401, in addition to a cutting (grinding or polishing) method such as a chemical mechanical polishing method, an etching (dry etching or wet etching) method or a plasma treatment is combined. May be. For example, after the removing step by the chemical mechanical polishing method, a dry etching method or plasma treatment (reverse sputtering or the like) may be performed to improve the flatness of the treated surface. In the case of performing a cutting (grinding or polishing) method in combination with an etching method, a plasma treatment, or the like, the order of steps is not particularly limited, and is adjusted according to the material, thickness, and surface roughness of the insulating layer 446 and the conductive layer 445. What is necessary is just to set suitably.

Note that in this embodiment, the source electrode layer 405 a and the drain electrode layer 405 b are provided so as to be in contact with the side surface of the sidewall insulating layer 412 provided on the side surface of the gate electrode layer 401. The source electrode layer 405 a and the drain electrode layer 405 b cover the sidewall insulating layer 412 to a position slightly lower than the upper end portion of the side surface of the sidewall insulating layer 412. The shapes of the source electrode layer 405a and the drain electrode layer 405b vary depending on the polishing conditions for removing the conductive layer 445. As shown in this embodiment mode, the polished surfaces of the sidewall insulating layer 412 and the insulating layer 413 are processed. In some cases, the shape may recede in the thickness direction. However, depending on the conditions of the polishing treatment, the upper end portions of the source electrode layer 405a and the drain electrode layer 405b and the upper end portion of the sidewall insulating layer 412 may roughly match.

Through the above steps, the transistor 440a of this embodiment is manufactured (see FIG. 5D).

In the manufacturing process, the transistor 440a is formed by removing the conductive layer 445 provided over the gate electrode layer 401, the insulating layer 413, and the sidewall insulating layer 412 by chemical mechanical polishing, and separating the conductive layer 445, so that the source electrode A layer 405a and a drain electrode layer 405b are formed.

The source electrode layer 405 a and the drain electrode layer 405 b are provided in contact with the exposed top surface of the oxide semiconductor layer 403 and the sidewall insulating layer 412. Therefore, the distance between the region (source region or drain region) where the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor layer 403 are in contact with the gate electrode layer 401 is the width in the channel length direction of the sidewall insulating layer 412. In addition to achieving further miniaturization, variations in the manufacturing process can be reduced.

In addition, since the distance between the gate electrode layer 401 and a region where the source electrode layer 405a or the drain electrode layer 405b and the oxide semiconductor layer 403 are in contact with each other (a source region or a drain region) can be shortened, the source electrode layer 405a or The resistance between the gate electrode layer 401 and the region (source region or drain region) where the drain electrode layer 405b and the oxide semiconductor layer 403 are in contact with each other is reduced, so that the on-state characteristics of the transistor 440a can be improved.

In addition, in the process of removing the conductive layer 445 over the gate electrode layer 401 in the process of forming the source electrode layer 405a and the drain electrode layer 405b, an etching process using a resist mask is not used, so that precise processing is performed accurately. Can do. Thus, in the manufacturing process of the semiconductor device, the transistor 440a having a fine structure with little variation in shape and characteristics can be manufactured with high yield.

Note that part of the insulating layer 413 or the entire insulating layer 413 may be removed in the step of removing the conductive layer 445 over the gate electrode layer 401 in the step of forming the source electrode layer 405a and the drain electrode layer 405b. FIG. 6C illustrates an example of the transistor 440c in which the insulating layer 413 is completely removed and the gate electrode layer 401 is exposed. Further, part of the gate electrode layer 401 may be removed. The structure in which the gate electrode layer 401 is exposed as in the transistor 440c can be used in an integrated circuit in which another wiring or a semiconductor element is stacked over the transistor 440c.

A highly dense inorganic insulating layer (typically an aluminum oxide layer) which serves as a protective insulating layer may be provided over the transistor 440a.

In this embodiment, the insulating layer 407 is formed in contact with the insulating layer 413, the source electrode layer 405a, the drain electrode layer 405b, the sidewall insulating layer 412, and the interlayer insulating layer 415 (see FIG. 3B).

Alternatively, the interlayer insulating layer 417 may not be formed, and a highly dense inorganic insulating layer (typically an aluminum oxide layer) serving as a protective insulating layer may be provided as the interlayer insulating layer 415. FIG. 6B illustrates an example of the transistor 440b in which the interlayer insulating layer 417 is not formed between the source and drain electrode layers 405a and 405b and the interlayer insulating layer 415.

The insulating layer 407 may be a single layer or a stacked layer, and preferably includes at least an aluminum oxide layer.

The insulating layer 407 can be formed by a plasma CVD method, a sputtering method, an evaporation method, or the like.

Examples of the material used for the insulating layer 407 other than aluminum oxide include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, and gallium oxide. Etc. can be used. Further, hafnium oxide, magnesium oxide, zirconium oxide, lanthanum oxide, barium oxide, or metal nitride can also be used.

In this embodiment, aluminum oxide is formed as the insulating layer 407 by a sputtering method. By making aluminum oxide have a high density (a density of 3.2 g / cm ³ or more, preferably 3.6 g / cm ³ or more), stable electrical characteristics can be imparted to the transistors 440a and 440b.

Aluminum oxide that can be used as the insulating layer 407 and the insulating layer 410 provided over the oxide semiconductor layer 403 has a blocking effect (blocking effect) that prevents both hydrogen, moisture and other impurities, and oxygen from passing through the film. high.

Therefore, an insulating layer formed using aluminum oxide is a main component material that forms impurities in the oxide semiconductor layer 403 and includes impurities such as hydrogen and moisture that cause variation during and after the manufacturing process. Which functions as a protective layer for preventing release of oxygen from the oxide semiconductor layer 403.

The insulating layer 407 is preferably formed by appropriately using a method (preferably a sputtering method or the like) in which an impurity such as water or hydrogen is not mixed into the insulating layer 407.

As in the formation of the oxide semiconductor layer, an adsorption vacuum pump (such as a cryopump) is preferably used to remove residual moisture in the deposition chamber. The concentration of impurities contained in the insulating layers 407 and 410 formed in the deposition chamber evacuated with a cryopump can be reduced. Further, as an evacuation unit for removing residual moisture in the film formation chamber, a turbo molecular pump provided with a cold trap may be used.

As a sputtering gas used for forming the insulating layer 407, a high-purity gas from which impurities such as hydrogen, water, a hydroxyl group, or hydride are removed is preferably used.

Further, a planarization insulating layer may be formed over the transistor in order to reduce surface unevenness due to the transistor. As the planarization insulating layer, an organic material such as polyimide, acrylic resin, or benzocyclobutene resin can be used. In addition to the organic material, a low dielectric constant material (low-k material) or the like can be used. Note that the planarization insulating layer may be formed by stacking a plurality of insulating layers formed using these materials.

6A, openings 433a and 433b reaching the source electrode layer 405a and the drain electrode layer 405b are formed in the insulating layer 407, the interlayer insulating layer 415, and the interlayer insulating layer 417, and the insulating layer 407 is formed over the insulating layer 407. An example is shown in which a wiring layer 435a electrically connected to the source electrode layer 405a through the opening 433a and a wiring layer 435b electrically connected to the drain electrode layer 405b through the opening 433b are formed. Various circuits can be formed by connecting the wiring layer 435a and the wiring layer 435b to other transistors and elements.

The openings 433a and 433b can be formed by selectively etching part of the insulating layer 407, the interlayer insulating layer 415, and the interlayer insulating layer 417 in the third photolithography step. The insulating layer 407, the interlayer insulating layer 415, and the interlayer insulating layer 417 may be etched by a dry etching method or a wet etching method, or both of them may be used.

The wiring layer 435a and the wiring layer 435b are formed with a conductive layer for forming the wiring layer 435a and the wiring layer 435b over the insulating layer 407 after the opening 433a and the opening 433b are formed, and the conductive layer is formed by a fourth photolithography process. A part of the layer can be formed by selective etching.

The conductive layer for forming the wiring layer 435a and the wiring layer 435b can be formed using a material similar to that of the gate electrode layer 401, the source electrode layer 405a, or the drain electrode layer 405b.

The conductive layer for forming the wiring layer 435a and the wiring layer 435b is formed using a material that can withstand heat treatment performed later. For example, selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), scandium (Sc), etc. Alternatively, a metal film containing any of the above elements or a metal nitride film (a titanium nitride film, a molybdenum nitride film, a tungsten nitride film) containing any of the above elements as a component can be used. Moreover, high or low such as titanium (Ti), molybdenum (Mo), tungsten (W), tantalum (Ta) or the like on one or both of the lower side or upper side of a low resistance metal film such as aluminum (Al), copper (Cu), etc. A structure in which a melting point metal film or a metal nitride film thereof (titanium nitride film, molybdenum nitride film, tungsten nitride film) is stacked may be employed. It is preferable to stack a refractory metal film or a metal nitride film thereof on one or both of the lower resistance metal film and the lower resistance metal film, because the metal migration (diffusion) of the low resistance metal film can be inhibited. . That is, the conductive layer for forming the wiring layer 435a and the wiring layer 435b is a stack of the first conductive layer, the metal film as the second conductive layer, and the third conductive layer, and the second conductive layer A low resistance conductive layer is used. A material capable of inhibiting the movement of the metal of the second conductive layer is used for at least one of the first conductive layer and the third conductive layer. Further, when the third conductive layer on the second conductive layer covers the end portion of the second conductive layer, the movement of the metal from the end portion of the second conductive layer can be suppressed. Therefore, it is preferable.

For example, as a conductive layer for forming the wiring layer 435a and the wiring layer 435b, a stack of tungsten (W), copper (Cu), and tantalum nitride is used, and low resistance copper (Cu) is used to move copper. What is necessary is just to sandwich between tungsten (W) and tantalum nitride which inhibit.

The conductive layer used for the wiring layer 435a and the wiring layer 435b may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ —SnO ₂ , abbreviated as ITO), oxidation Indium zinc oxide (In ₂ O ₃ —ZnO) or a metal oxide material containing silicon oxide can be used.

As the wiring layer 435a and the wiring layer 435b, a single layer of molybdenum, a stacked layer of tantalum nitride and copper, a stacked layer of tantalum nitride and tungsten, or the like can be used.

According to this embodiment, in the semiconductor device, the transistor 440a, the transistor 440b, and the transistor 440c with high on-state characteristics that have a minute structure with less variation in shape and characteristics can be provided with high yield.

Therefore, it is possible to provide a semiconductor device that is miniaturized and has high electrical characteristics, and a method for manufacturing the semiconductor device.

Note that the oxide semiconductor layer 403 may have a structure in which a plurality of oxide semiconductor layers are stacked. For example, the oxide semiconductor layer 403 is a stack of a first oxide semiconductor layer and a second oxide semiconductor layer, and the first oxide semiconductor layer and the second oxide semiconductor layer have different metal oxide compositions. May be used. For example, a ternary metal oxide may be used for the first oxide semiconductor layer, and a binary metal oxide may be used for the second oxide semiconductor layer. For example, both the first oxide semiconductor layer and the second oxide semiconductor layer may be ternary metal oxides.

Alternatively, the constituent elements of the first oxide semiconductor layer and the second oxide semiconductor layer may be the same, and the composition ratio of the two may be different. For example, the atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 1: 1, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 3: 1: 2. It is good. The atomic ratio of the first oxide semiconductor layer is In: Ga: Zn = 1: 3: 2, and the atomic ratio of the second oxide semiconductor layer is In: Ga: Zn = 2: 1: 3. It is good.

At this time, the In and Ga contents in the oxide semiconductor layer on the side close to the gate electrode (channel side) of the first oxide semiconductor layer and the second oxide semiconductor layer may be In> Ga. The content ratio of In and Ga in the oxide semiconductor layer far from the gate electrode (back channel side) is preferably In ≦ Ga.

In oxide semiconductors, heavy metal s orbitals mainly contribute to carrier conduction, and increasing the In content tends to increase the overlap of s orbitals. Compared with an oxide having a composition of In ≦ Ga, high mobility is provided. In addition, since Ga has a larger energy generation energy of oxygen deficiency than In, and oxygen deficiency is less likely to occur, an oxide having a composition of In ≦ Ga has stable characteristics compared to an oxide having a composition of In> Ga. Prepare.

By using an oxide semiconductor with an In> Ga composition on the channel side and an oxide semiconductor with an In ≦ Ga composition on the back channel side, the mobility and reliability of the transistor can be further improved. It becomes.

Alternatively, oxide semiconductors having different crystallinities may be used for the first oxide semiconductor layer and the second oxide semiconductor layer. That is, a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, an amorphous oxide semiconductor, or a CAAC-OS may be combined as appropriate. In addition, when an amorphous oxide semiconductor is applied to at least one of the first oxide semiconductor layer and the second oxide semiconductor layer, internal stress and external stress of the oxide semiconductor layer 403 are relieved, The variation in characteristics of the transistor is reduced, and the reliability of the transistor can be further improved.

On the other hand, an amorphous oxide semiconductor easily absorbs an impurity serving as a donor such as hydrogen, and oxygen vacancies easily occur. Therefore, an oxide semiconductor having crystallinity such as CAAC-OS is preferably used for the oxide semiconductor layer on the channel side.

In addition, in the case where a bottom-gate channel etching transistor is used as the transistor, if an amorphous oxide semiconductor is used on the back channel side, oxygen vacancies are generated due to etching treatment when the source electrode and the drain electrode are formed, and the n-type transistor Easy to be. Therefore, in the case of using a channel etching transistor, an oxide semiconductor having crystallinity is preferably used for the oxide semiconductor layer on the back channel side.

Alternatively, the oxide semiconductor layer 403 may have a stacked structure of three or more layers and a structure in which an amorphous oxide semiconductor layer is sandwiched between a plurality of oxide semiconductor layers having crystallinity. Alternatively, a structure in which an oxide semiconductor layer having crystallinity and an amorphous oxide semiconductor layer are alternately stacked may be employed.

The above structures in the case where the oxide semiconductor layer 403 has a stacked structure of a plurality of layers can be used in appropriate combination.

Alternatively, the oxide semiconductor layer 403 may have a stacked structure of a plurality of layers, and oxygen may be supplied after each oxide semiconductor layer is formed. Oxygen can be supplied by heat treatment in an oxygen atmosphere, ion implantation, ion doping, plasma immersion ion implantation, plasma treatment performed in an oxygen-containing atmosphere, or the like.

According to this embodiment, a semiconductor device with improved electrical characteristics can be provided.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

101 Arc chamber 102 Sample chamber 103 Ion acceleration chamber 104 Oxygen plasma chamber 107 Stage 108 Exhaust device 111 Filament 112 Extraction electrode 113 Acceleration electrode 114 Deceleration electrode 115 Ground electrode 116 Anode 120 Object 121a Holding means 121b Holding means 131 Extraction power supply 132 Acceleration power supply 133 Deceleration power supply 134 Gas introduction part 135 Oxygen introduction apparatus 136 Exhaust apparatus 138 Plasma 139 Oxygen plasma 141 Pipe 142 Coil 143 Power supply 145 Oxygen ion supply part 400 Substrate 401 Gate electrode layer 402 Gate insulation layer 402a First gate insulation layer 402b Second Gate insulating layer 403 Oxide semiconductor layer 404 Conductive layer 405a Source electrode layer 405b Drain electrode layer 406a Offset region 406b Offset region 407 Insulating layer 08 Insulating layer 410 Insulating layer 411 Insulating layer 412 Side wall insulating layer 413 Insulating layer 415 Interlayer insulating layer 417 Interlayer insulating layer 433a Opening 433b Opening 435a Wiring layer 435b Wiring layer 436 Base insulating layer 436a First base insulating layer 436b Second base Insulating layer 440a Transistor 440b Transistor 440c Transistor 442 Gate insulating layer 442a First gate insulating layer 442b Second gate insulating layer 445 Conductive layer 446 Insulating layer 447 Insulating layer

Claims (8)

An arc chamber having a gas introduction part into which an inert gas is introduced, and a filament that generates thermal electrons;
A first electrode for extracting ions of an inert gas ionized in the arc chamber;
A second electrode for accelerating ions of the inert gas drawn by the first electrode,
An oxygen ion supplying unit for supplying oxygen ions to a region where ions of the inert gas that is accelerated by the second electrode passes,
A sample chamber in which the said oxygen ions with an inert gas ions is introduced,
I have a,
The doping apparatus according to claim 1, wherein the oxygen ion supply unit generates oxygen ions by converting oxygen into plasma by inductively coupled plasma . In claim 1 ,
The oxygen ion supply unit includes an oxygen introducing device, a tube connected to the oxygen introducing device, and a coil wound around the tube. In claim 2 ,
The doping apparatus characterized in that the material of the tube is quartz glass. In any one of Claims 1 thru | or 3 ,
The doping apparatus according to claim 1, wherein a material of the filament is tungsten. In any one of Claims 1 thru | or 4 ,
The doping apparatus according to claim 1, wherein each of the first electrode and the second electrode is a porous electrode, and a material of the first electrode and the second electrode is tungsten. Current is passed through the filament to generate thermionic electrons,
The thermoelectrons collide with an inert gas to generate ions of the inert gas,
Accelerating the inert gas ions by applying a voltage to the generated inert gas ions with an electrode;
Oxygen is turned into plasma by inductively coupled plasma to generate oxygen ions,
A doping method comprising irradiating an object with the oxygen ions by causing the accelerated inert gas ions to collide with the oxygen ions. Using the doping method according to claim 6 ,
A method for manufacturing a semiconductor device , comprising: forming an insulating layer over a substrate; and irradiating the insulating layer with the oxygen ions. Using the doping method according to claim 6 ,
A method for manufacturing a semiconductor device , wherein the oxide semiconductor layer is irradiated with the oxygen ions.

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