JP5971499B2 - Solar cell and manufacturing method thereof - Google Patents

Description

  The present invention relates to a solar cell and a manufacturing method thereof.

  Patent Document 1 describes a back junction solar cell in which both a p-side electrode and an n-side electrode are provided on the back side as a solar cell that can improve photoelectric conversion efficiency. The solar cell described in Patent Document 1 is provided on a first semiconductor layer provided on a first region of one principal surface of a substrate made of a semiconductor material and on a second region on one principal surface. And a second semiconductor layer. One of the first and second semiconductor layers is p-type and the other is n-type. The second semiconductor layer is provided over the first semiconductor layer from the second region. In the first region, a recombination layer is provided between the first semiconductor layer and the second semiconductor layer. This recombination layer is a layer for reducing the resistance between the p-side electrode and the p-type amorphous semiconductor layer 11p. A substantially intrinsic i-type semiconductor layer is disposed between the second semiconductor layer and the recombination layer.

WO2010 / 098445 A1

  There is a desire to further improve the photoelectric conversion efficiency of solar cells.

  A main object of the present invention is to provide a solar cell having improved photoelectric conversion efficiency.

  A solar cell according to the present invention includes a substrate made of a semiconductor material, a substantially intrinsic i-type semiconductor layer, a first amorphous semiconductor layer, a first microcrystalline semiconductor layer, and a second microcrystalline semiconductor layer. And a second amorphous semiconductor layer. The i-type semiconductor layer is disposed on one main surface of the substrate. The first amorphous semiconductor layer is disposed on a part of the i-type semiconductor layer. The first amorphous semiconductor layer has one conductivity type. The first microcrystalline semiconductor layer is disposed on the first amorphous semiconductor layer. The first microcrystalline semiconductor layer has one conductivity type. The second microcrystalline semiconductor layer is disposed on the first microcrystalline semiconductor layer. The second microcrystalline semiconductor layer has another conductivity type. The second amorphous semiconductor layer is arranged over the second microcrystalline semiconductor layer and the exposed portion of the i-type semiconductor layer from the second microcrystalline semiconductor layer. The second amorphous semiconductor layer has another conductivity type. The second amorphous semiconductor layer and the second microcrystalline semiconductor layer are in contact with each other.

  In the method for manufacturing a solar cell according to the present invention, a substantially intrinsic i-type semiconductor layer is formed on one main surface of a substrate made of a semiconductor material. On the i-type semiconductor layer, a first amorphous semiconductor layer having one conductivity type, a first microcrystalline semiconductor layer having one conductivity type, and a second microcrystalline semiconductor layer having another conductivity type Are formed in this order. A part of the first amorphous semiconductor layer and the first and second microcrystalline semiconductor layers are removed by etching to partially expose the i-type semiconductor layer. A second amorphous semiconductor layer having another conductivity type is formed so as to straddle over the second microcrystalline semiconductor layer and the exposed portion of the i-type semiconductor layer.

  ADVANTAGE OF THE INVENTION According to this invention, the solar cell which has the improved photoelectric conversion efficiency can be provided.

FIG. 1 is a schematic cross-sectional view of a solar cell according to an embodiment of the present invention. FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process of the solar cell in one embodiment of the present invention.

  Hereinafter, an example of the preferable form which implemented this invention is demonstrated. However, the following embodiment is merely an example. The present invention is not limited to the following embodiments.

  Moreover, in each drawing referred in embodiment etc., the member which has a substantially the same function shall be referred with the same code | symbol. The drawings referred to in the embodiments and the like are schematically described, and the ratio of the dimensions of the objects drawn in the drawings may be different from the ratio of the dimensions of the actual objects. The dimensional ratio of the object may be different between the drawings. The specific dimensional ratio of the object should be determined in consideration of the following description.

(Configuration of solar cell 1)
As shown in FIG. 1, the solar cell 1 has a substrate 10n made of a semiconductor material. The substrate 10n has n-type or p-type conductivity. In the present embodiment, specifically, the conductivity type of the substrate 10n is n-type. The substrate 10n can be made of, for example, an n-type crystalline semiconductor material. Specifically, the substrate 10n can be composed of, for example, n-type crystalline silicon. Note that the crystalline semiconductor material includes a single crystal semiconductor material and a polycrystalline semiconductor material. Crystalline silicon includes single crystal silicon and polycrystalline silicon.

  Substrate 10n has a first main surface 10a and a second main surface 10b that mainly receive light. The first main surface 10a is located on the light receiving surface side. Here, the “light receiving surface” means a main surface on the side of mainly receiving light, out of the two main surfaces.

  On the first main surface 10a, a semiconductor layer 17i, a semiconductor layer 17n, and a protective layer 18 are provided in this order. The semiconductor layer 17i is made of a substantially intrinsic i-type semiconductor material. The semiconductor layer 17i can be made of, for example, i-type amorphous silicon. The thickness of the semiconductor layer 17i is preferably a thickness that does not substantially contribute to power generation (for example, about 0.1 nm to 25 nm). The conductivity type of the semiconductor layer 17n is an n-type which is the same conductivity type as the substrate 10n. The semiconductor layer 17n can be made of, for example, n-type amorphous silicon. The protective layer 18 can be made of, for example, silicon nitride. The protective layer 18 may have a function of suppressing surface reflection of incident light as well as a function of protecting the semiconductor layer 17n.

  A substantially intrinsic i-type semiconductor layer 11ia is disposed on the second main surface 10b of the substrate 10n. The i-type semiconductor layer 11ia is disposed on substantially the entire second main surface 10b. The i-type amorphous semiconductor layer 11ia has a thickness that does not substantially contribute to power generation (for example, about 0.1 nm to 25 nm). The i-type amorphous semiconductor layer 11ia can be made of, for example, i-type amorphous silicon.

  A first amorphous semiconductor layer 11na is disposed on a part of the i-type semiconductor layer 11ia. For this reason, a part of the i-type semiconductor layer 11ia is exposed from the first amorphous semiconductor layer 11na. The first amorphous semiconductor layer 11na has the same conductivity type as the substrate 10n. Specifically, the conductivity type of the first amorphous semiconductor layer 11na is n-type. However, the first amorphous semiconductor layer 11na may have a conductivity type different from that of the substrate 10n. The first amorphous semiconductor layer 11na can be made of, for example, n-type amorphous silicon. The thickness of the first amorphous semiconductor layer 11na can be, for example, about 1 nm to 30 nm.

  A microcrystalline semiconductor layer 13 is disposed on the first amorphous semiconductor layer 11na. The thickness of the microcrystalline semiconductor layer 13 is, for example, preferably about 2 nm to 60 nm, and more preferably 2 nm to 30 nm.

  The microcrystalline semiconductor layer 13 includes a first microcrystalline semiconductor layer 13nc and a second microcrystalline semiconductor layer 13pc. The first microcrystalline semiconductor layer 13nc is provided on the first amorphous semiconductor layer 11na. The first microcrystalline semiconductor layer 13nc is in contact with the first amorphous semiconductor layer 11na. The first microcrystalline semiconductor layer 13nc has the same conductivity type as the first amorphous semiconductor layer 11na. Specifically, the conductivity type of the first microcrystalline semiconductor layer 13nc is n-type. The first microcrystalline semiconductor layer 13nc can be made of, for example, n-type microcrystalline silicon. The thickness of the first microcrystalline semiconductor layer 13nc is, for example, preferably about 1 nm to 30 nm, and more preferably 1 nm to 15 nm.

  The second microcrystalline semiconductor layer 13pc is disposed on the first microcrystalline semiconductor layer 13nc. The second microcrystalline semiconductor layer 13pc is in contact with each of the first microcrystalline semiconductor layer 13nc and a second amorphous semiconductor layer 12pa described later. Second microcrystalline semiconductor layer 13pc has a conductivity type different from that of first microcrystalline semiconductor layer 13nc. Specifically, the conductivity type of the second microcrystalline semiconductor layer 13pc is p-type. The second microcrystalline semiconductor layer 13pc can be made of, for example, p-type microcrystalline silicon. The thickness of the second microcrystalline semiconductor layer 13pc is, for example, preferably about 1 nm to 30 nm, and more preferably 1 nm to 15 nm.

  Here, the microcrystalline semiconductor layer refers to a layer including a plurality of semiconductor crystal grains. The microcrystalline semiconductor layer includes a layer that substantially includes only semiconductor crystal grains. The microcrystalline semiconductor layer may include an amorphous region of a semiconductor in addition to the semiconductor crystal grains. Therefore, the microcrystalline semiconductor layer is a layer including a plurality of semiconductor crystal grains, and may be a layer including an amorphous region of a semiconductor similarly to the amorphous semiconductor layer.

  A second amorphous semiconductor layer 12pa is disposed on the second microcrystalline semiconductor layer 13pc and the exposed portion of the i-type semiconductor layer 11ia from the second microcrystalline semiconductor layer 13pc. The second amorphous semiconductor layer 12pa is arranged over the second microcrystalline semiconductor layer 13pc and the exposed portion of the i-type semiconductor layer 11ia from the second microcrystalline semiconductor layer 13pc. Yes. An i-type semiconductor layer is not provided between the second amorphous semiconductor layer 12pa and the second microcrystalline semiconductor layer 13pc. The second amorphous semiconductor layer 12pa is in direct contact with the second microcrystalline semiconductor layer 13pc. The second amorphous semiconductor layer 12pa has a conductivity type different from that of the substrate 10n. Specifically, the conductivity type of the second amorphous semiconductor layer 12pa is p-type. The second amorphous semiconductor layer 12pa can be made of, for example, p-type amorphous silicon. The thickness of the second amorphous semiconductor layer 12pa can be, for example, about 1 nm to 30 nm.

  The second amorphous semiconductor layer 12pa may be composed of a plurality of amorphous semiconductor layers. The second amorphous semiconductor layer 12pa may be configured by, for example, a stacked body of an amorphous semiconductor layer having a relatively low p-type dopant concentration and an amorphous semiconductor layer having a relatively high p-type dopant concentration.

  An n-side electrode 16n is provided on a portion of the second amorphous semiconductor layer 12pa located on the microcrystalline semiconductor layer 13. On the other hand, a p-side electrode 15p is provided on a portion of the second amorphous semiconductor layer 12pa located in a region where the microcrystalline semiconductor layer 13 is not provided. The electrodes 15p and 16n can be made of at least one of metals such as Ag and Cu, for example.

  In the solar cell 1, the microcrystalline semiconductor layer 13 is provided between the first amorphous semiconductor layer 11na and the second amorphous semiconductor layer 12pa. The microcrystalline semiconductor layer 13 is a layer that lowers the resistance between the first amorphous semiconductor layer 11na and the n-side electrode 16n. The microcrystalline semiconductor layer 13 has a defect level that can be a recombination center. For this reason, recombination of electrons and holes is likely to occur in the microcrystalline semiconductor layer 13. Therefore, current flows through the microcrystalline semiconductor layer 13.

(Manufacturing method of solar cell 1)
Next, an example of the manufacturing method of the solar cell 1 will be described.

  First, the i-type semiconductor layer 21ia is formed on the second main surface 10b of the substrate 10n made of a semiconductor material. This i-type semiconductor layer 21ia is for constituting the i-type semiconductor layer 11ia. The thickness of the i-type semiconductor layer 21ia is larger than the thickness of the i-type semiconductor layer 11ia. The i-type semiconductor layer 21ia can be formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Next, on the i-type semiconductor layer 21ia, a first amorphous semiconductor layer 21na having one conductivity type (n-type in this embodiment), a second microcrystalline semiconductor layer 23nc having one conductivity type, and Then, the second microcrystalline semiconductor layer 23pc having another conductivity type (p-type in this embodiment) is formed in this order. These semiconductor layers 21na, 23nc, and 23pc can also be formed by, for example, a CVD (Chemical Vapor Deposition) method, similarly to the i-type semiconductor layer 21ia.

  Next, by removing a part of the first amorphous semiconductor layer 21na and the first and second microcrystalline semiconductor layers 23nc and 23pc by etching, the i-type semiconductor layer 11ia is formed from the i-type semiconductor layer 21ia, and The first amorphous semiconductor layer 11na and the first and second microcrystalline semiconductor layers 13nc and 13pc are formed from the first amorphous semiconductor layer 21na and the first and second microcrystalline semiconductor layers 23nc and 23pc. The etching of the first amorphous semiconductor layer 21na and the first and second microcrystalline semiconductor layers 23nc and 23pc facilitates dissolution of the first amorphous semiconductor layer 21na and the first and second microcrystalline semiconductor layers 23nc and 23pc. It is preferable to use an etchant that hardly dissolves the i-type semiconductor layer 21ia. Examples of such an etchant include an etchant containing hydrofluoric acid.

  Next, the second amorphous semiconductor layer 12pa extends over the second microcrystalline semiconductor layer 13pc and the exposed portion of the i-type semiconductor layer 11ia from the second microcrystalline semiconductor layer 13pc. Form. The second amorphous semiconductor layer 12pa can also be formed by, for example, a CVD (Chemical Vapor Deposition) method.

  Thereafter, the solar cell 1 can be completed by forming the electrodes 15p and 16n. The electrodes 15p and 16n can be formed by, for example, plating or printing of a conductive paste.

  As described above, in the solar cell described in Patent Document 1, a substantially intrinsic i-type semiconductor layer is disposed between the second semiconductor layer and the recombination layer. This i-type semiconductor layer increases the electrical resistivity between the second semiconductor layer and the recombination layer.

  On the other hand, in the solar cell 1, no i-type semiconductor layer is provided between the second microcrystalline semiconductor layer 13pc and the second amorphous semiconductor layer 12pa, and the second microcrystalline semiconductor layer 13pc and the second microcrystalline semiconductor layer 13pc In contact with the amorphous semiconductor layer 12pa. For this reason, the electrical resistivity between the second microcrystalline semiconductor layer 13pc and the second amorphous semiconductor layer 12pa can be lowered. Therefore, improved photoelectric conversion efficiency can be realized.

  Further, after the i-type semiconductor layer 11ia is formed, the second main surface 10b of the substrate 10n is not exposed. For this reason, the fall of the passivation property of the 2nd main surface 10b can be suppressed. In addition, since it is not always necessary to provide an i-type semiconductor layer between the second microcrystalline semiconductor layer 13pc and the second amorphous semiconductor layer 12pa, the manufacturing process of the solar cell 1 can be simplified.

DESCRIPTION OF SYMBOLS 1 ... Solar cell 10n ... Board | substrate 10a ... 1st main surface 10b ... 2nd main surface 11ia ... i-type amorphous semiconductor layer 11na ... 1st amorphous semiconductor layer 12pa ... 2nd amorphous semiconductor layer 13 ... Microcrystalline semiconductor layer 13 nc: first microcrystalline semiconductor layer 13 pc: second microcrystalline semiconductor layer 15 p: p-side electrode 16 n: n-side electrode

Claims (3)

A substrate made of a semiconductor material;
A substantially intrinsic i-type semiconductor layer disposed on one major surface of the substrate;
A first amorphous semiconductor layer disposed on a portion of the i-type semiconductor layer and having one conductivity type;
A first microcrystalline semiconductor layer disposed on the first amorphous semiconductor layer and having the one conductivity type;
A second microcrystalline semiconductor layer disposed on the first microcrystalline semiconductor layer and having another conductivity type;
It extends over the second microcrystalline semiconductor layer and the exposed portion of the i-type semiconductor layer from the second microcrystalline semiconductor layer, and has the other conductivity type. A second amorphous semiconductor layer;
With
A solar cell in which the second amorphous semiconductor layer and the second microcrystalline semiconductor layer are in contact with each other.   The solar cell according to claim 1, wherein the one conductivity type is n-type and the other conductivity type is p-type. Forming a substantially intrinsic i-type semiconductor layer on one main surface of a substrate made of a semiconductor material;
On the i-type semiconductor layer, a first amorphous semiconductor layer having one conductivity type, a first microcrystalline semiconductor layer having the one conductivity type, and a second microcrystal having another conductivity type. Forming a semiconductor layer in this order;
Removing a part of the first amorphous semiconductor layer and the first and second microcrystalline semiconductor layers by etching to partially expose the i-type semiconductor layer;
Forming a second amorphous semiconductor layer having the other conductivity type so as to straddle over the second microcrystalline semiconductor layer and an exposed portion of the i-type semiconductor layer;
The manufacturing method of the solar cell which has this.

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