JP5969813B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that is controlled by a processor having a register.

In order to maintain the program maintainability and the processing speed, and to prevent unauthorized modification and improve the ease of discovering unauthorized modifications, the ROM address 0008H is 000.
The program for the variable stop command transmission process is stored at address FH, the program for the prize ball number command transmission process is stored at addresses 0020H to 0027H of the ROM, and these programs are called using the RST instruction. There is a known gaming machine (for example, Patent Document 1).

  In the configuration of the gaming machine of Patent Document 1, as shown in FIG. 22 of Patent Document 1, when the RST instruction is executed, the return address value of the calling module is stored in the stack and is stored in the calling submodule. Transition. Thereafter, by executing a RET instruction at the end of the callee submodule, the return address value stored in the stack is returned to the program counter, and the caller module is restored. As shown in paragraph [0148] of Patent Document 1, the same processing is performed even when a CALL instruction is used.

  Even if an RST instruction or CALL instruction is not executed as in Patent Document 1, when an interrupt such as a timer interrupt occurs, the return address value of the calling module is stored in the stack and called. There is also a gaming machine that performs processing to shift to the previous submodule (timer interrupt processing module).

  For example, in the gaming machine disclosed in Patent Document 2, when an interrupt such as a timer interrupt occurs as shown in paragraphs [0071] to [0073] of Patent Document 2, the value of the return address of the calling module Is stored in the stack, and the process proceeds to the called sub-module (timer interrupt processing module). Thereafter, the RETI instruction is executed when the callee submodule ends, thereby returning the value of the return address stored in the stack to the program counter and returning to the caller module.

  When performing such timer interrupt processing, as shown in FIG. 5 of Patent Document 3 and FIG. 6C of Patent Document 4, the value of the flag register is stored in the stack as an AF register at the beginning of the processing. It is usually done. Note that the value of the flag register stored in the stack is restored to the original flag register when the timer interrupt processing is completed and the RETI instruction is executed, as shown in FIG. It has become.

JP 2008-080004 A JP 2001-212330 A JP 2004-089476 A JP 2006-068568 A

If the value of the register used in the caller module is changed in the callee submodule, it will hinder the CPU processing. Therefore, in a conventional gaming machine, it is necessary to describe a PUSH instruction or a POP instruction in a call destination module, which causes an increase in program capacity.

The present invention has been made to solve the above-described problems, and an object thereof is to reduce the code amount of a game control program.

In a typical embodiment of the present invention, a game is executed by executing a game when a predetermined start condition is established, and performing a game control for generating a special game state in which a privilege is given to the player when the game has a special result. In the gaming machine provided with the control device, the game control device includes a game control program storage means for storing a game control program, an arithmetic processing means for performing a required arithmetic processing by the game control program, and the arithmetic processing. A register in which a value is stored, and the register includes a first register group and a second register group having the same configuration as the first register group, and the game control In the program, when a predetermined interrupt signal is generated during execution of a main loop routine that repeatedly executes predetermined processing and an instruction described in the main loop routine. An interrupt routine in which a process to be called is described, and the arithmetic processing means can access either the first register group or the second register group, and a predetermined activation signal is received. When this occurs, the first register group can be accessed, and the main loop routine executes processing using the first register group. While the main loop routine is being processed, the predetermined allocation is performed. An interrupt signal can be received, the interrupt routine executes processing using the second register group, and a common subroutine called from the main loop routine and the interrupt routine can be executed. And

  In the embodiment of the present specification, the “game machine” is described as a pachinko machine, but it may be a spinning-type game machine such as a slot machine or a smart ball. Even in a gaming machine other than these pachinko machines, the above-described problem is a problem that occurs as in the case of the pachinko machine.

  The “predetermined start condition” is, for example, a case where a game ball wins a start winning opening if it is a pachinko machine. Further, in the case of a slot machine, for example, the player operates a start lever after betting a game medium.

“ Game ” means that, for example, in a plurality of variable display areas provided with an area (display area) capable of displaying an image on the display screen, identification information is displayed in each variable display area, and each identification symbol is displayed in a variable manner It is a variable display game. The “special result” in the variable display game is, for example, a case where all the identification symbols to be variable displayed stop at the same symbol.

  The “game control program” includes a program for performing progress control of a game and a program for performing effect control. The “game control program” is stored in the “game control program storage means” and is executed by the “arithmetic processing means”. The “game control program storage means” may be readable / writable (volatile) or read-only (nonvolatile). The “arithmetic processing means” is a so-called CPU (or an instruction interpretation execution circuit included in the CPU).

  The “register” stores data accessed by the “arithmetic processing means”. When the “arithmetic processing means” accesses the data stored in the “game control program storage means” or the “update information storage means”, the data may be accessed via a “register” or may be directly accessible.

  The “flag register” is a register that stores a value indicating a calculation state of a CPU (arithmetic processing means). For example, a flag indicating whether the calculation result is positive, a flag indicating whether it is 0, or the like is included. The “arithmetic processing means” refers to the “flag register” to branch the processing or to control the execution order of the processing.

  The “predetermined interrupt signal” includes, for example, a case of outputting at a predetermined time interval (timer interrupt) and a case of outputting when a power failure occurs. When receiving the interrupt signal, the game control device (game control means) executes an interrupt process (second call destination routine) corresponding to the interrupt signal.

  "Stack area" temporarily stores data necessary for returning to the original process when calling another process from the process being executed or when interrupting the current process and executing the interrupt process. It is an area to do. The data stored in the stack area is taken out in the order of the called order and returned to the register or the update information storage means.

According to one aspect of the present invention, the code amount of the game control program can be reduced .

It is a figure explaining the structure of the game device of the 1st Embodiment of this invention. It is a rear view of the gaming machine of the first embodiment of the present invention. It is a front view of the game board of a 1st embodiment of the present invention. It is a block diagram of the gaming machine of the first embodiment of the present invention. 1 is a block diagram of a game arithmetic processing device (amuse chip) according to a first embodiment of the present invention. FIG. It is a block diagram which shows the structural example of the serial transmission circuit in the game control apparatus of the 1st Embodiment of this invention. It is a figure which shows the structural example of the transmission serial channel setting register of the 1st Embodiment of this invention. It is a figure which shows the structural example of the transmission control register of the 1st Embodiment of this invention. It is a figure which shows the structural example of the transmission data status register of the 1st Embodiment of this invention. It is a figure which shows the structural example of the transmission data register (for 1 step | paragraph) of the 1st Embodiment of this invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a game arithmetic processing device (amuse chip) provided in the game control device of the first embodiment of the present invention and its surroundings. It is a block diagram explaining the internal structure of the CPU core of the 1st Embodiment of this invention. It is a figure explaining the structure of the flag register of the 1st Embodiment of this invention. It is a figure which shows an example of the user work RAM of the 1st Embodiment of this invention. It is a figure explaining the specific example of the data stored in the work area allocated to the user work RAM of the 1st Embodiment of this invention, and the holding | maintenance counter, the various random number generation area, and the common random number storage area | region FIG. It is a figure explaining the specific example of the data stored in the work area allocated to the user work RAM of the 1st Embodiment of this invention, and various random numbers required in order to run a 1st special figure fluctuation display game It is a figure which shows the preservation | save area | region. It is a figure explaining the specific example of the data stored in the work area allocated to the user work RAM of the 1st Embodiment of this invention, and various random numbers required in order to run a 2nd special figure fluctuation display game It is a figure which shows the preservation | save area | region. It is a figure which shows an example of the stack area | region of the 1st Embodiment of this invention. It is a figure which shows an example of the stack area | region of the 1st Embodiment of this invention. It is a figure which shows the modification of the stack area | region of the 1st Embodiment of this invention. It is a figure explaining the instruction | indication of the assembly language for describing the game control program performed by CPU core of the 1st Embodiment of this invention, and the code | cord | chord after conversion does not contain an address part (after conversion) FIG. 5 is a diagram showing an instruction) in which the code data of (1) is composed of only an instruction code portion. It is a figure explaining the instruction | indication of the assembly language for describing the game control program performed by CPU core of the 1st Embodiment of this invention, and each of an instruction code part and an address part is added to the code data after conversion. It is a figure which shows the command containing. It is a flowchart of the power-on process of each device (game control device, payout control device, and effect control device) of the first embodiment of the present invention. It is a flowchart explaining the game control apparatus program start preparation process of the 1st Embodiment of this invention. It is a flowchart of the first half part of the game control apparatus main process of the 1st Embodiment of this invention. It is a flowchart of the latter half part of the game control apparatus main process of the 1st Embodiment of this invention. It is a figure explaining the process from step 2501 to step 2502B in the game control apparatus main process of the 1st Embodiment of this invention. It is a figure explaining the delay process of the 1st Embodiment of this invention. It is a flowchart which shows the timer interruption process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the initialization command transmission process which transmits the initialization command signal to the production | presentation control apparatus and the payout control apparatus from the game control apparatus of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the command transmission process for transmitting a command from the game control apparatus of the 1st Embodiment of this invention to an effect control apparatus and a payout control apparatus. It is a timing chart of the state of the serial transmission circuit with which the game control apparatus at the time of power activation of the 1st Embodiment of this invention at the time of power-on, the process which a payout control apparatus, and an effect control apparatus perform, and the game control apparatus. It is a figure which shows an example of the discharge | release instruction | command transmitted to the payout control apparatus from the game control apparatus of the 1st Embodiment of this invention. It is a time chart which shows the procedure which detects the rising of the switch of the 1st Embodiment of this invention. It is a figure which shows an example of the effect control command transmitted to the effect control apparatus from the game control apparatus of the 1st Embodiment of this invention. It is explanatory drawing which shows the structure of the transmission data transmitted to the production | presentation control apparatus from the game control apparatus of the 1st Embodiment of this invention, (a) shows schematic structure of transmission data, (b) is transmission data. The detailed structure of is shown. It is a flowchart which shows the procedure of the special figure game process of the 1st Embodiment of this invention. It is a figure explaining the process of a branch based on the game process number in the special figure game process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the start port SW monitoring process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the special figure starting port SW common process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the special figure pending | holding information determination process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the special figure jackpot determination process of the 1st Embodiment of this invention. It is a latter half fluctuation pattern table of a 1st embodiment of the present invention. It is a first half variation pattern table of the 1st embodiment of the present invention. It is a flowchart which shows the procedure of the special figure normal process of the 1st Embodiment of this invention. It is a flowchart which shows the procedure of the special figure 1 / special figure 2 fluctuation start process of the 1st Embodiment of this invention. It is a figure which shows an example of the program of the process which shifts the starting memory | storage in the 1st Embodiment of this invention, and is a program which reduced the memory capacity using the K register. It is a figure which shows an example of the program of the process which shifts the starting memory | storage in the 1st Embodiment of this invention, and is a conventional program. It is a figure explaining the example of the program which comprises the subroutine of the 1st Embodiment of this invention. It is a figure explaining the screen transition in the variable display game of the 1st Embodiment of this invention. It is a figure explaining the screen transition in the variable display game of the 1st Embodiment of this invention. FIG. 6 is a diagram for explaining a state in which a flag register value is saved in a stack area after a return address value in the first embodiment of the present invention. FIG. 10 is a diagram for explaining a state in which the value of the flag register is saved in the stack area before the return address value in the first embodiment of the present invention. FIG. 10 is a diagram for explaining a state where the return address value and the flag register value are configured with the same number of bytes in the first embodiment of the present invention. FIG. 6 is a diagram for explaining a state in which the return address value and the flag register value are configured with different numbers of bytes in the first embodiment of the present invention. It is a figure which shows an example of the user work RAM of the modification of the 1st Embodiment of this invention. It is a figure which shows the preservation | save area | region from the holding | maintenance 1 to 4 of various random numbers required in order to run the special figure fluctuation display game of the 2nd Embodiment of this invention. It is a figure which shows the preservation | save area | region from the hold | maintains 5-8 of the various random numbers required in order to run the special figure fluctuation display game of the 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the special figure pending | holding information determination process of the 2nd Embodiment of this invention. It is a flowchart which shows the procedure of the special figure normal process of the 2nd Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the following description of the embodiment, front, rear, left, and right refer to directions viewed from the player, that is, viewed from the game board (game machine).

(First embodiment)
FIG. 1 is a diagram illustrating the configuration of the gaming device 6 according to the first embodiment of this invention.

  The gaming device 6 includes a card unit 70 into which a storage medium for storing a valuable value is inserted, and a gaming machine 1 that can actually play a game and pay out the gaming medium.

  First, the gaming machine 1 will be described.

  The front frame 3 of the gaming machine 1 is assembled to the main body frame (outer frame) 2 so as to be capable of opening and closing by a hinge 4. The game board 5 (see FIG. 3) is housed in a storage portion (not shown) formed on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 5 is attached to the front frame 3.

  A decorative member 9 that emits decorative light is provided around the cover glass of the glass frame 18. The decoration member 9 is provided with a decoration device made up of a lamp, LED, or the like. By causing the decoration device to emit light in a predetermined light emitting mode, the decorative member 9 emits light in a predetermined light emitting mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 10 is provided above the glass frame 18. A decoration device is provided inside the lighting unit 10.

  On the right side of the lighting unit 10, an error notification LED 29 is provided for notifying the hall clerk of the occurrence of an error in the gaming machine 1 and the opening of the front frame 3.

  The open / close panel 20 below the front frame 3 is provided with an upper plate 21 for supplying game balls to a hitting ball launching device (not shown). Further, the fixed panel 22 is provided with an ashtray 15, a lower plate 23, an operation unit 24 of a ball hitting device, and the like. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  The upper edge of the upper plate 21 is provided with a select switch 40 and an operation switch 41 for receiving an operation input from a player.

  When the player operates the select switch 40, it is possible to select the contents of the effect of the variable display game on the display device 8 (see FIG. 3). In addition, when the player operates the operation switch 41, it is possible to perform an effect in which the player's operation is intervened in the variable display game on the display device 8.

  A ball lending button 26 that is operated when a player borrows a game medium and a discharge button 27 that is operated to discharge the prepaid card from the card unit 70 are provided on the upper right portion of the upper plate 21. Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.

  Next, the card unit 70 will be described.

  A card insertion slot 71 into which a card such as a prepaid card or a membership card can be inserted is provided below the card unit 70.

  A card such as a prepaid card or a member card stores a unique identifier of the card, member information of the owner (player) of the card, a balance, and the like. The membership information includes the card owner's address, name, age, occupation, and the like.

  When a card such as a prepaid card or a membership card is inserted into the card insertion slot 71, information stored in the card is read by a card reader / writer (not shown). And the balance memorize | stored in the said card | curd is displayed on the balance display part 72 provided near the balance display part 28 of the gaming machine 1 and the card unit 70.

  Above the balance display 72, a bill insertion slot 73 into which bills can be inserted is provided. The valuable value of the banknote inserted into the banknote insertion slot 73 is stored as a balance on the card.

  An operation display unit 74 is provided above the bill insertion slot 73. The operation display unit 74 is lit in a color corresponding to the operation of the card unit 70.

  Next, the back side of the gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine 1 according to the first embodiment of this invention.

  On the back side of the gaming machine 1, specifically, on the back side of the front frame 3, a frame-like back mechanism board 310 having a substantially square opening at the center is attached.

  Above the back mechanism board 310, a ball storage unit 320 is provided that stores game balls replenished from a replenishment device (not shown) provided in the island facility and causes the stored game balls to flow down.

  On the side of the back mechanism board 310 (on the right side in FIG. 2), a ball discharge unit 330 that pays out the game balls flowing down from the ball storage unit 320 to the upper plate 21 and the lower plate 23 disposed in front of the game machine. Is disposed.

  At the center of the back mechanism board 310, there are a game control device 100 that controls the game in an integrated manner, and an effect control device 150 that controls the effect of the variable display game based on the effect control command transmitted from the game control device 100. Is disposed.

  The game control device 100 is provided with an inspection device connection terminal 107 connected to an inspection device (not shown).

  At the bottom of the back mechanism board 310, a payout control device (granting control device) 210 for controlling the operation of the ball discharge unit 330 based on data transmitted from the game control device 100 and giving a prize ball to the player, A power supply device 160 is provided.

  The payout control device 210 is provided with an inspection device connection terminal 217 connected to an inspection device (not shown) and an error number display 222 for displaying the type of error that has occurred in the payout control device 210 in numbers.

  In addition, a card unit connection terminal 340 for connecting the gaming machine 1 to the card unit 70 is disposed on the back mechanism board 310 on the right side of the power supply device 160.

  Next, the game board 5 will be described with reference to FIG. FIG. 3 is a front view of the game board 5 according to the first embodiment of this invention.

  On the surface of the game board 5, a substantially circular game area 51 surrounded by the guide rail 55 is formed. The game area 51 is composed of resin side cases 52 and guide rails 55 provided on each of the four sides of the game board 5. The side case 52 on the lower right side of the game area 51 is covered with a black transparent certificate paper plate 53 at the center of the front surface.

  In the game area 51, a center case 300 provided with the display device 8 is arranged substantially at the center. The display device 8 is attached to a recess provided in the center case 300 at a position deeper than the front surface of the center case 300. That is, the center case 300 surrounds the display area of the display device 8 and is provided so as to protrude from the display area of the display device 8.

  In the lower right area of the game area 51, a symbol display unit (collective display) 45 in which a special figure display 120 and a general display display 121 described later in FIG. 4 are integrated is provided.

  The display device 8 has a display screen composed of, for example, an LCD (liquid crystal display), a CRT (CRT), or the like. The display screen image area (display area) has a plurality of variable display areas. Each variable display area produces identification information (special symbols) and special symbol (special symbols) variable display games. Character to be displayed. In the variable display area of the display screen, three special symbols assigned as identification information are displayed in a variable display (variable display), and a special map variable display game is played. In addition, an image (for example, jackpot display, fanfare display, ending display, etc.) based on the progress of the game is displayed on the display screen.

  A normal symbol starting gate 31 is provided on the left side of the center case 300. Three general winning openings 32 are provided on the lower left side of the center case 300, and one general winning opening 32 is provided on the lower right side of the center case 300.

  Below the center case 300, the first start winning opening 37 is arranged directly below the first starting winning opening 37, and is opened in a reverse “C” shape at the top so that the game ball can easily flow in. And a second start winning opening 34 having a normal variation winning device 33 including a pair of opening and closing members. And when a game ball wins the 1st start winning opening 37 or the 2nd starting winning opening 34, a special figure change display game is performed as an auxiliary game. That is, the start condition for starting the special figure changing display game is that the game ball wins at the first start winning opening 37 or the second starting winning opening 34. The winning opening 34 forms a variable starting winning device that generates the starting condition. The special figure variation display game executed when the game ball is won at the first start winning opening 37 is referred to as a first special figure fluctuation display game, and is executed when the game ball is won at the second start winning opening 34. The special figure fluctuation display game is referred to as a second special figure fluctuation display game.

  Further, below the start winning opening provided in the center case 300, a special variation that can be converted into a state in which a game ball is not accepted and a state in which it is easy to accept depending on the operation result of the display device 8 (result of the special figure variation display game). A winning device (large winning opening) 36 is provided.

  In the gaming machine 1, a game is played by launching a game ball (pachinko ball) from a launcher (not shown) toward the game area 51. The launched game ball flows down the game area 51 while changing the rolling direction by a direction changing member such as a nail or a windmill arranged in various places in the game area 51. Then, the normal symbol starting gate 31, the general winning port 32, the first starting winning port 37, the second starting winning port 34, or the special variable winning device 36 is won, or an out port provided at the bottom of the game area 51 39 is discharged.

  In addition, the state of the second start winning opening 34 includes a state in which the game ball is likely to win a prize (easy winning state) and a state where the game ball is difficult to win (a non-winning easy state) by opening and closing the normal variation winning device 33. is there.

  Usually, when the normal variation winning device 33 is in the closed state, the second start winning port 34 is in a state where it is difficult for the game ball to win. When the game ball passes through the normal symbol start gate 31, the general variation display game is executed, and when the result of the general variation display game is hit, the normal variation winning device 33 is converted to the open state, and the second start The winning opening 34 is in a state where a game ball can easily win.

  The winning of a game ball in the general winning opening 32 is detected by winning openings SW (switches) 32A to 32N (see FIG. 4) provided in the general winning opening 32.

  The winning of a game ball in the first start winning opening 37 is detected by a first special figure start SW (switch) 37A (see FIG. 4). Various random numbers extracted according to the passing timing of the game ball are stored in the special figure 1 start storage area in the game control device 100 as a special symbol winning memory for a predetermined number of times (for example, a maximum of four times).

  Also, the winning of a game ball in the second start winning opening 34 is detected by a second special figure start SW (switch) 34A (see FIG. 4). Various random numbers extracted according to the passing timing of the game ball are stored in the special figure 2 start storage area in the game control device 100 as a special symbol winning memory for a predetermined number of times (for example, a maximum of four times).

  Based on these special symbol winning memories, the game control device 100 uses the special symbol display 120 (see FIG. 4) forming the symbol display unit 45 to display the first special symbol dynamic display game and the second special graphic dynamic display game. I do.

  Here, the special figure display 120 will be described. The special figure indicator 120 includes a first special figure display unit, a first special figure winning memory number display unit, a second special symbol symbol display unit, and a second special figure winning memory number display unit (not shown).

  When the game ball wins the first start winning opening 37 and a special symbol winning memory is generated, the number of special symbol winning memories stored is displayed on the first special symbol winning memory number display section, and the first special symbol display is displayed. The first special figure variation display game is executed in the section. Similarly, when the game ball wins the second start winning opening 34 and the special symbol winning memory is generated, the number of the special symbol winning memory is displayed on the second special symbol winning memory display section, and the second special symbol memory is displayed. The second special figure variation display game is executed on the display unit.

  Note that when the winning to the first start winning opening 37 is made at a predetermined timing (specifically, when the winning random number at the time of winning detection is a winning value), the first special figure variation display game is displayed. As a result, a special result mode is derived from the display symbol. Specifically, a corresponding specific symbol (for example, any number from “1” to “9”) is stopped and displayed on the first symbol display unit. If the first special figure variation display game is out of play, a symbol corresponding to the outage (for example, “0” or the like) is stopped and displayed in the first special figure display section.

  Similarly, when a winning at the second start winning opening 34 is made at a predetermined timing (specifically, when the winning random number at the time of winning detection is a winning value), the second special figure variation display game. As a result of the above, a special result mode is derived from the display symbol. Specifically, the corresponding special symbol (for example, any number from “1” to “9”) is stopped and displayed on the second special symbol display unit. When the second special figure variation display game is out of play, a symbol corresponding to the outage (for example, “0” or the like) is stopped and displayed in the second special symbol display unit.

  When the special result mode is derived as a result of the first special figure variation display game, or when the special result mode is derived as a result of the second special figure variation display game, the big hit state (special game state) ) Occurs. At this time, the special variable prize winning device 36 is opened so that it can easily accept a game ball from a closed state in which it does not accept a game ball for a predetermined time (for example, 30 seconds) by energizing a large prize opening solenoid 38 (see FIG. 4). Converted to a state. That is, since the special variable winning device 36 opens greatly until a predetermined time or a predetermined number of game balls wins, a privilege that the player can acquire many game balls during this time is given.

  In the display device 8 as well, a decorative special symbol variation display game is executed in synchronization with the first special symbol variation display game and the second special diagram variation display game executed on the special symbol display unit 120 of the symbol display unit 45. Is done. At this time, the special symbol (identification information) composed of the numbers and the like described above starts variable display in the order of left (first special symbol), right (second special symbol), middle (third special symbol), An image related to the decorative special figure variation display game is displayed.

  When the first special figure fluctuation display game or the second special figure fluctuation display game derives the special result mode, the display device 8 also derives the symbol of the specific mode and displays it in a stopped state. Specifically, the display device 8 stops in a state where three special symbols are aligned (a jackpot symbol). When the first special figure fluctuation display game and the second special figure fluctuation display game do not derive the special result mode, the display device 8 is controlled not to stop and display the symbols of the specific mode.

  In the present embodiment, both the first special figure fluctuation display game and the second special figure fluctuation display game executed by the symbol display unit 45 and the decorative special figure fluctuation display game executed by the display device 8 are special. It shall be handled as a figure variation display game.

  The winning of the game ball to the special variation winning device 36 is detected by a count SW (switch) 36A (see FIG. 4).

  The passing of the game ball to the normal symbol start gate 31 is detected by a normal start SW (switch) 31A (see FIG. 4). The usual figure random number extracted by the passing timing of the game ball is stored in the usual figure starting storage area in the game control apparatus 100 as a normal symbol winning memory for a predetermined number of times (for example, a maximum of four times). The game control device 100 plays a universal symbol display game on the universal symbol display 121 (see FIG. 4) forming the symbol display unit 45 based on the normal symbol winning memory.

  Here, the general map display 121 will be described. The universal symbol display device 121 has a universal symbol display unit and a universal symbol winning memory number display unit (not shown). As described above, when the game ball passes through the normal symbol start gate 31 and the normal symbol winning memory is generated, the normal symbol change display game is executed in the normal symbol display section. In addition, the number of stored normal symbol winning memories is displayed on the common symbol winning memory number display section.

  When the game ball passes through the normal symbol start gate 31 and the normal symbol winning memory is generated, the number of the normal symbol winning memory is displayed on the general symbol winning memory number display portion, and the normal symbol display portion displays the normal symbol. A variable display game is executed.

  In addition, when the normal symbol start gate 31 is passed at a predetermined timing (specifically, when the winning random number at the time of passing is a winning value), the normal symbol displayed on the normal symbol display unit is displayed. The symbol stops in the hit state, and the normal figure change display game is won. At this time, the normal variation winning device 33 is energized to the ordinary solenoid 90 (see FIG. 4), and the entrance to the second starting winning port 34 is for a predetermined time (for example, 0.5 seconds to 2.9 seconds). The game ball is converted to be released only for a predetermined time within the range, and the winning of the game ball to the second start winning opening 34 is allowed. This makes it easier for the game ball to win the second start winning opening 34 and facilitates the start of the second special figure variation display game.

  In this way, when a game ball wins the general winning opening 32, the first starting winning opening 37, the second starting winning opening 34, or the special variable winning winning device 36, the number of winning balls according to the type of winning winning opening. Is discharged from the dispensing unit controlled by the dispensing control device 210 to the upper plate 21 or the lower plate 23 of the front frame 3.

  Note that the pachinko gaming machine according to the present embodiment corresponds to the result of the special figure fluctuation display game (strictly, it corresponds to the symbol that is stopped and displayed on the special figure display device 120 as a result of the special figure fluctuation display game). ), The probability of hitting the special figure variation display game thereafter may change, and the gaming state is always a low probability state where the special figure variation display game is a big hit with a low probability or a special figure than the low probability state. The variable display game is set to one of high probability states with a high probability of winning a big hit. The low probability state may be referred to as a normal state or a non-probability variation gaming state, and the high probability state may be referred to as a probability variation gaming state (probability variation state).

  Furthermore, in the gaming state of the pachinko gaming machine according to the present embodiment, the opening frequency of the normal variation winning device 33 may change corresponding to the result of the special figure variation display game, and the gaming state is always the normal variation winning. Either the winning suppression state in which the opening frequency of the device 33 is low or the winning promotion state in which the opening frequency of the normal variation winning device 33 is higher than that in the winning suppression state is set. The winning suppression state may be referred to as a normal state or a non-short-time gaming state, or the winning promotion state may be referred to as a short-time gaming state (short-time state).

  In the winning promotion state, the execution time of the normal fluctuation display game is controlled to be shorter than the execution time in the winning suppression state (for example, 10 seconds in the winning suppression state and 1 second in the winning promotion state). As a result, the number of times the normally variable winning device 33 is opened per unit time is controlled to be substantially increased.

  Further, in the winning promotion state, when the normal variation winning device 33 is released as a result of the normal fluctuation display game being won, the opening time may be controlled to be longer than the opening time of the normal gaming state. (For example, 2.9 seconds in the winning promotion state versus 0.5 seconds in the winning suppression state). Further, in the winning promotion state, the normal variation winning device 33 may be opened a plurality of times (for example, twice) instead of once for a single winning result of the normal symbol variation display game. Further, in the winning promotion state, control may be performed so that the probability that the result of the normal-variation display game is a win is higher than the winning suppression state. That is, in the winning promotion state, the opening frequency of the normal variation winning device 33 increases more than in the winning suppression state, and it becomes easier for a game ball to win the normal variation winning device 33 and the special figure variable display game can be easily started. Is granted.

  FIG. 4 is a block diagram of the gaming apparatus 6 according to the first embodiment of this invention.

  The game control device 100 includes a game microcomputer (game calculation processing device 600) 101, an input I / F (Interface) 105, an output I / F (Interface) 106, and an inspection device connection terminal 107.

  The gaming microcomputer 101 includes a CPU 102, a ROM (Read Only Memory) 103, and a RAM (Random Access Memory) 104.

  The CPU 102 is a main control device that controls the game in an integrated manner, and performs game control. The ROM 103 stores invariant information (program, data, etc.) for game control. The RAM 104 is used as a work area during game control.

  The game control device 100 is provided with an inspection device connection terminal 107 capable of outputting an identification number uniquely set in the game microcomputer 101. When an inspection device (not shown) is connected to the inspection device connection terminal 107, the inspection device can identify the gaming machine 1.

  The CPU 102 receives various detectors (first special figure start SW 37A, second special figure start SW 34A, general figure start SW 31A, count SW 36A, and winning opening SW32A to winning opening SW32N, overflow SW (switch) via the input I / F 105. 109, receiving a detection signal from the ball break SW (switch) 110 and the frame opening SW (switch) 111), various processes such as a big hit lottery are performed.

  The overflow switch 109 detects that a predetermined number or more of game balls are stored in the lower plate 23. The ball break switch 110 is disposed in the ball storage unit 320 and detects that the number of game balls stored in the ball storage unit 320 is less than or equal to a predetermined number. The frame opening switch 111 detects the opening of the front frame 3.

  In addition, the CPU 102, via the output I / F 106, displays a general-purpose indicator 121, a special-purpose indicator 120, a general electric power SOL (solenoid) 90, a special winning opening SOL (solenoid) 38, a payout control device 210, and an effect control device. A command signal is transmitted to 150, and the game is comprehensively controlled.

  As described above, the universal map display 121 displays a universal map display game. As described above, the special figure display 120 displays the first special figure fluctuation display game and the second special figure fluctuation display game.

  The general electric power SOL 90 opens the normal variation winning device 33 constituted by an opening / closing member provided in the second starting winning port 34 for a predetermined time so that a game ball can be won in the second starting winning port 34. .

  The big prize opening SOL38 is in an open state (advantageous to the player) from the closed state (a disadvantageous state for the player) that does not accept the game ball for a predetermined time. State).

  In addition, the game control device 100 outputs information related to the gaming machine 1 to an information collection terminal or a game hall internal management device (not shown) installed in the game store via the external information terminal 108.

  The game control device 100 transmits a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like to the effect control device 150 as an effect control command signal.

  Next, the payout control device 210 and the effect control device 150 will be described.

  The effect control device (display control device) 150 includes an error notification LED 29, a speaker 30, a decorative member 9 (FIG. 1) that performs a game effect by light emission, and the display device 8 based on various signals input from the game control device 100. Control.

  The effect control device 150 includes a game microcomputer (game operation processing device 600) 151, a driver 155, a sound circuit 156, and a VDP 157.

  The gaming microcomputer 151 includes a CPU 152, a ROM 153, and a RAM 154.

  The CPU 152 is a control device that performs effect control. The ROM 153 stores invariant information (programs, data, etc.) necessary for production control. The RAM 154 is used as a work area during production control.

  The driver 155 controls the error notification LED 29 and the decoration member 9 according to a command from the CPU 152. The sound circuit 156 generates a sound effect according to a command from the CPU 152 and outputs it from the speaker 30. The VDP 157 generates image data in response to a command from the CPU 152 and outputs the image data to the display device 8.

  Based on the prize ball command signal from the game control device 100, the payout control device 210 drives the payout motor 220 of the payout device and performs control for paying out the prize ball. Also, the payout control device 210 drives the payout motor 220 of the payout device based on the discharge command signal transmitted from the game control device 100 based on the loan request signal from the card unit 70, and pays out the rental money. Control to make it happen.

  The payout control device 210 includes a game microcomputer (game operation processing device 600) 211, an input I / F (Interface) 215, an input / output I / F (Interface) 216, and an inspection device connection terminal 217.

  The gaming microcomputer 211 includes a CPU 212, a ROM 213, and a RAM 214.

  The CPU 212 is a control device that comprehensively controls the payout and controls the payout control. The ROM 213 stores invariant information (program, data, etc.) for payout control. The RAM 214 is used as a work area during payout control.

  The CPU 212 receives inputs from the payout ball detection switch 112, the overflow switch 109, the ball break switch 110, the error release switch 223, the tax rate setting switch 226, and the lending fee setting switch 227 via the input I / F 215.

  The error release switch 223 is operated by the store clerk of the amusement store to cancel the error state when the cause of the error generated by the store clerk of the amusement store is resolved when an error occurs in the payout control device 210. It is a switch.

  The tax rate setting switch 226 is a switch for setting a tax rate of indirect tax imposed on the rental of game balls. The rental fee setting switch 227 is a switch for setting the valuable value of the game balls to be lent.

  Further, the CPU 212 transmits a command signal to the payout motor 220, the launch control device 221, the error number display 222, the tax rate display 224, and the rental charge display 225 via the input / output I / F 216. In addition, the CPU 212 receives various signals transmitted from the game control device 100 via the input / output I / F 216.

  The payout motor 220 is a motor that is actually driven to pay out the game ball by the payout device. Specifically, the payout motor 220 pays out the game ball by rotating a sprocket having a predetermined number of recesses capable of storing one game ball.

  The launch control device 221 controls a launch device for launching a game ball onto the game board 5. The error number display 222 is disposed on the back side of the payout control device 210 and displays the type of error that has occurred in the payout control device 210 so that it can be specified.

  The tax rate indicator 224 is disposed on the back side of the payout control device 210 and displays the tax rate of the indirect tax set by the tax rate setting switch 226. The rental charge indicator 225 is disposed on the back side of the payout control device 210 and displays the valuable value of the game balls to be lent set by the rental charge setting switch 227.

  The power supply device 160 includes a backup power supply 161 and a RAM clear switch 162. The game control device 100, the effect control device 150, and the payout control device 210 are connected to the power supply device 160.

  The backup power supply 161 supplies power to the game control device 100, the effect control device 150, and the payout control device 210 even during a power failure. It is not always necessary to supply power to the effect control device 150, and a command may be transmitted from the game control device 100 after recovery from a power failure.

  The RAM clear switch 162 is a switch that initializes information stored in the RAM 104 provided in the game control device 100 and the RAM 214 provided in the payout control device 210.

  Further, when the ball lending button 26 provided in the gaming machine 1 is operated, the card unit 70 subtracts the valuable value for the gaming ball to be lent from the valuable value stored in the card such as the prepaid card or the membership card. The value of the subtracted valuable value is displayed on the balance display unit 28 of the gaming machine 1. Further, when the discharge button 27 provided in the gaming machine 1 is operated, the card unit 70 discharges the card inserted into the card insertion slot 71.

  The game microcomputer 101 provided in the game control device 100 and the game microcomputer 211 provided in the payout control device 210 are connected to each other so that an encrypted encrypted signal (encrypted data) can be bidirectionally communicated. Further, an unencrypted signal (plaintext data) that is not encrypted is connected to the gaming microcomputer 211 provided in the payout control device 210 from the gaming microcomputer 101 provided in the gaming control device 100 so as to be able to perform one-way communication.

  In addition, the gaming microcomputer 101 provided in the game control device 100 and the gaming microcomputer 151 provided in the effect control device 150 are configured to simply transmit an unencrypted unencrypted signal (plaintext data) from the game control device 100 to the effect control device 150. It is connected so that it can communicate in the direction.

  Note that the game microcomputer 101 provided in the game control device 100, the game microcomputer 151 provided in the effect control device 150, and the game microcomputer 211 provided in the payout control device 210 include ports necessary for these connections.

  Next, with respect to the gaming microcomputer 101 provided in the game control device 100, the gaming microcomputer 151 provided in the effect control device 150, and the gaming microcomputer 211 provided in the payout control device 210 (hereinafter collectively referred to as gaming arithmetic processing device 600). This will be described in detail with reference to FIG.

  FIG. 5 is a block diagram of the game processing device (amuse chip) 600 according to the first embodiment of this invention.

  The game processing unit 600 is manufactured as an IC for a so-called amuse chip, and is divided into a game area unit 600A for performing game control and an information area unit 600B for managing information.

  First, the game area unit 600A includes a CPU core 601, user program ROM 602, HW parameter ROM 603, user work RAM 604, mirrored RAM 605, external bus interface (I / F) 606, bus switching circuit 607, random number generation circuit 608, clock generation circuit. 609, interrupt control circuit 610A, reset circuit 610B, address decoder 611, output control circuit 612, boot block 613, decryption / ROM writing circuit 614, serial transmission circuit 615A, serial transmission circuit 615B, serial reception circuit 625, encryption The transmission / reception circuit 616 and the bus 617 are included. The serial transmission circuit 615A and the serial transmission circuit 615B are collectively referred to as a serial transmission circuit 615.

  The CPU core 601 corresponds to the CPU 102, the CPU 152, or the CPU 212 in FIG. The user program ROM 602 corresponds to the ROM 103, ROM 153, or ROM 213 in FIG. The user program ROM 602 and the HW parameter ROM 603 are collectively referred to as ROM (nonvolatile storage means).

  The user work RAM 604 corresponds to the RAM 104, RAM 154, or RAM 214 in FIG. The user work RAM 604 and the mirrored RAM 605 are collectively referred to as RAM (volatile storage means).

  The CPU core 601 functions as arithmetic processing means for performing arithmetic processing for game control. The user program ROM 602 stores a control program. The control program is a game control program for controlling a game when the game arithmetic processing device 600 is the game microcomputer 101 provided in the game control device 100. In addition, when the game calculation processing device 600 is the game microcomputer 211 provided in the payout control device 210, it is a payout control program for paying out game balls. Furthermore, when the game arithmetic processing device 600 is the game microcomputer 151 provided in the effect control device 150, it is an effect control program for controlling the effect.

  The HW parameter ROM 603 stores validity confirmation information. The legitimacy confirmation information is information in the case of performing a simple check of the legitimacy of the gaming arithmetic processing device 600. For example, a unique ID indicating a unique identifier of the gaming machine 1, a manufacturer code (manufacturer of the gaming machine 1) A unique identifier assigned to each manufacturer), a rank code indicating the rank (1 type, 2 type, etc.) of the gaming machine 1, a model code set by the manufacturer for the type of the gaming machine 1, and an inspection number. An inspection code to be displayed, a RAM backup code indicating whether or not to back up the RAM when the power is turned on, a tax rate set by the tax rate setting switch 226, a lending fee set by the lending fee setting switch 227, and the like. Further, the HW parameter ROM 603 stores only one unique ID that is a unique identifier of the inspection apparatus that first transmitted the lending information request.

  When the third party organization or the manufacturer of the gaming machine 1 writes the program in the user program ROM 602, the validity confirmation information is written in the HW parameter ROM 603. The gaming processing unit 600 can perform a simple check as to whether or not the program written in the user program ROM 602 is valid when the power is turned on. Specifically, at the time of power-up of the gaming arithmetic processing device 600, the arithmetic value calculated by the gaming arithmetic processing device 600 itself and the validity confirmation information (that is, a result value preset by a third party organization or the like) Can be checked for a simple game processing unit 600.

  The user work RAM 604 is used as a work area (work area) when executing processing based on a program in the game area 600A. Since the user work RAM 604 is supplied with the backup power from the backup power supply 161 (FIG. 4), the stored data is retained even if the power supply to the gaming machine 1 is interrupted. The mirrored RAM 605 duplicates the information stored in the user work area at the fall of the clock and stores the duplicated information (if the CPU core is Z80, the process is executed at the rise of the clock. To prevent it from moving).

  The external bus interface 606 is an interface such as a memory request signal MREQ, an input / output request signal IORQ, a memory write signal WR, a memory read signal RD, and a mode signal MODE, and the bus switching circuit 607 is a 16-bit address signal A0. ˜A15 and 8-bit data signals D0 to D7.

  For example, if the data signals D0 to D7 are added while sequentially increasing the address signals A0 to A15 while the MODE signal is at a high level, the writing mode to the user program ROM 602 is set, and the gaming machine 1 manufacturer or The program can be written by a third party. Note that the write mode allows a program to be written, and does not allow a boot program stored in the boot block 613 to be written.

  Further, when the writing of the program to the user program ROM 602 is completed, a writing end code is recorded in a predetermined area of the HW parameter ROM 603 (for example, recorded by physically cutting a predetermined code or a predetermined bit). Thus, when a write end code is recorded in the HW parameter ROM 603, a new program cannot be written in the user program ROM 602.

  The random number generation circuit 608 generates a random number related to whether or not to add a game value (for example, jackpot) in the game execution process (random numbers are used to determine jackpots or symbols when stopped). A mathematical method (for example, a congruent method or an M-sequence method) for generating a uniform random number is used. Note that when the gaming arithmetic processing device 600 is the gaming microcomputer 211 provided in the payout control device 210, the random number generation circuit 608 is not necessary.

  The clock generation circuit 609 divides a system clock signal input from the outside of the gaming arithmetic processing device 600 and generates various periodic signals necessary for game control. Specifically, a clock signal for operating the CPU core 102, a clock signal for updating the random number counter value of the random number generation circuit 608, a timing signal for serial transmission / reception, and the like are generated. The clock generation circuit 609 has a CTC (Counter Timer Circuit) function, and a timer interrupt signal for causing the CPU core 102 to perform timer interrupt processing at a predetermined cycle (for example, 4 milliseconds). Has also generated.

  The interrupt control circuit 610A notifies the CPU core 102 of the occurrence of an interrupt based on the establishment of a predetermined interrupt condition. Note that the predetermined interrupt condition is that an interrupt request signal (INT signal, NMI signal) is input from the outside of the gaming arithmetic processing device 600, or a timer interrupt signal is output from the CTC of the clock generation circuit 609. This is the case.

  When an INT signal or an NMI signal is input, the CPU core 102 interrupts the currently executing process and executes a predetermined interrupt process. Note that interrupt (maskable interrupt) by the INT signal can be prohibited by program setting, but interrupt by NMI signal (non-maskable interrupt) cannot be prohibited by program setting. In addition, when the timer interrupt signal is output, the CPU core 102 executes the timer interrupt process shown in FIG.

  Further, when the reset circuit 610B detects a reset signal (signal RST0 from the RST0 terminal) input from the outside, the reset circuit 610B transmits the reset signal to each circuit and the CPU core 102 provided in the game arithmetic processing device 600. .

  Note that the reset circuit 610B also functions as the security circuit 630 (see FIG. 11). The security circuit 630 has a function of detecting that an abnormal access has occurred to each circuit provided in the game arithmetic processing device 600. When an abnormality is detected, a reset signal is sent to the CPU core 102. To communicate.

  The address decoder 611 decodes the location of the built-in device and the built-in control / status register group by the memory mapped I / O method and the I / O mapped I / O method.

  The output control circuit 612 performs signal control from the address decoder 611 and outputs an 8-bit chip select signal (CS0 to CS7) from an external terminal to the outside, and includes a circuit provided inside the game processing unit 600. It has a function of generating a chip select signal to be selected. The boot block 613 stores a boot program and performs processing related to initialization of the gaming arithmetic processing device 600 when the power is turned on.

  The decryption / ROM writing circuit 614 is used in the writing mode to the user program ROM 602 and the HW parameter ROM 603, and passes through the bus switching circuit 607 while the mode signal MODE is at the [H] level. The address signals A0 to A15 and the data signals D0 to D7 are fetched and the information (encrypted program and encrypted unique ID after change) included in the data signals D0 to D7 is decrypted, and then the bus The data is output (written) to the user program ROM 602 and the HW parameter ROM 603 via 617.

  The serial transmission circuit 615A and the serial transmission circuit 615B are circuits for transmitting plaintext data that is not encrypted. The serial transmission circuit 615A is connected to the effect control device 150 via the SIOTX0 terminal. The serial transmission circuit 615B is connected to the payout control device 210 via the SIOTX1 terminal. The serial receiving circuit 625 is a circuit for receiving unencrypted plain text data via the SIORX terminal.

  The encrypted transmission / reception circuit 616 is a circuit that transmits / receives encrypted data encrypted via the NJLINK terminal. For example, it is used when data is transmitted from the game control device 100 to the payout control device 210. Also, the game control device 100 and the payout control device 210 are connected by an NJLINK connection and are connected to the encrypted transmission / reception circuit 616. Is connected to the NJLINK signal line. The encrypted transmission / reception circuit 616 transmits / receives data via the NJLINK signal line.

  The bus 617 includes a data bus (data bus 660 in FIG. 11), an address bus (address bus 650 in FIG. 11), and a control bus, and extends to the information area 600B.

  Next, an information area unit 600B for managing information in the game processing unit 600 includes an HPG program ROM 618, an ID property memory 619, a bus monitor circuit 620, an HPG work RAM 621, a control circuit 622, an external communication control circuit 623, and a bus 624. , And a part of the bus 617 extending from the game area 600A.

  The HPG program ROM 618 stores an HPG program for performing various inspection operations.

  In the ID property memory 619, the information stored in the HW parameter ROM 603 can be immediately output to the inspection device (not shown) based on the request received from the inspection device (not shown) via the external communication control circuit 623. The information stored in the HW parameter is duplicated and stored when the computer processing unit 600 is powered on (system reset). The ID property memory 619 can be accessed from both the game area 600A side and the information area 600B side.

  The bus monitor circuit 620 monitors and controls the state of the bus 617 on the game area 600A side from the information area 600B side. The control here refers to timing control when the contents of the HW parameter ROM 603 are copied to the ID property memory 619, or when the program stored in the user program ROM 602 is output to the outside (the bus 617 on the game area 600A side is connected). Timing control at the time of opening and reading a program from the user program ROM 602 and outputting it to the outside from the information area 600B side. The program is output after being encrypted by the external communication control circuit 623.

  The HPG work RAM 621 is used as a work area (work area) when executing processing based on a program in the information area unit 600B.

  The control circuit 622 controls the information area 600B side and has a buffer memory. For example, the control circuit 622 monitors the operation of the CPU core 102 via the bus monitor circuit 620 and copies the contents stored in the user work RAM 604 of the game area unit 600A to the mirrored RAM 605 during non-operation. Further, the contents of the ID property memory 619 of the information area unit 600B are transferred to the outside in response to a request from an inspection apparatus (not shown), or the program in the user program ROM 602 is received via the bus monitor circuit 620 in response to a program request. To the outside. The memory of the control circuit 622 is used for timing adjustment at the time of transfer.

  The external communication control circuit 623 communicates with an inspection device (not shown). For example, information (for example, a unique ID, a program, an actual payout) stored in the game processing device 600 based on a command from the outside. The number is encrypted, and then transferred to the outside.

  In the game processing unit 600, the game area unit 600A and the information area unit 600B operate independently via the bus monitor circuit 620. That is, the information area 600B side can operate regardless of the operation of the CPU core 102 in the game area 600A (regardless of the program execution).

  Although not shown in FIG. 5, the gaming arithmetic processing device 600 includes a RAM access restriction circuit (update restriction means) 640 described later in FIG.

  FIG. 6 is a block diagram illustrating a configuration example of the serial transmission circuit 615 in the game control apparatus 100 according to the first embodiment of this invention.

  The serial transmission circuit 615 includes a transmission serial channel setting register 633, a transmission data status register 631, a transmission control register 632, a transmission data register 635 (transmission data buffer register 635A, transmission data shift register 635B), a baud rate generation circuit (transmission speed setting means) 634.

  The serial transmission circuit 615 selects a transmission destination based on the selection signal input from the output control circuit 612. Also, when the input of the reset signal is accepted, the values set in the various registers are cleared to zero.

  The transmission serial channel setting register 633 is a register for designating a communication speed and a communication format at the time of data transmission. Each value is set in the transmission serial channel setting register 633 by serial communication setting processing in main processing described later.

  FIG. 7 is a diagram illustrating a configuration example of the transmission serial channel setting register 633 according to the first embodiment of this invention. As shown in FIG. 7, the transmission serial channel setting register 633 has 16 bits, and all bits 0 to 15 can be written / read.

  In the transmission serial channel setting register 633, bits 0 to 12 are set with a baud rate setting value (for example, a frequency division ratio) for calculating a transmission baud rate (communication speed).

  Specifically, a value obtained by dividing the frequency (unit: Hz) of the system clock (MCLK) input to the game processing unit 600 by 32 and further divided by this baud rate set value is the transmission baud rate. It is set as (number of bits of data transmitted per second). For example, if 100 is set as the baud rate setting value, and the system clock frequency is 20 MHz, the transmission baud rate is 20,000,000 / 32/100 = 6250 (bps).

  Bit 13 is set to “0” when the transmission data length is 8 bits, and is set to “1” when the transmission data length is 9 bits.

  Bit 14 is set to “0” when no parity is added to transmission data, and is set to “1” when parity is added. Bit 15 is set to “0” when the parity added to the transmission data is an even parity, and is set to “1” when the parity is an odd parity. Bit 15 is valid when bit 14 is set to “1” (with parity).

  When a reset signal (RST0) is input to the game processing unit 600, the serial transmission circuit 615 is reset, and all the bits of the transmission serial channel setting register 633 are set to “0” (see FIG. 6 and the like). reference).

  Returning to the description of FIG. 6, the transmission control register 632 is a register for controlling the operation of the serial transmission circuit 615.

  FIG. 8 is a diagram illustrating a configuration example of the transmission control register 632 according to the first embodiment of this invention. As shown in FIG. 8, the transmission control register 632 is composed of, for example, 8 bits, bit 6 is read-only, and other bits 0, 4, 5, and 7 are writable / readable. In this embodiment, since bits 1 to 3 of the transmission control register 632 are unused, the description is omitted in FIG.

  Bit 0 of the transmission control register 632 is set to “1” when the transmission circuit (serial transmission circuit 615) is initialized. When the transmission circuit is initialized, all registers including the data in the transmission data register 635 are set to initial values.

  Bit 4 is set to “0” when data transmission from the transmission data register 635 (transmission data shift register 635B) is prohibited, and is set to “1” when data transmission is permitted.

  Bit 5 is set to “0” when a transmission interrupt is not requested when the transmission data register 635 is empty, and is set to “1” when a transmission interrupt is requested.

  Bit 6 is set to a value indicating whether or not a transmission interrupt request is generated (transmission interrupt state). If bit 6 is set to “0”, it indicates that a transmission interrupt is not requested, and if “1” is set, a transmission interrupt is requested. Indicates.

  In bit 7, the value of bit 8 of the transmission data register (when the data length is 9 bits) is set.

  When a reset signal (RST0) is input to the gaming arithmetic processing device 600, the serial transmission circuit 615 is reset and all the bits of the transmission control register 632 are set to “0” (see also FIG. 6 and the like). . As a result, since bit 4 of the transmission control register 632 becomes “0”, data transmission from the transmission data register 635 (transmission data shift register 635B) is prohibited and the data output is turned off.

  Returning to the description of FIG. 6, the transmission data status register 631 is a register indicating the state of the transmission data register 635. The CPU 102 can confirm the state of the transmission data register 635 based on the setting value of the transmission data status register 631.

  FIG. 9 is a diagram illustrating a configuration example of the transmission data status register 631 according to the first embodiment of this invention. The transmission data status register 631 is composed of, for example, 8 bits, and bits 0 to 5 and 7 are all read-only. In the present embodiment, bit 6 of the transmission data status register 631 is unused, and is omitted in FIG.

  In the transmission data status register 631, bits 0 to 5 are set to values indicating the remaining amount of transmission data. For example, if “00h” (hexadecimal “0”) is set in bits 0 to 5, it indicates that there is no transmission data. If “01h” is set, one byte of transmission data remains. When “20h” is set, it indicates that 32 bytes of transmission data remain.

  In bit 7, a value indicating the data transmission state in the transmission data register 635 is set. When “1” is set in bit 7, it indicates that data is not being transmitted, and when “0” is set, it indicates that data is being transmitted.

  When a reset signal (RST0) is input to the game processing unit 600, the serial transmission circuit 615 is reset and all bits of the transmission data status register 631 are set to “0” (see also FIG. 6 and the like). ). As a result, bits 0 to 5 of the transmission data status register 631 are set to “00h”, and there is no remaining transmission data.

  Returning to the description of FIG. 6, the transmission data register 635 is a register for storing data transmitted by the serial transmission circuit 615. The transmission data register 635 includes, for example, a one-stage transmission data shift register 635B and a 31-stage transmission data buffer register 635A.

  FIG. 10 is a diagram illustrating a configuration example of the transmission data register 635 (for one stage) according to the first embodiment of this invention. The one-stage transmission data register 635 is composed of, for example, 8 bits, and bits 0 to 7 are all dedicated to writing.

  This transmission data register 635 stores control command data generated by the timer interrupt process. If bit 4 of the transmission control register is set to “1” (transmission permission), the stored control command data is stored. Is automatically transmitted to the production control device 150.

  The control command data is composed of, for example, 2 bytes of 1-byte mode data and 1-byte action data, so that one control command data is stored in the two-stage transmission data register 635. In this embodiment, since the transmission data register 635 is composed of 32 stages, when a maximum of 16 control command data are generated by one timer interrupt process, all of them are stored in the transmission data register 635. can do.

  However, the CPU 102 can store new transmission data in the transmission data register 635 because the value of bits 0 to 5 (value indicating the remaining amount of transmission data) of the transmission data status register 631 is “00h” to “1Fh”. (In the case where 0 to 31 bytes of untransmitted data remain in the transmission data register 635).

  When the value of bits 0 to 5 of the transmission data status register 631 is “20h”, the transmission data register 635 has no space, and the data that the CPU 102 attempted to write to the transmission data register 635 is discarded. As a result, when the transmission data register 635 is full, the data stored in the transmission data register 635 is not destroyed even if data is written by the CPU 102 by mistake.

  When a reset signal (RST0) is input to the gaming arithmetic processing device 600, the serial transmission circuit 615 is reset and all the bits of the transmission data register 635 are set to “0” (see also FIG. 6 and the like). .

  Returning to the description of FIG. 6, the baud rate generation circuit 634 divides the clock signal output from the clock generation circuit 609 via the frequency dividing circuit 629 (system clock (MCLK) input to the game processing unit 600. Signal) and a setting value (baud rate setting value) set in the transmission serial channel setting register 633, a transmission baud rate used by the serial transmission circuit 615 is generated. At this time, the baud rate generation circuit 634 obtains the transmission baud rate using the above-described calculation formula based on the clock signal and the baud rate setting value. The frequency dividing circuit 629 also inputs the divided clock signal to the CPU 102. Note that the frequency divider 629 may be included in the clock generation circuit 609.

  The serial transmission circuit 615 writes or transmits data to be transmitted to the transmission data register 635 (transmission data buffer register 635A) after setting transmission permission (bit 4 of the transmission control register 632 is “1”). After data is written in the transmission data register 635, transmission is automatically started when transmission permission is set. When transmission is started, data in the transmission data buffer register 635A is transferred to the transmission data shift register 635B, serially converted from the transmission data shift register 635B, and sequentially output bit by bit from the least significant bit (bit 0). . When the data transmission is completed, the transmission data shift register 635B becomes empty, so that the next data written in the transmission data buffer register 635A is transferred to the transmission data shift register 635B and output.

  Therefore, in the serial transmission circuit 615, data (control command data) written in the transmission data register 635 (transmission data shift register 635B, transmission data buffer register 635A) is sequentially transmitted to the effect control device 150 bit by bit. It becomes.

  As described above, the serial transmission circuit (control command transmission means) 615 includes the transmission data register 635 for storing transmission data (for example, control command data). When the transmission data is stored in the transmission data register 635, the game control is performed. The stored transmission data is sequentially transmitted bit by bit in the direction from the device 100 to the effect control device 150 (so-called serial communication).

  Specifically, the transmission data register 635 has a transmission data shift register 635B that immediately transmits the stored data, a state that holds the stored data, and the transmission data shift register 635B can store the data (data The transmission data buffer register 635A transfers the stored data to the transmission data shift register 635B when the transmission is completed.

  Thereby, the transmission process of the control command data in the timer interrupt process, which is essential in the conventional parallel communication, can be omitted, so that the burden on the CPU 102 can be reduced.

  In addition, by using serial communication, the number of wires for transmitting control command data can be relatively reduced.

  The communication between the game control device 100 and the effect control device 150 is unidirectional communication in which data can be transmitted only from the game control device 100 to the effect control device 150, and no data is input to the game control device 100. , It can prevent fraud.

  In this embodiment, transmission data register 635 can store transmission data of up to 32 bytes, but the baud rate is set so that all of this 32 bytes of data can be output in one timer interrupt process. The value (bits 0 to 12 of the transmission serial channel setting register 633) is set.

  Specifically, the time Tb required for data transmission per byte output from the transmission data register 635, the generation period F of the timer interrupt signal, the upper limit number of bytes B of data that can be stored in the transmission data register 635, The baud rate setting value may be set to determine the transmission speed so that the relationship of F / B> Tb is satisfied.

  For example, if the timer interrupt signal generation cycle F = 4 milliseconds and the upper limit number of bytes B = 32 bytes of data that can be stored in the transmission data register 635, F / B = 4000/32 = 125 microseconds or less. Thus, the value of Tb is determined, and the value of the baud rate set value may be determined in consideration of the frequency of the system clock (MCLK) input to the gaming arithmetic processing device 600.

  With such a configuration, the serial transmission circuit (control command transmission means, transmission means) 615 can store all of a series of control command data generated in one timer interrupt process. It is possible to reliably transmit control command data generated for each interrupt.

  FIG. 11 is a block diagram of a game processing unit (amuse chip) 600 provided in the game control device 100 according to the first embodiment of the present invention and its surroundings.

  The gaming arithmetic processing device 600 includes a security circuit 630, a CPU core 102 (601 in FIG. 11), a RAM access restriction circuit 640, a user work RAM 104 (604 in FIG. 11), an address decoder 611, an output control circuit 612, and a user. A program ROM 103 (602 in FIG. 11) is provided.

  Note that these circuits and the like included in the gaming arithmetic processing device 600 are connected via an address bus 650 and a data bus 660. The address bus 650 is composed of 16-bit signal lines A0 to A15, and the data bus 660 is composed of 8-bit signal lines D0 to D7.

  Further, the game control device 100 includes a serial transmission circuit 615A connected to the effect control device 150 and a serial transmission circuit 615B connected to the payout control device 210.

  The production control device 150 and the payout control device 210 are provided with a reception circuit corresponding to the serial reception circuit 625 (FIG. 5), and the serial data output from the serial transmission circuits 615A and 615B, respectively. It is configured to receive.

  When power is supplied to the gaming arithmetic processing device 600, a reset signal (start signal) is input from the power supply device 160 via the RST0 terminal (FIG. 5), and the reset circuit 610B (FIG. 5) is activated.

  When this reset signal is input, the security circuit 630 executes a security check process using the validity confirmation information stored in the HW parameter ROM 603. This security check process is a process for determining the validity of the program stored in the user program ROM 103.

  While this security check process is being executed, the security circuit 630 continuously outputs a reset signal to the reset terminal (RES0 (negative logic)) of the CPU core 102, thereby waiting for the CPU core 102 to start up. .

  The CPU core 102 includes the aforementioned reset terminal (RES0 (negative logic)), a write command output terminal (WR (negative logic)), and a read command output terminal (RD (negative logic)). The reset terminal is connected to the security circuit 630, and when a reset signal is input to the gaming arithmetic processing device 600, as described above, the reset signal for the CPU core 102 is reset while the security check process is being executed. Input to the terminal.

  When a reset signal is input to the reset terminal of the CPU core 102, the CPU core 102 initializes a register (REG) provided in the CPU core 102.

  When the CPU core 102 outputs a write command for instructing the user work RAM 104 to write data, a low level signal having a voltage lower than a predetermined value is output from the write command output terminal of the CPU core 102. Is done. Similarly, when the CPU core 102 outputs a read command for instructing data read from the user work RAM 104, a low level signal having a voltage lower than a predetermined value is output from the read command output terminal of the CPU core 102. The

  That is, the normal voltage is maintained at a high level at the write command output terminal and the read command output terminal, and the voltage is at a low level only when reading / writing to the user work RAM 104 is performed.

  In addition, the CPU core 102 outputs an address designated on the address bus 650, and inputs / outputs data stored at the designated address via the data bus 660.

  First, reading of data from the user work RAM 104 will be described.

  When a read command is input from the CPU core 102 to a read command input terminal (RD (negative logic)) of the user work RAM 104, read data is output to the CPU core 102 via the address bus 650 and the data bus 660.

  At this time, the address of the user work RAM 104 is output from the CPU core 102 to the address bus 650, and a selection signal is input from the address decoder 611 to a chip selection terminal (corresponding to a so-called CS terminal, not shown) of the user work RAM 104. As a result, the user work RAM 104 is selected. Next, the selected user work RAM 104 outputs the data in the storage area designated by the address bus 650 to the data bus 660. Next, the CPU core 102 takes in the data output to the data bus 660. By such a procedure, the CPU core 102 reads data from the user work RAM 104.

  Next, data writing to the user work RAM 104 will be described.

  The write command output terminal provided in the CPU core 102 is connected to one input terminal of the two input terminals provided in the OR gate circuit 642 of the RAM access restriction circuit 640. The other input terminal of the OR gate circuit 642 is connected to the output terminal (Q (negative logic)) of the flip-flop circuit 641 of the RAM access restriction circuit 640, and the output terminal of the OR gate circuit 642 is the write of the user work RAM 104. It is connected to the command input terminal (WR (negative logic)).

  When a low level signal having a voltage equal to or lower than a predetermined value is input to the write command input terminal of the user work RAM 104, writing to the user work RAM 104 is permitted.

  Therefore, writing to the user work RAM 104 is not permitted unless low level signals are input to the two input terminals of the OR gate circuit 642, respectively. In other words, when a high level signal is input to at least one input terminal of the OR gate circuit 642, writing to the user work RAM 104 is restricted (prohibited).

  Here, the flip-flop circuit 641 of the RAM access restriction circuit 640 will be described.

  The flip-flop circuit 641 is a D-type flip-flop circuit, and includes a data terminal (D), a reset terminal (R (negative logic)), and an output enable terminal (OE (negative logic)) as input terminals. Output terminals (Q (positive logic), Q (negative logic)) are provided.

  One predetermined signal line (for example, D0) among the signal lines D0 to D7 constituting the data bus 660 is connected to the data terminal.

  A reset signal line is connected to the reset terminal from the power supply device 160, and when a reset signal is input, the reset terminal becomes low level. At this time, the flip-flop circuit 641 outputs a low level signal from the output terminal Q (positive logic) and outputs a high level signal from the output terminal Q (negative logic). The output from the output terminal Q (positive logic) and the output from the output terminal Q (negative logic) are at levels that are mutually inverted.

  The output enable signal transmitted from the output control circuit 612 is input to the output enable terminal. When the output enable signal is at a high level, a signal can be output from the output terminal.

  The signal level from the output terminal Q (negative logic) provided in the flip-flop circuit 641 can be freely set by the CPU core 102. This setting is realized by the CPU core 102 writing predetermined data in the storage area of the address assigned to the flip-flop circuit 641.

  Specifically, when the CPU core 102 performs processing to write data to the storage area of the address assigned to the flip-flop circuit 641, the address of the flip-flop circuit 641 is output from the CPU core 102 to the address bus 650. The Next, a clock signal is input from the address decoder 611 to the output enable terminal of the flip-flop circuit 641 via the output control circuit 612, and the voltage level of the output enable terminal rises to a high level.

  At this time, the flip-flop circuit 641 captures the signal input to the data terminal, outputs the captured signal from the output terminal Q (positive logic), and outputs the inverted value of the captured signal from the output terminal Q (negative logic). Output.

  Further, in the flip-flop circuit 641, when the output control circuit 612 finishes inputting the clock signal, the voltage level of the output enable terminal falls and becomes a low level, and the output terminal Q (positive logic) and the output terminal Q (negative). Logic) voltage level.

  The output terminal Q (negative logic) outputs a signal to the input terminal of the OR gate circuit 642. Nothing is connected to the output terminal Q (positive logic).

  Next, various operations according to the input state of the flip-flop circuit 641 will be described.

  As described above, the flip-flop circuit 641 reads the voltage level of the data terminal at the rise of the voltage level of the output enable terminal, that is, at the start of input of the output enable signal, and outputs the inverted value of the read voltage level to the output terminal Q (negative Output from logic).

  On the other hand, the flip-flop circuit 641 holds the output from the output terminal Q (negative logic) at the fall of the voltage level of the output enable terminal, that is, at the end of the input of the output enable signal. To do.

  When a high level signal is output from the output terminal Q (negative logic) to the input terminal of the OR gate circuit 642, either the low level signal or the high level signal is input to the other input terminal of the OR gate circuit 642. Also, a high level signal is output from the output terminal of the OR gate circuit 642.

  Therefore, if a high-level signal is output from the output terminal Q (negative logic) of the flip-flop circuit 641, even if a write command signal is input to the other input terminal of the OR gate circuit 642 (the other Even if a low level signal is input to the input terminal), the low level is not input to the write command input terminal of the user work RAM 104, and a RAM write inhibit state occurs.

  The voltage level input to the data terminal of the flip-flop circuit 641 when the clock signal is input to the flip-flop circuit 641 depends on whether the RAM access restriction circuit 640 is in the RAM write prohibition state or the RAM write permission state. Or based on the presence or absence of a reset signal input.

  As described above, the CPU core 102 can control the output control circuit 612 to control the output of the clock signal, and can also control the output of the signal line of the data bus 660, so that the output terminal Q (negative logic) of the flip-flop circuit 641. The signal output from can be controlled by the CPU core 102. In other words, the CPU core 102 can control the write state of the RAM access restriction circuit 640 by controlling the signal level of the data bus 660.

  Further, as described above, when a reset signal is input to the reset terminal of the flip-flop circuit 641, the flip-flop circuit 641 sets the voltage level of the output terminal Q to low, and therefore the output terminal Q (negative logic) The voltage level goes high. Therefore, when a reset signal is input to the flip-flop circuit 641, the RAM access restriction circuit 640 causes a RAM write prohibition state.

  As described above, when the output control circuit 612 inputs a clock signal to the serial transmission circuit 615B connected to the payout control device 210, the serial transmission circuit 615B receives data from the data bus 617 at the timing when the clock signal is input. The read data is stored in the transmission data buffer register 635A. Then, the data stored in the transmission data buffer register 635A is stored in the transmission data shift register 635B and sequentially output to the payout control device 210.

  Note that the activation (reset) of the security circuit 630, the RAM access restriction circuit 640, and the serial transmission circuit 615 described above is when the reset signal from the power supply device 160 is received via the reset circuit 610B (FIG. 5). To be executed. However, the reset signal from the power supply device 160 is not necessarily input to each circuit via the reset circuit 610B, and is input to each circuit via a separate signal line that does not pass through the reset circuit 610B. But you can.

  In the serial transmission circuit 615 (615A, 615B), as described above with reference to FIGS. 7 to 10, the data output to the effect control device 150 and the payout control device 210 is turned off by the reset signal.

  Further, the payout control device 210 is different from the game control device 100 shown in FIG. 6 in that it does not include the serial transmission circuit 615. Other configurations are the same as those of the game control apparatus 100 shown in FIG.

  In addition, the fact that the effect control device 150 does not include the serial transmission circuit 615 and that the game arithmetic processing device 600 does not include the RAM access restriction circuit 640 is different from the game control device 100 shown in FIG. Is different. About another structure, it is the same structure as the game control apparatus 100 shown in FIG.

  Note that the serial reception circuit 625 included in the payout control device 210 and the effect control device 150 is after the CPU 102 of the payout control device 210 (or the effect control device 150) is activated, the serial transmission circuit 615 of the game control device 100. The signal from can be accepted. Note that the serial receiving circuit 625 and the CPU 102 of the payout control device 210 (or the effect control device 150) are connected to each other via a data bus 617.

  FIG. 12 is a block diagram illustrating an internal configuration of the CPU core 102 according to the first embodiment of this invention. The CPU core 102 is configured as a Z80 CPU.

  The CPU core 102 shown in FIG. 12 includes a W register 1201A, an A register 1202A, a B register 1204A, a C register 1205A, a D register 1207A, an E register 1208A, an H register 1210A, and an L register 1211A each having a width of 8 bits. ing.

  These general-purpose registers can be used as a WA register 1203A having a 16-bit width by combining the W register 1201A and the A register 1202A. Similarly, a BC register 1206A combining the B register 1204A and the C register 1205A, a DE register 1209A combining the D register 1207A and the E register 1208A, and an HL register 1212A combining the H register 1210A and the L register 1211A are used. It is also possible.

  These general-purpose registers form one general-purpose register group (register group in bank 0) 1220A. On the other hand, the CPU core 102 includes another general-purpose register group (bank 1 register group) 1220B having the same configuration as that of the general-purpose registers included in the bank 0 register group 1220A.

  The bank 1 register group 1220B includes W registers 1201B to 1211B having the same functions as the bank 0 W registers 1201A to L1112A. Like the bank 0, these registers can also be used as 16-bit registers as the WA register 1203B to HL register 1212B.

  Further, the CPU core 102 includes a flag register 1200 having a width of 8 bits.

  The flag register 1200, which will be described in detail with reference to FIG. 13, stores an operation result using the register. Further, a register bank selector (RBS) 1301 (described later in FIG. 13) of the flag register 1200 selects which of the two general-purpose register groups 1220A and 1220B is used as an operation target.

  Each register belonging to the register group selected by the register bank selector (RBS) 1301 is used for calculation by an instruction interpretation execution circuit 1242 described later. On the other hand, each register belonging to the unselected register group holds a value until the value of the register bank selector (RBS) 1301 is changed and becomes a selection target.

  Further, the CPU core 102 includes a K register 1230 having a width of 8 bits and functioning as an upper address specification register. This register is an upper address designation register that designates an upper 8-bit address when an instruction interpretation execution circuit 1242, which will be described later, accesses data stored at a predetermined 16-bit address.

  Further, the CPU core 102 includes an IX register 1231, an IY register 1232, an SP register 1233 that functions as a stack pointer, and a PC register 1234 that functions as a program counter, each having a width of 16 bits.

  The IX register 1231 and the IY register 1232 are used as indexes when an instruction interpretation execution circuit 1242 described later accesses data. The stack pointer 1233 indicates the position of an area when data is stored (or retrieved) in the stack area (described later in FIG. 18). The program counter 1234 indicates an address where an instruction executed by an instruction interpretation execution circuit 1242 described later is stored.

  The instruction interpretation execution circuit 1242 executes a game control program and performs arithmetic processing using each register in the CPU core 102. Specifically, in the user program ROM 103, data stored at the address indicated by the program counter 1234 is read, and the read data is regarded as a code, and an instruction corresponding to the code is executed.

  Therefore, in the present embodiment, the CPU core 102 itself is exemplified as the arithmetic processing means. However, in the CPU core 102, the instruction interpretation execution circuit 1242 mainly functions as the arithmetic processing means.

  The instruction interpretation execution circuit 1242 corresponds to the instruction of the game control program, the user program ROM 103 outside the CPU core 102, the user work RAM 604, and others via the access circuit 1243, the address bus 650, and the data bus 660. In some cases, data is exchanged with other circuits.

  Further, the instruction interpretation execution circuit 1242 stores the address where the next instruction is stored in the program counter 1234 every time one instruction of the user program ROM 103 is executed. In this way, the game control program is sequentially executed by repeatedly executing the instruction and updating the program counter 1234. When an interrupt signal from interrupt control circuit 610A is received, the value of program counter 1234 is switched to a preset interrupt processing address value.

  Data is transmitted to and received from the instruction interpretation execution circuit 1242 and the registers included in the CPU core 102 through the internal bus 1235.

  The initial value setting circuit 1241 is a circuit that sets an initial value in each register included in the CPU core 102 in hardware.

  When the built-in reset circuit 1240 receives the reset signal from the security circuit 630, the built-in reset circuit 1240 activates the initial value setting circuit 1241, sets initial values in the registers included in the CPU core 102, and then activates the instruction interpretation execution circuit 1242. Let

  FIG. 13 is a diagram illustrating the configuration of the flag register 1200 according to the first embodiment of this invention. The value of each bit of the flag register 1200 is set by the instruction interpretation execution circuit 1242 in FIG.

  The interrupt master permission flag (IMF) 1300 is a flag for setting permission / inhibition of interrupt processing by an interrupt signal, and is permitted when set (value is “1”) and prohibited when cleared (value is “0”). .

  The register bank selector (RBS) 1301 is a flag that selects which of the two general-purpose register groups 1220A and 1220B is used when the instruction interpretation execution circuit 1242 in FIG. Is "1"), the register group 1220B of bank 1 is selected, and the register group 1220A of bank 0 is selected when clear (value is "0").

  The overflow flag (VF) 1302 is set (value is “1”) when a digit overflow (overflow) occurs in a general-purpose register to be calculated by a predetermined operation, and is cleared (value is “0”) in other cases. .

  The sign flag (SF) 1303 is set (value is “1”) when the most significant bit of the calculation target general-purpose register is “1” by a predetermined operation, and is cleared (value is “0”) in other cases. The

  The half carry flag (HF) 1304 is set (value is “1”) when carry (carry) or borrow (borrow) occurs in the 4th bit of the general-purpose register to be calculated as a result of 8-bit operation. In other cases, it is cleared (value is “0”).

  The carry flag (CF) 1305 is set (value is “1”) when a carry (carry) or borrow (borrow) is generated by a predetermined operation, and is cleared (value is “0”) in other cases. .

  The zero flag (ZF) 1306 is set (value is “1”) when a predetermined calculation result is “0”, and is cleared (value is “0”) in other cases.

  The jump status flag (JF) 1307 is set (value is “1”) when at least one of the carry flag (CF) 1305 or the zero flag (ZF) 1306 is set. Alternatively, even when the arithmetic processing is not performed, when the value of the general-purpose register becomes “00H”, it is set (value is “1”). When none of these conditions is satisfied, the value is cleared (value is “0”).

  When the CPU core 102 is reset, all the bits of the flag register are set to 0.

  FIG. 14 is a diagram illustrating an example of the user work RAM 104 according to the first embodiment of this invention.

  The user work RAM 104 includes a first power failure recovery area 701, a work area 702, a second power failure recovery area 703, a checksum area 704, a use prohibition area (access prohibition area) 705, and a stack area 706.

  Addresses “2800H” to “29FFH” are assigned to the user work RAM 104, addresses “2800H” are assigned to the first power failure recovery area 701, and addresses “2801H” to “2917H” are assigned to the work area 702. The address “2918H” is assigned to the second power failure recovery area 703, the address “2919H” is assigned to the checksum area 704, and the addresses “291AH” to “297FH” are assigned to the use prohibition area 705. The stack area 706 is assigned addresses “2980H” to “29FFH”.

  Each area of the user work RAM 104 will be described.

  The first power failure recovery area 701 and the second power failure recovery area 703 store information referred to when the power supply to the gaming machine 1 is started, and when the power supply is stopped immediately before (the occurrence of a power failure or the power supply of the gaming machine 1) Information (power cutoff confirmation flag) indicating whether or not the power shutdown processing has been executed correctly when the switch is turned off is stored.

  The work area 702 stores variables and the like necessary for game control, and these variables are updated by the game control device main process shown in FIGS. 25 and 26, the timer interrupt process shown in FIG. 29, and the like. Specifically, a special counter fluctuation display game and a hold counter for storing the number of suspensions of the special figure fluctuation display game, a random number generation area necessary for executing the special figure fluctuation display game, and a lottery fluctuation display game The work area 702 stores a random number (ordinary random number) generation area necessary for performing, a normal random number storage area, various random number storage areas necessary for executing the special figure variation display game, and the like. Details of these will be described later with reference to FIGS.

  The checksum area 704 stores the checksums of the first power failure recovery area 701, the work area 702, and the second power failure recovery area 703 of the user work RAM 104 that are calculated when a power failure occurs.

  The use-prohibited area 705 is a storage area that is not used, and the CPU core 102 is reset by the security circuit 630 (FIG. 6) when there is access to the area.

  The stack area 706 stores saved data when part of the data calculated by the CPU core 102 is temporarily saved. In addition, a return address when an interrupt occurs and a return address when a subroutine or function is called are also stored.

  In the present embodiment, in the work area 702, the high-order addresses of various random number generation and storage areas used for game control are set to be different from the high-order addresses of the areas to which the stack area 706 is allocated. Specifically, the upper address of the generation and storage area of various random numbers in the work area 702 is “28H” (first storage area), and the upper address of the stack area is “29H” (second storage area). This prevents the value of the stack area from being erroneously updated when the random number is updated or the value of the random number is erroneously updated when the stack area is updated.

  Furthermore, even if the upper address is set by mistake, the lower address of the various random number generation and storage areas is set so that it does not overlap with the lower address of the stack area so as not to cause a malfunction. .

  Specifically, various random number (starting memory) generation areas (2820H to 2827H), a normal random number generation area (2828H), a general random number generation area (2828H), and a common random number display game for executing the special figure variation display game described later with reference to FIGS. Random number storage area (282CH to 282FH), various random number (starting memory) storage areas (2830H to 284FH) for executing the first special figure fluctuation display game, and second special figure fluctuation display game This corresponds to a storage area (2850H to 286FH) of various random numbers (startup memory) for the purpose. An area obtained by replacing the upper addresses of these areas from “28H” to “29H” (that is, an area from 2920H to 296FH) is set as a use-prohibited area 705 as shown in FIG.

  15 to 17 are diagrams illustrating specific examples of data stored in the work area 702 allocated to the user work RAM 104 according to the first embodiment of this invention. FIG. 15 shows a hold counter, various random number generation areas, and a regular random number storage area. 16 shows a storage area for various random numbers necessary for executing the first special figure variation display game, and FIG. 17 shows a storage area for various random numbers necessary for executing the second special figure variation display game.

  Referring to FIG. 15, 281DH to 281FH are allocated as areas for storing the hold counter. Specifically, a first special figure hold counter (281DH) that stores the number of reserved memories of the first special figure variable display game, and a first special figure hold counter that stores the number of held memories of the second special figure variable display game ( 281EH), it is a universal figure holding counter (281FH) for storing the holding memory number of the common figure variable display game. Furthermore, various random number (starting memory) generation areas (2820H to 2827H), normal random number generation areas (2828H), and normal random number storage areas (282CH to 282FH) are allocated for executing the special figure variation display game. It has been.

  Various random numbers for executing the special figure fluctuation display game include a big hit random number (2 bytes) for determining the big hit of the special figure fluctuation display game, and a big hit symbol for determining the big hit symbol of the special figure fluctuation display game Includes a first variation P (pattern) random number (2 bytes), a second variation P (pattern) random number, and a third variation P (pattern) random number (2 bytes) for determining the variation pattern of the special figure variation display game. It is.

  Referring to FIG. 16, an area for storing various random numbers for executing the first special figure variation display game is allocated. In the present embodiment, the start memory of the first special figure variation display game (special figure 1 start memory) can be retained up to four times. These random numbers are set in the special figure starting port SW common process (FIG. 40).

  Specifically, the areas are allocated in the order in which the stored special figure 1 start-up memory is stored. Specifically, areas 1830H to 2837H, 238H to 283FH, 2840H to 2847H, 3840, and 2848H to 284FH are allocated to the reservation 1 and 2830H. Each area is further assigned with an area corresponding to various random numbers for executing the above-described special figure variation display game.

  Then, when the first special figure fluctuation display game corresponding to the first special figure 1 start memory to be held is executed, in the special figure normal fluctuation process (FIG. 45) described later, After obtaining (temporarily saving) each first random number, each random number stored in the area corresponding to the second to fourth special figure 1 start memory is held first to third The shift to the area corresponding to the start memory of FIG.

  Then, the game control device 100, in a special figure jackpot determination process (FIG. 42) to be described later, obtains the value of each random number (the first random number that has been temporarily saved) and a special feature that is defined in advance. 1 is compared with the big hit determination value for the variable display game to determine whether or not the special figure 1 variable display game is a big hit, and the special figure 1 start memory number (the value stored in the first special figure holding counter) 1 is subtracted.

  Referring to FIG. 17, as in the case of the first special figure fluctuation display game shown in FIG. 16, there are areas for storing various random numbers (special figure 2 start memory) for executing the second special figure fluctuation display game. Assigned. Various random numbers included in the special figure 2 start memory are processed in the same manner as the special figure 1 start memory.

  18 and 19 are diagrams illustrating an example of the stack area 706 according to the first embodiment of this invention. 18 and 19, a case where a return address and a predetermined register value are stored in the stack area 706 will be described.

  First, FIG. 18A shows a state immediately after power is turned on to the gaming machine 1 and shows a state where no data is stored in the stack area 706. In this case, the stack pointer (SP) 1233 indicates the last area (29FFH) of the stack area as the stack pointer initial value.

  FIG. 18B shows a state in which saved data is stored in the stack area 706, or data such as a return address is stored in the stack area 706 due to an interrupt or a subroutine call. In this case, the stack pointer 1233 indicates the address immediately above the area where the data (or address) is stored last.

  The return address is stored in the stack area 706 when an interrupt occurs or when a normal subroutine call is performed by executing a “CALL” instruction to be described later. The data stored in the stack area 706 differs between the former case and the latter case.

  FIG. 19C shows a state in which data is saved in the stack area 706 when a “CALL” instruction (to be described later) is executed in the call source routine to perform a normal subroutine call. This figure shows a state immediately after the “CALL” instruction is executed in the state of FIG.

  In FIG. 18B, when the “CALL” instruction is executed, the return address of the call source routine is stored in the stack area 706 separately into upper bytes and lower bytes. At this time, the stack pointer 1233 indicates the address one level above the area where the address was stored last.

  When a “RET” instruction, which will be described later, is executed at the end of the processing of the called subroutine, this return address is returned to the program counter 1234 and the value of the stack pointer 1233 is also set before the “CALL” instruction is executed. (Return to the state of FIG. 18B). As a result, the process can be returned to the calling routine.

  On the other hand, FIG. 19D shows how data is saved in the stack area 706 when an interrupt occurs in the call source routine and the call destination interrupt processing routine is executed. Note that FIG. 19D shows a state immediately after an interrupt occurs in the state of FIG.

  In FIG. 18B, when an interrupt occurs, the stack area 706 first stores the value of the flag register 1200 set in the call source routine, and then sets the caller routine return address as the upper byte. Stored separately in the lower byte. At this time, the stack pointer 1233 indicates the address one level above the area where the address was stored last.

  When a “RETI” or “RETN” instruction, which will be described later, is executed at the end of the interrupt processing routine of the call destination, the return address stored in the stack area 706 is returned to the program counter 1234, and the stack area The value of the flag register stored in 706 is also returned to the flag register 1200. Further, the value of the stack pointer 1233 is also returned to the value before the occurrence of the interrupt (returns to the state of FIG. 18B). As a result, the process can be returned to the calling routine.

  In this manner, data such as a return address stored in the stack area 706 is read first from a return address stored later.

  When a “PUSH” instruction, which will be described later, is executed, the value of the register designated by the instruction is stored in the stack area 706, and the value of the stack pointer 1233 is the same as in FIGS. 19C and 19D. Finally, it indicates the address one level above the area where data is stored.

  On the other hand, when a “POP” instruction to be described later is executed, the value stored in the stack area 706 is taken out and stored in the register designated by the instruction, and the value of the stack pointer 1233 is also changed from FIG. As shown in (B), this indicates the address of the area from which data was last extracted.

  As described above, in the present embodiment, the stack pointer 1233 indicates the address one address higher than the address at which the data was last stored in the stack area 706 (in other words, the address of the data that was last fetched). That is, the current stack pointer 1233 indicates the address of data stored in the next stack area 706.

  As another method, a method of indicating the address of data to be next fetched from the stack area 706 by the current stack pointer 1233 is also conceivable. Such a modification is shown in FIG.

  FIG. 20E shows a state immediately after the gaming machine 1 is turned on and no data is stored in the stack area 706. In this case, the stack pointer (SP) 1233 indicates the address (2A00H) immediately below the last area (29FFH) of the stack area as the stack pointer initial value. Note that the area indicated by the stack pointer initial value is an area that is not included in the stack area (in this embodiment, an area that is not included in the storage area of the user work RAM 104).

  FIG. 20F shows a state in which saved data is stored in the stack area 706, or data such as a return address is stored in the stack area 706 due to an interrupt or a subroutine call. In this case, the area where the data (or address) was stored last is indicated by the stack pointer 1233. When data is extracted from the stack area 706, the data may be extracted from the address currently indicated by the stack pointer 1233.

  If the allocation of the stack area 706 is limited to the area where the upper address is the same (for example, it is limited to being allocated to the area of 2900H to 29FFH), the stack pointer 1233 indicates only the lower address. Just specify and it works. In such a configuration, the stack pointer 1233 can be configured by a 1-byte register, and a configuration in which addressing by the stack pointer 1233 is performed by the method of FIGS. 18 and 19 rather than the method of FIG. It is effective.

  21 and 22 are diagrams illustrating assembly language instructions for describing the game control program executed by the CPU core 102 according to the first embodiment of this invention. Each instruction is converted into corresponding code data and stored in a predetermined address of the user program ROM 103. FIG. 21 shows an instruction that does not include an address part in the converted code data (an instruction in which the converted code data is composed only of the instruction code part), and FIG. An instruction including each of the address portions is shown. Here, the target register is the register shown in FIG.

  In FIG. 21, an instruction 2100 is an instruction for storing a designated register value in the A register 1202A. For example, “LD A, B” is an instruction for storing the value of the B register 1204A in the A register 1202A. Similarly, the other instructions “LD A, C” to “LD A, L” are instructions that extract values from the corresponding C register 1205A to L register 1211A and store them in the A register 1202A.

  The instruction 2101 is an instruction for storing the value of the A register 1202A in a designated register. For example, “LD B, A” is an instruction for storing the value of the A register 1202A in the value of the B register 1204A. Similarly, the other instructions “LD C, A” to “LD L, A” are instructions that extract values from the A register 1202A and store them in the corresponding C registers 1205A to L registers 1211A.

  The instruction 2102 is an instruction that performs a logical OR operation on the value of the A register 1202A and the value of the designated register and stores the operation result in the A register 1202A. For example, “OR B” is an instruction that performs a logical OR operation for each bit with the value of the A register 1202A and the value of the B register 1204A and stores the operation result in the A register 1202A. Similarly, the other “OR C” to “OR L” instructions perform an OR operation on the value of the A register 1202A and the value of the corresponding C register 1205A to L register 1211A, and the operation result is stored in the A register 1202A. Instruction to store.

  “ADD A, A” of the instruction 2103 is an instruction for adding the value of the same A register 1202A to the value of the A register 1202A and storing the operation result in the A register 1202A. In essence, this is an instruction for performing an operation in which the value of the A register 1202A is doubled. “ADD HL, BC” of the instruction 2104 is an instruction for adding the value of the BC register 1206A to the value of the HL register 1212A and storing the operation result in the HL register 1212A.

  “PUSH HL” of the instruction 2105 is an instruction for storing the value of the HL register 1212A in the stack area. “POP HL” of the instruction 2106 is an instruction for storing the value extracted from the stack area in the value of the HL register 1212A.

  “INC HL” of the instruction 2107 is an instruction for adding “1” to the value of the HL register 1212A. “DEC HL” of the instruction 2108 is an instruction for subtracting “1” from the value of the HL register 1212A.

  “JP (HL)” of the instruction 2109 is an instruction that regards the value of the HL register 1212A as an address and branches to the address destination. For example, if the value of the HL register 1212A is “1234H”, the instruction interpretation execution circuit 1242 changes the value of the program counter 1234 to “1234H”. As a result, the instruction executed by the instruction interpretation execution circuit 1242 is an instruction obtained by converting the code stored in the area whose address is “1234H”. Thereafter, the instruction interpretation execution circuit 1242 sequentially executes instructions after the changed address.

  The instruction 2110 is an instruction for returning from the calling destination processing routine to the calling source processing routine by returning the value stored in the stack area to the program counter 1234. Here, “RET” is an instruction that returns from a processing routine that is called by executing a “CALL nn” instruction that will be described later with reference to FIG. 22, and “RETI” that returns from a processing routine that is called by an INT interrupt. “RETN” is an instruction to return from the processing routine called by the NMI interrupt.

  The command 2111 is a command for setting whether to accept an interrupt. “DI” is an instruction for setting interrupt prohibition, and “EI” is an instruction for setting interrupt permission.

  The instruction 2112 is stored in the area of the address, considering the value stored in the K register 1230 as the upper byte and the value stored in the L register 1211A as the lower byte as a 2-byte value as the address. This is an instruction to set a value in the A register 1202A. Specifically, when the value stored at the address “2803H” is to be set in the A register 1202A, the value “28H” is stored in the K register 1230 in advance and the value “03H” is stored in the L register 1211A. And the instruction “LDK A, (L)” is executed in that state.

  In the case where the value of the A register 1202A is stored in a desired address area, the upper address of the storage destination is set in the K register 1230 and the lower address is set in the L register 1211A in advance. An instruction of the form LDK (L), A "is executed.

  “INC L” of the instruction 2113 is an instruction to add “1” to the value stored in the L register 1211A. However, if the “INC L” instruction is executed when the value of the L register 1211A is “FFH”, the value of the L register 1211A after execution of the instruction becomes “00H”.

  “DEC L” of the instruction 2114 is an instruction for subtracting “1” from the value stored in the L register 1211A. However, if the “DEC L” instruction is executed when the value of the L register 1211A is “00H”, the value of the L register 1211A after the instruction execution becomes “FFH”.

  The instruction 2115 is an instruction for setting a value in the “register bank selector” bit of the flag register 1200 described above with reference to FIG. “LD RBS, 0” is an instruction for setting a value of “0” in the corresponding bit, and “LD RBS, 1” is an instruction for setting a value of “1” in the corresponding bit.

  “PUSH FLG” of the instruction 2106 is an instruction for storing the value of the flag register 1200 in the stack area. “POP FLG” of the instruction 2107 is an instruction for storing the value extracted from the stack area in the flag register 1200.

  Of the instructions shown in FIG. 21, as shown in the figure, instructions from instruction 2100 to instruction 2114 are converted into code data constituting a 1-byte instruction code part when stored in user program ROM 103. For example, the instruction “LD A, B” is converted into 1-byte code data “78H” and stored in a predetermined address of the user program ROM 103.

  On the other hand, among the instructions shown in FIG. 21, the instructions from the instruction 2115 to the instruction 2117 are converted into code data constituting a 2-byte instruction code portion when stored in the user program ROM 103. For example, “LD RBS, 0” is converted into 2-byte code data “CBH” and “00H” and stored in a predetermined predetermined address of the user program ROM 103.

  Next, in FIG. 22, an instruction 2200 is an instruction for setting an arbitrary 1-byte value in a designated register. “N” in the figure indicates a value to be set in the register. For example, when it is desired to set a value of “42H” in the A register 1202A, the instruction is “LD A, 42H”.

  When the instruction 2200 is stored in the user program ROM 103, the instruction 2200 is converted into 2-byte code data including a 1-byte instruction code part and a 1-byte address part. For example, an instruction “LD A, 42H” is converted into 1-byte instruction code portion data “3EH” and 1-byte address portion data “42H”, and is transferred to a predetermined predetermined address in the user program ROM 103. “3EH” and “42H” are stored in this order.

  Similarly, “LD B, n” is an instruction to set an arbitrary 1-byte value (n) in the B register 1204A, and “LD K, n” is an arbitrary 1-byte value (in the K register 1230 ( n) is a command for setting. These instructions are also converted into data of a 1-byte instruction code portion and a 1-byte address portion, and stored at predetermined predetermined addresses in the user program ROM 103.

  The instruction 2201 is an instruction for setting a value stored in an area of an arbitrary address in the A register 1202A. In the figure, “nn” indicates a 2-byte address value. For example, when the value stored in the address “2901H” is to be set in the A register 1202A, the instruction “LD A, (2901H)” is used. Become.

  When the value of the A register 1202A is stored in the area of an arbitrary address, the instruction is in the form of “LD (nn), A” as shown in the figure. For example, when it is desired to store the value of the A register 1202A in the area of the address “2901H”, the instruction becomes “LD (2901H), A”.

  When this instruction 2201 is stored in the user program ROM 103, it is converted into a total of 3-byte code data consisting of a 1-byte instruction code part and a 2-byte address part. For example, an instruction “LD A, (2901H)” is converted into data “3AH” in a 1-byte instruction code part and data “01H” and “29H” in a 2-byte address part. Are stored in the order of “3AH”, “01H”, and “29H”.

  The instruction 2202 regards the value stored in the K register 1230 as an upper byte, and considers a 2-byte value obtained by combining a value indicated by an arbitrary 1-byte value as a lower byte as an address, and stores it in the address area. This is an instruction to set the stored value in the A register 1202A. An arbitrary one-byte lower address in this case corresponds to “n” in the figure.

  Specifically, when the value stored in the address “2803H” is to be set in the A register 1202A, the value “28H” is stored in the K register 1230 in advance, and “LDK A, (03H ) "Is executed.

  When the value of the A register 1202A is stored in a desired address area, the upper address of the storage destination is set in the K register 1230 in advance, and the format of “LDK (n), A” shown in the figure is used. Execute the instruction. For example, when the value of the A register 1202A is to be stored in the area of the address “2803H”, the instruction “LDK (03H), A” is executed with the value of the K register 1230 set to “28H”.

  When this instruction 2202 is stored in the user program ROM 103, it is converted into code data of a total of 2 bytes including a 1-byte instruction code part and a 1-byte address part. For example, an instruction “LDK A, (03H)” is converted into 1-byte instruction code portion data “3FH” and 1-byte address portion data “03H”. The addresses are stored in the order of “3FH” and “03H”.

  An instruction 2203 is an instruction for setting an arbitrary 2-byte value in a designated register. “Nn” in the figure indicates a 2-byte value set in the register. For example, when it is desired to set a value of “5678H” in the HL register 1212A, an instruction “LD HL, 5678H” is given.

  When this instruction 2203 is stored in the user program ROM 103, it is converted into code data of a total of 2 bytes including a 1-byte instruction code part and a 2-byte address part. For example, an instruction of “LD HL, 5678H” is converted into data “21H” of a 1-byte instruction code part and data “78H” and “56H” of a 2-byte address part. Are stored in the order of “21H”, “78H”, and “56H”.

  Similarly, “LD SP, nn” is an instruction for setting an arbitrary 2-byte value (n) in the stack pointer 1233. These instructions are also converted into data of a 1-byte instruction code part and a 2-byte address part, and stored in predetermined continuous addresses of the user program ROM 103.

  The instruction 2204 is an instruction for setting a 2-byte value stored in an arbitrary continuous address area in the HL register 1212A. “Nn” in the figure indicates the smaller consecutive address value. For example, when it is desired to set the values stored in the addresses “2901H” and “2902H” in the HL register 1212A, “LD HL, (2901H) ". At this time, the value stored at the address “2901H” is stored in the L register 1211A, and the value stored at the address “2902H” is stored in the H register 1210A.

  When the value of the HL register 1212A is stored in an arbitrary continuous address area, the instruction is in the form of “LD (nn), HL” as shown in the figure. For example, when it is desired to store the value of the HL register 1212A in each address area of “2901H” and “2902H”, the instruction is “LD (2901H), HL”. At this time, the value of the L register 1211A is stored at the address “2901H”, and the value of the H register 1210A is stored at the address “2902H”.

  When this instruction 2204 is stored in the user program ROM 103, it is converted into code data of a total of 3 bytes including a 1-byte instruction code part and a 2-byte address part. For example, an instruction “LD HL, (2901H)” is converted into data “2AH” in a 1-byte instruction code part and data “01H” and “29H” in a 2-byte address part. Are stored in the order of “2AH”, “01H”, and “29H”.

  The instruction 2205 regards the value stored in the K register 1230 as an upper byte, and considers a 2-byte value synthesized by using a value indicated by an arbitrary 1-byte value as a lower byte as an address, and stores it in the address area. This is an instruction for setting each of the stored value and the value stored at the address following the address in the HL register 1212A. An arbitrary one-byte lower address in this case corresponds to “n” in the figure.

  Specifically, when the values stored in the addresses “2803H” and “2804H” are to be set in the HL register 1212A, the value “28H” is stored in the K register 1230 in advance, and the “LDK” in that state is stored. The instruction “HL, (03H)” is executed. As a result, the value stored at the address “2803H” is stored in the L register 1211A, and the value stored at the address “2804H” is stored in the H register 1210A.

  When the value of the HL register 1212A is stored in a desired address area, the upper address of the storage destination is set in the K register 1230 in advance and is in the form of “LDK (n), HL” shown in the figure. Execute the instruction. For example, when the value of the HL register 1212A is to be stored in the area of the addresses “2803H” and “2804H”, the instruction “LDK (03H), HL” is set with the value of the K register 1230 set to “28H”. Execute.

  When this instruction 2205 is stored in the user program ROM 103, it is converted into 2-byte code data consisting of a 1-byte instruction code part and a 1-byte address part. For example, an instruction “LDK HL, (03H)” is converted into 1-byte instruction code portion data “2FH” and 1-byte address portion data “03H”. The addresses are stored in the order of “3FH” and “03H”.

  An instruction 2206 is an instruction that branches the process to a specified address. “Nn” in the figure indicates a branch destination address. For example, when branching to an address “5678H”, the instruction becomes “JP 5678H”. When this instruction is executed, the instruction interpretation execution circuit 1242 sets the value of the designated address in the program counter 1234.

  Note that an instruction shown in the format “JP nn” branches to a specified address regardless of the contents of the flag register 1200. If you want to branch only when the zero flag 1306 (FIG. 13) of the flag register 1200 is set, use the instruction “JP Z, nn”. If you want to branch only when the zero flag 1306 is cleared, The instruction “JP NZ, nn” is used.

  When this instruction 2206 is stored in the user program ROM 103, it is converted into a total of 2-byte code data consisting of a 1-byte instruction code part and a 2-byte address part. For example, an instruction “JP 5678H” is converted into data “C3H” of a 1-byte instruction code part and data “78H” “56H” of a 2-byte address part, and a predetermined predetermined address in the user program ROM 103 Are stored in the order of “C3H”, “78H”, and “56H”.

  “CALL nn” of the instruction 2207 is an instruction that calls processing at a specified address and temporarily branches to a processing routine of a call destination. “Nn” in the figure indicates the address of the call destination. For example, when calling the process of the address “5678H”, the instruction is “CALL 5678H”. When this instruction is executed, the instruction interpretation execution circuit 1242 stores the value of the address located at the next step of the instruction currently being executed in the stack area as the return destination address, and then sets the value of the branch destination address. Set in the program counter 1234.

  In the final step of the call destination processing routine, by executing the “RET” instruction described above, the value of the return destination address stored in the stack area can be returned to the program counter 1234. As a result, the process can be returned to the address of the calling process routine.

  When this instruction 2207 is stored in the user program ROM 103, it is converted into a total of 2-byte code data consisting of a 1-byte instruction code part and a 2-byte address part. For example, the instruction “CALL 5678H” is converted into data “CDH” of 1-byte instruction code part and data “78H” “56H” of 2-byte address part, and a predetermined predetermined address of the user program ROM 103 is converted. Are stored in the order of “C3H”, “78H”, and “56H”.

  FIG. 23 is a flowchart of power-on processing for each device (game control device 100, payout control device 210, and effect control device 150) according to the first embodiment of the present invention.

  Specifically, FIG. 23A is a flowchart of the power-on process of the game control apparatus 100, and FIG. 23B is a flowchart of the power-on process of the payout control apparatus 210. C) is a flowchart of the power-on process of the effect control device 150.

  First, the processing when the game control device 100 is turned on (FIG. 23A) will be described. This power-on process is not executed by the game control program stored in the user program ROM 602 (see FIG. 5), but executed by various hardware (hardware around the CPU core 102) provided in the game control device 100. Process.

  First, the game control device 100 receives the reset signal output from the power supply device 160 (2301).

  This reset signal is input from the power supply device 160 to the security circuit 630 (see FIG. 11), the reset terminal (see FIG. 11) of the flip-flop circuit 641 of the RAM access restriction circuit 640, and the reset terminal of the serial transmission circuit 615. . Specifically, when the power is turned on, a reset signal is input to these reset terminals by applying a voltage equal to or lower than a predetermined voltage (for example, 5 V) for a predetermined time. As a result, the reset signal is not input.

  When the reset signal is input from the power supply device 160, the security circuit 630 continues to output the reset signal to the reset terminal of the CPU core 102 until the security check process described later is completed, and waits for the CPU core 102 to start up. Let

  When a reset signal is input to the reset terminal of the serial transmission circuit 615, the voltage levels of the input terminal and the output terminal of the serial transmission circuit 615 are controlled to be low, and various devices (such as ordinary electric power SOL90, big prize opening SOL38). The serial transmission circuit 615 and the output I / F 106 are initialized by the hardware by setting all the ports of the output I / F 106 connected to 0 to 0 (2302).

  Next, the RAM access restriction circuit 640 generates a RAM write prohibition state in which writing to the user work RAM 104 is restricted (2303).

  Specifically, as described with reference to FIG. 11, since the reset signal is input to the clear terminal of the flip-flop circuit 641, a high-level signal is output from the output terminal Q (negative logic) of the flip-flop circuit 641. It becomes a state. As a result, whether a high level signal is input to the other input terminal of the OR gate circuit 642 or a low level signal is input, a high level signal is input to the write command input terminal of the user work RAM 104. As a result, a RAM write prohibition state occurs. Thus, by generating the RAM write prohibition state when the power is turned on, it is possible to prevent the user work RAM 104 from being updated at an incorrect timing.

  Next, the security circuit 630 shown in FIG. 11 to which the reset signal is input executes a self-diagnosis process (2304). The self-diagnosis process is a process for determining whether or not the security circuit 630 has been initialized.

  If it is determined by the self-diagnosis process that the security circuit 630 has been initialized, the security circuit 630 executes a security check process (2305). As described with reference to FIG. 11, the security check process uses the validity confirmation information stored in the HW parameter ROM 603 (see FIG. 5) to verify the validity of the program stored in the user program ROM 602 (see FIG. 5). This is a process for making a determination.

  When the security check process is executed in the process of step 2305, the process proceeds to the game control apparatus program start preparation process. At this time, the security circuit 630 stops the reset signal output to the reset terminal of the CPU core 102, whereby the CPU core 102 is activated. Therefore, the game control device program start preparation process is executed by the CPU core 102. The game control device program start preparation process will be described later with reference to FIG.

  Next, the power-on process (FIG. 23B) of the payout control apparatus 210 will be described. As described above, the payout control device 210 has the same configuration as the game control device 100 shown in FIG. 11 except that it does not include the serial transmission circuit 615. The same components as those of the game control apparatus 100 shown in FIG.

  First, the payout control device 210 receives the reset signal output from the power supply device 160 (2311). Note that the processing in step 2311 is the same as the processing in step 2301.

  When a reset signal is input to the payout control device 210, the voltage level of the output port (included in the input / output I / F 216 in FIG. 4) of the payout control device 210 is set to 0, and various devices (the payout motor 220). And the ports of the input / output I / F 216 connected to the launch control device 221 and the like are all set to 0, and the input / output I / F 216 is initialized by hardware (2312).

  Next, a RAM write prohibition state in which writing to the RAM 214 is restricted by the RAM access restriction circuit 640 of the payout control device 210 occurs (2313). Note that the specific description of the processing in step 2313 is the same as the processing in step 2303.

  Next, the security circuit 630 of the payout control device 210 to which the reset signal is input executes a self-diagnosis process (2314). Note that the specific description of the process of step 2314 is the same as the process of step 2304.

  If the self-diagnosis process determines that the security circuit 630 has been initialized, the security circuit 630 executes a security check process (2315). Note that the specific description of the processing in step 2315 is the same as the processing in step 2305.

  Then, the payout control device 210 executes an initialization process at power-on (2316). The initialization process at power-on is a process for initializing the RAM 214 and the like, and is executed by the CPU 212. Further, before the RAM 214 is initialized, the RAM write prohibition state generated in the process of step 2313 is canceled, and the RAM 214 becomes a RAM writable state.

  Next, the payout control device 210 generates a state in which a command from the game control device 100 can be received (2317). Then, the CPU 212 of the payout control device 210 determines whether or not the command transmitted from the game control device 100 is an initialization command (2319). If it is determined in step 2319 that the command transmitted from the game control device 100 is not an initialization command (the result of 2319 is “N”), the process waits until the initialization command is fetched.

  On the other hand, when it is determined that the command transmitted from the game control device 100 is an initialization command (the result of 2319 is “N”), the payout control device 210 executes an initialization process at the start of communication ( 2320), the process proceeds to the payout control apparatus main process.

  Next, the power-on process (FIG. 23C) of the effect control device 150 will be described. As described above, the effect control device 150 does not include the serial transmission circuit 615, and the game control processing shown in FIG. 11 except that the game processing unit 600 does not include the RAM access restriction circuit 640. The configuration is the same as that of the device 100. The same components as those of the game control apparatus 100 shown in FIG.

  First, the effect control device 150 receives the reset signal output from the power supply device 160 (2321). Note that the processing in step 2321 is the same as the processing in step 2301.

  When a reset signal is input to the effect control device 150, the output port of the effect control device 150 is initialized by hardware (2322).

  Then, the effect control device 150 executes an initialization process when the power is turned on (2323). The initialization process at power-on is a process for initializing the RAM 154 and the like, and is executed by the CPU 152.

  Next, the production control device 150 generates a state in which a command from the game control device 100 can be received (2324). Then, it is determined whether or not the command transmitted from the game control device 100 is an initialization command (2326).

  When it is determined that the command transmitted from the game control device 100 is not the initialization command (the result of 2326 is “N”), the effect control device 150 waits until the initialization command is fetched.

  On the other hand, the effect control device 150 determines that the command transmitted from the game control device 100 is an initialization command (the result of 2326 is “Y”, the effect control device 150 performs an initialization process at the start of communication). Is executed (2327), and the flow shifts to the production control device main process.

  FIG. 24 is a flowchart illustrating the game control device program start preparation process according to the first embodiment of this invention. The first half of the game control device program start preparation process (until the reset address is set in the program counter 1234) is not a process executed by the game control program stored in the user program ROM 602 (see FIG. 5). This is a process executed by the initial value setting circuit 124 (see FIG. 12) provided in the CPU core 102.

  When the CPU core 102 receives the reset signal from the security circuit 630, the built-in reset circuit 1240 causes the initial value setting circuit 1241 to operate. At this time, the built-in reset circuit 1240 causes the instruction interpretation execution circuit 1242 to wait until the initial value setting circuit 1241 sets initial values in the respective registers.

  When the initial value setting circuit 1241 starts operating, the initial value “29FFH” is set in the stack pointer 1233, “28H” is set in the K register 1230, and the reset address “4000H” is set in the HL register 1212A. A value of “00H” (a value of “0000H” in the 16-bit register) is set in the other registers (2401). The reset address may be “0000H”.

  Next, the initial value setting circuit 1241 sets a value of “4000H” as a reset address in the program counter 1234 (2402). As a result, an initial value is set in each register. Next, when the built-in reset circuit 1240 operates the instruction interpretation execution circuit 1242 that has been waiting, the instruction interpretation execution circuit 1242 sets the address indicated by the program counter 1234 (to the reset address of the user program ROM 602 storing the game control program). The program starts running from the equivalent). The process after the instruction interpretation execution circuit 1242 starts executing the program will be described in the game control apparatus main process of FIG.

  Next, game control device main processing executed by the CPU 102 of the game control device 100 will be described with reference to FIGS. 25 and 26. FIG.

  FIG. 25 is a flowchart of the first half of the game control device main process according to the first embodiment of the present invention, and FIG. 26 shows the second half of the game control device main process according to the first embodiment of the present invention. It is a flowchart. Note that these processes are executed by the game control apparatus 100, but strictly, the instruction interpretation execution circuit 1242 is realized by executing the game control program while referring to each register in the CPU core 102. .

  First, the game control device 100 prohibits interruption to the CPU 102 (2501). Then, the game control device 100 sets an initial value “29FFH” in the stack pointer 1233 (FIG. 12) (2502A). As a result, if the value of the stack pointer 1233 is not “29FFH”, it is changed to “29FFH”. Even if the initial value “29FFH” is already set in the stack pointer 1233, the value “29FFH” is set again.

  Next, the game control device 100 sets a value of “28H” in the K register 1230 (2502B). As a result, if the value of the K register 1230 is not “28H”, it is changed to “28H”. Even if the initial value “28H” is already set in the K register 1230, the value “28H” is set again.

  Next, the game control device 100 sets an interrupt mode (2503). The interrupt mode allows the CPU 102 to process an interrupt request from a built-in device and to set a position for executing the interrupt request process in a program.

  Next, the game control apparatus 100 takes in the state of the RAM clear SW signal from the input I / F 105 and stores the state of the fetched RAM clear SW signal in the register of the CPU 102 (2504).

  Then, the game control device 100 executes a delay process that does not use the RAM 104 (2505). This delay process is a process for waiting for a predetermined time. Specifically, the delay process is a process of continuously decrementing until a predetermined number becomes 0 in a storage area where a checksum is not calculated. The delay process becomes a timer timing means for measuring the predetermined time by setting the predetermined number to a time corresponding to the time for waiting. Details of the delay process will be described later with reference to FIG.

  Next, the game control device 100 takes in the state of the RAM clear SW signal again from the input I / F 105 and stores the state of the fetched RAM clear SW signal in the register of the CPU 102 (2506). Note that the CPU 102 stores the state of the RAM clear SW signal in step 2504 and the state of the RAM clear SW signal in step 2506 so that the CPU 102 can compare the states of the two RAM clear signals. The register areas to be used are different areas.

  Next, the game control device 100 sets the RAM write prohibited state generated in the process of step 2303 in FIG. 23 to a RAM writable state (2507).

  Specifically, a clock signal is input from the output control circuit 612 to the clock terminal of the flip-flop circuit 641 in accordance with a command from the CPU 102, and the signal level of the signal line connected to the data terminal of the flip-flop circuit 641 is set to a high level. To. As a result, a high level signal is output from the output terminal Q (positive logic) of the flip-flop circuit 641, and a low level signal is output from the output terminal Q (negative logic). When a low level signal is input, the RAM becomes writable.

  Next, the game control device 100 executes various setting processes using the stack area 706 (2508). This setting process is, for example, a process of setting initial data in various storage areas necessary for game control by calling a subroutine or a function. In this setting process, the CPU 102 sets initial values of the respective bits of the transmission serial channel setting register 633, the transmission control register 632, and the transmission data status register 631 described above with reference to FIGS. Is set.

  These subroutines and functions are called from a plurality of locations described in the game control program, and contribute to reducing the capacity of the game control program. On the other hand, when a subroutine or function is called, processing for saving the return address in the stack area 706 is required as described above.

  Then, the game control device 100 compares the state of the RAM clear SW signal stored in the register in the process of step 2504 with the state of the RAM clear SW signal stored in the register in the process of step 2508, and determines which RAM It is determined whether the state of the clear SW signal also indicates that the RAM clear SW 162 has been operated (2509).

  In the processing of step 2509, it is determined whether or not the RAM clear SW 162 has been operated based on the state of the RAM clear signal acquired at different timings, so that erroneous determination due to noise or the like can be prevented.

  If it is determined in step 2509 that the RAM clear SW 162 has been operated, the game control device 100 initializes all storage areas of the user work RAM 104 (2510).

  Then, the game control device 100 transmits an initialization command signal to the payout control device 210 and the effect control device 150 (2511), and proceeds to the processing of step 2517 shown in FIG.

  On the other hand, if it is determined in step 2509 that the RAM clear SW 162 is not operated, the game control device 100 confirms the power-off confirmation in the first power failure recovery area 701 and the second power failure recovery area 703 of the user work RAM 104. It is confirmed whether the flag is stored (more precisely, whether the power shutdown confirmation flag is on) (2512).

  Then, the game control device 100 determines whether or not the power-off process has been correctly executed when the power supply was stopped immediately before (2513). Specifically, in the game control device 100, when the power shutdown confirmation flag is stored in both the first power failure recovery area 701 and the second power failure recovery area 703, the power shutdown process is correctly executed. On the other hand, when the power shutdown confirmation flag is not stored in at least one of the first power failure recovery area 701 and the second power failure restoration area 703 (when at least one power interruption confirmation flag is OFF). Determines that the power-off process is not correctly executed.

  If it is determined in step 2513 that the power-off process has been correctly executed, the game control device 100 determines that the first power failure recovery area 701, the work area 702, and the second power failure recovery area 703 of the user work RAM 104. The checksum is calculated using, and it is checked whether or not the calculated checksum matches the checksum stored in the checksum area 704 (2514).

  The checksum stored in the checksum area 704 is calculated by using the first power failure recovery area 701, the work area 702, and the second power failure recovery area 703 of the user work RAM 104 when a power failure is detected. , Stored.

  That is, the process of step 2514 is a process of collating whether the information stored in the user work RAM 104 at the time of power failure detection matches the information stored in the user work RAM 104 at the time of power-on.

  Then, it is determined whether or not the collation result of the processing in step 2514 matches the calculated checksum and the checksum stored in the checksum area 704 (2515).

  If it is determined in step 2515 that the checksum calculated in step 2514 does not match the checksum stored in checksum area 704, that is, the information stored in user work RAM 104 when a power failure is detected If the information stored in the user work RAM 104 at the time of power-on does not match, the game control device 100 proceeds to the process of step 2510, initializes all areas of the user work RAM 104, and in the process of step 2511 An initialization command is transmitted to the payout control device 210 and the effect control device 150.

  On the other hand, if the checksum calculated in step 2514 matches the checksum stored in the checksum area 704, the information stored in the user work RAM 104 at the time of power failure detection is determined in step 2515. And the information stored in the user work RAM 104 at the time of power-on match, the game control device 100 initializes an area necessary for starting the game control apparatus 100 (part of the user work RAM 104). (2516). At this time, the power shutdown confirmation flag is erased in each of the first power failure restoration area 701 and the second power interruption restoration area 703 of the user work RAM 104 (more precisely, the power interruption confirmation flag is turned off in each area). Then, the game control device 100 transmits an initialization command to the payout control device 210 and the effect control device 150 (2511).

  When these processes are completed, the initialization process related to the game control device 100 is completed. Next, the processing proceeds to step 2517 shown in FIG.

  Next, after the initialization command is transmitted to the payout control device 210 and the effect control device 150 in the process of step 2511, the game control device 100 performs CTC (Counter Timer Circuit) for measuring various times and performing timer interrupts. Is started (2517), and a random number generation circuit 608 (FIG. 5) for generating random numbers related to game control is initialized (2518). Then, the game control device 100 permits an interrupt to the CPU 102 that is prohibited in the processing of step 2501 (2519).

  Next, the game control device 100 executes an initial value random number update process for updating the initial value random number (2520). The initial value random number returns to the initial value when a random number counter related to game control (for example, a random number counter acquired at the timing of winning the starting prize opening) reaches an upper limit value, but determines the initial value. It is a random number for.

  Then, the game control device 100 confirms whether or not a power failure detection signal is input (2521), and determines whether or not the confirmation result in the processing of step 2521 indicates that the power failure detection signal is input. (2522).

  When the game control apparatus 100 determines that the power failure detection signal is not input (the result of step 2522 is “N”), the power failure has not occurred, and the process returns to step 2520.

  On the other hand, if it is determined in step 2522 that a power failure detection signal has been input (the result of step 2522 is “Y”), the game control device 100 executes power failure processing. First, the game control device 100 prohibits interruption to the CPU 102 (2523), and sets the voltage level of the output port provided in the output I / F 106 to a low level (2524).

  Next, the game control apparatus 100 stores the power shutdown confirmation flag in the first power failure recovery area 701 and the second power failure restoration area 703 of the user work RAM 104 (more precisely, the power interruption confirmation flag is turned on in each area). (2525), a checksum is calculated using the first power failure recovery area 701, work area 702, and second power failure recovery area 703 of the user work RAM 104, and the calculated checksum is stored in the checksum area 704 ( 2526).

  Next, the game control device 100 puts the user work RAM 104 into the RAM write prohibited state by the RAM access restriction circuit 640 (2527).

  Specifically, a clock signal is input from the output control circuit 612 to the clock terminal of the flip-flop circuit 641 in accordance with a command from the CPU 102, and the signal level of the signal line connected to the data terminal of the flip-flop circuit 641 is set to a low level. To. As a result, a low level signal is output from the output terminal Q (positive logic) of the flip-flop circuit 641, and a high level signal is output from the output terminal Q (negative logic). When a high level signal is input, the RAM write inhibit state is entered.

  Then, the game control device 100 stands by until the gaming machine 1 is turned off (2528). In addition, since the backup power supply is connected to the game control apparatus 100, even if a power failure occurs, the power supply is not immediately turned off.

  In the present embodiment, the process of step 2514 makes the RAM writable state by the process of step 2507 before determining the validity of the user work RAM 104 when the power is turned off and the user work RAM 104 when the power is turned on. The timing to make the RAM writable state may be immediately before the initialization process of the user work RAM 104 in the process of step 2510 or 2516 performed according to the legitimacy of the process of step 2514 at the latest.

  As described above, when the power supply is cut off in the gaming machine 1, the user work RAM 104 is set to the RAM writing prohibited state after the necessary power-off process is executed, and the game machine 1 supplies power again. Even when the process returns, the user work RAM 104 is not immediately brought into the RAM writable state, the initialization process related to hardware is executed for a certain period of time, and the process of step 2510 or 2516 performed according to the validity of the process of step 2514 Immediately before executing the initialization process of the user work RAM 104 in the process, by finally making the RAM writable state, it is possible to prevent inadvertent writing of the user work RAM 104 until the user work RAM 104 is initialized.

  Therefore, immediately before the validity determination in the process of step 2514 is performed, the RAM write prohibition state is set. Therefore, erroneous writing is performed in the user work RAM 104 after power-on, and an erroneous determination is made in the process of step 2514. Can be prevented.

  In this embodiment, in order to execute various setting processes using the stack area 706 in the process of step 2508, the RAM write-enable state is set in the process of step 2507 before the validity determination process in the process of step 2514. ing.

  As a result, various setting processes using the stack area 706 that is not the target of the validity determination can be performed before the validity determination is performed, so that various settings of the game control device 100 can be performed at an early stage. Therefore, the game control apparatus 100 can be started up at high speed, and the stack area 706 can be used, so that the processing program can be shared and the program capacity can be reduced.

  In FIG. 15, after initialization of the user work RAM 104 in the process of step 2510 or 2516, an initialization command signal is transmitted in the process of step 2515, but step 2508 before execution of the validity determination in step 2514. An initialization command signal may be transmitted after execution of the process.

  In this case, since it is before execution of the validity determination in the processing of step 2514, an initialization command signal is transmitted using the stack area 706 that does not contribute to the validity determination or a register provided in the CPU 102.

  Even if the register provided in the CPU 102 is not used, for example, a predetermined timer circuit or the like is provided in the game control device 100 separately from the user work RAM 104, and the storage area provided in the timer circuit is updated. It can also be realized by the method. In other words, any storage area that does not affect the validity determination can be used, and preferably, the user work RAM 104 and the storage area can be separated to simplify the program of the CPU 102. It is to be done.

  In the process of step 2510 or 2516, the process of step 2516, which is a process of initializing a part of the RAM 104, takes longer than the process of step 2510, which is a process of initializing the entire area of the RAM 104. Depending on whether the processing of 2510 or the processing of step 2516 is executed, the time for which the initialization command signal is transmitted differs.

  By transmitting the initialization command signal before executing the validity determination in the processing of step 2514, the initialization command signal can be transmitted earlier than transmitting the initialization command signal in the processing of step 2511. In addition, the initialization command signal can be transmitted in a certain time after the power is turned on.

  FIG. 27 is a diagram illustrating processing from step 2501 to step 2502B in the game control device main processing (FIG. 25) according to the first embodiment of this invention. Here, description will be made using the various registers described above with reference to FIG. 12 and the assembly language described with reference to FIGS. 21 and 22.

  Note that a column 2710 in FIG. 27 indicates the address of the user program ROM 103 in which the game control program is stored, and a column 2720 indicates the data stored in the address. For example, “F3H” data is stored in the “4000H” address of the user program ROM 103, “31H” data is stored in the subsequent “4001H” address, and “00H” is stored in the subsequent “4002H” address. The data “2AH” is stored at the subsequent address “4003H”.

  The “DI” instruction in line 2701 corresponds to the interrupt prohibition process in step 2501 of the game control apparatus main process (FIG. 25), and the value of the code “F3H” corresponding to this instruction is stored in the area of the address “4000H”. Is done.

  The instruction in line 2702 also corresponds to the processing in step 2502A, and sets “29FFH” as an initial address in the SP register 1233 corresponding to the stack pointer (SP).

  The instruction in line 2703 similarly corresponds to the processing in step 2502B, and sets the default initial value “28H” of the upper address in the K register 1230. In this way, by setting “28H” in the K register 1230 in advance, a 2-byte value obtained by combining “28H” as an upper byte and a value indicated by an arbitrary 1-byte value as a lower byte is obtained. Assuming an address, the value stored in the address area can be set in a predetermined register. For example, in order to set the value stored at the address “2803H” in the A register 1202A, an instruction “LDK A, (03H)” may be executed. In this way, the code amount can be reduced by 1 byte compared to the case where all of the 2-byte addresses are directly specified. In particular, the amount of code to be reduced can be increased as the frequency of designating a specific area is increased. In the present embodiment, for example, it is shifted every time a variable display game is executed, and is used when an address for storing a start memory frequently accessed is designated. Further, in order to effectively use the K register, the upper addresses of these start-up memories are arranged to be “28H”.

  Note that the address “4000H” of the user program ROM 103 is a reset address as described above. Therefore, when the reset signal is generated, first, the instruction of the code arranged at “4000H” is executed, and thereafter, the instructions arranged at the subsequent addresses are sequentially executed.

  Incidentally, when a reset signal is generated, “29FFH” is set in hardware in the SP register 1233 by the initial value setting circuit 1241, so the instruction in the row 2702 is omitted (in other words, step 2502A in FIG. 25 is omitted). It is also possible. Similarly, when a reset signal is generated, “28H” is hardware-set in the K register 1230 by the initial value setting circuit 1241, so the instruction in the row 2703 is omitted (in other words, step 2502B in FIG. 25 is omitted). It is also possible to do. However, if it is assumed that the initial value setting circuit 1241 does not function and only the value of the program counter 1234 is changed to the value of the reset address, the instructions on the lines 2702 and 2703 are arranged. Is also meaningful.

  FIG. 28 is a diagram illustrating delay processing according to the first embodiment of this invention.

  The delay process shown in FIG. 28 is executed in step 2505 of FIG. 25. At the time when the delay process is executed, the RAM write prohibition state is set so that the value of the user work RAM 104 cannot be updated. This is because the checksum stored at the time of the power failure immediately before is checked against the current checksum immediately after the power is turned on.

  For this reason, the delay process in step 2505 shown in FIG. 25 does not use the user work RAM 104 that includes the storage area in which the validity is determined, and does not use the other storage area (not subject to the determination of validity. The delay processing must be executed using the storage area. Therefore, the delay processing of this embodiment is executed using a register (general-purpose register) provided in the CPU core 102.

  Hereinafter, a delay process using a register without using the storage area of the user work RAM 104 including the non-determination storage area will be described. Since a CPU of the Z80 system is used as the CPU core 102, description will be made using a register and an assembly language used in the CPU of the Z80 system.

  A column 2810 in FIG. 28 indicates the address of the user program ROM 103 in which the game control program is stored as in the column 2710 in FIG. 27, and a column 2820 is stored at the address as in the column 2720 in FIG. The data is shown.

  First, line 2801 corresponds to the first processing of the delay processing, and “0603H” is loaded into the HL register configured as one pair of the H register and the L register of the register of the CPU core 102 (see FIG. 11). . Specifically, “06H” is loaded into the H register, and “03H” is loaded into the L register.

  Next, line 2802 is executed, and the value of the HL register is decremented (subtracted by 1). Therefore, after the line 2802 is executed for the first time, the value of the HL register becomes “0602H”.

  Subsequently, line 2803 is executed, and the value stored in the H register is loaded into the A register. Then, the line 2804 is executed to calculate the logical sum of the A register and the L register. In the row 2805, if the logical sum calculated in the row 2804 is not zero (NZ), the processing returns to the row 2802 (the row whose address is 4023H). Therefore, the processing from the lines 2802 to 2805 is repeated until both the H register and the L register become “00H”.

  That is, in FIG. 28, “0603H” (= 1539) stored in the H register and L register used as the maintenance timer is decremented until “0000H”, and the decrement is performed a total of 1539 times. During this time, the game control apparatus main process shown in FIG. 25 waits in the process of step 2505, so that the activation of the game control apparatus 100 is delayed.

  Here, the delay time is specifically calculated. The delay time is the time when the processes from the rows 2802 to 2805 are executed by the number of repetitions (“0603H” = 1539). Therefore, the execution time of each line from line 2803 to 2805 is calculated. Each line defines an instruction to be executed, and each instruction corresponds to the number of CPU clock cycles (number of states) necessary for execution. Therefore, the execution time of each instruction can be calculated by multiplying the time per state by the number of states corresponding to each instruction.

  In the first embodiment of the present invention, 10 Mhz obtained by dividing the number of clocks 20 Mhz by two is the CPU operation clock, so 1/10000000 = 100 nsec is the processing time per state. Hereinafter, the processing time for each row is specifically calculated.

  The state (number) of the decrement “DEC” instruction executed in line 2802 is 6. Therefore, the processing time of the row 2802 is 6 × 100 n seconds = 600 n seconds. Similarly, the state (number) of the load “LD” instruction executed in the line 2803 is 4 and the state (number) of the load “OR” instruction executed in the line 2804 is 4. The time is 4 × 100 n seconds = 400 n seconds. Further, the state (number) of the jump “JP” instruction executed on the line 2805 is 12 when the operation result on the line 2804 is non-zero, and 7 when the result is 0. Since 0 is only at the end of the delay time, if the number of states is 12, the processing time is 12 × 100 n seconds = 1200 n seconds.

  From the above, the processing time in one iteration is 600 nsec + 400 nsec + 400 nsec + 1200 nsec = 2600 nsec. Since the number of repetitions is 1539, 2600 nsec × 1539 = 1.0014 msec, which is a delay time of about 4 sec. Therefore, the delay process in this case is a timer timing means for timing 4 seconds.

  Further, during this delay process, the user work RAM 104 is not accessed at all. That is, the delay process can be executed without rewriting the value of the user work RAM 104 including the storage area where the validity is determined.

  As described with reference to FIG. 28, in the present embodiment, hardware is not used, and it is realized by software using a region that does not contribute to the validity determination, that is, the checksum is not calculated (the maintenance timer is timed). Therefore, it is possible to accurately perform the legitimacy determination in step 2514 shown in FIG. 25, and it can be realized at a lower cost than the delay processing by hardware.

  For example, as a gaming machine that realizes delay processing with hardware, a technique disclosed in Japanese Patent Application Laid-Open No. 2002-224394 is known, and in this gaming machine, payout is performed at the time of return after power is turned off. In order to stop the award medium payout operation until the inconvenience of the problem is resolved, and to prevent troubles between the player and the hall with respect to the award medium payout, At the time of return, when the payout control means is activated prior to the main control means and the payout control is started, the payout operation return processing is executed because the initialization switch is not operated, and then the payout from the main control means is performed. Until the resumption command is received, the payout operation is stopped and the apparatus waits in a state where the payout can be resumed.

  Further, in this gaming machine, when the main control means activated later does not detect an error relating to payout based on the detection switch from the supply replenishment detection switch or the fullness detection switch, a payout restart command is transmitted from the main control means. Therefore, the payout control means is configured to resume the payout operation in response to receipt of the payout restart command.

  In this gaming machine, a delay circuit 90 is provided in the main control means (main control board 39) in order to activate the main control means with a delay from the payout control means, and reset from the reset signal generating means 77. Since the signal arrives at the main control means with a delay of time t from reaching the payout control means (payout control board 46) (see paragraphs [0051] to [0051] of JP-A-2002-224394). [0053] Refer to FIG. 9 and FIG. 11) Since hardware such as the delay circuit 90 is necessary, there is a problem that the cost increases. Further, since the delay circuit 90 is configured by hardware, there is a problem in that the delay time value cannot be changed by a program.

In this case, a function corresponding to the delay circuit 90 is provided in the main control means (main control board 39).
If implemented by software using a PU, the problem in terms of cost will be solved, but in order to measure the delay time using a CPU, the backup memory 39b of the main control means (main control board 39) must be used. In this case, the main control means confirms the validity of the backup memory 39b after activation, and measures the delay time after the backup memory 39b becomes usable. Was left behind. Therefore, it is possible to provide a gaming machine that prevents the activation of the entire gaming machine from being delayed while reducing the cost by delaying the activation of the gaming control apparatus from the activation of the dependent control apparatus by software. It was desired.

  Returning to the present embodiment, when the number of registers that can be used by the CPU core 102 is small, it is more effective to execute the delay process using the stack area. However, it is desirable to prevent as much as possible that the storage areas of the first power failure recovery area 701, work area 702, second power failure recovery area 703, and checksum area 704, which are subject to the validity determination, are rewritten due to noise or the like. In this case, it can be said that it is more effective to set the user work RAM 104 to the RAM write prohibited state during the delay process and execute the delay process not using the stack area shown in FIG.

  In addition, it is possible to increase the processing speed of the CPU by setting the number of operation clocks high. However, if the processing speed is increased, the number of loops in the delay processing (“0603H” in FIG. 28 = 1539). ) Needs to be increased by the speed. However, if the calculation processing speed is increased too much, the number of loops becomes too large, the number of bytes in the register for storing the number of loops exceeds a predetermined number of bytes (for example, 2 bytes), and the capacity of the program increases. End up. Therefore, as described with reference to FIG. 28, by setting the operation speed (number of clocks) of the CPU 102 so that the number of bytes of the register for storing the number of loops falls within 2 bytes (the number of loops does not exceed 65536). Thus, it is possible to suppress an increase in program capacity while realizing high-speed communication.

  FIG. 29 is a flowchart illustrating timer interrupt processing according to the first embodiment of this invention. This timer interrupt process is executed by the CPU core 102 of the game control apparatus 100.

  When the power of the gaming machine is turned on, the game control device main process (see FIGS. 25 and 26) is executed. When a timer interrupt is generated at a predetermined time period (for example, a period of 4 milliseconds) by the CTC activated in the process of step 2517, the timer interrupt process is repeatedly executed by the CPU 102 of the game control apparatus 100. However, these processes (processes 2912 to 2922) do not necessarily have to be performed every time an interrupt occurs. For example, in the input / output process of step 2912, the input signal is monitored every time, but the output process may be executed every other occurrence of an interrupt. That is, instead of completing all the processes in one interrupt process, this interrupt process may be repeatedly executed a plurality of times to complete a series of game control processes.

  In the timer interrupt process of the present embodiment, the game control device 100 first saves the register data in the stack area 706 (2911). Here, by executing an instruction described in the game control program, it is used in a process (caller process) immediately before the timer interrupt process is called out from a register inside the CPU core 102 (see FIG. 12). A process for selecting the saved data and saving it in the stack area 706 is performed.

  However, regarding the flag register 1200 (see FIG. 12), as shown in FIG. 19D, the instruction is executed again because it has already been saved in the stack area 706 when the timer interrupt processing starts. There is no need.

  Next, the game control device 100 executes an input / output process (2912). The input / output process includes an input process and an output process. In the input process, signals input from various sensors (special drawing start SW 34A, universal drawing start SW 31A, count SW 36A, winning opening SW 32A to 32N, overflow SW 109, out of ball SW 110, frame opening SW 111, etc.) via the input I / F 105. This is a process of performing processing such as chattering removal and determining input information.

  The output process is performed through the output I / F 106 based on the parameters set in the special figure game process (2919) and the general figure game process (2920), and the special figure display unit 120, the general figure display unit 121, Signals for controlling the electric SOL 90 and the special winning opening SOL38 are output.

  As described above, the input process and the output process do not have to be executed simultaneously by one timer interrupt.

  Next, the game control device 100 performs command transmission processing for outputting (command) set in the transmission buffer in various processings to the effect control device 150 and the payout control device 210 (2913). Specifically, an effect command signal (effect command) related to the special symbol variation display game is output to the effect control device 150, or a discharge command signal (payout command signal, payout command) is output to the payout control device 210. . Details of the command transmission processing will be described later with reference to FIG. The payout command will be described in detail with reference to FIG. 33, and the effect command will be described in detail with reference to FIG.

  After that, the game control device 100 performs a random number update process 1 in which the value of the big hit random number counter (the big hit random number generation region in FIG. 15) for determining whether the special symbol variation display game is missed is incremented by one (2914). . In this random number update processing 1, in order to determine the value of the big hit symbol random number counter (the big hit symbol random number generation region in FIG. 15) for determining the stop symbol of the special symbol change display game, the hit difference of the normal symbol change display game. 1 is also added to the normal random number counter (the normal random number generation area in FIG. 15).

  Next, the game control apparatus 100 updates the initial value of the random number, and executes an initial value random number update process for breaking the temporal regularity of the random number (2915). The initial value random number update process in step 2915 is the same as the initial value random number update process (2520) shown in FIG.

  Then, the game control device 100 updates the random display pattern random number counter (the first variation P random number of FIG. 15) for updating the random number for determining the variation display pattern in the decorative special symbol variation display game related to the special symbol variation display game. A random number update process 2 is performed in which the values of the generation area, the second fluctuation P random number generation area, and the third fluctuation P random number generation area) are added one by one (2916).

  Next, the game control device 100 performs a winning opening monitoring process in order to monitor whether or not a gaming ball has won a winning opening (2917). Specifically, whether or not there is a signal input from the first special figure start SW 37A, the second special figure start SW 34A, the general figure start SW 31A, the count SW 36A, and the winning openings SW 32A to 32N (a signal indicating detection of a game ball) Is monitored).

  At this time, when a big hit occurs and the special variation winning device 36 is open, the number of game balls detected is counted by the count SW 36A, and the number of game balls won to the special variation winning device 36 is counted. When the counted result reaches a predetermined number (for example, 10), the special variable winning device 36 is closed and the process of updating to the next round is performed.

  At this time, if a game ball is detected by the general chart start SW 31A, it is increased by “1” on condition that the value of the general chart hold counter is less than a predetermined number (for example, less than “four”), The common random number counter value (the common random number generation area in FIG. 15) is stored in the common figure start winning storage area (FIG. 15) corresponding to the common figure hold counter.

  If a game ball is detected by the first special figure start SW 37A, various random numbers are stored in the first special figure start winning storage area (FIG. 16) in the “start opening SW monitoring process” described later. . Similarly, if a game ball is detected by the second special figure start SW 34A, various random numbers are stored in the second special figure start winning storage area (FIG. 17) in the “start opening SW monitoring process” described later. The

  After that, the game control device 100 performs an error monitoring process for monitoring the clogging of the discharged balls, abnormalities of various switches, sensors, etc. (2918).

  Thereafter, the game control apparatus 100 performs a special figure game process (2919) for performing a process related to the special symbol variation display game, and a general figure game process (2920) for performing a process regarding the normal symbol variation display game.

  The special figure game process (2919) is extracted based on the winning of the game ball at the start winning opening detected by the first special figure starting SW 37A and the second special figure starting SW 34A, and stored in the special symbol starting winning memory. It is determined whether or not the special symbol random number counter value is a hit, and the special symbol display 120 executes a special symbol variation display game. The special figure starting winning memory stores the extracted random number as the starting winning memory when the game ball wins the starting winning opening in a state where the variable display game cannot be immediately executed. Details of the special game process will be described later with reference to FIG.

  In the special figure game process (2919), a process for displaying the variation of the identification information corresponding to the display on the special figure indicator 120 is performed. If the extracted random number is a predetermined value, a hit state related to the special symbol is entered, and the variation display of the identification information stops at the hit symbol. Also, when the winning state is reached, the open state is such that the special variation winning device 36 can easily accept the game ball.

  The normal game process (2920) is extracted based on the passing of the game ball to the normal symbol start gate 31 detected by the normal symbol start SW 31A, and is stored in the normal symbol start winning memory (2917). It is determined whether or not the random number related to the result of the normal symbol variation display game extracted and stored in the process of (1) is a hit, the value of the general symbol hold counter is decremented by 1, and the normal symbol display 121 changes the normal symbol. Run the display game. If the common random number counter value is a predetermined value, a hit state related to the common figure is set, and a parameter is set for stopping the fluctuation display of the normal symbol in the hit state.

  Next, the game control device 100 performs processing for editing signals output to the segment LEDs (special display display 120 and general display display 121) that are provided in the gaming machine 1 and display various information related to the game (2921). ). Specifically, when the special symbol variation display game is started, the special symbol winning memory number obtained by subtracting the number of executions of the special symbol variation display game started this time is displayed on the special symbol memory display unit of the special symbol display 120. Edit the parameters for: Similarly, when the normal symbol variation display game is started, the normal symbol winning memory number obtained by reducing the number of times of execution of the normal symbol variation display game started this time is displayed on the general symbol display of the general symbol display 121. Edit the parameters.

  Thereafter, the game control device 100 performs an external information editing process for editing external information for outputting the state of the gaming machine 1 to the management computer connected via the inspection device connection terminal 107 (2922). External information includes information related to the progress status of the variable display game, such as whether the symbol has been confirmed, winning, changing the probability, shortening the variable time, starting the variable display game, etc. It is. An error signal indicating that an error has occurred is also included.

  Next, the game control device 100 declares the end of the timer interrupt process (2923).

  After that, the game control apparatus 100 performs a return process (2924) for restoring the registers saved in the stack area 706. Here, by executing an instruction described in the game control program, the value of the register saved in step S2911 is restored. Next, processing for setting permission of the interrupt that has been prohibited is performed (2925).

  And a timer interruption process is complete | finished and it returns to a game control apparatus main process (FIG.25 and FIG.26). Here, the “RETI” instruction is executed instead of the “RET” instruction, and the process returns to the caller process. Therefore, the value of the flag register 1200 (see FIG. 12) saved in the stack area 706 is also restored, and the value indicated by the stack pointer 1233 is also changed from (D) in FIG. 19 to (B) in FIG. To change.

  A register used as an operation target is executed by executing an instruction 2115 (“LD RBS, 0” or “LD RBS, 1”) for switching the “register bank selector” shown in FIG. 21 at the beginning of the timer interrupt processing. It is also possible to switch the group (general-purpose register groups 1220A, 1220B). For example, while the call source process uses the register of the general register group 1220A, the timer interrupt process can be switched to use the register of the general register group 1220B.

  When performing such register bank switching, a register group register different from the call source process is used in the timer interrupt process. In addition, the process of restoring the register in step S2911 is not necessary.

  Even in the timer interrupt processing, since the “RETI” instruction is finally executed, the value of the flag register 1200 (see FIG. 12) saved in the stack area 706 is restored, and the register of the flag register 1200 is restored. The value of the bank selector (RBS) 1301 (see FIG. 13) is also restored to the state before the call. Therefore, the instruction 2115 (“LD RBS, 0” or “LD RBS, 1”) for switching the “register bank selector” shown in FIG. 21 need only be executed once at the beginning of the timer interrupt process.

  Then, the initial value random number update process and the like (the processes of steps 2520 to 2522 in FIG. 26) are repeated until the next timer interrupt occurs.

  FIG. 30 is a flowchart illustrating a procedure of initialization command transmission processing for transmitting an initialization command signal from the game control device 100 according to the first embodiment of this invention to the effect control device 150 and the payout control device 210. This processing corresponds to the initialization command transmission processing in step 2511 of FIG.

  First, the game control device 100 sets the transmission of the effect command and the discharge command to a prohibited state (3001). Specifically, the bit 4 of the transmission control register 632 (FIG. 8) is set to “0” to set the signal output from the transmission data register 635 to a prohibited state.

  Next, the game control apparatus 100 stores an effect command at the time of activation in the transmission data register 635 (3002). Then, the processing is continued until all the production instructions at the time of activation are stored in the transmission data register 635 (3003).

  When all the production commands are stored in the transmission data register 635 (the result of 3003 is “N”), the game control apparatus 100 stores the discharge command at startup in the transmission data register 635 (3004). Then, the processing is continued until all the discharge commands at the time of activation are stored in the transmission data register 635 (3005).

  Finally, the game control device 100 sets the transmission of the effect command and the discharge command that were set to the prohibited state in the process of step 3001 to the permitted state (3006). Specifically, the bit 4 of the transmission control register 632 (FIG. 8) is set to “1” to set the signal output from the transmission data register 635 to be permitted.

  FIG. 31 is a flowchart illustrating a procedure of command transmission processing for transmitting a command from the game control apparatus 100 according to the first embodiment of this invention to the effect control apparatus 150 and the payout control apparatus 210. This processing corresponds to the command transmission processing in step 2913 in FIG.

  The game control device 100 sets bit 4 of the transmission control register 632 (FIG. 8) to “0” in the same manner as the initialization command transmission process, and first sets the transmission of the production command and the discharge command to a prohibited state ( 3101).

  Next, the game control device 100 determines whether or not there is an effect command waiting for transmission (whether there is data to be written in the transmission data register 635 corresponding to the effect control device 150 at the timing of the timer interrupt process this time). (No) is determined (3102). If there is no transmission instruction waiting to be transmitted (the result of 3102 is “N”), processing related to the discharge instruction after step 3112 is executed.

  On the other hand, when there is an effect command waiting for transmission (the result of 3102 is “Y”), the game control apparatus 100 determines whether or not the effect command for start of variation is included in the effect command waiting for transmission. (3103). The variation start effect command is a command corresponding to each of a “stop symbol designation command (MODE = B0H)” and a “decoration symbol variation pattern designation command (MODE = B1H to BFH)” described later in FIG. The presentation control device 150 starts execution of the variable display game on the display device 8 when this command is received.

  When the production command for variation start is included in the production command waiting for transmission (the result of 3103 is “Y”), the game control apparatus 100 stores the production command for variation start in the transmission data register (3104). . Then, the processing is continued until all the change start effect commands included in the effect command waiting for transmission are stored in the transmission data register (3105).

  The game control apparatus 100, when the production command for variation start is not included in the production command waiting for transmission (the result of 3103 is “N”), or the production command for variation start included in the production command waiting for transmission. Are stored in the transmission data register (the result of 3105 is “Y”), it is determined whether or not another effect command is included in the effect command waiting to be transmitted (3106).

  When the effect command other than the start of variation is not included in the effect command waiting for transmission (the result of 3106 is “N”), the game control apparatus 100 executes the process of step 3111, and subsequently relates to the discharge command. Execute the process.

  On the other hand, in the case where an effect command other than the start of variation is included in the effect command waiting for transmission (the result of 3106 is “Y”), the game control device 100 has an empty space in the transmission buffer (transmission data buffer register 635A). It is determined whether or not there is (3107). Specifically, if the value of bits 0 to 5 (value indicating the remaining amount of transmission data) in the transmission data status register 631 (FIG. 9) is “00h” to “1Fh”, it is determined that there is an empty space. .

  If there is no space in the transmission buffer (the result of 3107 is “N”), the production command waiting for transmission is carried over to the next transmission timing (3108), the processing of step 3111 is executed, and then the processing related to the discharge command is performed. Execute.

  When there is an empty transmission buffer (the result of 3107 is “Y”), the game control apparatus 100 stores an effect command other than the start of fluctuation in the transmission data register (3109). Then, the processing from step 3107 to 2110 is continued until the transmission buffer becomes full or all the rendering commands are stored in the transmission data register (3110).

  When the process of storing the effect command waiting for transmission in the transmission buffer ends, the game control device 100 sets the bit 4 of the transmission control register 632 (FIG. 8) to “1”, thereby prohibiting the process in step 3101. The transmission of the production command set to “3” is set to the permitted state (3111).

  As described above, when the effect command is transmitted to the effect control device 150 in the command transmission process, the state of change display game in the game control device 100 and the effect control are transmitted by giving priority to the effect command for starting the change. The time difference from the progress state of the variable display game in the device 150 is always fixed. Therefore, it becomes possible to prevent such a problem that the time difference changes every time the variable display game is started, and the variable display executed on the display device 8 while the game control device 100 and the effect control device 150 are synchronized. The game can be executed more reliably. When the transmission of the effect command is completed, processing for transmitting the discharge command to the payout control device 210 is subsequently executed.

  The game control device 100 first checks the SW control area and monitors whether or not the prize ball discharge target switch (SW) has risen (3112). When a game ball wins a prize opening for discharging a prize ball, the prize ball discharge target SW is set to ON. Then, the game control device 100 determines whether or not there is a switch corresponding to the prize ball discharge (3113).

  The SW control area is a storage area for storing detection states of various switches provided in the gaming machine for each timer interrupt. Here, in the SW control area, only the switch from which the winning ball is discharged by the detection of the game ball is targeted, and among these switches, there is a switch whose “rise information” is on. It is determined whether or not.

  The game control apparatus 100 (when the result of 3113 is “Y”) when there is a switch corresponding to the discharge of the prize ball (when there is a SW of the prize ball discharge target whose “rise information” is on). ), One of the prize ball discharge target SWs that is turned on is selected, and a discharge command corresponding to the selected SW is stored in the transmission data register (3114).

  Next, it is confirmed whether or not there are other SWs subject to prize ball discharge whose “rise information” is on at that time. The game control device 100 further selects one of the prize ball discharge target SWs that are on if another prize ball discharge target SW is turned on, and issues a discharge command corresponding to the selected SW. Store in the transmission data register. Then, the processing is continued until a command for discharging all prize balls is stored in the transmission data register (3115).

  When there is no switch corresponding to the prize ball discharge (the result of 3113 is “N”), the game control apparatus 100 sends all the discharge commands corresponding to the switch corresponding to the prize ball discharge to the transmission data register. If it is stored, it is determined whether there is another discharge command waiting for transmission (a command for instructing the payout control device 210 to generate an error or to cancel the error) (3116).

  When there is no other discharge command waiting for transmission (the result of 3116 is “N”), the game control apparatus 100 sets transmission related to the discharge command to the permitted state (3121), and returns to the caller.

  On the other hand, when there is another discharge command waiting for transmission (the result of 3116 is “Y”), the game control apparatus 100 determines whether or not there is an empty transmission buffer (3117). Specifically, if the value of bits 0 to 5 (value indicating the remaining amount of transmission data) in the transmission data status register 631 (FIG. 9) is “00h” to “1Fh”, it is determined that there is an empty space. .

  If there is no space in the transmission buffer (the result of 3117 is “N”), the discharge command waiting for transmission is carried over to the next transmission timing (3118), the transmission related to the discharge command is set to the permitted state (3121), and called. Return to the original.

  When there is an empty transmission buffer (the result of 3117 is “Y”), the game control apparatus 100 stores a discharge command waiting for transmission in the transmission data register (3119). Then, the processing from steps 3117 to 3120 is continued until there is no space left in the transmission buffer or all discharge instructions are stored in the transmission data register (3120). Finally, transmission related to the discharge command is set to a permitted state (3121), and the process returns to the caller.

  As described above, in this embodiment, when a discharge command is transmitted to the payout control device 210 in the command transmission process, the prize ball discharge command is transmitted with priority over other discharge commands (error generation / cancellation commands). By doing so, the prize balls are surely ejected even when the plurality of switches to which the prize balls are to be ejected are simultaneously turned on within the same timer interruption period.

  In this way, control commands such as production commands and prize ball discharge commands are preferentially transmitted according to the contents to control the game so that the game progresses smoothly. By transmitting at the time of occurrence, it is possible to realize accurate command transmission without transmission omission.

  FIG. 32 shows processing performed by the game control device 100, the payout control device 210, and the effect control device 150 when the power is turned on according to the first embodiment of the present invention, and the serial transmission circuit 615 included in the game control device 100. It is a timing chart of a state.

  When the reset signal is transmitted to the serial transmission circuit 615B connected to the payout control apparatus 210 and the serial transmission circuit 615A connected to the effect control apparatus 150, each serial transmission circuit 615 is processed by the process of step 2302 shown in FIG. Transition from the undefined state (3201) to the initial state (3202).

  In this indefinite state, it is not guaranteed whether the level of the signal line output from the serial transmission circuit 615 (serial transmission circuits 615A and 615B) is high level or low level. On the other hand, when the serial transmission circuit 615 is initialized by the reset signal and transits to the initial state, the output signal from the serial transmission circuit 615B is determined to a level indicating OFF.

  The initial state of the serial transmission circuit 615 continues (3203) until the initialization command is set in each serial transmission circuit 615 in order for the game control device 100 to transmit the initialization command in the process of step 2511 shown in FIG. To do.

  On the other hand, when the reset signal is transmitted to the security circuit 630 of the game control apparatus 100, the self-diagnosis process is executed in the process of step 2304 shown in FIG. 23, and the security check process is executed in the process of step 2305 (3204). After the security check process is executed, the CPU 102 is activated, and the game control apparatus main process (FIGS. 25 and 26) is executed by the CPU 102.

  The CPU 102 fetches the first RAM clear signal (3205) before executing the delay process (3206), and fetches the second RAM clear signal (3207) after executing the delay process. In other words, the first RAM clear signal capture (3205) and the second RAM clear signal capture (3207) are executed with a delay process (3206) interposed therebetween.

  As described above, since the delay process is executed during the RAM clear signal fetching executed at the respective times 2205 and 2207, the chattering removal etc. fetched by the first RAM clear signal fetching is performed during the delay process. be able to.

  After waiting in the delay process (3206), the RAM 104 is initialized in steps 2516 and 1510 shown in FIG. 25 (3208). After the initialization command is sent in step 2511, the normal process is performed. The game control is performed (3209).

  When the normal game control is executed, the payout control command is set in the serial transmission circuit 615B connected to the payout control device 210 in order to send the payout control command to the payout control device 210 according to the gaming state. (3210). Further, during the execution of the normal game control, the effect control command is set in the serial transmission circuit 615A connected to the effect control device 150 in order to transmit the effect control command to the effect control device 150 according to the game state. (3211).

  On the other hand, when the reset signal is transmitted to the security circuit of the payout control apparatus 210, the security circuit of the payout control apparatus 210 executes a self-diagnosis process in the process of step 2314 shown in FIG. Check processing is executed (3212). After executing the security check process, the CPU 212 is activated, and the CPU 212 executes an initialization process at power-on in the process of step 2316 in FIG. 14 (3213). When the initialization process of the payout control device 210 is executed, the serial receiving circuit 625 of the payout control device 210 is made ready to receive a command from the game control device 100 (3214).

  When the reset signal is transmitted to the production control device 150, the production control device 150 executes the initialization process at the time of power-on in the process of step 2323 in FIG. 23 (3215). When the initialization process of the effect control device 150 is executed, the serial receiving circuit 625 of the effect control device 150 is set in a state where it can receive a command from the game control device 100 (3216).

  The game control apparatus 100 delays the execution start timing of the initialization process of the RAM 104 by executing the delay process. In other words, the timing for transmitting the initialization command to the effect control device 150 and the payout control device 210 is delayed by the delay process.

  For this reason, the delay process ensures sufficient time for the serial transmission circuit 615B connected to the payout control device 210 and the serial transmission circuit 615A connected to the effect control device 150 to maintain the initial state, and during that time payout control is performed. The device 210 and the effect control device 150 can execute an initialization process so as to be able to receive a command from the game control device 100 via its own serial reception circuit 625.

  Therefore, by providing a delay process, as shown in FIG. 25, even if the gaming machine has a configuration in which the reset signal is simultaneously transmitted to the game control device 100, the payout control device 210, and the effect control device 150, hardware or the like The timing at which each control device starts to start can be appropriately set without providing the delay circuit configured as described above.

  Therefore, as shown in FIG. 32, first, the serial transmission circuit 615B connected to the payout control device 210 and the serial transmission circuit 615A connected to the effect control device 150 are maintained in the initial state. Then, the serial receiving circuit 625 of the effect control device 150 becomes ready to receive the command, and then it is possible to surely execute the sending of the initialization command to the payout control device 210 and the effect control device 150.

  If the serial transmission circuit 615B connected to the payout control device 210 of the gaming control device 100 and the serial transmission circuit 615A connected to the effect control device 150 are maintained in the initial state immediately after the power to the gaming machine 1 is turned on. When the serial reception circuit 625 of the payout control device 210 or the effect control device 150 becomes ready to receive a command, the serial transmission circuit 615B connected to the payout control device 210 and the serial transmission circuit 615A connected to the effect control device 150 Since the output signal level is unstable, there is a possibility that the payout control device 210 or the production control device 150 may erroneously receive this unstable signal level information as a normal signal. May cause.

  Further, before the serial reception circuit 625 of the payout control device 210 or the effect control device 150 becomes ready for command reception, the game control device 100 transmits an initialization command to the payout control device 210 or the effect control device 150. Then, the payout control device 210 and the production control device 150 cannot receive the initialization command, which may cause a malfunction.

  In particular, as in the gaming machine of the present embodiment, a configuration in which a command is transmitted from the game control device 100 to the payout control device 210 in a single direction, or a configuration in which a command is transmitted from the game control device 100 to the effect control device 150 in a single direction. In this case, since it is difficult to confirm whether or not the commanded information is correctly transmitted, it is effective to delay the processing at the time of initialization.

  FIG. 32 shows an example in which the RAM clear signal is fetched twice, but it may be a plurality of times. By executing the delay process between a plurality of times, the time required for chattering removal of the RAM clear signal fetching immediately before the execution of the delay process can be overlapped with the delay time by the delay process. Can do.

  FIG. 33 is a diagram illustrating an example of a discharge command transmitted from the game control apparatus 100 to the payout control apparatus 210 according to the first embodiment of this invention.

  The discharge command transmitted to the payout control device 210 notifies a command to initialize the payout control device 210 (initialization command signal), a command to discharge the prize ball (discharge command signal), and the occurrence and release of an error. There is a command (error notification signal), which is transmitted in a common format consisting of a mode part and an action part.

  First, the initialization command signal will be described. In the initialization command signal, the mode portion has a value of “80H” and the action portion has any value of “00H to 7FH”. The action part of the initialization command signal becomes a value (any value of “00H to 7FH”) corresponding to the authentication code set in the payout control device 210. It is assumed that a value corresponding to the authentication code set in the payout control device 210 is set in the RAM 104, for example. The mode part is set to a value of “80H” or higher, and the action part is set to a value of less than “80H”. When the mode part is received, a value of less than “80H” is transmitted. It is possible to determine that a command has been transmitted.

  The output timing of the initialization command signal is when the game control apparatus 100 is powered on, and specifically, is the process of step 2511 shown in FIG.

  Next, the discharge command signal will be described. Fifteen discharge command signals are prepared corresponding to the number of game media to be paid out by the payout control device 210.

  The mode part of the discharge command signal is “A1H to AFH”. Note that the lower byte of this mode part matches the number of game media for which the discharge command signal commands payout. The action part of the discharge command signal is “5EH to 50H”. This action part has a value obtained by inverting the logic of each bit of the mode part.

  For example, the mode part of the discharge command signal for instructing the payout of one game medium is “A1H”, and the action part is “5EH”. That is, the discharge command signal is composed of 2-byte data including a mode part and an action part.

  The output timing of the discharge command signal is output at the timing when the game ball is won in the general winning opening 32, the first starting winning opening 37, the second starting winning opening 34, and the special variable winning apparatus (large winning opening) 36. .

  Further, when the dispensing control device 210 receives the discharge command signal, if the value obtained by inverting the logic of each bit of the mode portion of the received discharge command signal does not match the value of each bit of the action portion, the received discharge command signal is received. Dispensing of game media corresponding to the command signal is not permitted.

  Finally, the error notification signal will be described. When the discharge command is an error occurrence notification, “C0H” indicating that an error has occurred is set in the mode section. In the action part of the error notification signal, a value corresponding to the type of error that has occurred (any value of “00H to 7FH”) is set.

  When the discharge command is an error release notification, “C1H” indicating that the error has been released is set in the mode section. Further, the action part of the error cancellation signal is set to a value corresponding to the type of error that has occurred (any value of “00H to 7FH”), as in the case of the error notification signal.

  FIG. 34 is a time chart illustrating a procedure for detecting the rise of the switch according to the first embodiment of this invention. In the figure, f is an interrupt cycle, and a timer interrupt is generated at the beginning of the interrupt cycle. D represents a delay time. The rise of the switch, that is, whether or not the switch has been turned on is determined in the input / output process of step 2912 of the timer interrupt process shown in FIG. Note that the first physical level, the second physical level, the logical level, and the rise information shown below are updated each time a timer interrupt occurs, and are arranged for each switch provided in the gaming machine to be the SW control area ( Stored in FIG. 31).

  First, the rise time (3401) and fall time (3402) of the switch will be described. In the input / output process (step 2912 in FIG. 29) when the timer interrupt occurs, the CPU 102 determines that the level of the switch detection signal is different from the previously set first physical level (from low level to high level or high level). The first physical level is newly set to the level of the detection signal. Then, when the detection signal of the switch is different from the previously set second physical level after a predetermined delay time has elapsed, the second physical level is set to the level of the detection signal. Note that the first physical level and the second physical level differ only in detection timing.

  At this time, if the first physical level and the second physical level match, it is determined that the detection signal has changed, and the level is set as the logical level. When the logic level changes from the low level to the high level, the rising information is set on until the delay time elapses after the next timer interrupt occurs. That is, after the rising edge information is set to ON, it is set to OFF when the next timer interrupt occurs.

  Further, in the first embodiment of the present invention, when the signal levels of the first physical level and the second physical level are different, that is, as shown in 3403, when the first physical level is detected, the second physical level is detected. When the level of the detection signal of the switch is different from that at the time of detection, it is assumed that noise has occurred and the logic level is not changed. By configuring in this way, it is possible to prevent the rising information from being set to ON by mistake when noise occurs, and to prevent the prize ball discharge command from being erroneously transmitted to the payout control device 210, as will be described later. it can.

  Further, in the first embodiment of the present invention, when a switch for which the rising edge information shown in the timing chart of FIG. The prize ball discharge command is transmitted from the game control device 100 to the payout control device 210 by storing the prize ball discharge command in the transmission data buffer register 635A) of FIG. Further, the prize ball discharge command is issued for each winning switch (first special figure start SW 37A, second special figure start SW 34A, count SW 36A, and prize opening SW32A to prize opening SW32N in FIG. 4) that is the target of the prize ball discharge. Defined. In the first embodiment of the present invention, there are 16 winning switches that are subject to winning ball discharge.

  At this time, if all the prize ball discharge commands stored in the transmission buffer are not transmitted in one transmission within the timer interruption period, the rise of the switch for prize ball discharge will occur at the next timer interruption. There is a possibility that the prize ball discharge command newly generated when the information is turned on cannot be taken into the transmission buffer. To prevent this, every time a new prize ball discharge command is issued, it is checked whether or not there is a vacancy in the transmission buffer. If there is no vacancy, the prize ball discharge command must be held until the next transmission. In other words, a storage area for holding a prize ball discharge command that cannot be transmitted (for example, an area for temporarily saving the rising information of the SW control area described above) is required. In addition, it is necessary to save the prize ball discharge command that could not be stored in the transmission buffer.

  For example, if the number of prize ball discharge target switches is five and the size of the prize ball discharge command is 2 bytes, data that can be stored in a buffer (transmission data register 635) for transmitting the command to the payout control device 210. If the maximum number of bytes is set to 10 bytes, even if all the switches for discharging the prize balls are simultaneously turned on within the same timer interruption period, all the prize ball discharge commands can be taken into the buffer. However, if the number of prize ball discharge target switches exceeds five, the buffer needs more capacity.

  In the first embodiment of the present invention, since the capacity of the transmission buffer is set to 32 bytes, if there are 16 or less prize ball discharge target switches, all prize balls are discharged when one interrupt occurs. A command can be transmitted from the game control device 100 to the payout control device 210. Therefore, it does not require a storage area for holding a prize ball discharge command that has not been transmitted, and also eliminates the need to save a prize ball discharge command that has not been transmitted. The control program of the game control device 100 can be simplified.

  FIG. 35 is a diagram illustrating an example of the effect control command transmitted from the game control device 100 to the effect control device 150 according to the first embodiment of this invention.

  The commands transmitted to the effect control device 150 include an initialization command and an effect command that is a normal command, and are transmitted in a common format constituted by these mode part and action part.

  First, the initialization command will be described.

  The initialization command includes a power-on command indicating whether or not all areas of the RAM 104 have been initialized, and a series machine specifying command for specifying the series of the gaming machine 1. In addition, a command for notifying the gaming state (low probability state, high probability state, winning suppression state, winning promotion state) of the gaming machine 1 at the time of the previous power shutdown or the number of special symbol winning memories at the time of the previous power shutdown is notified. The command to be included is also included in the initialization command.

  As shown in FIG. 35, the mode part of the power-on command A indicating that all areas of the RAM 104 have been initialized is “80H”, and the action part is “01H”. That all areas of the RAM 104 have been initialized means that the processing of step 2510 shown in FIG. 25 has been executed.

  On the other hand, the mode part of the power-on command B indicating that all areas of the RAM 104 are not initialized, that is, a part of the area of the RAM 104 has been initialized is “80H”, and the action part is “02H”. Is. That all the areas of the RAM 104 have not been initialized, that is, that a part of the area of the RAM 104 has been initialized means that the processing of step 2516 shown in FIG. 25 has been executed.

  Therefore, when the process of step 2510 shown in FIG. 25 is executed, a power-on command A having a mode part “80H” and an action part “01H” is transmitted in step 2511. When the process of step 2516 shown in FIG. 25 is executed, a power-on command A having a mode part “80H” and an action part “02H” is transmitted in step 2511.

  When receiving the power-on command A indicating that all areas of the RAM 104 have been initialized, the effect control apparatus 150 displays on the display device 8 that all areas of the RAM 104 have been initialized.

  Further, when receiving the power-on command B indicating that not all areas of the RAM 104 have been initialized, the effect control apparatus 150 displays on the display device 8 that all areas of the RAM 104 have not been initialized.

  Also, the mode part of the series machine specific command is “81H”, and the action part is “01H to 7FH”. The action part is one of values “01H” to “7FH” corresponding to the series of gaming machines 1. Note that values corresponding to the series of gaming machines 1 are set in the ROM 103.

  Further, the command for notifying the game state (low probability state, high probability state, winning suppression state, winning promotion state) has a mode portion of “90H”, and the action portion has a game at the time of the previous power cut-off. A value associated with each state is stored. For example, the action part is “01H” in the low probability state, and the action part is “02H” in the high probability state. When receiving the command for notifying the game state, the effect control device 150 performs an effect for notifying the game state.

  Further, in the hold information command for notifying the number of special symbol winning memories, the mode portion is “A0H” and the action portion is any value from “00H to 04H”. The action part is a value corresponding to the starting memory number (0 to 4) at the time of the previous power shutdown. Upon receiving the hold information command, the effect control device 150 responds to the received hold information command in the storage display unit (first storage display unit 4920 or second storage display unit 4930 described later in FIG. 49) of the display device 8. The starting memory number to be displayed is displayed.

  The output timing of these series machine identification signals, the command for notifying the gaming state, and the command for notifying the number of special symbol winning memories is when the power is turned on, and is transmitted in the process of step 2511 shown in FIG. Note that the output order of these signals and the power-on command may be either first or second. Furthermore, when there is other information to be notified from the game control device 100 to the effect control device 150 when the power is turned on, it may be transmitted together as an initialization command.

  Next, each effect command will be described.

  First, in the variable display game executed on the display device 8, a pre-change effect designation command that instructs an effect that is output at the timing when a game ball is won at the start opening and is executed before the start of symbol change will be described.

  The mode part of the pre-change effect designation command is “A1H to AFH”, and the action part is any value of “01H to 7FH”. The mode portion corresponds to the first half variation pattern number, and the action portion corresponds to the second half variation pattern number.

  Upon receiving the pre-change effect designation command, the effect control device 150 executes an effect before the start of change of the identification symbol on the display device 8, for example, an effect such as the appearance of a character as a pre-reading notice, and then the change display of the symbol To start the variable display game.

  A decorative symbol variation pattern designation command for designating a symbol variation pattern in the variation display game executed on the display device 8 will be described.

  The mode part of the decorative symbol variation pattern designation command is “B1H”, and the action part is any value of “01H to 7FH”. The mode portion corresponds to the first half variation pattern number, and the action portion corresponds to the second half variation pattern number.

  When receiving the decorative symbol variation pattern designation command, the effect control device 150 starts symbol variation display on the display device 8 and starts a variation display game.

  The decorative symbol variation pattern designation command is transmitted at the timing at which the variation display game symbol variation display is started on the display device 8. Specifically, it is a case where there is a start memory when the variable display game is finished on the display device 8, or a case where a game ball is won at the start winning opening when the variable display game is not executed on the display device 8. .

  Next, a stop symbol designation command for designating a stop symbol in the variable display game on the display device 8 will be described.

  The mode part of the stop symbol designation command is “B0H”, and the action part is one of the values “01H to 7FH”. The action part is a value corresponding to the stop symbol.

  When receiving the stop symbol designation command, the effect control device 150 specifies the stop symbol of the variable display game on the display device 8 based on the received stop symbol designation command.

  The stop symbol designation command is transmitted when the variation display of the variation display game on the display device 8 is started.

  Next, a symbol variation stop command for stopping the symbol whose variation time has elapsed and displaying the variation is described.

  The mode part of the symbol variation stop command is “C0H”, and the action part is “01H”.

  When receiving the symbol variation stop command, the effect control device 150 stops the symbol that is variably displayed on the display device 8.

  The symbol fluctuation stop command is transmitted when the fluctuation time has elapsed.

  Next, a jackpot related command transmitted during the occurrence of a special gaming state will be described.

  The mode portion of the big hit related effect command signal is “D0H”, and the action portion is any value of “01H to 7FH”. The action part is a value corresponding to the progress status of the special game state.

  When receiving the jackpot related command, the performance control device 150 performs an effect related to the special gaming state based on the received jackpot related command.

  An error-related command for notifying the occurrence of an error when an error occurs in the gaming machine 1 will be described.

  The mode part of the error-related command is “70H”, and the action part is one of values “01H to 7FH”. The action part is a value corresponding to the error that has occurred.

  When receiving the error-related command, the effect control device 150 performs an effect for notifying the error that has occurred based on the error-related command.

  The error-related command is transmitted when the game control device 100 detects an error.

  Note that the above-described command (mode portion = “90H”) for notifying the gaming state is transmitted not only when the power is turned on, but also when the gaming state changes during normal gaming. For example, when a low probability state occurs during a game, a command of mode portion = “90H” and action portion = “01H” is transmitted, and when a high probability state occurs during a game, the mode portion = “ 90H "and action part =" 02H "are transmitted.

  In addition, the command (mode part = “A0H”) for notifying the number of special symbol winning memories mentioned above is not only when the power is turned on, but when the game ball is won at the starting winning opening during normal games, Sent when the number increases. For example, when the game ball is won at the start winning opening during the game and the start memory number is changed to “3”, a signal of mode portion = “A0H” and action portion = “03H” is transmitted.

  Therefore, the signal for notifying these gaming states and the signal for notifying the number of special symbol winning memories also function as effect commands.

  As described above, among these signals, the pre-fluctuation effect designation command is fetched into a buffer (transmission data register 635) for transmitting data to the effect control device 150 with priority over other signals. . Thus, the time difference between the progress state of the variable display game in the game control device 100 and the progress state of the variable display game in the effect control device 150 is always fixed.

  FIG. 36 is an explanatory diagram illustrating a configuration of transmission data transmitted from the game control device 100 to the effect control device 150 according to the first embodiment of this invention. FIG. 36A shows a schematic configuration of transmission data, and FIG. 36B shows a detailed configuration of transmission data. The configuration of transmission data transmitted from the game control device 100 to the payout control device 210 is the same.

  As shown in FIG. 36 (a), one set of control command data is composed of mode data DCm for identifying the command classification and action data DCa indicating the content (function) of the command to be executed. These mode data DCm and action data DCa correspond to the prize ball discharge command MODE and ACTION shown in FIG. 33 and the effect control command MODE and ACTION shown in FIG. 35, respectively.

  In this embodiment, the data transmission speed is set so that all the control command data (maximum 32 bytes) set in the transmission buffer can be transmitted in one interrupt cycle. Therefore, without complicating the control program of the game control device 100, processing such as temporarily interrupting command transmission to the effect control device 150 is not required, and the game control device may be delayed due to a delay in command transmission. It is possible to prevent the progress of each control of 100 and the effect control device 150 from deviating.

  Further, as shown in FIG. 36 (b), the mode data DCm and action data DCa constituting one set of control command data are 8 bits of command data, a start bit indicating the start of one frame, Bit parity data, a stop bit indicating the end of one frame is added, and one frame is transmitted as a processing unit. Therefore, the time of one frame is the data transmission time per byte (the time necessary for transmitting one byte of control command data stored in the transmission buffer).

  That is, in this embodiment, the control command data is transmitted using serial communication using an asynchronous method (start-stop synchronization method).

  The effect control device 150 analyzes the received set of control command data (mode data DCm + action data DCa), and generates control data for controlling the display device 8, the sound circuit 156, the decoration control device, and the like.

  In this embodiment, when a series of control command data generated by one interrupt process is transmitted, all the control command data is transmitted at a time within a timer interrupt cycle. That is, after storing a series of control command data in the transmission data register 635, the serial transmission circuit 615 is set in a transmission-permitted state (transmission enable in the transmission control register 632 is set to transmission permission) and transmission is started.

  The effect control device 150 as a subordinate control device recognizes continuously received data as a series of control command data. Then, the rendering device (for example, the display device 8) is controlled using this series of control command data as a processing unit.

  Thereby, the production control device 150 can specify a series of control command data generated for each timer interrupt process, and the production control apparatus 150 can use the series of control command data generated by one timer interruption process as a processing unit. Since it controls, the production based on a series of control command data can be executed continuously (without time lag).

  Next, with reference to FIG. 37, the details of the special game process (2918) in the timer interruption process of FIG. 29 will be described. FIG. 37 is a flow chart showing the procedure of the special figure game process according to the first embodiment of this invention.

  The game control device 100 monitors the winning of the game ball to the first start winning port 37 (see FIG. 3) and the second starting winning port of the normal variation winning device 33 (see FIG. 3), and various random number values based on the winning. Is executed (3700). The details of the start port SW monitoring process will be described later with reference to FIG.

  The game control apparatus 100 performs a count switch monitoring process for monitoring an input from the count SW 36A (see FIG. 3) (3701).

  The game control apparatus 100 determines whether or not the special figure game process timer set in each process of steps 3706 to 3712 is 0 (3702).

  If it is determined that the special figure game processing timer is not 0 (the result of 3702 is “N”), the game control device 100 updates the special figure game processing timer by −1 (3703), and the updated special figure is displayed. It is determined whether or not the game processing timer has timed up to 0 (3704). If the special game process timer has not expired (the result of 3704 is “N”), the game control apparatus 100 executes the process of step 3714.

  On the other hand, when it is determined that the special figure game process timer is 0 (the result of 3702 is “Y”), or when it is determined that the special figure game process timer is up (the result of 3704 is “Y”), the game control apparatus 100 acquires a game process number, and performs a game branch process for selecting a process to be executed based on the acquired game process number (3705).

  When the game process number is 0, the game control device 100 monitors the start of fluctuation of the special figure fluctuation display game, and performs the setting of the fluctuation start of the special figure fluctuation display game, the setting of effects, and the special figure fluctuation processing. A special figure routine process for setting information necessary for the execution is executed (3706). In the special figure routine process, information related to the fluctuation of the special figure fluctuation display game is set, and a process or special figure for decrementing the start memory by one in accordance with the execution of the special figure fluctuation display game based on the start memory. A process for setting a change time in a change display game is performed. Details of the special figure routine processing will be described later with reference to FIG.

  When the game process number is 1, the game control apparatus 100 sets information necessary for performing the special figure display processing (3708) (such as a stop display time of the result in the special figure variable display game). The special figure changing process is executed (3707).

  When the game process number is 2, the game control apparatus 100 executes a special figure display process (3708). In the special figure display processing, when the result of the special figure fluctuation display game is a big hit, information necessary for performing the fanfare interval process (3709) is set, and the result of the special figure fluctuation display game is out of sync Is set with information necessary for performing the special figure routine processing (3706).

  When the game process number is 3, the game control apparatus 100 executes a fanfare interval process for performing a process such as updating the number of times the special winning opening is opened in the special game state (3709). In this process, a round start command is set.

  When the game process number is 4, the game control apparatus 100 performs a special winning opening opening process (3710). In the special prize opening opening process, if the special game state is not the final round, information (including the interval command) necessary for performing the fanfare interval process (3709) is set, and if the special game state is the final round Information necessary for setting a special game state end screen command (a jackpot end command) and performing a winning ball remaining ball process (3711) is set.

  If the game process number is 5, the game control device 100 performs a big winning opening remaining ball process (3711). In the special winning opening remaining ball processing, when the special gaming state is the final round, a time is set until all the gaming balls remaining in the special winning opening are detected by the count SW 42c after the special winning opening is closed. .

  If the game process number is 6, the game control device 100 executes a jackpot end process (3712). In the big hit ending process, a process for ending the special gaming state is performed, and information necessary for performing the special figure routine process (3706) is set.

  After performing the processing of steps 3706 to 3712 based on the game processing number, the game control device 100 executes table data saving processing for saving various set data (3713). After that, the game control device 100 executes a special figure 1 fluctuation control process (3714) for updating the game process timer of the special figure 1 fluctuation display game, and updates the game process timer of the special figure 2 fluctuation display game. The special figure 2 fluctuation control process (3715) to be executed is executed, and the special figure game process is terminated.

  FIG. 38 is a diagram illustrating a branching process based on the game process number in the special figure game process according to the first embodiment of this invention. This branching process is executed in step 3705 of FIG. 37, and the instructions in line 3801 to line 3807 are executed in order. Here, description will be made using the various registers described above with reference to FIG. 12 and the assembly language described with reference to FIGS. 21 and 22.

  Note that a column 3821 in FIG. 38 indicates an address of the user program ROM 103 in which the game control program is stored, and a column 3822 indicates data stored in the address. For example, “F5H” data is stored in the “4800H” address of the user program ROM 103, “0CH” data is stored in the subsequent “4801H” address, and “48H” is stored in the subsequent “4802H” address. The data “3AH” is stored at the subsequent address “4803H”. In subsequent addresses “4804H” to “480BH”, data “10H”, “28H”, “87H”,..., “09H”, “E9H” are stored.

  Furthermore, the values “20H” and “48H” are stored in the addresses “480CH” and “480DH”. The data “4820H” expressing this 2-byte data as 16-bit data (however, the lower address side and the upper address side are interchanged) corresponds to the head address of the special figure routine processing executed in step 3706 of FIG. To do. Similarly, “4840H” in which the data stored in the addresses “480EH” and “480FH” is expressed in 16 bits corresponds to the start address of the special figure changing process executed in step 3707 of FIG.

  Hereinafter, the 16-bit data “4860H”, “4880H”, “48A0H”, etc. stored after “4810H” are executed in steps 3708, 3709, 3710,... Of FIG. This corresponds to the top address of each of the processing during display, fanfare interval processing, winning prize opening processing,. In this manner, in the area of the address values 480CH to 4819H, the start address of each process is stored in the order of the process number, thereby forming a predetermined branch address table.

  The instruction in the line 3801 loads the address value “480CH” that is the head of the above-described branch address table into the HL register 1212A. Next, the instruction in line 3802 is executed, and the game processing number (see 3705 in FIG. 37) is loaded into the A register 1202A. Next, the instruction in line 3803 is executed, and the value of the A register 1202A is doubled.

  Next, the value of the A register 1202A is loaded to the C register 1205A by the line 3804, and the value of “0” is loaded to the B register 1204A by the line 3805, so that the value of the A register 1202A is set to the BC register 1206A. The

  Next, in line 3806, the value of the BC register 1206A is added to the HL register 1212A. Thereby, the branch destination address of the process corresponding to the game process number is set in the HL register 1212A. Finally, by executing the “JP (HL)” instruction in line 3807, the processing is shifted to the address indicated by the HL register 1212A.

  Here, the relationship between each command in the rows 3801 to 3807 and each data in the column 3722 stored in the user program ROM 103 in which the game control program is stored will be described.

  The assembly language instruction describing the game control program is converted into the code described above with reference to FIGS. 21 and 22 and stored in the user program ROM 103. For example, the instruction “LD HL, 480CH” in the row 3801 is converted into values “F5H”, “0CH”, “48H” arranged at addresses “4800H” to “4803H” and stored in the user program ROM 103. Has been. The instructions in rows 3802 to 3807 are also converted into corresponding codes and stored in order at addresses “4803H” to “480BH” of the user program ROM 103.

  In the description after line 3808, the special address routine process, special chart change process, special chart display process, fanfare interval process, big prize opening release process, etc. are arranged in the program. When the corresponding address data is set in the addresses after “480CH” in the user program ROM 103, the above-described branch address table is configured.

  As described above, the start address (“480CH”) of a predetermined branch address table is set in the HL register, and the value corresponding to the process number is updated by updating the value of the HL register according to the process number (SEQNO). can do. Therefore, the HL register functions as a branch address setting register.

  In addition to “JP (HL)”, if there is an instruction to branch by regarding a value indicated by a specific register as an address, the register functions as a branch address setting register. For example, although not shown in FIG. 21, if the instruction “JP (IX)” for branching the process to the address indicated by the IX register 1231 is used, the IX register 1231 functions as a branch address setting register. Will be.

  Further, there is another method in which the value indicated by the HL register is regarded as an address and processing is branched to that address without using the “JP (HL)” instruction. For example, if the “PUSH HL” instruction is executed, the value of the HL register is temporarily stored in the stack area 706, and immediately after the “RET” instruction is executed, the HL register stored in the stack area 706 is stored. The value is stored in the program counter 1234. As a result, the process can be branched to the address of the value indicated by the HL register.

  If such a method is used, it is possible to cause a register other than the HL register 1212A to function as a branch address setting register. For example, if the “RET” instruction is executed immediately after the DE register 1209A is stored in the stack area 706, it branches to the address indicated by the DE register 1209A. In this case, the DE register 1209A functions as a branch address setting register. Will do.

  Next, the details of the start port SW monitoring process (3700) in the special game process of FIG. 37 will be described with reference to FIG. FIG. 39 is a flowchart illustrating a procedure of start port SW monitoring processing according to the first embodiment of this invention.

  In the start port SW monitoring process, the game control device 100 first determines whether or not there is a first start prize (3900). Whether or not there is a prize at the first start prize opening 37 is determined by the presence or absence of a detection signal of a game ball output from the first special figure start SW 37A when there is a prize at the first start prize opening 37. The If there is no first start prize (the result of 3900 is “N”), the game control device 100 executes the process of step 3901. On the other hand, when there is the first start winning (the result of 3900 is “Y”), the game control device 100 executes the special figure start port SW common process (3904) and ends the start port SW monitoring process. To do. Details of the special figure start port SW common process will be described later with reference to FIG.

  The game control apparatus 100 determines whether or not a normal power operation is in progress (3901). Specifically, the game control device 100 determines whether or not the open / close member of the normal variation winning device 33 serving as a general electric (ordinary electric accessory) is in an open state in which a game ball can be won. To do. If the opening / closing member is in the open state and is operating in normal power (the result of 3901 is “Y”), the game control device 100 executes the process of step 3903. On the other hand, when the opening / closing member is in the closed state and is not operating in normal power (the result of 3901 is “N”), the game control device 100 executes the process of step 3902.

  The game control apparatus 100 determines whether or not an illegal winning error has occurred (3902). Specifically, the game control device 100 determines whether or not there is an illegal winning that has occurred while the opening / closing member of the normal variation winning device 33 is in the closed state. Note that a winning detected in a predetermined period after the opening / closing member of the normal variation winning device 33 is closed is determined not to be an illegal winning. If an illegal winning error has occurred (the result of 3902 is “Y”), the game control device 100 ends the start port SW monitoring process. On the other hand, when an illegal winning error has not occurred (the result of 3902 is “N”), the game control device 100 executes the process of step 3903.

  The game control device 100 determines whether or not there is a second start prize (winning to the second start prize port 34 of the normal variation prize winning device 33) (3903). Whether or not there is a prize at the second start prize opening 34 of the normal variable prize winning device 33 is determined by detecting a game ball output from the second special figure start SW 34A when a prize is awarded at the second start prize slot 34. It is determined by the presence or absence of a signal. If there is no second start winning (the result of 3903 is “N”), the game control device 100 ends the start port SW monitoring process. On the other hand, when there is a second start winning (the result of 3903 is “Y”), the game control device 100 executes the special figure start port SW common process (3904) and ends the start port SW monitoring process. To do.

  With reference to FIG. 40, the details of the special view start port SW common process (3904) in the start port SW monitoring process of FIG. 39 will be described. FIG. 40 is a flowchart illustrating the procedure of the special figure start port SW common process according to the first embodiment of this invention.

  In the special figure start port SW common process, the game control device 100 first executes a process of setting a corresponding start winning flag (4000). The game control device 100 starts the winning prize flag based on which of the first starting winning port 37 and the second starting winning port 34 of the normal variable winning device 33 is started by the winning of the special figure starting port SW common processing. Set. As the start winning flag, when the special figure starting port SW common process is started by winning the first starting winning port 37, the special figure 1 flag is set and the second winning winning port 34 of the normal variable winning device 33 is set. When the special figure start port SW common process is started by winning, the special figure 2 flag is set. In the following processing, if the special figure 1 flag is set, the special figure 1 start storage process is performed as a corresponding process, and if the special figure 2 flag is set, the special figure 2 start storage is performed as a corresponding process. Is processed.

  First, the game control device 100 sets a flag corresponding to the start winning opening where the game ball has won (4000). Specifically, a first start winning flag is set when a game ball has won a first start winning opening, and a second start winning flag is set when a gaming ball has won a second starting winning opening.

  Next, the game control device 100 determines whether or not the corresponding number of holds is an upper limit (for example, 4) (4001). The corresponding number of holds is the value of the first special figure hold counter when a game ball wins the first start winning opening 37, and when the game ball wins the second start pay opening 34. The value of the second special figure hold counter is targeted (see FIG. 15 for both).

  At this time, if the number of corresponding holds is the upper limit and the corresponding start memory cannot be stored any more (the result of 4001 is “Y”), the game control device 100 ends this processing and starts the start port. The SW monitoring process ends. On the other hand, when the corresponding hold is not the upper limit (the result of 4001 is “N”), the game control device 100 sets the corresponding start memory number (that is, the first special figure hold counter or the second special figure hold). A process of incrementing one of the counters corresponding to the winning start opening) is executed (4002), and then the process of step 4003 is executed.

  The game control apparatus 100 executes a process for setting the number-of-holds information (4003). The game control device 100 sets the number-of-holds information, which is information on the number of start memories, based on the corresponding start memory number being incremented by one. Note that the number-of-holds information is later transmitted to the effect control device 150 as one of the hold information commands (see FIG. 35) including information related to the start memory. Thereafter, the game control device 100 obtains a corresponding jackpot determination random number (4004), obtains a corresponding jackpot symbol random number (4005), and obtains a variation pattern random number for the corresponding special figure variation display game. (4006) is executed. Here, the random value is acquired from each generation region of the big hit random number, the big hit design random number, and the first to third variation pattern random numbers shown in FIG.

  The game control apparatus 100 executes a special figure hold information determination process using the various random values acquired in steps 4004 to 4006 (4007). Details of the special figure hold information determination process will be described later with reference to FIG.

  Then, the game control device 100 executes processing for storing the corresponding jackpot determination random number (4008), processing for storing the corresponding jackpot symbol random number (4009), and processing for storing the corresponding variation pattern random number (4010). . Here, the game control apparatus 100 stores the various random number values acquired in steps 4004 to 4006 in the corresponding random number storage area.

  The corresponding random number storage area is a storage area for various random numbers necessary for executing the first special figure variation display game described above with reference to FIG. 16 if the start opening to be processed is the first start winning opening 37. Of these, the area corresponding to the first special figure hold counter corresponds. Similarly, if the start opening to be processed is the second start winning opening 34, among the various random number storage areas necessary for executing the second special figure variation display game described above with reference to FIG. This corresponds to the area corresponding to the figure hold counter.

  For example, if the second special figure hold counter is incremented by 1 in the process of step 4002 to “3” as a result of winning the game ball in the second start winning opening 34, “save hold 3” in FIG. The various random number values acquired in steps 4004 to 4006 are stored in the storage area for the various random numbers assigned to “area”.

  Next, the game control device 100 executes a process of setting a hold information command (4011), and ends this process. The hold information command is a command for notifying the number of holds (the value of the first special figure hold counter or the second special figure hold counter) after being updated by winning at the start opening, and is sent to the effect control device 150 immediately after. (To be precise, it is transmitted at the timing when the command transmission process (2912) of the next timer interruption process (FIG. 29) is executed).

  Next, with reference to FIG. 41, the details of the special figure hold information determination process (4007) in the special figure start port SW common process of FIG. 40 will be described. FIG. 41 is a flowchart illustrating a procedure of special figure hold information determination processing according to the first embodiment of this invention.

  In the special figure hold information determination process, when the start memory is newly stored in the random number storage area, that is, the game ball is won in the first start winning port 37 or the second starting winning port 34 (ordinary variable winning device 33). At this timing, the result related information corresponding to the start-up memory is determined. That is, in the special figure hold information determination process, a prefetching process for determining the result related information corresponding to the start memory is performed before the start timing of the special figure variation display game based on the newly stored start memory. It will be.

  In the special figure hold information determination process, the game control device 100 first determines whether or not the process is a special figure 2 start storage process (4100). In the case of the process for the special figure 2 start memory (the result of 4100 is “Y”), the game control apparatus 100 executes the process of step 4103 in order to always execute the prefetch process.

  On the other hand, if the process is not for the special figure 2 start memory (the result of 4100 is “N”), that is, if the process is for the special figure 1 start memory, the game control device 100 receives the normal variation prize. It is determined whether or not the operating state of the device 33 is a suppressed state (4101). When the operation state of the normal variation winning device 33 is not in the suppressed state (the result of 4101 is “N”), the game control device 100 does not execute the pre-reading effect related to the special FIG. The information determination process ends.

  On the other hand, when the normal variation winning device 33 is in the restrained state, the game control device 100 determines whether or not the big hit is being made (4102). When the gaming state is the special gaming state and the jackpot is being hit (the result of 4102 is “Y”), the game control device 100 does not perform the pre-reading effect on the special figure 1 start memory, and the special figure holding information. The determination process ends.

  On the other hand, when it is not a big hit (the result of 4102 is “N”), the game control device 100 determines whether the big hit random number matches the big hit determination value with respect to the start memory, and is a big hit. The special figure jackpot determination process for determining the type and variation pattern of the jackpot is executed (4103). Details of the special figure big hit determination process will be described later with reference to FIG.

  The game control apparatus 100 sets a pre-change effect designating command using information for specifying the jackpot type and information for specifying the change pattern that are temporarily stored in the process of step 4103 (4104). The pre-change effect designation command is set using a change pattern table shown in FIGS. 43 and 44 described later, and is temporarily stored in the RAM 104 of the game control apparatus 100. Then, when the next timer interrupt process (see FIG. 29) is executed and the pre-change effect designation command is transmitted from the game control device 100 to the effect control device 150, the change pattern information storage area of the effect control device 150 is stored. Remembered.

  The details of the special figure jackpot determination process (4103) in the special figure hold information determination process of FIG. 41 will be described with reference to FIG. The process of FIG. 42 is also performed when executing the special figure big hit determination process (4103) in the special figure 1 fluctuation start process (special figure 2 fluctuation start process) of FIG. 46 described later. FIG. 42 is a flowchart illustrating a procedure of special figure jackpot determination processing according to the first embodiment of this invention.

  In the special figure jackpot determination process, a process of determining the jackpot type and variation pattern of the start memory to be determined is performed. Note that when the special figure jackpot determination process of the special figure hold information determination process of FIG. 41 is executed, the start memory newly stored in the random number storage area becomes the determination target, but the special figure 1 fluctuation start process of FIG. When executing the special figure jackpot determination process (special figure 2 fluctuation start process), the start-up memory at which the fluctuation starts is a determination target. That is, the special figure jackpot determination process is a common module that is referred to by a plurality of callers.

  The game control apparatus 100 first determines whether or not the special figure probability changing flag is on (4200). When the special figure probability change flag is on (the result of 4200 is “Y”), the game control apparatus 100 executes jackpot determination in the probability change state, that is, when the special figure probability is high (4201). The special figure certainty flag is set to ON / OFF in the special figure display processing (step 3708 in FIG. 37).

  If the special figure probability change flag is not on (the result of 4200 is “N”), the game control apparatus 100 executes a jackpot determination when the probability of special figure is low, that is, when the special figure probability is low (4202).

  Next, the game control device 100 determines whether or not the corresponding start memory is a big hit (4203). That is, it is determined whether or not the value of the jackpot random number in the start memory matches the jackpot determination value.

  If it is a big hit (the result of 4203 is “Y”), the game control device 100 determines the type of big hit such as a probability big hit or a normal big hit using the corresponding big hit symbol random number of the start memory (4204). ).

  On the other hand, if the corresponding start-up memory is not a big hit, the game control device 100 temporarily stores in the RWM that the type of the big hit is “out of place” (4205).

  Subsequently, the game control device 100 determines whether or not a condition for changing the corresponding special map change display game in the start memory for a short time change is satisfied (4206). Here, when the determination target is the start memory of the special figure 2 fluctuation display game, it is considered that the condition for a short-time fluctuation is satisfied. Alternatively, even if the determination target is the start memory of the special figure 1 variable display game, the start memory number of the special figure 1 variable display game at the time of the determination is the upper limit number (4 in this case), or the normal fluctuation When the operating state of the winning device 33 is in the accelerated state, it is considered that the condition that changes for a short time is satisfied.

  If the condition for short-term fluctuation is satisfied (the result of 4206 is “Y”), the game control device 100 uses the first to third fluctuation pattern random numbers in the corresponding start memory to change the fluctuation pattern of the short-term fluctuation. Is determined (4207).

  On the other hand, if the condition for the short-time fluctuation is not satisfied (the result of 4206 is “N”), the game control device 100 uses the first to third fluctuation pattern random numbers in the corresponding start memory for a long time. A variation pattern of variation is determined (4208). Details of how to determine the variation pattern will be described later with reference to FIGS.

  Finally, the game control device 100 temporarily stores information for specifying the jackpot type including the disparity and information for specifying the variation pattern in the RWM (4209). Here, the information to be specified is a variation pattern number. Thereafter, the game control device 100 ends the special figure jackpot determination process.

  With reference to FIGS. 43 and 44, determination of the variation pattern (steps 4207 and 4208) in FIG. 42 and determination of the variation pattern number in step 4209 will be described. FIG. 43 is a second half variation pattern table according to the first embodiment of this invention. FIG. 44 is a first half variation pattern table according to the first embodiment of this invention.

  FIG. 43A is a table that is selected when it is determined that the corresponding start-up memory is not a big hit in the process of step 4203 of FIG. 42, and the second half variation pattern of the special figure variation display game is determined. The

  First, one of the group numbers 0 to 2 is selected according to the value of the first variation pattern random number in the corresponding start memory. Here, the group number “0” indicates “no reach”, the number “1” indicates “normal reach”, and the number “2” indicates “SP reach”. The probability that “no reach” is selected is 2701/3001, the probability that “normal reach” is selected is 295/3001, and the probability that “SP reach” is selected is 5/3001.

  Next, one of the second half variation pattern numbers 01h to 23h is selected according to the value of the second variation pattern random number in the corresponding start memory. Here, the latter half variation pattern number “01h” is “variation without reach” and indicates a variation time of 2 seconds. The second half fluctuation pattern numbers 11h to 13h are “normal reach” fluctuations, the number “11h” is “normal reach short fluctuation” with a fluctuation time of 9 seconds, the number “12h” is “normal fluctuation during normal reach” with a fluctuation time of 10 seconds, and the number “13h”. "Represents" normal reach length fluctuation "with a fluctuation time of 11 seconds. The second half variation pattern numbers 21h to 23h are “SP reach” variations, the number “21h” is “SP reach short variation” with a variation time of 37 seconds, and the number “22h” is “variation during SP reach” with a variation time of 38 seconds. ”And“ 23h ”indicate“ SP reach length fluctuation ”with a fluctuation time of 39 seconds.

  FIG. 43B is a table that is selected when it is determined in step 4203 of FIG. 42 that the corresponding start-up memory is a big hit, and the second half variation pattern of the special figure variation display game is determined. Here, a difference from FIG. 43A will be described.

  When a big hit occurs, “no reach” of group number “0” is not selected in the latter half fluctuation pattern. “Normal reach” or “SP reach” is selected. The probability that “normal reach” is selected is 1501/3001, and the probability that “SP reach” is selected is 1500/3001.

  The second half variation pattern numbers selected from “normal reach” according to the second variation pattern random numbers are 51h to 53h, which correspond to 11h to 13h, respectively, and have the same probability of being selected. Similarly, the latter half variation pattern numbers of “SP reach” are 61h to 63h (corresponding to 21h to 23h).

  As described above, in determining the fluctuation pattern, first, the reach type (including none) of the second half fluctuation is determined using the first fluctuation pattern random number, and then the second half fluctuation pattern (fluctuation) using the second fluctuation pattern random number. Time). Then, the first half variation pattern is determined using the second half variation pattern number indicating the second half variation pattern and the third variation pattern random number (see FIG. 44).

  Next, the first half variation pattern table will be described with reference to FIG.

  In FIG. 44, the first half variation pattern is determined using the third variation pattern random number according to the distribution ratio set for each of the second half variation pattern numbers 01h to 63h.

  The first-half variation patterns include “first-half character A appearance variation”, “first-half character B appearance variation”, and “first-half character variation” that shortens the variation time of “first-half character absence variation”. Each variation time is set to 10 seconds, 10 seconds, 10 seconds, and 1 second.

  As a result of using the first fluctuation pattern random number and the second fluctuation pattern random number, when the second half fluctuation pattern is determined to be “normal reach fluctuation”, when the value of the third fluctuation pattern random number is 0 to 200, “ “First Half Character A Appearance Variation” is selected, “First Variation Character B Appearance Variation” is selected when the value of the third variation pattern random number is 201 to 205, and “3rd Variation Pattern Random Value” is 206 to 400. Select “No First Character Variation”.

  As a result of using the first variation pattern random number and the second variation pattern random number, if it is determined that the latter half variation pattern is “SP reach variation”, the character is controlled to appear without fail, and the third variation pattern When the value of the random number is 0 to 200, “first half character A appearance variation” is selected, and when the value of the third variation pattern random number is 201 to 400, “first half character B appearance variation” is selected.

  As a result of using the first fluctuation pattern random number and the second fluctuation pattern random number, when the latter half fluctuation pattern is determined to be “unreachable fluctuation” (in the case of the latter half fluctuation pattern number = 01h), the third fluctuation pattern When the value of the random number is 0 to 5, “first character A appearance variation” is selected. When the value of the third variation pattern random number is 6 to 400, “first half shortened variation” is selected when the condition for short-term variation in step 4206 in FIG. 42 is satisfied, and this condition is not satisfied. In this case, “change without first half character” is selected.

  In the first embodiment of the present invention, the “first half shortening variation” is set only in the case of “non-reach variation” of the second half variation pattern number 01h. Then, “variation without reach” is selected with a high probability when the type of jackpot is “out of place”. In addition, in the case of “variation without reach”, the probability that “change without first-half character” is selected is low, and the probability that “variation without first-half character” or “variation without first-half character” is selected is high.

  Accordingly, when there is a large number of reserved memories, there is a high probability that “no reach / first half shortened variation” will be selected when there is a shift, so the overall average variation time is shortened. When the number of reserved memories is small, the probability that “no reach / no first half character fluctuation” is selected is high when there is a shift.

  On the other hand, when there is a loss, there is a low probability that a change with reach (“normal reach change” and “SP reach change”) or “no reach / first character A appearance change” without reach will be selected. ing. Note that the probability that the special figure variation display game is a big hit is 1/301 at a low probability and 1/61 at a high probability.

  In the present embodiment, fluctuations with reach (“normal reach fluctuation” and “SP reach fluctuation”) and “no reach / first character A appearance fluctuation” are represented by a common fluctuation time regardless of the number of reserved memories. The common variation mode is set. Since these fluctuation modes are determined by the jackpot result of the special figure and the first to third fluctuation pattern random numbers, they are determined without depending on the number of the reserved storage numbers at the time of performing the determination process. . That is, if it is the same hold storage, the fluctuation mode determined by the special figure big hit determination process (4104) of the special figure hold information determination process (FIG. 41) and the special figure 1 (special figure 2) fluctuation start process (FIG. The variation mode determined by the special figure jackpot determination process (4606) of 46) matches.

  On the other hand, “no reach / first half shortening variation” and “no reach / first half character variation” are variation patterns in which one of them is selected based on the number of reserved storage numbers, and are therefore inherent variation modes. . These fluctuation modes are determined not only depending on the jackpot result of the special figure and the first to third fluctuation pattern random numbers, but also depending on the number of reserved storage numbers at the time of performing the determination process. That is, even in the same hold storage, the variation mode determined by the special figure jackpot determination process (4104) of the special figure hold information determination process (FIG. 41) and the special figure 1 (special figure 2) fluctuation start process ( The variation mode determined by the special figure big hit determination process (4606) of FIG. 46) does not always match. However, if the variation mode determined in the former process is an inherent variation mode, the variation mode determined in the latter process is also set to be the inherent variation mode.

  These first-half variation patterns are provided with first-half variation pattern numbers, but the first-half variation pattern numbers differ depending on whether the first-half variation pattern is determined at the timing of starting winning or variation start.

  The special figure jackpot determination process of FIG. 42 using this table is a special figure holding information determination process executed when a game ball wins the first start winning port 37 or the second starting winning port of the normal variation winning device 33 ( 41) is executed for prefetching the result of the start-up storage of the object, and is also executed in the special figure 1 (special figure 2) fluctuation start process (FIG. 46) described later.

  This is because the number of stored memories is different or the game state is different at the time of starting winning and at the start of variation. That is, the processing result in the special figure big hit determination process of FIG. 42 may be different between the start winning prize and the fluctuation start, and the selected first half fluctuation pattern may be different. Therefore, it is possible to determine whether the first half variation pattern number is determined at the time of starting winning or at the start of variation.

  Here, the first letter of the first variation pattern number determined at the time of starting winning is “A”, and the first letter of the first variation pattern number determined at the start of fluctuation is “B”. In the case of “first character A appearance variation”, the number following E / C is “1h”, in the case of “first character B appearance variation”, it is “2h”, and in the case of “first character non-character variation”, “3h”. And “4h” in the case of “first half shortening fluctuation”. In this way, modules that are common to each other are used.

  As will be described later with reference to FIG. 50, in this embodiment, “Character A” appears in “First half character A appearance variation”, and “Character B” appears in “First half character B appearance variation”. .

  Next, with reference to FIG. 45, details of the special figure routine process (3706) in the special figure game process of FIG. 37 will be described. FIG. 45 is a flowchart showing the procedure of the special figure normal processing according to the first embodiment of this invention.

  In the special figure normal processing, the game control device 100 first determines whether or not there is a special figure 2 start memory that is suspended (4500).

  If there is a special figure 2 start memory (the result of 4500 is “Y”), the game control device 100 executes a special figure 2 fluctuation start process (4501), and then the special figure game process shown in FIG. Then, the special figure game process number is set to 1 so that the special figure changing process is executed (4504).

  Further, the game control device 100 executes a process of setting the total fluctuation time corresponding to the determined first half fluctuation pattern and the latter half fluctuation pattern calculated in the special figure 2 fluctuation start process in the special figure game processing timer (step 4505). . Thereafter, the special figure routine processing is terminated. Note that since the variation time is set in the special figure game process timer in the process of step 4505, the special figure variation process (3707) in FIG. 37 is not executed until the variation time has elapsed.

  On the other hand, when there is no special figure 2 start memory (the result of 4500 is “N”), the game control device 100 determines whether or not there is a special special figure 1 start memory (4502). When there is special figure 1 start memory (the result of 4502 is “N”), the game control device 100 executes special figure 1 fluctuation start processing (4503). Thereafter, the game control device 100 executes a process of setting the special figure game process number to 1 (4504). Further, a process for setting the determined fluctuation time in the special figure game process timer calculated in the special figure 1 fluctuation start process is executed (4505), and the special figure routine process is terminated.

  If it is determined that there is no special figure 1 start memory (the result of 4502 is “N”), the game control device 100 determines whether or not a customer waiting demo flag is set (4506). When the customer waiting demo flag is set (the result of 4506 is “Y”), the game control device 100 ends the special figure routine processing. On the other hand, when the customer waiting demo flag is not set (the result of 4506 is “N”), the game control device 100 executes a process of setting the customer waiting demo flag (4507). Furthermore, the setting of the customer waiting demo command is executed (4508), and the special figure routine processing is terminated.

  The customer waiting demonstration command set in the processing of step 4507 is transmitted to the effect control device 150 later. The production control device 150 executes, for example, a process of displaying the customer waiting demo image on the display unit of the display device 8 based on the reception of the customer waiting demo command.

  As shown in FIG. 45, in this embodiment, the game control device 100 changes the special figure 2 variation display game based on the special figure 2 start memory to the special figure 1 start memory when there is the special figure 2 start memory. It is executed preferentially over the special figure 1 variation display game based on it.

  Next, the details of the special figure 1 / special figure 2 variation start process (step 4503, step 4501) in the special figure ordinary process of FIG. 45 will be described with reference to FIG. FIG. 46 is a flowchart showing the procedure of the special figure 1 / special figure 2 fluctuation start process according to the first embodiment of this invention.

  First, in the special figure 1 fluctuation start process, the game control device 100, among various random number storage areas (see FIG. 16) related to the first special figure fluctuation display game, the area subject to the next fluctuation, that is, one hold. A reserved random number storage area corresponding to the eye is designated (4600). Next, after acquiring the big hit random number, the big hit symbol random number, and the first to third variation pattern random numbers from the storage area designated in the processing of step 4600, the hold 2 is stored in the hold random number storage area corresponding to the first to third hold. Each random number in the reserved random number storage area corresponding to the fourth (the storage area corresponding to the subsequent change) is shifted (4601). Then, 1 is subtracted from the number of holdings in FIG. 1 (4602), and the processing after step 4606 is executed.

  Next, the game control device 100 executes the special figure jackpot determination process shown in FIG. 42 using the various first random numbers held in the process of step 4601 (4606). Next, using the information temporarily stored in step 4209 of the special figure jackpot determination process of FIG. 42, a decorative symbol variation pattern command to be transmitted to the effect control device 150 is set (4607). The decorative symbol variation pattern command is a command for determining the content of the decorative special symbol variation display game executed on the display device 8.

  Further, the game control device 100 sets a hold information command (4608). As described above, the hold information command is a command for notifying the number of hold of the special figure 1 or the special figure 2, and here, the hold number of the special figure to be changed is set in the special figure 1 or the special figure 2. . Then, in step 4609, the variation time corresponding to the determined variation pattern set in step 4505 of the special figure normal processing in FIG. 45 is acquired (4609), and then the special figure 1 variation start process is terminated.

  Similarly, in the special figure 2 fluctuation start process, the game control apparatus 100 executes the processes of steps 4603 to 4605 in response to the processes of steps 4600 to 4602 of the special figure 1 fluctuation start process described above.

  The game control device 100 designates an area to be subjected to the next change, that is, a reserved random number storage area corresponding to the first hold among the various random number storage areas (see FIG. 17) related to the second special figure change display game. (4603). Next, after acquiring the big hit random number, the big hit symbol random number, and the first to third variation pattern random numbers from the storage area designated in the processing of step 4603, the hold 2 is stored in the hold random number storage area corresponding to the first to third hold. Each random number in the reserved random number storage area corresponding to the fourth (the storage area corresponding to the subsequent change) is shifted (4604). Then, 1 is subtracted from the number of holds in FIG. 2 (4605), and the processing after step 4606 is executed.

  In step 4606, the special figure jackpot determination process shown in FIG. 42 is executed using the first various random numbers held in the process of step 4604.

  As described above, the special contents big hit determination process is executed even when the fluctuation of the special figure 1 or the special figure 2 is started, thereby determining the display content of the decoration special figure fluctuation display game.

  47A and 47B are diagrams illustrating an example of a program for processing for shifting the start-up memory according to the first embodiment of this invention. The programs shown in FIGS. 47A and 47B correspond to the process of step 4601 in FIG. FIG. 47A shows a program in which the code amount of the program is reduced using the K register, and FIG. 47B shows a program that does not use the K register.

  Referring to FIG. 47A, first, as shown in line 4701, “28H” is set in the K register, and then, as shown in line 4702, the lower address specified by the LDK instruction and the upper address set in the K register. Access an address combined with an address. In this way, the CPU core 102 serves as a unique value setting means for setting a unique upper address in the K register.

  As described above, when the start memory corresponding to the hold 2 is shifted to the area corresponding to the hold 1, the addresses “2838H” to “283FH” of the start memory corresponding to the hold 2 are shown in FIG. Are moved to addresses “2830H” to “2837H” in the start memory corresponding to the hold 1. In line 4702, the data stored in the address 2838H is stored in the A register, and in step 4703, the data stored in the A register is stored in the address 2830H, thereby moving the data. Similarly, the data stored in “2839H” to “283FH” is moved to “2831H” to “2837H” to shift the start memory corresponding to the hold 2 to the area corresponding to the hold 1.

  The process of shifting the start memory corresponding to the hold 3 to the start memory corresponding to the hold 2 and the process of shifting the start memory corresponding to the hold 4 to the start memory corresponding to the hold 3 are also shown in the figure. It is executed by the second half program.

  FIG. 47B shows a processing program for shifting the start memory as the start memory is digested, as in FIG. 47A, and the same processing as when the program of FIG. 47A is executed is executed. However, in the program shown in FIG. 47B, a 2-byte address is directly specified (for example, “2838H” in line 4722).

  As described above, in the program shown in FIG. 47A, only the lower address of 1 byte needs to be specified in order to specify the address of the area where the start memory is stored (4710). On the other hand, the program shown in FIG. 47B requires a 2-byte capacity for address designation (4730), and requires more capacity than the program shown in FIG. 47A. Therefore, when data is stored in a continuous area like the area for storing the start memory and accessed, the upper address is held in the K register in advance as in the program shown in FIG. 47A. Thus, the program capacity can be reduced by accessing the data.

  In addition, as described above, a specific address value (upper address, for example, “28H”) is set in advance in the K register (upper address specifying register). Therefore, the processing load on the CPU core (arithmetic processing means) 102 can be reduced.

  FIG. 48 is a diagram illustrating an example of a program configuring a subroutine (submodule) according to the first embodiment of this invention. (A) and (B) show an example of a subroutine called when a subroutine calling instruction (CALL instruction or RST instruction) described in the program is executed. On the other hand, (C) shows an example of a subroutine called by the generation of an interrupt signal.

  First, (A) is an example of a program configured such that the value of the flag register stored in the call source routine is not rewritten in the process of the call destination subroutine. This subroutine is an example of starting processing from an address of 5200H, and by first executing the instruction “PUSH FLG”, the value of the flag register is saved in the stack area (line 4811).

  Note that even if a register other than the flag register stored in the call source routine is configured so that it cannot be rewritten in the subroutine, the corresponding register is saved in the stack area using the “PUSH” instruction. be able to. For example, as shown in line 4812, by executing the instruction “PUSH HL”, the value of the HL register can be saved in the stack area.

  When the execution of the series of programs described in the subroutine is finished, the “POP” instruction is executed to restore the values of the HL register and flag register saved in the stack area (line 4813, 4814), the “RET” instruction is executed to return to the caller process (line 4815).

  On the other hand, (B) is an example of a program that sets an operation result in the flag register in the process of the subroutine and returns the value of the flag register to the calling routine. This subroutine is an example of starting processing from an address of 5100H. As shown in (A), using the “PUSH” and “POP” instructions, processing is performed such that the value of the flag register is put into and out of the stack area. Not.

  When the execution of a series of programs described in the subroutine is completed, the operation result is set in the flag register by calculating the logical sum of the values of the A register and the E register (line 4821). After the value is loaded into the A register (line 4822), the "RET" instruction is executed to return to the caller (line 4823).

  The structure of the subroutine as shown in (B) executes a predetermined operation in the subroutine, stores the operation result in the flag register, and returns the stored flag register value to the calling source routine. It is suitable for the case where it is used from the beginning. Therefore, the “PUSH” and “POP” instructions for loading / unloading the value of the flag register into / from the stack area are not described in the subroutine program to be called.

  Such a subroutine configuration is suitable for executing a common process in various places in the game control program. The common process block is arranged in the program as a subroutine in advance and called. This can be realized by executing a CALL instruction (or RST instruction) in the original program.

  However, considering the position of the program producer, there are cases where the flag register used in the subroutine and the flag register used in the caller routine are to be handled separately as in (A), as in (B). In some cases, it is desirable to treat the flag register used in the subroutine and the flag register used in the call source routine as the same.

  Therefore, it is necessary to select whether to save the value of the flag register according to the purpose of calling the subroutine. Therefore, it is preferable that the flag register is selected so as to be taken into or out of the stack area depending on whether or not the “PUSH” and “POP” instructions are described in the program constituting the subroutine.

  On the other hand, (C) is an example of a program that constitutes a subroutine (interrupt processing) called by an interrupt signal such as a timer interrupt. When this subroutine is called, as shown in FIG. 19D, the value of the flag register is saved in the stack area without executing the “PUSH” instruction. At this time, if the bank of the register group used in the call source routine is 0 (table register), the RBS bit of the flag register is “0”.

  Since this subroutine is executed by interrupting the processing being executed in the calling source routine at an arbitrary timing, the value of the flag register used in the called subroutine and the flag used in the calling source routine There is no correlation between register values. For this reason, if the value of the flag register used in the calling source routine is changed in the interrupt processing subroutine, the processing result becomes unexpected.

  Therefore, when the interrupt processing subroutine is called, it is necessary to save the value of the flag register to the stack area without exception. With the configuration of (C), the code of the “PUSH” instruction that saves the value of the flag register in the stack area becomes unnecessary, so that the code amount of the program describing the interrupt processing subroutine can be reduced.

  Incidentally, the interrupt processing subroutine (C) is an example in which processing is started from an address of 5300H. When “LD RBS, 1” in line 4831 is executed, the RBS bit of the flag register becomes “1”. As a result, the usable register group is switched from bank 0 (front register) used in the call source routine to bank 1 (back register). At this time, the value stored in each register of the bank 0 register group is held as it is, and the interrupt processing subroutine is executed using the register of the bank 1 register group.

  Furthermore, by executing “RETI” at the end of the interrupt processing subroutine, the processing returns to the calling source processing (line 4832). At this time, the value of the flag register saved in the stack area is restored, so that the RBS bit of the flag register is restored to “0”, and the bank of the register group used thereafter is restored to 0.

  In the subroutine (A), when the usable register group is switched to the bank 1 (back register), after executing “PUSH FLG” in the row 4811, the instruction “LD RBS, 1” may be executed. . As a result, the RBS bit of the flag register is set to “1”, and the usable register group is switched from bank 0 (front register) used in the call source routine to bank 1 (back register). In this case, by executing “POP FLG” in line 4814, the RBS bit of the flag register is returned to “0”, and the bank of the register group is returned to 0 immediately before returning to the calling source process. .

  In the subroutine (B), when the usable register group is switched to the bank 1 (back register), the instruction “LD RBS, 1” may be executed in the program, but immediately before returning to the calling routine. The instruction “LD RBS, 0” needs to be executed.

  As described above, as shown in FIGS. 48A to 48C, in this embodiment, a subroutine call instruction (CALL instruction or RST instruction) described in the program is executed in the call source routine. When an interrupt signal is generated, a subroutine is called, and at this time, the return address value included in the calling source routine is stored in the stack area.

  In this case, since the interrupt signal is generated regardless of the address under execution of the calling source routine, an interrupt signal is generated when calling the interrupt processing subroutine as shown in (C). It is preferable to save the value of the flag register 1200 at the point of time in the stack area so that it is not destroyed during the processing of the called routine.

  Therefore, as shown in FIG. 19D, not only the return address value included in the call source routine, but also the value of the flag register 1200 is stored in the stack area, and the process proceeds to the call destination processing. It has become. As a result, the value of the flag register is automatically stored in the stack area even if an instruction (“PUSH FLG”) for storing the flag register in the stack area is not described in the program of the called routine. , Can save the code amount of the program.

  On the other hand, when a call instruction such as a CALL instruction described in the call source routine is executed, the value of the flag register 1200 set in the call source routine is set as shown in FIG. However, as shown in (B), the value of the flag register 1200 set during the processing of the call destination routine is changed to the call source routine. It may be returned and used for calculation. That is, whether or not the value of the flag register 1200 set in the call source routine should be saved in the stack area is case by case.

  For this reason, as shown in FIG. 19C, only the return address value included in the call source routine is stored, and the value of the flag register 1200 is not stored in the stack area, and the process proceeds to the call destination process. It is the composition which makes it. Whether or not the value is to be saved depends on whether or not an instruction (for example, “PUSH FLG”) that stores the value of the flag register 1200 in the stack area is described in the program of the called routine. The configuration is selectable.

  Further, as shown in FIGS. 48A to 48C, in the present embodiment, since it has a function of switching the bank of general-purpose registers, by switching the bank in the call destination routine, A register different from the caller can be used.

  In particular, in the interrupt processing subroutine shown in (C), even if an instruction for restoring the value of the flag register is not executed, “RETI” is executed at the end of the processing to save the stack area. The flag register value is automatically restored. Therefore, it is possible to return the bank when returning to the call source routine without executing an instruction for restoring the value of the flag register in the subroutine, so that the code amount of the program can be further saved.

  FIG. 49 and FIG. 50 are diagrams for explaining screen transitions in the decorative special figure variation display game executed on the display device 8 in the first embodiment of the present invention.

  Screen (a) shows the state before the start of variation, and when the start-up memory is exhausted, as shown in screen (b), each identification symbol starts to vary in symbol display area 4910. A first storage display unit 4920 and a second storage display unit 4930 are set below the symbol display area 4910. In each of these memory display units, a mark (normal hold memory display) 4940 indicating that there is a reserved memory and a mark 4950 indicating that there is no reserved memory are displayed. After that, as shown in the screen (c), the variation of the identification symbol is stopped in the order of the left symbol and the right symbol, and finally the variation of the middle symbol is stopped, and the variation is stopped as shown in the screen (d). It becomes a state.

  At this time, when the left symbol and the right symbol are stopped at the same symbol, the reach state is reached as shown in the screen (e), and then the variation of the middle symbol is continued. If the result of the variable display game is out of place, as shown in the screen (f), the middle symbol stops with a symbol different from the left and right identification symbols. Further, when the result of the variable display game is a big hit, as shown in the screen (g), the middle symbol stops at the same identification symbol as the left and right identification symbols. When a big win is obtained in the variable display game, as described above, a transition is made to the special game state, and the player can obtain a lot of game values.

  In addition, the reach shown on the screen (e) is a normal reach. However, instead of the screen (e) or after the reach shown on the screen (e), the middle symbol is rotated as shown on the screen (h). Super (SP) reach may be generated. When the SP reach occurs, the probability that the result of the variable display game is a big hit is set to be larger than that of the normal reach.

  Moreover, although the screen (i) shows the state after the start of fluctuation, the prefetch notification is executed for one of the start memories. Specifically, the prefetch notification is executed when the first half variation pattern number set at the time of starting winning is for performing the first half variation in which the character A or the character B appears. At this time, the pre-read notification is performed by displaying a specific hold storage display 5010 having a display mode different from the normal hold storage display 4940 on the storage display unit.

  After that, when the start memory is digested (screen (j)) and the variable display game based on the start memory for which the pre-read notification has been made is started (screen (k)), a notice effect in which the character appears is executed (screen). (L), screen (m)).

  A character A (first character) 5020 appears on the screen (l), and a character B (second character) 5030 appears on the screen (m). These characters A and B preferably have different display modes. However, even if the display modes are the same, the size, number of appearances, moving speed, etc. of the appearing characters are made different between the characters A and B so that the player can distinguish them. If it is, it will not be specifically limited.

  In the present embodiment, the character appears in the first half of the change (a state before the change of some of the identification symbols stops and the reach state occurs). Thereafter, the left and right identification symbols are stopped, and a reach state is generated (screen (n)). At this time, super reach or normal reach occurs. Note that the character described above may appear in this reach state.

  In the present embodiment, in the winning opening SW monitoring process (step 2917 in FIG. 29), when a game ball is detected by the general game start SW 31A, the normal random number counter value (the general random number generation area in FIG. 15) is detected. ) Is stored in the usual figure start winning storage area (FIG. 15), but another random number may be stored as long as it is a random number related to the usual figure variation display game. For example, the random number generation circuit 608 generates a random number related to the general fluctuation display game (generates a hard random number), and when the general game start SW 31A detects a game ball, the generated random number is normally started. You may make it memorize | store in a prize memory | storage area | region (FIG. 15).

  Further, in the present embodiment, each of the big hit random numbers, big hit symbol random numbers, and first to third variation pattern random numbers shown in FIG. 15 is generated in the processing of steps 4004 to 4006 of the special figure start port SW common processing (FIG. 40). Although the random number value is acquired from the area, another random number may be acquired as long as it is a random number related to the special figure variation display game. For example, the random number generation circuit 608 generates all or part of the jackpot random number, jackpot symbol random number, and first to third variation pattern random numbers (generates a hard random number), and executes the processing of steps 4004 to 4006 The generated random number may be acquired.

  Here, in this embodiment, the order in which the value of the flag register and the return address value are stored in the stack area when an interrupt process is called will be described.

  First, in contrast to the first embodiment of the present invention, FIG. 51A shows that when an interrupt process is called, the return address value is first stored in the stack area, and then the value of the flag register is stacked. It is a figure at the time of assuming storing in an area | region. With reference to (A) to (C) of FIG. 51A, how the data saved in the stack area changes during the execution of the interrupt processing routine will be described.

  Note that “FLG” in FIG. 51A indicates the value of the 1-byte flag register. “ADR_H” indicates the value of the upper byte of the return address, “ADR_L” indicates the value of the lower byte of the return address, and the return address value of 2 bytes is obtained by combining “ADR_H” and “ADR_L”. Is configured.

  First, FIG. 51A (A) shows a state immediately after an interrupt process occurs and the return address value and the flag register value are stored in the stack area. Next, when a “PUSH” or “CALL” instruction is executed in the interrupt processing routine, another save data is accumulated in the stack area as shown in FIG. 51A (B).

  Next, when a “POP” instruction or the like is executed in the subsequent interrupt processing routine, the stored saved data is gradually restored, and when the final stage of the interrupt processing routine is reached, the state returns to the state of FIG. 51A (A). It will be. When the “RETI” instruction is executed at the end of the interrupt processing routine, the value of “FLG” is returned from the stack area to the flag register and stored, and the return address values of “ADR_H” and “ADR_L” are restored. By storing in the program counter, the process moves to the address of the call source routine corresponding to the time when the interrupt signal is generated, and the subsequent processes are continued.

  Until the “RETI” instruction is executed, the value of the stack pointer during execution of this interrupt processing routine is always smaller than the address (29F9H in the figure) of the area where the value of the flag register is stored. Increase or decrease within the range of values (2980H to 29F8H).

  However, if there is a bug in the interrupt processing routine program, the stack pointer value may fall outside the expected range. For example, if the “POP” instruction is executed once more than the number intended by the program developer, the value of the stack pointer is set to the address (29F9H) of the area where the value of the flag register is stored. It will point temporarily. If the “PUSH” instruction is executed only once in this state, another value is overwritten on the value of “FLG” saved at the address 29F9H.

  When such a bug exists, when the “RETI” instruction is executed at the end of the interrupt processing routine, as shown in (C) of FIG. 51A, the “evacuated” addresses 29FAH to 29FBH are saved. There is a possibility that only “FLG” saved in the address 29F9H is rewritten to an abnormal value without rewriting “ADR_H” and “ADR_L”.

  In this case, since the value stored in the flag register after the return is an abnormal value, it is considered that the subsequent processing does not operate normally and a failure occurs. However, since the return address values ("ADR_H" and "ADR_L") that return to the program counter are normal values, if the "RETI" instruction is executed at the end of the interrupt processing routine, the program does not run out of control. Return to the routine and continue processing.

  Therefore, during the game machine development period, the developer may not be aware of the presence of bugs in the program. Even if the occurrence of a failure is noticed, there is a high possibility that the program will not run out of control, so it may be difficult to identify the cause of the failure.

  On the other hand, FIG. 51B shows that the flag register value is first stored in the stack area when the interrupt processing is called, and then the return address value is stored in the stack area, as in the first embodiment of the present invention. It is a figure at the time of storing. With reference to (A) to (C) of FIG. 51B, how the data saved in the stack area changes during the execution of the interrupt processing routine will be described. Note that “FLG”, “ADR_H”, and “ADR_L” in FIG. 51B have the same configuration as in FIG. 51A.

  First, (A) of FIG. 51B shows a state immediately after an interrupt process occurs and the return address value and the flag register value are stored in the stack area. Next, when a “PUSH” or “CALL” instruction is executed in the interrupt processing routine, another save data is accumulated in the stack area as shown in FIG. 51B (B).

  Next, when the “POP” instruction or the like is executed in the subsequent interrupt processing routine, the stored saved data is gradually restored, and when the final stage of the interrupt processing routine is reached, the state returns to the state shown in FIG. 51B (A). It will be. When the “RETI” instruction is executed at the end of the interrupt processing routine, the value of “FLG” is returned from the stack area to the flag register and stored, and the return address values of “ADR_H” and “ADR_L” are restored. By storing in the program counter, the process moves to the address of the call source routine corresponding to the time when the interrupt signal is generated, and the subsequent processes are continued.

  Until the “RETI” instruction is executed, the value of the stack pointer during execution of this interrupt processing routine is always smaller than the address (29F9H in the figure) of the area where the return address value is stored. Increase or decrease within the range of (2980H to 29F8H).

  At this time, as in FIG. 51A described above, if there is a bug or the like in the interrupt processing routine program, the value of the stack pointer may deviate from the expected range. In this case, values such as “ADR_L”, “ADR_H”, and “FLG” saved in the stack area may be overwritten with another value, and the “RETI” instruction is executed at the end of the interrupt processing routine. Sometimes, the value of the flag register does not return to normal.

  However, unlike FIG. 51A described above, the configuration of FIG. 51B rewrites only “FLG” saved in the stack area without rewriting the values of “ADR_H” and “ADR_L” saved in the stack area. That is impossible. The reason for this is that, as shown in (C) of FIG. 51B, since there is a characteristic in the order of putting data in and out of the stack area, when “FLG” is rewritten to an abnormal value, it is saved above it. This is because the values of “ADR_H” and “ADR_L” are also considered to be rewritten.

  In this way, the state shown in FIG. 51B (C) is reached at the end of the interrupt processing routine, and when the “RETI” instruction is executed in this state, the abnormal address value saved to the addresses 29F9H to 29FAH is stored in the program counter. Since it is stored, it cannot return to the calling routine, and the program will run out of control.

  That is, with the configuration of FIG. 51B similar to the present embodiment, if the value stored in the flag register after return becomes an abnormal value, the program counter after execution of the “RETI” instruction is also abnormal. The address value is always stored. Therefore, if there is a bug in the interrupt processing routine, the program runs out of control during the development period of the gaming machine, and the developer can easily recognize the occurrence of the failure. Therefore, it is possible to realize a gaming machine in which program bugs are easier to find than in the configuration of FIG. 51A.

  Next, in the present embodiment, the relationship between the number of bytes of the flag register value and the number of bytes of the return address value stored in the stack area when the interrupt process is called will be described.

  First, in FIG. 51C, in contrast to the first embodiment of the present invention, it is assumed that the number of bytes of the flag register value and the number of bytes of the return address value are both composed of 2 bytes. FIG. 51A to 51D, the saved data state in the stack area immediately after the start of the interrupt process and immediately before the end, and the state in the stack area immediately after the start of the subroutine called by the CALL instruction and immediately before the end. The state of saved data will be described.

  Note that “FLG” in FIG. 51C indicates the value of the 2-byte flag register. Further, “ADRW_H” and “ADRW_L” indicate the values of the upper byte and the lower byte of the return address value stored when the interrupt process occurs. Further, “ADR2_H” and “ADR2_L”, and “ADR1_H” and “ADR1_L” are the upper byte and the lower byte of the address value stored before the interrupt processing occurs. Note that “ADR3_H” and “ADR3_L” indicate the upper byte and lower byte values of the return address value stored when the subroutine by the CALL instruction is started instead of the occurrence of the interrupt processing.

  First, FIG. 51C (A) shows a state immediately after an interrupt process occurs and the return address value and the flag register value are stored in the stack area. In the last step of this interrupt processing, the “RETI” instruction is executed, whereby the 2-byte flag register value and 2-byte return address value are restored from the stack area. It should be noted that the value of the stack pointer is also increased or decreased in accordance with the storage status of data in the stack area, and when returning to the calling process after execution of the “RETI” instruction, the stack area is shown in FIG. 51C. The state shown in FIG.

  On the other hand, when the subroutine is called by executing the CALL instruction in the call source process instead of the interrupt process, only the return address value is stored in the stack area as shown in FIG. 51C (C). The value of the flag register is not stored. In the last step of this subroutine, only the 2-byte return address value is restored from the stack area by executing the “RET” instruction. It should be noted that the value of the stack pointer is also increased or decreased according to the data storage status in the stack area. When the process returns to the caller after execution of the “RET” instruction, the stack area is shown in FIG. 51C. The state shown in FIG.

  However, if there is a bug in the subroutine program called by the CALL instruction, and the “RETI” instruction is executed by mistake instead of the “RET” instruction at the end of the subroutine, (C) in FIG. 51C. From the state shown, not only the values of “ADR3_H” and “ADR3_L” are returned to the program counter as return address values, but also the values of “ADR2_H” and “ADR2_L” are regarded as values of the 2-byte flag register and returned. It will be. Therefore, when returning to the caller process after executing the “RETI” instruction, the stack area is in the state shown in FIG. 51C (D).

  Thereafter, when the “RET” instruction is further executed in the calling source process, the return address values of “ADR1_H” and “ADR1_L” are acquired from the state of (D) in FIG. 51C, and the program counter is returned to that address. Will be transferred to. This is because the process is performed at an address different from the original return address values (“ADR2_H” and “ADR2_L” in FIG. 51C (B)) that should be acquired when the “RET” instruction is executed in the caller process. This is equivalent to migrating.

  In this case, since a process different from the process that should be originally performed is performed, some kind of failure should occur. However, the return address values of “ADR1_H” and “ADR1_L” that are acquired by mistake are used as address values on the program. This is the value being used. Therefore, the program returns to the calling routine without continuing the runaway and the processing is continued.

  Therefore, during the game machine development period, the developer may not be aware of the presence of bugs in the program. Even if the occurrence of a failure is noticed, there is a high possibility that the program will not run out of control, so it may be difficult to identify the cause of the failure.

  On the other hand, FIG. 51D is a diagram in the case where the number of bytes of the flag register value is different from the number of bytes of the return address value, as in the first embodiment of the present invention. 51A to 51C, the state of the saved data in the stack area immediately after the start and immediately before the end of the interrupt processing, and the state in the stack area immediately after the start of the subroutine called by the CALL instruction and immediately before the end. The state of saved data will be described.

  Note that “ADR1_H”, “ADR1_L”, “ADR2_H”, “ADR2_L”, “ADR3_H”, and “ADR3_L” in FIG. 51D have the same configuration as in FIG. 51C. However, “FLG” in FIG. 51D is composed of 1 byte, which is different from FIG. 51C.

  First, (A) of FIG. 51D shows a state immediately after the return address value is stored in the stack area when the CALL instruction is executed in the call source process to call a subroutine. In this case, only the return address value is stored in the stack area, and the value of the flag register is not stored. In the last step of this subroutine, only the 2-byte return address value is restored from the stack area by executing the “RET” instruction. It should be noted that the value of the stack pointer is also increased or decreased in accordance with the data storage status in the stack area, and when returning to the caller process after executing the “RET” instruction, the stack area is shown in FIG. 51D. The state shown in FIG.

  However, if there is a bug in the subroutine program called by the CALL instruction and the “RETI” instruction is executed by mistake instead of the “RET” instruction at the end of the subroutine, the process shown in FIG. From the state shown, not only the values of “ADR3_H” and “ADR3_L” are returned to the program counter as return address values, but also the value of “ADR2_L” is regarded as the value of the 1-byte flag register. Therefore, when returning to the caller process after executing the “RETI” instruction, the stack area is in the state shown in FIG. 51C (C).

  Thereafter, when the “RET” instruction is further executed in the calling source process, the values of “ADR1_L” and “ADR2_H” are acquired as return address values from the state of (C) in FIG. 51D and stored in the program counter. It will move to the place indicated by the program counter. This is because the processing is performed at an address different from the original return address values (“ADR2_H” and “ADR2_L” in FIG. 51D (A)) that should be acquired when the “RET” instruction is executed in the calling source processing. This is equivalent to migrating.

  In this case, among the addresses acquired in error, “ADR2_H” is recognized as the lower byte of the address and “ADR1_L” is recognized as the upper byte of the address, so an address that is not actually in the correct combination is generated. Therefore, it is considered that the address value is not used as an address value on the program. Therefore, when the “RET” instruction is subsequently executed, an abnormal address value is stored in the program counter, and therefore, the possibility of the CPU running out of control increases. Therefore, if there is a bug in the interrupt processing routine, the program runs out of control during the development period of the gaming machine, and the developer can easily recognize the occurrence of the failure. Therefore, it is possible to realize a gaming machine in which a bug in the program is easier to find than in the configuration of FIG. 51C.

  By configuring as described above, even when the flag register and the return address are saved in the stack area, even if the data stored in the stack area is rewritten due to noise or the like, the failure is caused early. Since it becomes possible to identify the cause, it becomes easy to identify the cause when a failure occurs, and it is possible to improve development efficiency.

  Here, the contrast between the prior art and the present invention as opposed to the present invention is performed.

  First, a gaming machine as disclosed in Japanese Patent Application Laid-Open No. 2009-183500 is known as Patent Document A. In this gaming machine, in order to reduce the program code and reduce the storage capacity of the storage means than before. In addition, storage means having at least a storage area accessible from the CPU via the I / O space is provided.

  In this gaming machine, as described in paragraphs [0137] to [0142] of Patent Document A, the LD instruction, the IN instruction, and the OUT instruction are properly used, so that the number of states and the program code amount of the entire program can be reduced. Reduced.

  Further, in this gaming machine, as described in FIG. 13 of Patent Document A, an LD instruction for storing data from a designated RAM area into a register, or conversely, an LD for storing data into a RAM area designated from a register. Instruction is used.

  Specifically, “LD A, (2810H)” for storing data at address 2810H in the RAM area in the A register, and “LD (2810H), for storing data in register A at address 2810H in the RAM area. A ”,“ LD HL, (2810H) ”for storing the data at address 2810H in the RAM area in the HL register, and“ LD (2810H), HL ”for storing the data in the HL register at address 2810H in the RAM area And so on.

  Although these instructions are also described in FIG. 13 of Patent Document A, they are instructions that require a 3-byte program code amount. The program code is an arbitrary instruction expressed by a numerical value of a predetermined number of bytes using a combination of an instruction code part (opcode part) and an address part (operand part).

  The instruction code portion is a code necessary for identifying instructions, and is an LD instruction for storing data in a designated RAM area in the A register, such as “LD A, (2810H)”, for example. If there is, a 1-byte value such as “3AH” is assigned. On the other hand, the address portion is a code for designating the address of the RAM area. For example, when designating access to address 2810H, a 2-byte value of “28H” and “10H” is set by the program.

  Since such LD instructions are frequently used in game programs, it is needless to say that the instructions can be expressed with as few bytes as possible in order to reduce the code amount of the entire program. However, when specifying the address of the RAM area, it is necessary to assign a code of at least 2 bytes to the address part, and at least 1 byte of the code of the instruction code part for identifying the instructions is required. The program code for expressing such an LD instruction cannot be reduced to 2 bytes or less.

  Therefore, the present invention aims to reduce the code amount of the entire game control program in order to solve the above-described problems.

  For example, according to the first embodiment of the present invention, an instruction for accessing a RAM (update information storage means) can be realized with a code having a small number of bytes by using an upper address specification register. It becomes. Therefore, the code amount of the entire game control program can be reduced by using the instruction for the game control program.

  Since the upper address specification register itself is a 1-byte register, in order to specify the specific address for the purpose of extracting data from the range of 128 bytes before and after the specific address (or 127 bytes before and after each specific address). Compared to a method using two-byte registers, the register configuration for addressing is simplified.

  Further, by setting a unique address value (“28H”) in the K register (upper address designation register) (unique value setting means), when a reset (startup) signal is generated, the CPU (arithmetic processing means) performs K There is no need to set a unique address value in the register. Therefore, after resetting, it is possible to read / write data from / to the RAM without setting a unique address value in the K register in the game control program. Further, the processing load on the CPU is reduced, and the code amount of the game control program can be reduced.

  In addition, a RAM access restriction circuit for restricting the update of information stored in the RAM is provided, and when a predetermined activation signal is generated, the RAM access restriction circuit causes the RAM to be prohibited from being updated. Since the update prohibition state is released, and then game control is started using information stored at the address specified by the upper address specification register, it is possible to prevent the RAM value from being updated at an incorrect timing. .

  Furthermore, according to the first embodiment of the present invention, since the work area that holds the start memory and the like and the stack area are held in different upper address areas, the stack area is mistakenly changed at the time of random number update or the like. Since it is possible to prevent the data stored in the database from being updated, malfunctions can be prevented.

  In particular, the area that holds the start memory (for example, the random number storage area illustrated in FIG. 16, FIG. 17, FIG. 53A, or FIG. 53B, or the universal random number storage area illustrated in FIG. 15) starts the variable display game. The stored random numbers will be shifted, but since the upper addresses of these areas are all set to be the same (28H), the upper address is designated when the shift process is performed. There is no need to change the register value, and the processing is simplified.

  In addition, if the lower address of the work area is the same and the upper address is the same as the stack area, the CPU is used to update the start-up memory when the upper address value is incorrect by setting the use prohibited area. Is reset to prevent malfunction.

  Next, a pachinko machine as disclosed in Japanese Patent Application Laid-Open No. 10-033804 is known as Patent Document B, and in the program of the control device of the pachinko machine, different instructions are executed corresponding to the gaming state. As described above, branch processing is performed in the program. In Patent Document B, as described in paragraphs [0072] to [0073], a process for branching control is performed in accordance with the value of a process flag, and in that branch, the process is stored in the ROM of the basic circuit 30. This is performed with reference to the process jump table (FIG. 13 of Patent Document B).

  On the other hand, as a CPU used for a control device of a pachinko machine or the like, a Z80 CPU disclosed in Japanese Patent Application Laid-Open No. 11-232099 as Patent Document C is known. As a Z80 series command, a “JP (HL)” command as shown in paragraph [0020] of Patent Document C is prepared. This instruction causes the value stored in the HL register to be recognized as an address, and branches the process to the location of the program indicated by the address. Note that when the CPU is activated, the value of the HL register is an indefinite value.

  When branch processing is performed in the prior art gaming machine program of Patent Literature B, the “JP (HL)” of the CPU of Patent Literature C may be used. In this case, the branch destination is stored in the HL register. After storing the address value, the “JP (HL)” instruction is executed.

  However, since the gaming machine of the prior art of Patent Document B is exposed to a noise environment, there is a risk that the CPU may run away. In particular, when a conventional CPU such as Patent Document C is used, the value of the HL register is an indefinite value immediately after the game machine is turned on and the CPU starts up. When the “JP (HL)” instruction is executed, the CPU may run away because the branch destination is indefinite.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to operate a CPU normally even in a noisy environment in order to solve the above problems.

  For example, according to the first embodiment of the present invention, the eigenvalue setting means (initial value setting circuit in FIG. 12) is provided, and when a start signal (reset signal) is generated, the eigenvalue setting means causes the branch address setting register to Since a unique address value is set, even if a noise or the like occurs immediately after the start of the game control program and a specific command is executed by mistake, the address indicated by the unique address value is set. Processing can be branched. Therefore, even if noise or the like occurs immediately after the start of the game control program, the runaway of the arithmetic processing means can be prevented.

  That is, a program instruction (an instruction for reset processing, etc.) to be executed when the arithmetic processing means runs away is arranged in advance at an address (for example, a reset address of the game control program) indicated by a unique address value. Therefore, even if noise or the like occurs immediately after the start of the game control program, it can be dealt with.

  In the first embodiment of the present invention, the branch address setting register is used to perform branch processing corresponding to the control state of the special figure variation display game (each game state corresponding to the game process number). Even if the control state is sequentially switched, an efficient game control program can be configured so that the branch destination process corresponding to the switched control state can be performed each time. Note that the branching process corresponding to the control state of the normal map display game may also be performed using the branch address setting register.

  Furthermore, according to the first embodiment of the present invention, the stack pointer provided in the CPU core 102 by the initial value setting circuit (unique value setting means) 1241 before the game control program is started when the power is turned on. The initial value is set in hardware. Therefore, even if an interrupt process occurs due to noise or the like immediately after the execution of the game control program starts, the return address of the calling routine can be reliably stored in the stack area. When returning to the calling routine, processing can be continued without any problem.

  Further, even when a specific instruction (JP (HL)) is executed with the reset address value stored in the branch address setting register (HL register), the value of the stack pointer can be set.

  Even if an abnormality occurs during game control and the CPU core 102 is reset by the reset circuit 610B (security circuit 630), the processing of the CPU core 102 is returned to the reset address.

  In this case, even if the initial value is not set in the stack pointer by the initial value setting circuit 1241, the initial value is set in the stack pointer by software immediately after the instruction from the reset address is executed (the game shown in FIG. 25). Since step 2502A) of the control device main process, it becomes possible to set an initial value to the stack pointer corresponding to any reset state. For the same reason, an initial value is also set in the upper address designation register by software (step 2502B of the game control device main process in FIG. 25).

  Further, the game control program is executed when a call instruction such as a CALL instruction described in the call source routine is executed (when the first call condition is satisfied) or during execution of the instruction of the call source routine. When the interrupt signal is generated (when the second call condition is satisfied), the return address value included in the call source routine is stored in the stack area, and the process proceeds to the call destination process. It has a configuration.

  In this case, since the latter predetermined interrupt signal is generated regardless of the address during execution of the call source routine, the value of the flag register 1200 at the time when the interrupt signal is generated is determined by the call destination. It is preferable to save in the stack area so as not to be destroyed during the processing of this routine.

  Therefore, when the latter second calling condition is satisfied, as shown in FIG. 19D, not only the value of the return address included in the calling source routine but also the value of the flag register 1200 is stored in the stack area. It is stored and transferred to the call destination process. Therefore, if the latter second calling condition is satisfied, the flag register can be stored even if an instruction (“PUSH FLG”) for storing the flag register in the stack area is not described in the program of the called routine. Since the value of is automatically stored in the stack area, the code amount of the program can be saved.

  On the other hand, when a call instruction such as a CALL instruction described in the call source routine is executed as in the former case, the value of the flag register 1200 set in the call source routine is set to the value of the call destination routine. Although there is a case where it cannot be destroyed during the processing, the value of the flag register 1200 set during the processing of the call destination routine may be returned to the call source routine and used for the calculation. Therefore, whether or not the value of the flag register 1200 set in the call source routine should be saved in the stack area is case by case. Therefore, during the program of the call destination routine, the value of the flag register 1200 is included in the program. It is more convenient to describe an instruction (for example, “PUSH FLG”) for storing the value in the stack area and determine whether to save the value.

  Therefore, when the former first calling condition is satisfied, as shown in FIG. 19C, the value of the return address included in the calling source routine is stored in the stack area, but the value of the flag register 1200 is stored. Is not automatically stored in the stack area.

  As shown in FIG. 19D and FIG. 51B, since the flag register value is stored in the stack area first and the return address value is set later, the return address value is set. A situation in which only the value of the flag register is destroyed without destruction does not occur. Therefore, as in the gaming machine having the configuration illustrated in FIG. 51A, the process returns to the calling source routine smoothly and continues with the flag register value being destroyed in the calling destination interrupt processing routine. There is nothing.

  Further, as shown in FIGS. 19D and 51D, the value of the return address stored in the stack area is 2 bytes, whereas the value of the flag register stored in the stack area is 1 byte. It has a configuration. As described above, when the return address stored in the stack area and the number of bytes of the flag register are different from each other, the value of the flag register is erroneously returned as the return address in the call destination routine. There is no problem as in the gaming machine having the exemplified configuration, and the return address cannot be obtained in the subsequent processing, so that it is easy to find a bug in the program.

  Further, as shown in FIG. 21 and FIG. 48C, there is a function of switching the bank of general-purpose registers by executing the “LD RBS, 1” instruction (or “LD RBS, 0” instruction). Therefore, a register different from the call source can be utilized by switching the bank in the call destination routine.

  As shown in FIG. 14, in the first embodiment, in the user work RAM 104, the upper address boundary, that is, the boundary between the upper address “28H” area and the “29H” area is continuously provided. Although it is possible to access, a use prohibition area may be provided at this boundary.

  Further, a pachinko machine as disclosed in Japanese Patent Application Laid-Open No. 2009-142666 is known as Patent Document D. In order to reduce the capacity of a program for controlling a gaming machine, the main control board of the pachinko machine When an in / out command for accessing the IO from the CPU is output, the area classification determination unit switches the access destination to either IO or RAM according to the address value, and identifies the IO according to the result A configuration for activating a signal or chip selector signal is disclosed.

  In the configuration of the gaming machine disclosed in Patent Document D, a part of the RAM (pseudo RAM area) can be accessed using in / out commands. In addition to the allocation, the stack area is allocated so that data is sequentially accumulated on the side where the address becomes smaller, starting from the end address.

  In general, it is more convenient to leave the stack to which area of the RAM is left to the discretion of the control device designer because the degree of design freedom increases. Therefore, it is preferable that the initial value of the stack pointer is set to an indefinite value when the CPU is activated, and the initial value of the stack pointer is set by software after the CPU starts executing the program. Therefore, also in the gaming machine of this Patent Document D, it is considered that the initial value of the stack pointer when the CPU is activated is an indefinite value.

  However, when an interrupt signal is generated due to noise or the like when the initial value of the stack pointer is indefinite, there is a possibility that the CPU may perform processing while the area indicated by the indefinite value is regarded as the stack area. Even in this case, the CPU moves the processing to the interrupt processing routine. Even if an instruction such as RETI is executed at the end of the interrupt processing routine, the return address is stored in the area pointed to by the stack pointer at that time. Since there is no guarantee that the value is stored, the CPU may run away. As a result, there is a possibility that a regular game cannot be performed due to an unexpected big hit or the like.

  For this reason, pachinko machines and other gaming machines that are exposed to a noise environment have a problem that it is better to focus on the configuration so that the CPU does not run out of control rather than the degree of design freedom for setting the stack area. .

  In the conventional gaming machine, the stack area allocated in the RAM area has the return address value of the address of the caller module when the CPU calls a predetermined submodule while the game program is being executed. There was something stored as. Then, after the callee submodule is executed, the value of the return address stored in the stack area is returned to the program counter, so that the CPU processing returns to the caller module.

  For example, in the gaming machine disclosed in Patent Document E (Japanese Patent Laid-Open No. 2008-080004), as shown in FIG. 22 of Patent Document E, when an RST instruction is executed, the return address value of the calling module is stacked. And move to the called submodule. Thereafter, by executing a RET instruction at the end of the callee submodule, the return address value stored in the stack area is returned to the program counter, and the caller module is restored. Note that, as shown in paragraph [0148] of Patent Document E, similar processing is performed even when a CALL instruction is used.

  Further, in Patent Document E, there is a change from 0008H to 000FH in ROM in order to suppress unauthorized modification and improve ease of discovery of unauthorized modification while maintaining program maintainability and processing speed. A program for stop command transmission processing is stored, and a program for command ball number command transmission processing is stored at addresses 0020H to 0027H of the ROM, and these programs are called using an RST instruction.

  Even if an RST instruction or CALL instruction is not executed as in Patent Document E, when an interrupt such as a timer interrupt occurs, the return address value of the calling module is stored in the stack and called. There is also a gaming machine that performs processing to shift to the previous submodule (timer interrupt processing module).

  For example, in the gaming machine disclosed in Patent Document F (Japanese Patent Laid-Open No. 2001-212330), as shown in paragraphs [0071] to [0073] of Patent Document F, when an interrupt such as a timer interrupt occurs, The return address value of the caller module is stored in the stack, and the process proceeds to the callee submodule (timer interrupt processing module). Thereafter, the RETI instruction is executed when the callee submodule ends, thereby returning the value of the return address stored in the stack to the program counter and returning to the caller module.

  When such timer interrupt processing is performed, as shown in FIG. 5 of Patent Document G (Japanese Patent Laid-Open No. 2004-089476) and FIG. 6 (c) of Patent Document H (Japanese Patent Laid-Open No. 2006-068568). In general, the flag register value is stored in the stack as an AF register at the beginning of the process. As shown in FIG. 5 of Patent Document G, the value of the flag register stored in the stack is restored to the original flag register when the timer interrupt processing is finished and the RETI instruction is executed. It has become.

  However, if the value of the register used in the caller module is changed in the callee submodule, the CPU processing will be hindered. Therefore, in the conventional gaming machine, as shown in S11 of FIG. 5 of Patent Document G, the process of saving the register value to the stack area using the PUSH instruction is usually performed at the beginning of the process, and the POP is performed at the end of the process. Processing for restoring the value of the register from the stack area using an instruction is performed. At this time, as shown in FIG. 6C of Patent Document H, various register values are temporarily stored in the stack area. For this reason, it is necessary to describe a PUSH instruction or a POP instruction in the callee module, which increases the program capacity.

  The process of putting a register value in and out of the stack using such a PUSH instruction and a POP instruction is not limited to the timer interrupt process disclosed in Patent Document E, but an RST instruction as shown in Patent Document D (or This is also frequently done in submodules called using the CALL instruction. For this reason, it is necessary to describe a PUSH instruction or a POP instruction in such a submodule, which increases the program capacity.

  In the former timer interrupt process, the value of the flag register had to be stored in the stack unconditionally, whereas in the latter module process called using the latter RST instruction (or CALL instruction) Whether or not the flag register should be saved has not been uniquely determined by the purpose of the module. Therefore, a device for reducing the program capacity while satisfying such conditions has been required.

  Next, FIG. 52 is a diagram illustrating an example of a user work RAM 104 according to a modification of the first embodiment of this invention. In the user work RAM 104 shown in FIG. 52, a use prohibition area is provided at an upper address boundary (an area including a boundary line where the RAM address changes from “28FFH” to “2900H”). In this way, by providing a use-prohibited area at the boundary where the higher address changes (changes from “28H” to “29H”), it is possible to prevent attempts to access consecutive areas without changing the upper address. And malfunction can be prevented.

  For example, consider that the values of the A register 1202A are collectively stored in areas before and after such a boundary line. In this case, while the value of the K register 1230, which is the upper address designation register, is fixed to “28H”, the “INK L” instruction (see FIG. 21) is executed to increase the value of the L register 1211A, The instruction (L), A ”(see FIG. 21) is executed.

  At this time, there is a timing when the value of the L register 1211A changes from “FFH” to “00H” by the execution of the “INC L” instruction. This is the timing when the storage location of the value of the A register 1202A crosses the boundary, but in order to specify the correct storage location, it is necessary to change the value of the subsequent K register 1230 to “29H”. Therefore, originally, an instruction to change the value of the K register 1230 to “29H” must be executed in the game program, but there is a possibility that the program producer may miss it.

  In FIG. 52, the work area is set so as to be distributed in two areas having upper addresses “28H” and “29H”. However, the work area may be limited to the area having the upper address “28H”. Good. Even in this case, when the CPU 102 of the game control device 100 executes the initialization process, the entire area of the user work RAM 104 (an area where the upper addresses are different from each other, specifically, the upper address is “28H” and Data is read from and written to all the areas “29H”. This is because it is necessary to initialize the area other than the work area (for example, the stack area).

  When the initialization process is completed, the value of the K register 1230, which is an upper address designation register, is set to “28H”. After that, until the power failure process occurs, the value of the K register 1230 is set to “28H”. , The game control is continued by the CPU 102.

  With this configuration, the frequency of changing the value set in the K register can be greatly reduced, so that the number of executions of the process of changing the register value can be reduced. Therefore, it is possible to further reduce the program capacity and to expect a high speed game control process.

(Second Embodiment)
In the first embodiment, the second special figure fluctuation display game is configured to be executed in preference to the first special figure fluctuation display game. However, in the second embodiment, the second special figure fluctuation display game is executed. The special figure fluctuation display game is executed in the order of winning without distinguishing between the figure fluctuation display game and the first special figure fluctuation display game.

  Therefore, in the first embodiment, the big hit random number, the big hit symbol random number, and the variation pattern random number are included in the start memory. It is distinguished whether the game ball has won the second start winning opening 34, that is, the special figure variation display game to be executed is the first special figure variation display game, or the second special figure variation A special figure identification bit for distinguishing whether the game is a display game is included in the start-up memory. In addition, since the upper limit of the starting storage is practically eight, a storage area for random numbers of eight blocks is secured in the user work RAM 104, and this is assigned as reserved 1 to reserved 8.

  53A and 53B are diagrams showing storage areas for various random numbers necessary for executing the special figure variation display game according to the second embodiment of the present invention, and FIG. 53A is a hold 1 to 4, FIG. 53B Indicates a storage area for various random numbers corresponding to the reservations 5 to 8.

  In the present embodiment, as shown in FIGS. 53A and 53B, the top bit of the area storing the third variation pattern random number is set as a special figure identification bit.

  In addition, when executing the special figure start port SW common process of FIG. 40, various random number values acquired in steps 4004 to 4006 are recorded in the corresponding random number storage areas in steps 4008 to 4010. The area to be different is different from the first embodiment. The corresponding random number storage area in the second embodiment is an area corresponding to the total value of the first special figure reservation counter and the second special figure reservation counter.

  For example, when the game ball is won at the first start winning opening 37 or the second starting winning opening 34, the sum of the first special figure holding counter and the second special figure holding counter becomes “2”. The various random number values acquired in steps 4004 to 4006 are stored in the random number storage area assigned to the “hold 2 storage area” in FIG. 53A. At this time, if the winning is to the first start winning opening 37, “0” is set in the special figure identification bit of “hold 2 storage area”, and if the winning is to the second starting winning opening 34, “hold” is set. “1” is set in the special figure identification bit of “2 storage area”.

  Similarly, when the game ball is won at the first start winning opening 37 or the second starting winning opening 34, the total value of the first special figure holding counter and the second special figure holding counter becomes “7”. 53B, the various random number values acquired in steps 4004 to 4006 are stored in the various random number storage areas assigned to the “hold 7 storage area”. At this time, if the winning is to the first start winning opening 37, “0” is set in the special figure identification bit of “hold 7 storage area”, and if the winning is to the second starting winning opening 34, “hold” “1” is set in the special figure identification bit of “7 storage area”.

  FIG. 54 is a flowchart illustrating a procedure of special figure hold information determination processing according to the second embodiment of this invention. In addition, about the process common to the special figure pending | holding information determination process of 1st Embodiment, the code | symbol same as FIG. 41 is allocated and description is abbreviate | omitted.

  In the second embodiment of the present invention, the game control device 100 handles the start-up memory without distinguishing between the special figure 1 and the special figure 2, so that the steps 4100 to 4102 in the first embodiment are performed. The special figure big hit determination process (4103) is executed unconditionally without setting a special condition.

  FIG. 55 is a flowchart showing the procedure of the special figure normal processing according to the second embodiment of this invention. In addition, about the process which is common in 1st Embodiment, the code | symbol same as FIG. 45 is allocated and description is abbreviate | omitted.

  In the second embodiment of the present invention, priority is not given to the special figure 2 starting memory. Therefore, first, the game control device 100 sums up the number of holdings of the special figure 1 and the special figure 2 (5500), and whether or not the total number of holdings is larger than 0, that is, the holding of the special figure 1 or the special figure 2 is not. It is determined whether or not there is (5501). If there is a hold, it is determined in step 5502 whether or not the next hold is the hold in FIG. Then, when the hold is special figure 1, special figure 1 fluctuation start processing (4503) is executed. Further, when the holding is not FIG. 1 but FIG. 2, the special figure 2 fluctuation start process (4504) is executed.

  Regardless of whether the special figure 1 fluctuation start process or the special figure 2 fluctuation start process is performed, in the process of FIG. 46, the game control device 100 sets the storage area of the hold 1 in FIG. It is specified as the object of change (4600 or 4603). Further, after acquiring the big hit random number, the big hit symbol random number, and the first to third variation pattern random numbers from the designated storage area, the reserved random number storage areas (FIGS. 53A and 53B) corresponding to the first to seventh hold are stored. The random numbers in the reserved random number storage areas corresponding to the second to eighth reserved areas (storage areas corresponding to the subsequent changes: see FIGS. 53A and 53B) are shifted (4601 or 4604), and the subsequent processing (4602 or 4605) is executed.

  On the other hand, if the total number of holds is 0 in the process of step 5501, the game control device 100 executes the processes after step 4506.

  Thus, according to the second embodiment of the present invention, even if the second special figure variation display game is not executed preferentially, the entire game control program is similar to the first embodiment. It is possible to reduce the amount of code.

  In addition, although the auxiliary | assistant game in embodiment disclosed this time has disclosed the variable display game as an example, it is not limited to this. For example, a game in which a player performs a selection operation using a button or the like during the execution of a game and a game result is derived in response to the operation input is also included. Alternatively, a game in which a physical lottery is performed as to whether or not a game medium such as a game ball or medal wins a predetermined area during the execution of the game, and a game result is derived in accordance with the lottery result Is also included in auxiliary games. In this case, it is a “special result” that the game medium wins a predetermined area.

  In addition, various gaming machines other than pachinko machines can be applied to the gaming machines in the embodiment disclosed this time. For example, the present invention can be applied to a pachislot machine, an allen ball machine, a ball ball game machine, and the like.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  As described above, the present invention can be applied to a gaming machine in which a game control device including a processor including a register performs game control.

1 gaming machine 2 body frame (outer frame)
DESCRIPTION OF SYMBOLS 3 Front frame 5 Game board 6 Game apparatus 8 Display apparatus 18 Glass frame 31 Normal symbol start gate 32 General winning opening 33 Normal variation winning apparatus 34 2nd starting winning opening 36 Special variable winning apparatus 37 1st starting winning opening 51 Game area 70 Card unit 100 Game control device 101 Game microcomputer 102, 601 CPU core 103, 602 User program ROM
104, 604 User work RAM
150 Production control device (display control device)
160 power supply device 161 backup power supply 210 payout control device 600 arithmetic processing device for game (amuse chip)
603 HW parameter ROM
608 Random number generation circuit 609 Clock generation circuit 610A Interrupt control circuit 610B Reset circuit 611 Address decoder 618 HPG program ROM
619 ID property memory 621 HPG work RAM
629 Frequency divider circuit 630 Security circuit 640 RAM access restriction circuit (update restriction means)
641 Flip-flop circuit 642 OR gate circuit 650 Address bus 660 Data bus 702 Work area 705 Use prohibited area (access prohibited area)
706 Stack area 1200 Flag register 1203A, 1203B WA register 1206A, 1206B BC register 1209A, 1209B DE register 1212A, 1212B HL register 1220A, 1220B General purpose register group 1230 K register 1233 Stack pointer (SP) register 1234 Program counter (PC) register 1240 Built-in reset circuit 1241 Initial value setting circuit (unique value setting means)
1242 Instruction interpretation execution circuit 1243 Access circuit

Claims (1)

In a gaming machine equipped with a game control device that executes a game by establishing a predetermined start condition and performs a game control that generates a special game state that gives a privilege to the player when the game has a special result,
In the game control device,
Game control program storage means for storing a game control program;
Arithmetic processing means for performing required arithmetic processing by the game control program;
A register for storing a value when performing the arithmetic processing;
With
The registers include a first register group and a second register group having the same configuration as the first register group,
The game control program includes
A main loop routine that repeatedly executes a predetermined process;
An interrupt routine describing a process to be called when a predetermined interrupt signal is generated during execution of the instruction described in the main loop routine, and
The arithmetic processing means includes:
Either one of the first register group or the second register group is accessible;
When the predetermined activation signal is generated, the first register group can be accessed,
In the main loop routine, processing is performed using the first register group, and the predetermined interrupt signal can be received while the processing of the main loop routine is being performed.
In the interrupt routine, processing is performed using the second register group ,
A gaming machine characterized in that a common subroutine called from the main loop routine and the interrupt routine can be executed .

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