JP5961059B2 - Information processing apparatus and activation method thereof - Google Patents

Description

  The present invention relates to an information processing apparatus that performs hibernation that restores an operation state at the time of restart when power supply is cut off, and a startup method thereof.

  A technique using a security chip called a TPM (Trusted Platform Module) has been proposed to detect falsification of software installed in a computer. According to this technology, data is encrypted and stored in a hard disk or the like after preconditions that allow decryption only when the hash values of the software match each other. When the software is started, the software hash value is registered in the TPM. Thereafter, when using the encrypted data stored in the hard disk, the software transmits the encrypted data to the TPM. Then, the TPM compares the registered hash value with the decryption condition of the received encrypted data, and decrypts the encrypted data only when they match, and returns it to the software. On the other hand, when the tampered software is activated, the hash value registered in the TPM and the decryption condition of the encrypted data do not match, so the TPM does not decrypt the encrypted data. As a result, only legitimate software that has not been tampered with can decrypt and use the encrypted data.

  A technique in which this TPM technique is applied to hibernation has been proposed (see, for example, Patent Document 1). Here, hibernation is a technique in which the contents of the volatile memory are stored as hibernation data in an external storage device (HDD) when suspended, and then the computer is turned off. When the power is turned on again, the state before suspend is restored by restoring the contents of the volatile memory using the hibernation data stored in the HDD.

  According to the technique described in Patent Document 1, when suspending by hibernation, the hash value of the hibernation data is registered in the TPM, and the registered content is added to the encrypted data so that it is included in the decryption conditions of the encrypted data. . When returning from suspend, the hash value of hibernation data is registered in the TPM, and the state before suspend is restored. After that, when using the encrypted data, the decryption of the encrypted data is performed only when one of the multiple decryption conditions included in the encrypted data matches the hash value registered in the TPM. Allowed.

  According to the technique described in Patent Document 1, it is possible to verify the validity of software in the same way when returning to hibernation in addition to the normal startup of the software. At the time of verification in this hibernation return, the hibernation data is reflected in the decryption condition of the encrypted data, that is, the validity verification of the hibernation data is executed. Therefore, for example, when hibernation data is falsified during hibernation suspension, it is possible to prevent the use of encrypted data.

JP 2010-267246 A

  However, according to the technique of applying TPM to hibernation described in Patent Document 1, when a hash value is registered in the TPM, the hash value already registered in the TPM at that time is not taken into consideration. Therefore, if some hash value has already been registered in the TPM, the decryption condition in the encrypted data may not match the hash value registered in the TPM when hibernation data is valid even though the hibernation data is valid. There is. In the above technique, for example, at the second and subsequent hibernations (re-hibernation), the hash value of the hibernation data at the time of the previous hibernation is registered in the TPM.

  An object of the present invention is to realize the following functions in an information processing apparatus that performs hibernation using a security chip that encrypts and decrypts security data according to a registered value. That is, considering the value already registered in the security chip when the power supply is cut off, it is possible to restore the operation state before the power cut off at the time of restart.

  As a means for achieving the above object, an information processing apparatus of the present invention comprises the following arrangement. That is, security data used for maintaining the security of the information processing device based on the power management means for managing the power supply of the information processing device, the volatile main storage means and the nonvolatile auxiliary storage means, and the registered value of the security chip Encryption means for performing encryption and decryption, and hibernation control means for executing hibernation using the auxiliary storage means, wherein the hibernation control means requests the power supply disconnection request from the power management means Is received, the first encrypted data held in advance in the auxiliary storage means is decrypted by the encryption means, operation state data indicating the storage content of the main storage means is stored in the auxiliary storage means, A hash value of operation state data is registered in the security chip, and the first encryption is performed by the encryption means. Generating second encrypted data obtained by encrypting the security data decrypted from the data, storing the second encrypted data in the auxiliary storage means, and permitting the power management means to disconnect the power supply. It transmits, It is characterized by the above-mentioned.

  According to the present invention, the following effects can be obtained in an information processing apparatus that performs hibernation using a security chip that encrypts and decrypts security data according to a registered value. In other words, it is possible to restore the operating state before the power is turned off at the time of restart in consideration of the value already registered in the security chip when the power supply is turned off.

A block diagram showing a configuration of an information processing device in the first embodiment, A flowchart showing start processing of the information processing apparatus; A flowchart showing normal startup processing; A flowchart showing hibernation processing; A flowchart showing hibernation return processing; A flowchart showing hibernation auxiliary value registration processing; A diagram showing an example of data transition in the information processing apparatus, Figure showing an example of encrypted data It is a figure which shows the example of a hibernation auxiliary value.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments do not limit the present invention related to the scope of claims, and all combinations of features described in the present embodiments are essential for the solution means of the present invention. Is not limited.

<First Embodiment>
Device Configuration The information processing apparatus according to the present embodiment has a hibernation function that restores the operating state when the power supply is cut off upon restart. FIG. 1 is a block diagram showing a basic configuration of the information processing apparatus according to the present embodiment. An information processing apparatus 18 shown in FIG. 1 is, for example, a widely used personal computer (PC), and includes a ROM 11, an HDD 12, a TPM 13, a RAM 14, a CPU 19, and a power controller 20.

  The ROM 11 is a nonvolatile memory that cannot be physically or logically rewritten, and is an auxiliary storage unit that can store the BIOS 15 and various programs and data (not shown). Since the ROM 11 is a nonvolatile memory, it is possible to keep the stored contents even when power is not supplied. The BIOS 15 is a program that controls the entire information processing apparatus 18, and is a program that is first activated inside the apparatus when the information processing apparatus 18 is powered on.

  The HDD 12 is an auxiliary storage unit that can store hibernation data (operation state data), a hibernation auxiliary value, and various programs and data (not shown), which will be described later, in addition to the boot loader 16 and the OS 17. Like the ROM 11, the HDD 12 can continue to hold the stored contents even when power is not supplied. The boot loader 16 is a program that controls the OS to be started. The OS 17 is a program for starting an application program held in the HDD 12 or the like, managing the memory of the RAM 14, and controlling input / output functions such as input from a keyboard (not shown) and screen output.

  The TPM 13 is a security chip that encrypts and decrypts data using values registered in an internal register, and has tamper resistance. The tamper resistance is a characteristic that makes it difficult to analyze from the outside and destroys the program or data stored inside when trying to analyze from the outside. The TPM 13 includes a plurality of registers (PCR0, PCR1, PCR2) called PCR. The PCR is composed of a volatile memory and can hold its contents only while power is supplied. The TPM 13 has a function called “registration” that converts data input from the outside into a predetermined format and stores the data in a predetermined PCR. A specific registration format is a hash value calculated according to the following equation (1).

DATA_i + 1 = h (DATA_i | INPUT)… (1)
In Expression (1), “INPUT” is data input from the outside of the TPM 13 or its hash value, and DATA_i is a value already recorded in the PCR at the time of registration in the TPM 13. H (x) is a hash function for the value x. For example, a hash value is calculated by an operation such as generating a fixed-length pseudorandom number from the original text (x). As the hash function, an existing hash function such as SHA1, SHA256, or SHA512 can be used. “X | y” is a concatenation of the value x and the value y. DATA_i + 1 is a result value calculated when the value INPUT is input from the outside, and DATA_i + 1 is stored in a predetermined PCR.

  The RAM 14 is a main storage unit that temporarily stores programs and various data (operation states) for processing by the CPU 19. Since the RAM 14 is a volatile memory, the stored contents can be held only during a period in which the power supply is continued.

  The CPU 19 is an electronic circuit that can control the operation of each unit in the information processing apparatus 18 or execute a program loaded in the RAM 14.

  The power controller 20 is a power management unit that manages power supply from an external power source (not shown) or an internal power source to the information processing apparatus 18. The hibernation process of this embodiment is started in response to the generation of a power supply disconnection permission request by the power controller 20.

  The configuration of the information processing apparatus in the present embodiment has been described above. Hereinafter, a startup process, a hibernation process, and a hibernation return process in the information processing apparatus according to the present embodiment will be described. FIG. 7 is also used in order to supplement each description. FIG. 7 is a diagram illustrating a specific example of data transition in the information processing apparatus 18. That is, it shows how the data (hibernation data and hibernation auxiliary value, which will be described later) held in the PCR and the HDD 12 are changed by normal activation processing, hibernation processing, and hibernation return processing which will be described later. Hereinafter, refer to the state transition shown in FIG. 7 together with the flowchart for explaining each process.

● Startup process (whole)
First, the startup process in the information processing apparatus of this embodiment will be described with reference to the flowchart of FIG. When the information processing apparatus 18 is powered on under the control of the power controller 20, the information processing apparatus 18 first activates the BIOS 15 (S21). Before the information processing device 18 is turned on, the values of the PCR in the TPM 13, the RAM 14, and the hibernation data (HBR) in the HDD 12 are all “0” as shown in the state 71 of FIG. Then, the BIOS 15 executes initialization of the TPM 13 (S22). By this initialization, all the PCRs in the TPM 13 are initialized to predetermined values, respectively. In this embodiment, it is assumed that all PCRs are initialized to “0”. However, the present invention is not limited to this example, and all PCRs are initialized to a value other than “0”. It is also possible to initialize to a different value.

  When the initialization of the TPM 13 is completed, the BIOS 15 calculates its own hash value according to the above equation (1) and registers it in the TPM 13 (S23). In this embodiment, it is assumed that the hash value of BIOS is registered in PCR0. In this embodiment, since the PCR is initialized to “0” in S22 before the BIOS 15 is registered, as a result, the value calculated by the following equation (2) is registered in the PCR0.

PCR0 = h (0 | h (BIOS))… (2)
In the formula (2), “BIOS” is a program code of BIOS15. As a result of the BIOS registration process in S23, h (0 | h (BIOS)) is registered in PCR0 as shown in state 72 in FIG.

  When the registration of the BIOS 15 is completed, the BIOS 15 determines whether or not the current activation is a return from sleep (S24). Here, the sleep is a power saving mode in which the operation of various circuits such as the CPU 19 in the apparatus is stopped while power is continuously supplied to the information processing apparatus 18. It should be noted that since the power is continuously supplied during the sleep, the RAM 14 keeps the stored contents.

  If it is determined in S24 that the mode is the return from sleep, hibernation encrypted data is deleted from encrypted data to be described later (S25), and the activation process is terminated. At this time, if there is no encrypted data for hibernation, no processing is executed. In the case of returning from sleep, since the operation state of the information processing apparatus 18 before sleep is held in the RAM 14, the information processing apparatus 18 has returned to the operation state before sleep at this point.

  On the other hand, if it is determined in S24 that the sleep is not resumed, the BIOS 15 next judges whether or not the hibernation is resumed (S26). Here, the hibernation is a power saving mode in which no power is supplied to the information processing apparatus 18, and the hibernation recovery is the information processing apparatus 18 by restarting the power supply after the power supply is cut off by the hibernation. Is to be activated. Note that the contents of the RAM 14 and the state of the CPU 19 are not retained because power is not supplied during hibernation. Therefore, before hibernation, the contents of the RAM 14 and the state of the CPU 19 are generated as hibernation data, the generated hibernation data is recorded in the HDD 12, and then the power supply is stopped. Details of the hibernation process will be described later.

  If it is determined in S26 that the hibernation is restored, the hibernation restoration process is executed (S27). If it is determined that the hibernation is not restored, the normal activation process is executed (S28). Details of the hibernation return process in S27 and the normal activation process in S28 will be described later.

Normal startup process (S28)
Hereinafter, the normal activation process in S28 will be described with reference to the flowchart of FIG. First, the BIOS 15 calculates the hash value of the boot loader 16 according to the equation (1) and registers it in the TPM 13 (S31). In the present embodiment, it is assumed that the hash value of the boot loader is registered in PCR1. Since PCR is initialized to “0” in S22, as a result, a value calculated by the following equation (3) is registered in PCR1.

PCR1 ＝ h (0 | h (BL))… (3)
In Expression (3), “BL” is the program code of the boot loader 16. As a result of the boot loader registration process in S31, h (0 | h (BL)) is registered in PCR1, as shown in state 72 in FIG.

  When the registration of the boot loader 16 is completed, the BIOS 15 activates the boot loader 16 (S32). When the boot loader 16 is activated, the boot loader 16 calculates the hash value of the OS 17 according to the equation (1) and registers it in the TPM 13 (S33). In this embodiment, the hash value of OS17 is registered in PCR2. Since PCR is initialized to “0” in S22, as a result, the value calculated by the following equation (4) is registered in PCR2.

PCR2 ＝ h (0 | h (OS))… (4)
In Expression (4), “OS” is the program code of OS17. As a result of the OS registration process in S33, h (0 | h (OS)) is registered in PCR2, as shown in state 72 in FIG.

  When the registration of the OS 17 is completed, the boot loader 16 starts the OS 17 (S34) and ends the normal startup process.

  Through the startup process (FIG. 2) and the normal startup process (FIG. 3) described above, the information processing apparatus 18 registers the hash value of each software component in PCR0, PCR1, and PCR2 as shown in the state 72 of FIG. It will be in the state.

Hibernation Process Hereinafter, the hibernation process executed in the information processing apparatus 18 of the present embodiment will be described with reference to the flowchart of FIG. The hibernation process is executed when the power supply is cut off after the information processing apparatus 18 is activated by the activation process shown in FIG. For example, when the user instructs hibernation to the information processing device 18 using a keyboard or mouse (not shown), a power supply disconnection permission request is issued from the power controller 20, and is executed by the BIOS 15 or OS 17 that receives the request. Is done. Alternatively, it is automatically executed when there is no input to the information processing device 18 for a predetermined time. In the present embodiment, the description will be continued on the assumption that the OS 17 functions as a hibernation control unit for executing hibernation processing. However, the present invention is not limited to this example, and the hibernation processing can be similarly executed in the BIOS 15.

  First, the OS 17 determines whether or not there is encrypted data for hibernation in the encrypted data storage area secured in advance in the HDD 12 (S41). If there is encrypted data for hibernation, the encrypted data for hibernation is acquired (S42), and if not, the encrypted data for normal activation is acquired (S43).

  Here, the encrypted data storage area and the encrypted data in this embodiment will be described with reference to FIG.

  First, FIG. 8D shows a configuration example of the encrypted data storage area in the present embodiment. The encrypted data storage area includes a normal startup encrypted data storage area 81 and a hibernation encrypted data storage area 82. In the normal activation encrypted data storage area 81, encrypted data for normal activation described later is recorded, and in the encrypted data storage area for hibernation 82, encrypted data for hibernation described later is recorded. As these encrypted data storage areas, non-volatile storage media such as the HDD 12 are used.

  Next, encrypted data in this embodiment will be described with reference to FIGS. 8 (a) and 8 (b). The encrypted data in this embodiment is data encrypted with a decryption condition. The decryption condition is a condition indicating what value the PCR value in the TPM 13 is allowed to decrypt the encrypted data.

  FIG. 8A shows an example of encrypted data in the present embodiment. In FIG. 8 (a), DataP is security data used for maintaining the security of the information processing device 18, such as device-specific secret information. Also, h (0 | h (BIOS)), h (0 | h (BL)) and h (0 | h (OS)) are decryption conditions (first decryption conditions), and security data and decryption conditions The whole is encrypted. In the following description, it is assumed that the decoding conditions correspond to the values of PCR0, PCR1, and PCR2 in order from the left. That is, in the case of the encrypted data shown in FIG. 8 (a), PCR0 is h (0 | h (BIOS)), PCR1 is h (0 | h (BL)), and PCR2 is h (0 | h (OS) ), The encrypted data can be decrypted. By decrypting the encrypted data, security data (DataP) can be acquired as a result. Here, the values calculated by the above equations (2), (3), and (4) are stored in PCR0, PCR1, and PCR2, respectively. That is, the encrypted data shown in FIG. 8A indicates that the encrypted data can be decrypted when normally booted using the valid BIOS 15, boot loader 16, and OS 17. The encrypted data shown in FIG. 8 (a) is held in the normal activation encrypted data storage area 81 as normal activation encrypted data (first encrypted data). The normal startup encrypted data is generated in advance by the manufacturer or user of the information processing apparatus 18 or the software vendor.

  FIG. 8 (b) shows another example of encrypted data in the present embodiment. FIG. 8 (b) shows encrypted data whose decryption conditions (second decryption conditions) are h (0 | h (BIOS)) and h (h (0 | h (OS)) | h (HBR1)). Show. That is, in the case of the encrypted data shown in FIG. 8 (b), when PCR0 is h (0 | h (BIOS)) and PCR2 is h (h (0 | h (OS)) | h (HBR1)) In addition, the encrypted data can be decrypted. Here, the value calculated by the above equation (2) is stored in PCR0, and the value based on the hibernation data calculated by equation (5) described later is stored in PCR2. That is, the encrypted data shown in FIG. 8B is encrypted data that can be decrypted when a hibernation restoration process described later is executed using the valid BIOS 15 and the hibernation data HBR1. The encrypted data shown in FIG. 8B is recorded in the hibernation encrypted data storage area 82 as hibernation encrypted data (second encrypted data) in S410 described later.

  Therefore, at the stage of executing the first hibernation process after the normal activation, the encrypted data is not recorded in the hibernation encrypted data storage area 82. Thereby, at the time of the first hibernation process, it is determined that the encrypted data for hibernation is “none” in S41, and as a result, the encrypted data for normal activation is acquired in S43. On the other hand, when executing the second and subsequent hibernation processes (for example, the hibernation process after returning to hibernation), the encrypted data is recorded in the hibernation encrypted data storage area 82 in S410 (described later) during the previous hibernation process. Has been. Thus, in the second and subsequent hibernation processes, it is determined that there is encrypted data for hibernation in S41, and as a result, encrypted data for hibernation is acquired in S42.

  Returning to FIG. 4, the description will be continued. As described above, after acquiring the encrypted data in S42 or S43, the OS 17 decrypts the encrypted data using the TPM 13 (S44). Then, it is determined whether or not the decryption of the encrypted data by the TPM 13 is successful (S45). If it is determined that the decryption is successful, the process proceeds to S46, and if it is determined that the decryption is unsuccessful, the hibernation process is terminated.

  Here, a method for determining whether or not the decoding is successful in S45 will be described. In the present embodiment, the information processing apparatus 18 can be activated by the normal activation process described with reference to FIG. 3 or the hibernation return process illustrated in FIG. 5 described later. Here, a case where the information processing apparatus 18 is activated by the normal activation process will be described. The case of activation by the hibernation return process will be described later.

  As described above, when the information processing apparatus 18 is normally started up, if the BIOS 15, the boot loader 16, and the OS 17 are not tampered with, the PCR0 to PCR2 have h (0 | h (BIOS)), h (0 | h (BL)) and h (0 | h (OS)) are registered. In this embodiment, as described above, the encrypted data shown in FIG. 8 (a) is to be decrypted. Therefore, the TPM 13 can decrypt the encrypted data received from the OS 17 because the hash value registered in each PCR matches the decryption condition of the encrypted data. On the other hand, if at least one of BIOS15, boot loader 16, and OS17 has been tampered with, h (0 | h (BIOS)), h (0 | h (BL )), values other than h (0 | h (OS)) are registered. Therefore, in this case, the TPM 13 does not decrypt the encrypted data received from the OS 17. That is, in S45, the hash value registered in each PCR is compared with the decryption condition of the encrypted data.

  If it is determined in S45 that the decryption of the encrypted data has been successful, the OS 17 generates hibernation data based on the contents of the RAM 14 and the state of the CPU 19 (S46), and holds it in the HDD 12 (S47).

  Here, the hibernation data will be described. As described above, hibernation is a power saving mode in which power is not supplied to the information processing apparatus 18. Since power is not supplied, the contents of the RAM 14 as a volatile memory and the register (not shown) in the CPU 19 are erased during hibernation. For this reason, the hibernation data is generated by copying the contents of the registers in the RAM 14 and CPU 19 to a file before hibernation, and the file is held in the HDD 12. Since the HDD 12 is non-volatile, the storage contents of the RAM 14 before hibernation and the registers in the CPU 19 can be retained even after the power supply is cut off. The registers in the RAM 14 and the CPU 19 include data such as a program to be executed, data used by the program during execution, and the address of the program currently being executed. In the present embodiment, these data are referred to as operation state data. That is, the hibernation data is data in which operation state data at the time of hibernation is held as a file.

  In the present embodiment, as shown in state 73 of FIG. 7, the operation state at the time of the first hibernation process is expressed as “operation state 1”, and the generated hibernation data is expressed as HBR1.

  Next, the OS 17 calculates the hash value of the hibernation data according to the above formula (1) and registers it in the TPM 13 (S48). In this embodiment, the hash value of hibernation data is registered in PCR2. Here, in the normal startup process shown in FIG. 3, the hash value of OS17 is already registered in PCR2 as h (0 | h (OS)) in S33. Therefore, in S48, the value calculated by the following equation (5) is registered in PCR2 as a result.

PCR2 = h (h (0 | h (OS)) | h (HBR1)) (5)
In Expression (5), “HBR1” is hibernation data. As a result of the registration process in S48, h (h (0 | h (OS)) | h (HBR1)) is registered in PCR2, as shown in state 73 of FIG. In other words, the hash value h (HBR1) of the hibernation data HBR1 is additionally registered in the PCR2 by the first hibernation with respect to h (0 | h (OS)) registered at the normal startup.

  After registering the hibernation data in S48, the OS 17 encrypts the security data (DataP) obtained by the decryption in S44 using the TPM 13 (S49: encryption means). In other words, the TPM 13 encrypts the received security data (DataP) using the values of PCR0 and PCR2 at the time of the encryption process as decryption conditions, and returns the encrypted data to the OS 17. At the time of encryption processing, h (0 | h (BIOS)) and h (h (0 | h (OS)) | h (HBR1)) are registered in PCR0 and PCR2, respectively. As (second decryption condition), the encrypted data shown in FIG. 8B is generated. That is, in S49, the security data (DataP) decrypted in S44 is encrypted so that it can be decrypted according to the decryption conditions reflecting the contents registered in the TPM 13 at the present time, and hibernation encrypted data is generated.

  Then, the OS 17 stores the encrypted data encrypted by the TPM 13 in the hibernation encrypted data storage area 82 (S410), and transmits a power supply disconnection permission to the power controller 20, thereby ending the hibernation process. At this time, if encrypted data already exists in the hibernation encrypted data storage area 82, it is overwritten. As a result, when the hibernation process is completed, the encrypted data storage area holds two encrypted data for normal activation shown in FIG. 8 (a) and encrypted data for hibernation shown in FIG. 8 (b). Will be.

  The hibernation process according to the present embodiment has been described above. By this hibernation process, PCR0, PCR1, and PCR2 in the TPM 13 become as shown in a state 73 in FIG. Thereafter, when the power supply to the information processing apparatus 18 is cut off, the data of the PCR, RAM 14 and CPU 19 which are volatile memories are erased (becomes 0), and the state shown in state 74 in FIG. 7 is obtained.

Hibernation Return Process Next, the hibernation return process executed in the information processing apparatus of this embodiment will be described with reference to the flowchart of FIG. In the present embodiment, the BIOS 15 is described as executing the hibernation return process, but the present invention is not limited to this example, and the OS 17 can similarly execute the hibernation return process. As described above, the hibernation return process in the present embodiment is executed in S27 after the BIOS is registered in S23 of FIG. Therefore, it should be noted that at the start of the hibernation restoration process, h (0 | h (BIOS)) is registered in PCR0 as shown in state 75 in FIG.

  First, the BIOS 15 registers the OS 17 in the TPM 13 according to the equation (1) (S51). In this embodiment, the hash value of the OS is registered in PCR2. Since each PCR is initialized to “0” in S22 of FIG. 2, as a result, a value calculated by the following equation (6) is registered in PCR2.

PCR2 ＝ h (0 | h (OS))… (6)
In Expression (6), “OS” is the program code of OS17.

  After the OS17 registration is completed in S51, the BIOS 15 executes registration of the hibernation auxiliary value (S52). Here, the hibernation auxiliary value registration process in S52 will be described with reference to the flowchart of FIG.

  First, the BIOS 15 initializes the counter i to 1 (S61). Then, it is determined whether or not the i-th hibernation auxiliary value exists in the HDD 12 (S62). If it exists, the process proceeds to S63, and if it does not exist, the hibernation auxiliary value registration process ends.

  Here, the hibernation assistance value in the present embodiment will be described. The hibernation auxiliary value is auxiliary data that is referred to in order to reliably perform the hibernation restoration process in the present embodiment, and specifically, is a hash value of the hibernation data generated at the time of hibernation. The hash value of the hibernation data is generated in S54, which will be described later, and accumulated in the HDD 12 as a hibernation auxiliary value. That is, as the hibernation auxiliary value, a different value is generated for each hibernation, and by accumulating the value, the hibernation auxiliary value having a different value corresponding to the number of times of hibernation is held in the HDD 12. The accumulated state of the hibernation auxiliary value in the HDD 12 represents the hibernation history.

  FIG. 9 is a diagram for explaining an example of the hibernation auxiliary value in the present embodiment. FIGS. 9 (a), 9 (b), and 9 (c) show the hibernation assistance values after the first hibernation return, the second hibernation return, and the third hibernation return, respectively. In FIG. 9, h (HBR1), h (HBR2), and h (HBR3) are a hash value of the first hibernation data, a hash value of the second hibernation data, and a hash value of the third hibernation data, respectively. As shown in FIG. 9, in the present embodiment, the number of hibernation assistance values increases each time hibernation returns. Note that in the present embodiment, during the hibernation restoration process, a hibernation assistance value is generated and added in S54, which will be described later, and therefore it should be noted that there is no hibernation assistance value at the time of the first hibernation restoration. That is, at the time of the first hibernation return, it is determined “NO” in S62, and the hibernation auxiliary value is not registered here (S52).

  Returning to FIG. If it is determined in S62 that the i-th hibernation auxiliary value exists in the HDD 12, the hash value of the i-th hibernation auxiliary value is registered in the TPM 13 (S63). In this embodiment, the hash value of the hibernation auxiliary value is registered in PCR2. Note that since h (0 | h (OS)) is already registered in PCR2 in S51, as a result, the value calculated by the following equation (7) is registered in PCR2.

PCR2 = h (h (0 | h (OS)) | h (HBR1)) (7)
In Expression (7), “h (HBR1)” is the first, that is, the first hibernation assistance value.

  After registering the i-th hibernation auxiliary value in S63, the BIOS 15 increments the counter i by 1 (S64), and advances the process to S62.

  By repeating the processing of S62, S63, and S64 described above, for example, the value calculated by the following equation (8) is registered in PCR2 after the third hibernation auxiliary value is registered.

PCR2 = h (h (h (h (h | 0 (OS)) | h (HBR1)) | h (HBR2)) | h (HBR3)) (8)
In Expression (8), “h (HBR2)” and “h (HBR3)” are the second and third hibernation auxiliary values, respectively. As described above, in this embodiment, all the hibernation assistance values held in the HDD 12 are sequentially registered in the TPM 13. In the following, for the sake of simplicity, the first hibernation return will be described first. In this case, “NO” is determined in S62, the hibernation auxiliary value is not yet registered, and the value (OS hash value) shown in Equation (6) is registered in PCR2. The case of the second and subsequent hibernation return will be described later. The hibernation auxiliary value registration process (S52) in the present embodiment has been described above. Hereinafter, returning to FIG. 5, the description of the hibernation return process will be continued.

  When the registration of the cumulative hibernation auxiliary value in S52 is completed, the BIOS 15 acquires the latest hibernation data from the HDD 12, calculates the hash value according to the equation (1), and registers it in the TPM 13 (S53). In this embodiment, the hash value of hibernation data is registered in PCR2. Here, if no hibernation assistance value is registered in S52, h (0 | h (OS)) shown in Equation (6) is registered in PCR2, and as a result, the following equation is obtained: The value calculated in (9) is registered in PCR2.

PCR2 = h (h (0 | h (OS)) | h (HBR1)) (9)
In Expression (9), “h (HBR1)” is a hash value of the hibernation data acquired from the HDD 12. As a result of the registration processing in S53, h (h (0 | h (OS)) | h (HBR1)) is registered in PCR2 as shown in state 75 in FIG.

  After registering the hibernation data in S53, the BIOS 15 calculates a hash value of the hibernation data acquired from the HDD 12, and stores the calculated value in the HDD 12 as a hibernation auxiliary value (S54). As shown in FIG. 9, this hibernation auxiliary value is held so as to be added to the previously held hibernation auxiliary value. In the state 75 of FIG. 7, the hibernation auxiliary value h (HBR1) is held in the HDD 12.

  Here, by the processing of S52 to S54, all the hibernation auxiliary values accumulated in the HDD 12 including the latest hibernation are registered in the PCR2 of the TPM 13, but if such registration can be realized, these S52 to S54 The order of processing does not matter. For example, if the process of S52 is performed after the latest hibernation assist value in S54 is registered in the HDD 12, the process of S53 is included in S63 and thus becomes unnecessary.

  Next, the BIOS 15 decrypts the encrypted data (in this case, encrypted data for hibernation) held in the HDD 12 using the TPM 13 (S55). Then, it is determined whether or not the decoding is successful (S56). If it is determined that the decoding is successful, the process proceeds to S57. If it is determined that the decoding is unsuccessful, the process proceeds to S58.

  Here, a method for determining success or failure of decoding in S56 will be described. First, it should be noted that before S56 is executed, in S23, S51, and S53, the BIOS 15, OS17, and the hash value of the hibernation data are registered in the TPM 13. That is, at the time of the first return to hibernation, the values shown in equations (2) and (9) are registered in PCR0 and PCR2 at S56, respectively. On the other hand, at the time of the first hibernation, encrypted data for hibernation shown in FIG. 8 (b) is generated in S49. Therefore, when attempting to return to hibernation using legitimate hibernation data, the hash value registered in the TPM 13 matches the decryption condition of the encrypted data, so that the decryption is determined to be successful in S56. If the hibernation data has been tampered with, the hash value registered in the TPM 13 and the decryption condition in the encrypted data do not match, so it is determined in S56 that decryption has failed. Therefore, in S56, the validity of the hibernation data is appropriately verified.

  If it is determined in S56 that decoding is successful, the BIOS 15 loads the hibernation data into the RAM 14 (S57). Thereby, the operating state of the information processing apparatus 18 before hibernation is restored. That is, as shown in the state 75 in FIG. 7, the storage contents of the registers of the RAM 14 and the CPU 19 are “operation state 1”. On the other hand, if it is determined in S56 that the decryption has failed, the BIOS 15 deletes the hibernation encryption data and the hibernation auxiliary value shown in FIG. 8B (or FIG. 8C) from the HDD 12 (S58), and the information The processing device 18 is restarted (S59). After the restart, the start process shown in FIG. 2 is executed again. In this case, neither the sleep return nor the hibernation return is performed, and as a result, the normal start process of S28 is executed.

  Heretofore, the first hibernation return process in the present embodiment has been described. By this hibernation return processing, the information processing apparatus 18 is in a state indicated by a state 75 in FIG.

The second and subsequent hibernation and restoration processes The above has described the case where the first hibernation and the hibernation restoration are performed after the information processing apparatus 18 is activated by the normal activation process. Hereinafter, a case will be described in which the hibernation is resumed after the second and subsequent hibernations are performed after the hibernation is resumed.

  First, the second and subsequent hibernation processes after the first hibernation return will be described with reference to FIG. In order to simplify the explanation below, an example is shown in which the second hibernation process is executed after the first hibernation return process. However, the same process may be repeated after the second hibernation return process. .

  When the information processing apparatus 18 is activated by the hibernation restoration process, the hibernation encrypted data is registered in the hibernation encrypted data storage area 82 at S410 at the previous hibernation. Therefore, in the second and subsequent hibernations, it is first determined in S41 that there is encrypted data for hibernation, and in S42, the encrypted data for hibernation shown in FIG. 8 (b) generated in S49 during the previous hibernation. Is acquired.

  Then, the obtained encrypted data for hibernation is decrypted by the TPM 13 (S44), and it is determined whether or not the decryption is successful (S45), but this determination processing is different from that at the first hibernation. When the information processing apparatus 18 is activated by the hibernation return, the return processing shown in FIG. 5 causes the PCR0 and PCR2 to have h (0 | h (BIOS)), h (h (0 | h (OS)) | h (HBR1)) is registered (see state 75 in FIG. 7). Therefore, the TPM 13 can decrypt the encrypted data received from the OS 17 because the PCR hash value matches the decryption condition of the encrypted data (FIG. 8B). On the other hand, when either the BIOS 15 or the hibernation data is falsified, the decryption conditions for the PCR hash value and the encrypted data do not match, so the TPM 13 does not decrypt the encrypted data.

  After determining that the decoding is successful in S45, the OS 17 generates hibernation data again (S46), and holds the generated HBR2 in the HDD 12 (S47). The information processing apparatus 18 at this time is as shown in a state 76 in FIG. That is, the operating state is changed to the operating state 2, and new hibernation data HBR2 corresponding to the operating state is held in the HDD 12. Thereby, it is possible to cope with a change in the operating state of the information processing apparatus 18 during the period from the return of hibernation to the time of hibernation again.

  Next, the hash value of the hibernation data is registered in the TPM 13 (S48). As described above, the hash value of hibernation data is registered in PCR2. At this time, in PCR2, h (h (0 | h (OS)) | h (HBR1)) registered in S53 during the first hibernation restoration process is registered (see 75 PCR2 in FIG. 7). . Therefore, as a result, the value calculated by the following equation (10) is registered in PCR2.

PCR2 = h (h (h (0 | h (OS)) | h (HBR1)) | h (HBR2))… (10)
In Expression (10), “h (HBR2)” is the second hibernation auxiliary value. As a result of the registration process in S48, h (h (h (0 | h (OS)) | h (HBR1)) | h (HBR2)) is registered in PCR2, as shown in state 76 in FIG. Become. In other words, the hash value h (HBR2) of the hibernation data HBR2 is additionally registered in the PCR2 by the second hibernation with respect to the value registered at the time of the first hibernation return.

  After registering the hibernation data in S48, the OS 17 encrypts the security data (DataP) obtained by the decryption in S44 using the TPM 13 (S49). At this time, the TPM 13 encrypts PCR0 and PCR2 so as to satisfy the decryption conditions, and returns encrypted data as shown in FIG. Note that in FIG. 8 (c), the decryption conditions of the encrypted data are the same as those in PCR2 in the state 76 of FIG. The OS 17 then overwrites the encrypted data encrypted by the TPM 13 in the hibernation encrypted data storage area 82 (S410) and ends the hibernation process. Thus, at the time when the second hibernation process is completed, the encrypted data storage area contains the normal activation encrypted data shown in FIG. 8 (a) and the hibernation encrypted data shown in FIG. 8 (c). Two will be held.

  The example in which the information processing apparatus 18 is activated by the hibernation return process and then executes hibernation again has been described. By this second hibernation process, each PCR in the TPM 13 in the information processing apparatus 18 becomes as shown in a state 76 in FIG. After that, when the power supply to the information processing device 18 is cut off, the PCR, RAM, and CPU registers, which are volatile memories, are erased (becomes 0), and a state 77 in FIG. 7 is obtained.

  Next, processing (second hibernation return processing) in the case of returning to hibernation again after the second hibernation processing described above will be described with reference to FIG. In order to simplify the description, the second hibernation return process will be described below, but the same process may be repeated for the third and subsequent return processes.

  In the second hibernation return process, first, h (0 | h (OS)) is registered in the PCR 2 according to the equation (6) (S51). Next, the hibernation auxiliary value is registered (S52). At this time, since the first hibernation auxiliary value h (HBR1) stored in the HDD 12 at S54 at the time of the previous return to hibernation exists, the hibernation auxiliary value h (HBR1) is registered in the TPM 13 in S63 of FIG. The In the present embodiment, since the hibernation auxiliary value is registered in PCR2, here, the value calculated by the following equation (11) is registered in PCR2.

PCR2 = h (h (0 | h (OS)) | h (HBR1)) (11)
Next, the hash value of the second hibernation data held in the HDD 12 is registered in the TPM 13 (S53). In the present embodiment, since the auxiliary value of the hibernation data is registered in PCR2, here, the value calculated by the following equation (12) is registered in PCR2.

PCR2 = h (h (h (0 | h (OS)) | h (HBR1)) | h (HBR2))… (12)
In Expression (12), “h (HBR2)” is a hash value of the second hibernation data. As a result of this registration process, h (h (h (0 | h (OS)) | h (HBR1)) | h (HBR2)) is registered in PCR2, as shown in state 78 in FIG. Become.

  Then, the hash value of the second hibernation data is added to the HDD 12 as a hibernation auxiliary value (S54). As a result, the hibernation auxiliary value is accumulated as shown in FIG. 9 (b), and as shown in the state 78 of FIG. 7, the HDD 12 has h (HBR2) in addition to the first hibernation auxiliary value h (HBR1). Added.

  After the addition of the hibernation auxiliary value, the OS 17 decrypts the encrypted data using the TPM 13 (S55), and determines whether or not this decryption process is successful (S56). At the time of the second hibernation return, the values shown in equations (2) and (12) are registered in PCR0 and PCR2 at S56 (see state 78 in FIG. 7). Also, during the second hibernation, the encrypted data shown in FIG. 8C is generated in S49. Therefore, when attempting to return to hibernation using legitimate hibernation data, the hash value registered in the TPM 13 matches the decryption condition in the encrypted data, and therefore it is determined that decryption is successful in S56. On the other hand, if the hibernation data has been tampered with, the hash value registered in the TPM 13 and the decryption condition in the encrypted data do not match, so it is determined that decryption has failed in S56.

  The case of the second hibernation return process has been described above. By this hibernation return processing, the information processing apparatus 18 is in a state indicated by a state 78 in FIG.

  As described above, according to the present embodiment, when the power is turned off due to hibernation, the encrypted data is decrypted using the TPM 13, and the encrypted data for hibernation is created by reflecting the operation state at that time in the decryption conditions. And keep it in HDD12. Then, when returning to hibernation, the operation state at the time of the previous hibernation is accumulated and stored, and the TPM 13 decrypts the encrypted data for hibernation using the accumulated operation state as a decryption condition. Therefore, even when a hash value is already registered in the TPM 13 at the time of hibernation, the correctness of the hibernation data can be correctly verified, and the hibernation can be reliably restored. Further, it is possible to prevent the decryption condition for hibernation data from being added by, for example, counterfeit software.

  Also, when it is determined that the hibernation data is not valid (validity verification failure), the storage area of the HDD 12 can be released by deleting the encrypted data and the hibernation auxiliary value. When hibernation based on valid hibernation data is repeatedly executed, for example, a capacity of the storage area for the hibernation auxiliary value may be limited, and verification failure may be determined when the limit is reached. Of course, an alert notification or the like may be performed at a timing when the limit is likely to be reached.

Note that this embodiment can also be applied when executing a startup process that combines sleep and hibernation. For example, when shifting to hibernation after sleeping for a predetermined time, it is conceivable to apply the present embodiment to the hibernation. In this case, for example, compared with the case where the technique described in Patent Document 1 is applied, in the present embodiment, the sleep recovery and the hibernation recovery are distinguished (S24, S26), and processing is performed, so that a high speed recovery after the hibernation is performed. It becomes possible.
<Other embodiments>
The present invention is also realized by executing the following processing. That is, software (program) that realizes the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and the computer of the system or apparatus (or CPU, MPU, etc.) reads the program. It is a process to be executed.

Claims (7)

Power management means for managing the power supply of the information processing apparatus;
Volatile main storage means and nonvolatile auxiliary storage means;
An encryption means for encrypting and decrypting security data used for maintaining security of the information processing device based on the registered value of the security chip;
Hibernation control means for executing hibernation using the auxiliary storage means,
When the hibernation control unit receives the power supply disconnection permission request from the power management unit,
Causing the encryption means to decrypt the first encrypted data held in advance in the auxiliary storage means,
Storing operation state data indicating the storage contents of the main storage means in the auxiliary storage means;
Registering the hash value of the operating state data in the security chip,
Generating second encrypted data obtained by encrypting the security data decrypted from the first encrypted data by the encryption means, and storing the second encrypted data in the auxiliary storage means;
An information processing apparatus that transmits a power supply disconnection permission to the power management means. When the power supply is resumed after the power supply is disconnected by the power management means, the hibernation control means is
A hash value of the operation state data stored in the auxiliary storage unit is accumulated and stored in the auxiliary storage unit as auxiliary data,
Register all the auxiliary data accumulated in the auxiliary storage means in the security chip;
Allowing the encryption means to decrypt the second encrypted data held in the auxiliary storage means, and determining whether the second encrypted data is successfully decrypted;
2. The information processing apparatus according to claim 1, wherein when the decryption of the second encrypted data is successful, the operation state data stored in the auxiliary storage unit is restored to the main storage unit. The hibernation control means includes
3. The information processing apparatus according to claim 2, wherein when the decryption of the second encrypted data fails, the second encrypted data is deleted from the auxiliary storage unit. The hibernation control means includes
4. The hash value of the operation state data is registered after registering a hash value of a program code related to activation of an information processing apparatus in the security chip. Information processing device. When the hibernation control means receives the power supply disconnection permission request from the power management means after the power supply is resumed by the power management means,
5. The decryption by the encryption unit is performed using the second encrypted data held in the auxiliary storage unit as the new first encrypted data, according to any one of claims 1 to 4. The information processing apparatus described. Power management means for managing the power supply of the information processing apparatus;
Volatile main storage means and nonvolatile auxiliary storage means;
An encryption means for encrypting and decrypting security data used for maintaining security of the information processing device based on the registered value of the security chip;
Hibernation control means for executing hibernation using the auxiliary storage means;
An information processing apparatus start-up method comprising:
When the hibernation control unit receives the power supply disconnection permission request from the power management unit,
Causing the encryption means to decrypt the first encrypted data held in advance in the auxiliary storage means,
Storing operation state data indicating the storage contents of the main storage means in the auxiliary storage means;
Registering the hash value of the operating state data in the security chip,
Generating second encrypted data obtained by encrypting the security data decrypted from the first encrypted data by the encryption means, and storing the second encrypted data in the auxiliary storage means;
Transmitting the power supply disconnection permission to the power management means;
A method for starting an information processing apparatus.   6. A non-transitory computer-readable storage medium storing a program for causing a computer device to function as the hibernation control unit in the information processing device according to claim 1 when executed on the computer device.

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