JP5958656B2 - Multiplexed storage device and multiplexed storage control method - Google Patents

Description

  The present invention relates to a multiplexed storage device and a multiplexed storage control method.

  For the purpose of improving the fault tolerance of storage units such as HDD (Hard Disk Drive) and SSD (Solid State Drive), there is a technology that provides multiple storage units to make data redundant (hereinafter such technology). A device that uses this is called a “multiplexed storage device”). The multiplexed storage device writes the same data to a plurality of storage units to make the data redundant. Then, even if one storage unit fails, the multiplexed storage device can read data from other normal storage units. That is, the multiplexed storage device can improve the fault tolerance of the device by making the storage unit redundant.

  The multiplexed storage device needs to write to all redundant storage units. Here, when writing to a plurality of storage units, the phase difference between the plurality of writes affects the performance of the multiplexed storage device.

  20A and 20B are diagrams illustrating examples of read latency and write throughput when the phase difference is increased, and FIGS. 21A and 21B are diagrams illustrating examples of read latency and write throughput when the phase difference is decreased. is there. In these figures, data is duplicated in two storage units.

  The CPU is a CPU of an information processing apparatus that uses a multiplexed storage device. Write Req (X) is a write request for data X, Read Req (X) is a read request for data X, Read (X) is a read of data X from the storage unit, and Write (X) is stored Data X is written to the unit. Read Cpl with Data (X) is read completion of data X, and Write Cpl (X) is write completion of data X. X is A or B.

As shown in FIG. 20A, when the phase difference is increased, if Write Req (A) and Read Req (B) are issued continuously from the CPU, the data A is being written to the storage unit ₂ . The data B can be read from the storage unit ₁ . Therefore, the read latency is shortened.

  On the other hand, when the phase difference is increased, as shown in FIG. 20B, write processing for each storage unit is not performed in parallel, so that the completion of the write request is delayed and the throughput for the write request is deteriorated.

  On the other hand, when the phase difference is reduced, as shown in FIG. 21A, when Write Req (A) and Read Req (B) are issued continuously from the CPU, writing of data A is not completed. And data B cannot be read. Therefore, the read latency increases.

  On the other hand, when the phase difference is reduced, as shown in FIG. 21B, write processing for each storage unit is performed in parallel, so that the completion of the write request is accelerated and the throughput for the write request is improved.

  As a conventional technology related to the multiplexed storage device, one of the three disk devices reads and writes, one writes, the other one stands by, and three at regular intervals. There is a backup technology that extends the life of a disk device by shifting roles.

  In addition, during the period when data is being written from the access device, a write suspension instruction is accepted from the access device, writing is paused, and writing of new data from the access device is accepted. There is a technique for writing in parallel so that no problem occurs.

JP-A-7-64870 JP-A-2005-250644 JP 2011-210235 A

  As shown in FIGS. 20A to 21B, when the phase shift amount is set large, the throughput performance for the write request is lowered, and when the phase shift amount is set small, the effect of improving the latency for the read request is reduced. .

  An object of one aspect of the present invention is to improve latency for a read request while preventing a decrease in throughput performance for a write request.

  In one aspect, a multiplexed storage device disclosed in the present application includes a determination unit that determines a phase shift amount between a plurality of write instructions respectively associated with a plurality of storage devices based on a read request and a status of the write request. Prepare. Further, the multiplexed storage device disclosed in the present application includes an issuing unit that issues the plurality of write instructions for the same data by shifting the phase shift amount determined by the determining unit.

  According to one embodiment, it is possible to improve latency for a read request while preventing a decrease in throughput performance for a write request.

FIG. 1 is a diagram illustrating the configuration of the multiplexed storage device according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of the multiplexing control unit. FIG. 3 is a diagram illustrating an example of entries in the request queue. FIG. 4 is a diagram illustrating an example of entries in the device status table. FIG. 5 is a diagram illustrating an example of entries in the request history queue. FIG. 6 is a diagram illustrating an example of the phase shift amount decoding table. FIG. 7 is a flowchart showing an operation flow of the device request generation unit at the time of write request processing. FIG. 8 is a flowchart showing an operation flow of the device request generation unit at the time of read request processing. FIG. 9 is a flowchart showing an operation flow of the response processing unit. FIG. 10 is a flowchart showing an operation flow of the request number statistics unit. FIG. 11 is a diagram illustrating an effect when the frequency of read requests is high. FIG. 12 is a diagram illustrating an effect when the frequency of write requests is high. FIG. 13 is a diagram illustrating a hardware configuration of a device control unit in which some functions are realized by the device control program. FIG. 14 is a diagram illustrating an example of the read latency performance improvement effect in the second embodiment. FIG. 15 is a diagram illustrating the configuration of the multiplexed storage device according to the third embodiment. FIG. 16 is a diagram illustrating a configuration of the multiplexing control unit. FIG. 17 is a diagram illustrating an example of entries in the request queue. FIG. 18 is a diagram showing an example of entries in the device status table. FIG. 19 is a diagram illustrating an example of a phase shift amount decoding table. FIG. 20A is a diagram illustrating an example of read latency when the phase difference is increased. FIG. 20B is a diagram illustrating an example of the write throughput when the phase difference is increased. FIG. 21A is a diagram illustrating an example of read latency when the phase difference is reduced. FIG. 21B is a diagram illustrating an example of the write throughput when the phase difference is reduced.

  Embodiments of a multiplexed storage device and a multiplexed storage control method disclosed in the present application will be described below in detail with reference to the drawings. Note that these embodiments do not limit the disclosed technology.

  First, the configuration of the multiplexed storage device according to the first embodiment will be described. FIG. 1 is a diagram illustrating the configuration of the multiplexed storage device according to the first embodiment. As shown in FIG. 1, the multiplexed storage device 1 includes a device control unit 2 and n storage units 3. The device control unit 2 controls the multiplexed storage device 1, and the storage unit 3 stores n-duplicated data used by the CPU.

  The device control unit 2 includes a host I / F control unit 4, an address conversion unit 5, a multiplexing control unit 6, and n device access control units 7. The host I / F control unit 4 is an interface with the CPU. The host I / F control unit 4 receives an access request to the multiplexed storage device 1 from the CPU, passes it to the multiplexing control unit 6 via the address conversion unit 5, and multiplexes the access request. The response from the control unit 6 is returned to the CPU.

  The address conversion unit 5 converts a logical address used by the CPU into a physical address used by the storage unit 3. The device access control unit 7 corresponds to each storage unit 3 and controls access to the storage unit 3.

  The multiplexing control unit 6 controls access to the storage unit 3 based on an access request from the CPU. The multiplexing control unit 6 performs control to multiplex data and write the data to a plurality of storage units 3 when the access request is a write request. The multiplexing control unit 6 includes a request issuance / response processing unit 61, a request count statistics unit 62, and a phase shift amount adjustment unit 63.

  The request issuance / response processor 61 issues an access request to the storage unit 3 based on the access request from the CPU, receives a response from the storage unit 3, and returns a response to the CPU. The request issuing / response processing unit 61 multiplexes the write request based on the phase shift amount and issues the write request to the storage unit 3. The request number statistics unit 62 manages the issuance status of recent access requests, and counts the number of read requests among the access requests.

  The phase shift amount adjustment unit 63 dynamically adjusts the phase shift amount for issuing a write request based on the recent access request issue status. The phase shift amount adjustment unit 63 uses the latest access request issuance status obtained from the request count statistics unit 62 to increase the phase shift amount if there are many recent read requests, and conversely if there are many write requests. Adjust to reduce the amount of phase shift.

  FIG. 2 is a diagram illustrating a configuration of the multiplexing control unit 6. As illustrated in FIG. 2, the request issuance / response processing unit 61 includes a request queue 71, a device status table 72, a device request generation unit 73, and a response processing unit 74.

  The request queue 71 is a queue that stores an access request from the CPU. The number of stages of queues is the number necessary to fill the data bus for storage unit access based on the access latency for the storage unit 3.

  FIG. 3 is a diagram illustrating an example of entries in the request queue 71. As shown in FIG. 3, the entry of the request queue 71 includes fields for valid, request type, address, and write data. “valid” indicates whether or not the entry is valid. The request type indicates the type of request and indicates write or read. The address indicates an access destination address. The write data is data that is written to the storage unit 3 when the request type is write.

  The device status table 72 is a table for managing the request issue status for each storage unit 3. FIG. 4 is a diagram illustrating an example of entries in the device status table 72. As shown in FIG. 4, the device status table 72 has one entry corresponding to each of the write request and the read request, and each entry includes valid, address, and status of request issuance to each storage unit 3. Is included.

  The valid is 1-bit information indicating whether or not the entry is valid, and is “1” when the entry is valid and “0” when the entry is not valid. address indicates the address of the request issue destination. The request issue status indicates the issue status of a request to each storage unit 3 and is “Wait”, “Run”, or “Done”. “Wait” represents a situation in which a request has to be issued but has not been issued. “Run” represents a situation in which the request has been issued and the storage unit 3 is processing the request. “Done” indicates that the request has been issued and the request processing of the storage unit 3 has been completed.

  When there is a request in the request queue 71, the device request generation unit 73 extracts the first request from the request queue 71, and generates and issues a request for each storage unit 3 in accordance with the extracted request. At this time, in the case of a write request, the device request generator 73 issues a request to all the storage units 3 while shifting the issue timing for each storage unit 3. The phase amount to be shifted is a value managed by the phase shift amount adjusting unit 63. On the other hand, when issuing a read request, the device request generator 73 searches for one idle storage unit 3 and issues a read request to the searched storage unit 3.

  The response processing unit 74 receives a response from each storage unit 3, processes the received response, and returns a processing result to the CPU.

  The request count statistics unit 62 includes a request history queue 75 and a read counter 76. The request history queue 75 is a queue that stores whether or not the most recent access request was a read request. The number of stages in the request history queue 75 is determined by how many recent request histories are referred to in determining the phase shift amount, and is 16 stages, for example.

  FIG. 5 is a diagram illustrating an example of entries in the request history queue 75. As shown in FIG. 5, the entry of the request history queue 75 includes valid and request type as fields. “valid” indicates whether or not the entry is valid. The request type indicates the type of access request and indicates write or read.

  The read counter 76 is a counter that counts the number of the latest read requests. The read counter 76 counts the number of read requests in the request history queue 75.

  The phase shift amount adjustment unit 63 includes a phase shift amount decoding table 77, a phase shift amount determination unit 78, and a phase shift amount storage unit 79. The phase shift amount decoding table 77 is a table for determining the phase shift amount according to the number of the latest read requests counted by the read counter 76.

  FIG. 6 is a diagram illustrating an example of the phase shift amount decoding table 77. As shown in FIG. 6, the phase shift amount decoding table 77 stores the read counter value and the phase shift amount in association with each other. The read counter value is the value of the read counter 76. The phase shift amount is an interval between write requests issued to a plurality of storage units 3 for the same data, and its unit is microseconds (μS).

  As shown in FIG. 6, the phase shift amount is small when the number of leads is very short, and the phase shift amount is large when the number of leads is very close. The phase shift amount is a value that enables processing of a read request by shifting the phase. For example, taking SSD as an example, if the time required for reading is 50 μS, if the value of the read counter 76 is 1, even if one read comes after the write, the phase shift amount can be immediately responded to that read. Is 60 μS.

  Further, the maximum amount of phase shift is set so that the write processing of each storage unit 3 becomes completely serial. For example, taking SSD as an example, if the time required for writing is 500 μS, the maximum value of the phase shift amount is up to 500 μS. This is due to the following reason. By setting the phase shift amount to 500 μS, any one of the storage units 3 is expected to be in an idle state. Therefore, the read access following the write access can be assigned to any one of the storage units 3, and the read response performance The improvement effect is always obtained. On the other hand, although increasing the phase shift amount further does not contribute to further improvement of the read response performance, the write throughput is lowered. Therefore, in order to avoid unnecessary performance degradation of the write throughput, the phase shift amount is set to 500 μS at the maximum.

  The phase shift amount determination unit 78 searches the phase shift amount decode table 77 from the value of the read counter 76 to determine the phase shift amount, and stores the determined phase shift amount in the phase shift amount storage unit 79. The phase shift amount storage unit 79 stores the phase shift amount determined by the phase shift amount determination unit 78.

  Next, an operation flow of the device request generation unit 73 at the time of write request processing will be described. FIG. 7 is a flowchart showing an operation flow of the device request generation unit 73 at the time of write request processing. FIG. 7 shows an operation flow of the device request generator 73 when the first request in the request queue 71 is a write request.

  As shown in FIG. 7, the device request generator 73 determines whether or not the valid bit of the write entry in the device status table 72 is clear (step S1). .

  On the other hand, if it is clear, the device request generation unit 73 extracts the first request from the request queue 71 (step S2), and sets the valid bit of the write entry of the device status table 72 to 1 (step S3). Then, the device request generation unit 73 sets all the request issue status fields of the write entries in the device status table 72 to “Wait” (step S4).

  Then, the device request generation unit 73 refers to the request issue status field of the device status table 72 (step S5). Then, the device request generation unit 73 determines whether or not there is an idle storage unit 3 that has not been issued (step S6). If there is no storage unit 3, the process returns to step S5. Here, the write unissued and idle state is a state where the write entry issuance status is “Wait” and the read entry request issuance status is other than “Run”.

  On the other hand, if there is a storage unit 3 that has not been issued and is idle, the device request generation unit 73 issues a write request to one storage unit 3 (step S7). Then, the device request generation unit 73 updates the request issue status corresponding to the storage unit 3 in the write entry of the device status table 72 to “Run” (step S8).

  Then, the device request generation unit 73 determines whether or not a write request has been issued to all the storage units 3 (step S9). If the write request has been issued to all of the storage units 3, the process is terminated. . Here, “write requests have been issued to all storage units 3” means that the request issue status of write requests corresponding to all storage units 3 is “Run” or “Done”.

  On the other hand, if there is a storage unit 3 that has not issued a write request, the device request generator 73 waits for the time indicated by the phase shift amount (step S10), returns to step S5, and writes to the other storage unit 3. Process to issue a request.

  As described above, when the device request generation unit 73 issues a write request to one storage unit 3, the device request generation unit 73 waits for the amount of phase shift, thereby writing the write request when writing the same data to the plurality of storage units 3. It can be issued by shifting.

  Next, an operation flow of the device request generation unit 73 at the time of read request processing will be described. FIG. 8 is a flowchart showing an operation flow of the device request generation unit 73 at the time of read request processing. FIG. 8 shows an operation flow of the device request generator 73 when the first request in the request queue 71 is a read request.

  As shown in FIG. 8, the device request generation unit 73 determines whether or not the valid bit of the read entry of the device status table 72 is clear (step S11), and if not clear, waits until it is cleared. .

  On the other hand, if it is clear, the device request generator 73 retrieves the first request from the request queue 71 (step S12), and sets the valid bit of the read entry of the device status table 72 to 1 (step S13). Then, the device request generation unit 73 sets all the request issue status fields of the read entries of the device status table 72 to “Wait” (step S14).

  Then, the device request generation unit 73 refers to the request issue status field of the device status table 72 (step S15). Then, the device request generation unit 73 determines whether or not the idle storage unit 3 exists (step 16), and if not, returns to step S15. Here, the idle state is a state in which the request issue status of the read entry is “Wait” and the request issue status of the write entry is other than “Run”.

  On the other hand, when there is an idle storage unit 3, the device request generator 73 issues a read request to one storage unit 3 (step S17). Then, the device request generation unit 73 updates the request issue status corresponding to the storage unit 3 in the read entry of the device status table 72 to “Run” (step S18).

  As described above, the device request generation unit 73 can issue a read request by specifying the idle storage unit 3 based on the device status table 72.

Next, the operation flow of the response processing unit 74 will be described. FIG. 9 is a flowchart showing an operation flow of the response processing unit 74. As shown in FIG. 9, when the response processing unit 74 receives a response from the storage unit _i , the response processing unit 74 determines whether the response is a response to the write request (step S21). Here, i is 0 to n-1.

As a result, if it is a response to the write request, the response processing unit 74 updates the request issuance status corresponding to the storage unit _i of the write entry in the device status table 72 to “Done” (step S22). Then, the response processing unit 74 determines whether or not the request issue status of all the storage units 3 is “Done” for the write entry (step S23), and there is a storage unit 3 whose request issue status is not “Done”. If so, the process ends.

  On the other hand, when the request issue status of all the storage units 3 is “Done”, the response processing unit 74 transmits a write response to the CPU (step S24) and clears the valid of the write entry (step S25). ).

If the response is not a response to the write request, the response processing unit 74 updates the request issuance status corresponding to the storage unit _i of the read entry in the device status table 72 to “Done” (step S26). ). Then, the response processing unit 74 transmits a read response to the CPU (step S27), and clears the valid value of the read entry (step S28).

  As described above, the response processing unit 74 does not respond to the CPU until responses from all the storage units 3 are received in response to the write request. Therefore, the CPU performs multiple data writing according to the response from the response processing unit 74. Can be confirmed.

  Next, the operation flow of the request number statistics unit 62 will be described. FIG. 10 is a flowchart showing an operation flow of the request number statistics unit 62. The request count statistic unit 62 operates when a request fetched from the request queue 71 is received.

  As shown in FIG. 10, the request number statistics unit 62 determines whether or not the received request is a read request (step S31). If the request is a read request, the read counter 76 is incremented (step S32). ).

  Then, the request number statistics unit 62 extracts the oldest request from the request history queue 75 (step S33), and determines whether or not the extracted request is a read request (step S34). As a result, if the request is a read request, the request count statistic unit 62 subtracts the read counter 76 (step S35).

  Then, the request count statistic unit 62 adds the newly received request to the request history queue 75 (step S36).

  As described above, the request count statistics unit 62 uses the read counter 76 to count the number of read requests among the most recent predetermined number of requests, so that the multiplexing control unit 6 grasps the status of the most recent request. be able to. The operation shown in FIG. 10 shows the operation after the request history queue 75 becomes full entry, and the processing from step S33 to step S35 is not performed until the request history queue 75 becomes full entry.

  As described above, in the first embodiment, the phase shift amount decoding table 77 stores the phase shift amount in association with the number of the latest read requests. Then, the request number statistics unit 62 counts the number of read requests among the most recent predetermined number of requests, and the phase shift amount determination unit 78 determines the phase based on the phase shift amount decoding table 77 and the number of the latest read requests. Determine the shift amount. Then, the device request generation unit 73 issues a write request to the plurality of storage units 3 to which the same data is written, shifted by the phase shift amount. Therefore, the multiplexing control unit 6 can dynamically change the phase shift amount based on the frequency of the most recent read request, and improves the latency for the read request while preventing the throughput performance for the write request from being lowered. be able to.

  FIG. 11 is a diagram illustrating an effect when the frequency of read requests is high. FIG. 11 shows a case where the number of storage units 3 is two. As shown in FIG. 11, when there are many recent read requests, the multiplexing control unit 6 increases the phase difference of the write start timing (1). Therefore, since the period during which one storage unit 3 is idle is extended, the multiplexed storage device 1 can immediately respond when a read request comes immediately after the write request (2).

  FIG. 12 is a diagram illustrating an effect when the frequency of write requests is high. FIG. 12 shows a case where the number of storage units 3 is two. As shown in FIG. 12, when there are many write requests most recently, the multiplexing control unit 6 decreases the phase difference of the write start timing (1). Therefore, since the data is written in parallel in both storage units 3, the multiplexed storage device 1 can improve the write throughput (2).

  Although the device control unit 2 has been described in the first embodiment, a device control program having the same function can be obtained by realizing a part of the configuration of the device control unit 2 with software. Therefore, a hardware configuration of a device control unit that realizes a part of functions by the device control program will be described.

  FIG. 13 is a diagram illustrating a hardware configuration of a device control unit in which some functions are realized by the device control program. As illustrated in FIG. 13, the device control unit 20 includes a main memory 21, a controller 22, and a flash memory 26.

  The main memory 21 is a memory for storing a program and a program execution result. The main memory 21 implements the request queue 71, the device status table 72, the request history queue 75, the read counter 76, the phase shift amount decoding table 77, and the phase shift amount storage unit 79 shown in FIG.

  The controller 22 includes a CPU 23, an address conversion unit 24, and a device access control unit 25. The CPU 23 is a central processing unit that reads a program from the main memory 21 and executes it. The address conversion unit 24 converts a logical address used by the CPU 23 into a physical address used by the storage unit 3. The device access control unit 25 corresponds to each storage unit 3 and controls access to the storage unit 3.

  The flash memory 26 is a non-volatile memory and stores a device control program 27. The device control program 27 is read from the flash memory 26 to the main memory 21 and executed by the CPU 23, whereby the request issue / response unit 61, the request number statistics unit 62, and the phase shift amount adjustment unit 63 shown in FIG. Realize the function.

  Thus, by executing the device control program 27 by the CPU 23, the multiplexing control function according to the first embodiment can be realized by software.

  By the way, in the first embodiment, the case where the phase shift amount is dynamically changed based on the frequency of the most recent read request has been described. However, the phase shift amount is considered in consideration of the order of the read request and the write request waiting for execution. May be adjusted. For example, when the storage unit is an SSD and write requests and read requests are waiting to be executed in this order, the multiplexed storage device can simultaneously read request processing simultaneously with the write request processing by setting the phase shift amount to 60 μS. Can be processed.

  To adjust the phase shift amount, the request issuance / response processing unit notifies the request queue information to the phase shift amount adjustment unit, and the phase shift amount adjustment unit determines the request queue when determining the phase shift amount. You can add information.

  FIG. 14 is a diagram illustrating an example of the read latency performance improvement effect in the second embodiment. As shown in FIG. 14, when a read request comes after the write request, the phase shift amount adjustment unit sets the phase difference of the write start timing to 60 μS at the minimum (1). Then, the multiplexed storage device can immediately respond to the subsequent read request (2).

  As described above, in the second embodiment, the phase shift amount adjustment unit adjusts the phase shift amount in consideration of the combination of the read request and the write request that are in the execution waiting state, so that the multiplexed storage device can increase the read latency. Can be improved.

  In the first embodiment, the case where the start timing interval of the process for the write request is dynamically changed has been described. However, the same technique is not limited to the process for the write request, and can be applied. For example, in SSD or the like, unnecessary data is erased, that is, garbage collected, in the background when the storage unit 3 is in an idle state. The device control unit erases unnecessary data for all the storage units. However, the device control unit does not start for all the storage units at the same time, but can start them at intervals for each storage unit. Therefore, in a third embodiment, a multiplexed storage device that automatically adjusts the phase shift amount in garbage collection will be described.

  First, the configuration of the multiplexed storage device according to the third embodiment will be described. FIG. 15 is a diagram illustrating the configuration of the multiplexed storage device according to the third embodiment. Here, for convenience of explanation, functional units that play the same functions as the respective units shown in FIG.

  As shown in FIG. 15, the multiplexed storage device 1a includes a device control unit 2a and n storage units 3a. The device control unit 2a controls the multiplexed storage device 1a, and the storage unit 3a stores the data used by the CPU of the information processing device in n-layers. The storage unit 3a is an SSD. The device control unit 2 a includes a host I / F control unit 4, an address conversion unit 5, a multiplexing control unit 6 a, n device access control units 7, and an SSD control unit 8.

  The multiplexing control unit 6a performs control to multiplex data and write it to the plurality of storage units 3a. The multiplexing control unit 6a includes a request issuance / response processing unit 61a, a request count statistics unit 62a, and a phase shift amount adjustment unit 63a. The request issuance / response processing unit 61a and the request number statistics unit 62a also process a GC (garbage collection) request from the SSD control unit 8 in addition to an access request from the CPU. The SSD control unit 8 includes a garbage collection control unit 80. The garbage collection control unit 80 determines whether or not to perform GC, and issues a GC request when it is determined to perform GC.

  FIG. 16 is a diagram illustrating a configuration of the multiplexing control unit 6a. As illustrated in FIG. 16, the request issuance / response processing unit 61a includes a request queue 71a, a device status table 72a, a device request generation unit 73a, and a response processing unit 74a.

  The request queue 71 a is a queue that stores an access request from the CPU and a GC request from the garbage collection control unit 80. FIG. 17 is a diagram illustrating an example of entries in the request queue 71a. As shown in FIG. 17, the entry of the request queue 71a includes fields of valid, request type, address, and write data, and the request type indicates write, read, or GC.

  The device status table 72a is a table for managing the request issue status for each storage unit 3a. FIG. 18 shows an example of entries in the device status table 72a. As shown in FIG. 18, the device status table 72a has one entry each corresponding to a write request, a read request, and a GC request.

  In addition to the processing of the device request generator 73, the device request generator 73a issues a GC request while shifting the issue timing to each storage unit 3a when the request taken out from the request queue 71a is a GC request. To do. In addition to the processing of the response processing unit 74, the response processing unit 74 a returns a response to the GC request to the garbage collection control unit 80.

  The request count statistics unit 62 a includes a request history queue 75 a and a read counter 76. The request history queue 75a stores the same information as the request history queue 75, but stores write, read, or GC as the request type.

  The phase shift amount adjustment unit 63a includes a phase shift amount decoding table 77a, a phase shift amount determination unit 78a, a write phase shift amount storage unit 79a, and a GC phase shift amount storage unit 79b. The phase shift amount decoding table 77a is a table for determining the write phase shift amount and the GC phase shift amount according to the number of the latest read counters 76 counted by the request number statistics unit 62. Here, the write phase shift amount is the phase shift amount for the write request, and the GC phase shift amount is the phase shift amount for the GC request.

  FIG. 19 is a diagram illustrating an example of the phase shift amount decoding table 77a. As illustrated in FIG. 19, the phase shift amount decoding table 77a stores a read counter value, a write phase shift amount, and a GC phase shift amount in association with each other.

  The reason for distinguishing the write phase shift amount from the GC phase shift amount is that there is a difference in latency between the processing for the write request and the processing for the garbage collection in the SSD. In order to avoid the situation where each SSD performs garbage collection at the same time, the phase shift amount of the process for garbage collection is larger than that for the process of write request depending on the time required for garbage collection.

  The phase shift amount determination unit 78a searches the phase shift amount decode table 77a from the value of the read counter 76 to determine the write phase shift amount and the GC phase shift amount. The write phase shift amount storage unit 79a stores the write phase shift amount determined by the phase shift amount determination unit 78a, and the GC phase shift amount storage unit 79b stores the GC phase shift amount determined by the phase shift amount determination unit 78a. Remember.

  As described above, in the third embodiment, the phase shift amount determination unit 78a determines the GC phase shift amount based on the value of the read counter 76 and the phase shift amount decode table 77a, and the determined GC phase shift amount is set to the GC phase. Stored in the shift amount storage unit 79b. The device request generation unit 73a issues a GC request while shifting the issue timing to each storage unit 3a based on the GC phase shift amount stored in the GC phase shift amount storage unit 79b. Therefore, the multiplexing control unit 6 can dynamically change the phase shift amount based on the frequency of the most recent read request with respect to the GC request, and while preventing a decrease in throughput performance for the GC request, The latency with respect to can be improved.

1, 1a Multiplex storage device 2, 2a, 20 Device control unit 3, 3a Storage unit 4 Host I / F control unit 5, 24 Address conversion unit 6, 6a Multiplex control unit 7, 25 Device access control unit 8 SSD control Unit 21 Main memory 22 Controller 23 CPU
26 Flash memory 27 Device control program 61, 61a Request issuance / response processing unit 62, 62a Request number statistics unit 63, 63a Phase shift amount adjustment unit 71, 71a Request queue 72, 72a Device status table 73, 73a Device request generation unit 74 , 74a Response processing unit 75, 75a Request history queue 76 Read counter 77, 77a Phase shift amount decoding table 78, 78a Phase shift amount determination unit 79 Phase shift amount storage unit 79a Write phase shift amount storage unit 79b GC phase shift amount storage unit 80 Garbage collection controller

Claims (6)

In a multiplexed storage device that multiplexes and stores data in a plurality of storage devices,
A determination unit that determines a phase shift amount between a plurality of write instructions respectively associated with a plurality of storage devices based on a status of the read request and the write request;
A multiplexing storage device comprising: an issuing unit that issues the plurality of write instructions for the same data by shifting the phase shift amount determined by the determining unit. The write request is a request from an information processing device using the multiplexed storage device,
The multiplexed storage device according to claim 1, wherein the issuing unit issues a data write instruction included in a write request from the information processing device. The write request is a request based on garbage collection by a control device that controls the multiplexed storage device.
The multiplexed storage apparatus according to claim 1, wherein the issuing unit issues an instruction to write predetermined data based on the garbage collection. A statistical processing unit that performs statistical processing on the read request;
The multiplexed storage device according to claim 1, wherein the determination unit determines the phase shift amount based on a result of statistical processing by the statistical processing unit. A determination unit for determining the order of a read request and a write request that are waiting to be executed;
The multiplexing storage device according to claim 1, wherein the determination unit determines the phase shift amount based on a determination result by the determination unit. In a multiplexed storage control method by a multiplexed storage device for multiplexing and storing data in a plurality of storage devices,
Determining a phase shift amount between a plurality of write instructions respectively associated with a plurality of storage devices based on the status of the read request and the write request;
A multiplexed storage control method, comprising: processing for issuing the plurality of write instructions for the same data by shifting the determined phase shift amount.

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