JP5944472B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine that performs a lottery process caused by a gaming operation and executes an image effect corresponding to the lottery result, and more particularly to a gaming machine that can enrich the content of the effect while having a simple circuit configuration.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a game state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start opening, and the above symbol variation operation is based on this lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  In this type of gaming machine, it is desired to make the various demands complicated and rich, and a configuration that can meet the above requirements without complicating the circuit configuration is desired.

  This invention is made in view of said subject, Comprising: It aims at providing the game machine which can enrich production content, without complicating a circuit structure.

In order to achieve the above object, the present invention is specified by a control command and a main control means for executing a lottery process caused by a predetermined switch signal and outputting a control command for specifying a lottery result by the lottery process. An effect control means for executing a series of image effects corresponding to the lottery results using a display device, wherein the effect control means is a sound synchronized with the image effects. A memory for storing a control program for controlling a sound effect and / or a lamp effect synchronized with an image effect, wherein the data bus and the address bus of the computer element are configured by a single computer element for controlling the effect and / or the lamp effect. Connected to the device, connected to a real-time clock that can grasp the necessary timekeeping information and a memory device that can store the required presentation data in a nonvolatile manner Are, are charged at power-on, after power-off, provided with a detectable abnormality detector abnormality drop in the power supply voltage of the secondary power source for driving the real time clock, said real-time clock, the abnormality detecting unit is the power supply voltage On the condition that no abnormal drop is detected, access from the computer element is permitted .

The real-time clock is configured to set a predetermined abnormality flag when a signal received from the abnormality detection unit becomes an abnormal level, and the abnormality flag is preferably configured to be accessible by a memory element.

  The memory element is preferably configured to store game information and / or abnormality information related to the game operation together with timekeeping information acquired from the real-time clock. It is also preferable that the storage contents of the memory element are totaled based on the totaling instruction received. Moreover, it is preferable that the production control means is configured to display necessary information on the display device based on a notification instruction received from the player.

  In any configuration, it is preferable that the computer element has a built-in serial port capable of transmitting and receiving serial data, and that all or part of the lamp effect is executed via the serial port.

  Further, the effect control means includes a non-volatile memory for storing still image compression data constituting a still image, a sprite buffer for temporarily storing expansion data obtained by decoding still image compression data, and expansion data stored in the sprite buffer. A frame buffer that temporarily stores image data formed based on the command, a command memory that temporarily stores a command list that defines its own operation content, each buffer and each memory can be accessed, and operates based on the command list It is preferable that the image data temporarily stored in the frame buffer is output to the display device, and the still image is displayed on the display device. Here, the drawing control means is optimally configured to read out the command list, generate image data to be drawn on the display device, and store the image data in the frame buffer.

  According to the above-described gaming machine of the present invention, it is possible to enrich the production contents without complicating the circuit configuration.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of FIG. It is a block diagram illustrating a circuit configuration of an effect control unit. It is a block diagram which illustrates the internal structure of a digital amplifier. It is a block diagram which illustrates the internal structure of a motor / lamp drive board | substrate. It is a block diagram which illustrates the circuit structure of an image control part. 4 is a diagram schematically illustrating memory configurations of an effect control unit and an image control unit. It is drawing explaining the memory element which comprises CGROM. 9 is a diagram for explaining the address configuration of the memory element and the checksum calculation procedure. 2 is a diagram illustrating an internal configuration and operation of a power supply sequence circuit. It is drawing explaining the internal structure and internal operation | movement of VDP. It is drawing explaining a command list. It is drawing explaining the connection relation of VDP and a display apparatus. It is drawing which shows image production operation. It is drawing which shows the data structure of the production | presentation table which prescribes | regulates the operation | movement of FIG. It is drawing which shows a part of FIG. 15 in detail. It is a flowchart explaining operation | movement of an image production part. It is drawing for demonstrating the operation | movement of FIG. It is a circuit block diagram explaining the Example which implement | achieves unified production | presentation operation | movement. It is drawing which shows a part of structure of FIG.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 from the front side, not from the back side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be openable and closable.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A display device DS composed of a large liquid crystal color display (LCD) is disposed in the central opening HO. The display device DS is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. This display device DS has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area in which the game ball falls and moves, the first symbol start port 15a, the second symbol start port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17 and the gate 18 are arranged. It is installed. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  In other words, when a game ball wins the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., which game value is given based on the lottery result according to the winning timing of the game ball in advance It is determined.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 shows a part of it in detail. As shown in FIG. 3, the pachinko machine GM receives 24V AC and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, and the like, and a game control operation. Main control board 21 that centrally handles the sound, an effect control board 22 that executes a lamp effect and a sound effect based on a control command CMD received from the main control board 21, and a control command CMD ′ received from the effect control board 22 Based on the image control board 23 for driving the display device DS, the payout control board 24 for controlling the payout motor M based on the control command CMD "received from the main control board 21, and paying out the game balls, A launch control board 25 that launches a game ball in response to an operation is mainly configured.

  However, in this embodiment, the control command CMD output from the main control board 21 is transmitted to the effect control board 22 via the command relay board 26 and the effect interface board 27. The control command CMD ′ output from the effect control board 22 is transmitted to the image control board 23 via the effect interface board 27 and the image interface board 28, and is output from the main control board 21. Is transmitted to the payout control board 24 via the main board relay board 32. Although the control commands CMD, CMD ′, and CMD ″ are all 16 bits long, the main control board 21 and the payout control board 24 are used. The control commands related to are transmitted in parallel every two 8 bit lengths. On the other hand, the control command CMD 'transmitted from the effect control board 22 to the image control board 23 is 16 bits in length and transmitted in parallel. Therefore, even when the notification effects including the movable notification effect are diversified and a large number of control commands are continuously transmitted and received, the processing can be completed quickly, and other control operations are not hindered.

  By the way, in the present embodiment, the production interface board 27 and the production control board 22 are directly connected to each other by a male connector and a female connector without passing through a wiring cable, and two circuit boards are laminated. . Similarly, with respect to the image interface board 28 and the image control board 23, two circuit boards are laminated by directly connecting a male connector and a female connector without going through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit is complicated and sophisticated, the storage space of the entire board can be minimized, and noise resistance can be improved by minimizing the connection lines.

  A computer circuit including a one-chip microcomputer (MC) is mounted on each of the main control board 21, the effect control board 22, the image control board 23, and the payout control board 24. Therefore, in this specification, the control board 21 to 24, the circuits mounted on the interface boards 27 to 28, and the operations realized by the circuits are generically named. May be referred to as a section 22 ′, an image control section 23 ′, and a payout control section 24. That is, in this embodiment, the effect control board 22 and the effect interface board 27 constitute an effect control part 22 ′, and the image control board 23 and the image interface board 28 constitute an image control part 23 ′. . Note that all or part of the effect control unit 22 ′, the image control unit 23 ′, and the payout control unit 24 are sub-control units.

  The pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 includes a power supply board 20, a payout control board 24, a launch control board 25, and a frame relay board 35. Each is fixed in place on the front frame 3. On the other hand, a main control board 21, an effect control board 22, and an image control board 23 are fixed to the back of the game board 5 together with the display device DS and other circuit boards. And the frame side member GM1 and the board | substrate side member GM2 are electrically connected by the connection connectors C1-C4 concentratedly arranged in one place.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  Incidentally, the system reset signal of this embodiment is generated by a DC power supply based on an AC power supply. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power relay board 33 outputs the system reset signal SYS received from the power board 20 and the AC and DC power supply voltages to the effect interface board 27 as they are. The effect interface board 27 outputs the received system reset signal SYS to the effect control unit 22 'and the image control unit 23' as it is.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board, and directly receives the same power abnormality signal ABN2 and backup power supply BAK as the main control unit 21 receives together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V has been applied to the power supply board 20, and one of the effect control unit 22 ′ and the image control unit 23 ′ is generated by the power supply reset signal. The chip microcomputer is reset together with other IC elements.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 24, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 24 is abnormally reset. The production control unit 22 ′ and the image control unit 23 ′ perform production operations dependently on the basis of the control command from the main control unit 21. The system reset signal SYS output from is used.

  By the way, the reset circuits RST provided in the main control unit 21 and the payout control unit 24 each have a built-in watchdog timer, and unless a regular clear pulse is received from the CPUs of the control units 21 and 24, Each CPU is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 24. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  The main control unit 21 and the payout control unit 24 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 24 even after the AC power supply 24V is shut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 24 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As shown in FIG. 3, the main control unit 21 transmits a control command CMD ″ to the payout control unit 24 via the main board relay board 32, while the payout control unit 24 indicates a game ball payout operation. A prize ball counting signal, a status signal CON relating to an abnormality in the payout operation, and an operation start signal BGN are received, and the status signal CON includes, for example, a replenishment signal, a payout shortage error signal, and a lower plate full signal. The operation start signal BGN is a signal for notifying the main control unit 21 that the initial operation of the payout control unit 24 has been completed after the power is turned on.

  The main control unit 21 is connected to each game component of the game board 5 via the game board relay board 31. And while receiving the switch signal of the detection switch built in each winning opening 16-18 on a game board, solenoids, such as an electric tulip, are driven. The solenoids and the detection switch are configured to operate with the power supply voltage VB (12 V) distributed from the main control unit 21. Each switch signal indicating a winning state to the symbol start opening 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates with the power supply voltage VB (12 V) and the power supply voltage Vcc (5 V). And then transmitted to the main control unit 21.

  As described above, the effect control board 22 and the effect interface board 27 are integrated by connector connection, and the effect control unit 22 ′ is connected to each level from the power supply board 20 via the power relay board 33. A DC voltage (5V, 12V, 32V) and a system reset signal SYS are received (see FIGS. 3 and 4).

  The effect control unit 22 'receives the control command CMD and the strobe signal STB from the main control unit 21 via the command relay board 26 (see FIGS. 3 and 4). However, in an operation test executed at the product development stage or the like, various test control commands are supplied from the inspection device to the effect control unit 22 'together with a strobe signal.

  The effect control unit 22 ′ drives a lamp group composed of a large number of LED lamps and electric lamps by outputting a lamp driving signal to the lamp driving substrate 29. Further, by outputting a lamp drive signal and a motor drive signal to the motor / lamp drive board 30, the lamp group is driven and the effect motor groups M1 to Mn configured by a plurality of stepping motors are driven. Note that the lamp drive signal and the motor drive signal are both serial signals, and no matter how much the number of lamps or production motors is increased in order to enrich the production contents, the number of wiring cables will not increase, and the equipment configuration will be Simplified.

  The lamp group realizes the lamp effect almost constantly, while the effect motor group suddenly starts operation and realizes the movable notice effect by the movable effector.

  In addition, the effect control unit 22 ′ sends a control command CMD ′ and a strobe signal STB ′ to the image control unit 23 ′, a system reset signal SYS received from the power supply board 20, and two types of DC voltages (12V, 5V). ) Is output (see FIGS. 3 and 4).

  Then, the image controller 23 'drives the display device DS based on the control command CMD' to execute various image effects. As shown in FIG. 4, the display device DS emits light by the LED backlight, and five pairs of LVDS (Low voltage differential signaling) signals from the image interface board 28 and the backlight power supply voltage (12 V). ) And driven. The backlight of the display device DS is configured such that the luminance by PWM control can be controlled.

  Next, the configurations of the effect control unit 22 'and the image control unit 23' described above will be described in more detail with reference to FIG. As shown in FIG. 4, the production interface board 27 receives three types of DC voltages (5V, 12V, and 32V) from the power supply board 20 via the power supply relay board 33. Here, the DC voltage 5V is distributed to the rendering interface board 27, the lamp driving board 29, the motor / lamp driving board 30, the image interface board 28, and the image control board 23 as the power supply voltage of the digital logic circuit. The digital circuit is operating.

  However, the direct current voltage 5V is not distributed on the effect control board 22, and the direct current voltage 3.3V stepped down from 12V by the DC / DC converter and the direct current stepped down from 3.3V by the DC / DC converter. Only the voltage 1.8V is distributed from the production interface board 27 to the production control board 22.

  In this way, the production control board 22 of the present embodiment is driven by the power supply voltage of 3.3V or lower because all the circuits are driven. Therefore, even if the production interface board 27 is arranged and laminated immediately above the production control board 22, there is no problem in heat dissipation.

  The direct current voltage 12V received from the power supply board 20 by the effect interface board 27 is used as the power supply voltage of the digital amplifier 46 as it is, and is distributed to the motor / lamp drive board 30 and the lamp drive board 29 for each lamp. Group power supply voltage. On the other hand, the direct current voltage 32V received from the power supply board 20 is stepped down to the direct current voltage 13V in the DC / DC converter of the production interface board and distributed to the motor / lamp drive board 30.

  As shown in FIG. 4, the effect control unit 22 ′ includes a one-chip microcomputer 40 that executes processing such as voice effect, lamp effect, notice effect by effect movable body, and data transfer, and a control program PGMe of the one-chip microcomputer 40. A flash memory 41 for storing various effect data EN, a voice synthesis circuit 42 for reproducing and outputting a voice signal based on an instruction from the one-chip microcomputer 40, and original data of the reproduced voice signal An audio memory 43 for storing certain compressed audio data is provided.

  The voice synthesis circuit 42 and the voice memory 43 are connected by a 26-bit voice address bus and a 16-bit voice data bus. Therefore, 1G-bit compressed audio data can be stored in the audio memory 43. Then, the compressed voice data (16 bits) designated by the voice address bus (26 bits) is output to the voice data bus, and is decompressed by the voice synthesis circuit 42 to reproduce the voice data.

  Incidentally, in the case of the present embodiment, the effect data EN stored in the flash memory 41 includes scenario data for managing the progress of the effect of the lamp effect and the sound effect, the lamp drive data for determining the blinking mode of the LED, the motor Motor driving data for determining the rotation mode of the motor. The lamp driving data and the motor driving data are sequentially output bit by bit to become a lamp driving serial signal and a motor driving serial signal.

  As shown in FIGS. 4 and 8, the one-chip microcomputer 40 and the flash memory 41 are connected by a 23-bit CPU address bus and a 16-bit CPU data bus. The flash memory 41 of the embodiment has a memory capacity of 8M (= 223) × 16 bits. However, the control program stored in the flash memory 41 is checked for the entire control program PGMe including the effect data EN. Built-in program that performs sum calculation. In this checksum calculation, data in the flash memory 41 is added in units of 1 byte, and the result of the addition is stored in a 2-byte length. Therefore, the checksum value is 2 bytes long.

  By the way, the one-chip microcomputer 40, the flash memory 41, and the voice memory 43 operate at a power supply voltage of 3.3V, and the voice synthesis circuit 42 operates at a power supply voltage of 3.3V and a power supply voltage of 1.8V. Therefore, significant power saving is realized. Here, 1.8V is the power supply voltage of the computer core part of the speech synthesis circuit, and 3.3V is the power supply voltage of the I / O part.

  The one-chip microcomputer 40 includes a plurality of parallel input / output ports PIO. The control command CMD and the strobe signal STB from the main control unit 21 are input to the first input port PO1, and the control command CMD ′ and the strobe signal STB ′ are output from the second input port PO2. Has been.

  Specifically, the control command CMD and the strobe signal (interrupt signal) STB output from the main control board 21 are supplied to the first input port PO1 at the power supply voltage 3.3V in the buffer 44 of the effect interface board 27. Is converted into a logic level corresponding to, and supplied twice in units of 8 bits. The interrupt signal STB is supplied to the interrupt terminal of the one-chip microcomputer, and the effect control unit 22 'is configured to acquire the control command CMD by the reception interrupt process.

  The control command CMD acquired by the effect control unit 22 ′ includes (1) an abnormality notification and other notification control commands, and (2) control for specifying an outline of various effect operations resulting from winning at the symbol start opening. A command (variation pattern command) and a control command (symbol designation command) for designating a symbol type are included. Here, the outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end and the result of winning or failing in the jackpot lottery.

  In addition, the symbol designating command includes information for identifying information on the jackpot type (15R probability variation, 2R probability variation, 15R normal, 2R normal, etc.) in the case of a jackpot according to the result of the jackpot lottery. In some cases, information for identifying a loss is included. The outline of the production operation specified by the variation pattern command includes the production total time from the production start to the production end, and the result of success or failure in the big hit lottery. In addition to these, the change pattern command including the presence or absence of the reach effect or the notice effect may be specified, but even in this case, the specific content of the effect content is not specified.

  Therefore, when the change pattern command is acquired, the effect control unit 22 ′ performs an effect lottery subsequently to further specify the effect outline specified by the acquired change pattern command. For example, the specific contents of the reach effect and the notice effect are determined. Then, in accordance with the determined specific game content, a lamp effect by blinking LEDs and a sound effect preparation operation by a speaker are performed, and an effect operation by a lamp or speaker is performed on the image control unit 23 ′. A control command CMD ′ relating to the synchronized image effect is output.

  In order to realize such an image effect synchronized with the effect operation, the effect control unit 22 ′ controls the 16-bit length together with the strobe signal (interrupt signal) STB ′ for the image control unit 23 ′ through the second input port PO2. The command CMD ′ is output toward the effect interface board 27. In addition, when receiving the symbol designating command, the notification control command related to the display device DS, and other control commands, the effect control unit 22 ′ collects the control commands in units of 8 bits into a 16-bit length. In this state, it is output toward the effect interface board 27 together with the interrupt signal STB ′.

  Corresponding to the configuration of the production control board 22 described above, the production interface board 27 is provided with an output buffer 45, and a 16-bit control command CMD ′ and a 1-bit interrupt signal STB ′ are sent to the image interface. It is output to the substrate 28. These data CMD ′ and STB ′ are transmitted to the image control board 23 via the image interface board 28.

  The effect interface board 27 is provided with a digital amplifier 46 that receives the audio signal output from the audio synthesis circuit 42. As described above, the speech synthesis circuit 42 operates with power supply voltages of 3.3 V and 1.8 V, and the digital amplifier 46 performs class D amplification operation with a power supply voltage of 12 V, reducing power consumption. It is possible to produce a loud sound while suppressing it.

  The left and right speakers at the upper part of the gaming machine and the speakers at the lower part of the gaming machine are driven by the output of the digital amplifier 46. Therefore, the voice synthesis circuit 42 needs to generate a three-channel voice signal, and if this is transmitted in parallel, the wiring between the voice synthesis circuit 42 and the digital amplifier 46 becomes complicated.

  Therefore, in this embodiment, the voice synthesis circuit 42 and the digital amplifier 46 are connected by four signal lines in order to prevent deterioration of sound quality and avoid complicated wiring. In this case, the transfer clock signal SCLK, the channel control signal LRCLK, and the 2-bit length serial signals SDATA1 and SDATA2 are suppressed to a total of 4 bit signal lines. Note that the amplitude level of any signal is 3.3V.

  Here, SDATA1 is a serial signal for PCM data specifying the stereo signals R and L of the left and right speakers arranged at the upper part of the gaming machine, and SDATA2 is a monaural signal of the heavy bass speaker arranged at the lower part of the gaming machine. This is a serial signal for the PCM data to be specified. The voice synthesis circuit 42 transmits the left channel audio signal L while maintaining the channel control signal LRCLK at the L level, and maintains the channel control signal LRCLK at H level while maintaining the channel control signal LRCLK at the L level. Is transmitted. Since there is one heavy bass speaker in this embodiment, a monaural audio signal is transmitted, but it is of course possible to transmit it as a stereo audio signal.

  In any case, in this embodiment, four types of audio signals can be transmitted with four cables, and therefore, signal transmission without audio deterioration due to noise can be performed with the minimum number of cables. That is, since it is serial transmission, the number of cables is overwhelmingly smaller than parallel transmission. When analog transmission is employed, the number of cables is the same, but noise is superimposed on an analog signal having an amplitude of 3.3 V, and the sound quality is greatly deteriorated. On the other hand, when the amplitude level is increased, the power supply wiring becomes complicated and the power consumption increases.

  Such serial signals SDATA1 and SDATA2 are acquired by the digital amplifier 46 in synchronization with the rising edge of the clock signal SCLK. In the digital amplifier 46, parallel conversion is performed for each predetermined bit length, and after D / A conversion, D-class amplification is performed and supplied to each speaker.

  Although the internal configuration of the digital amplifier 46 is appropriate, FIG. 5 shows an internal configuration diagram when YDA171 (YAMAHA) is used as the digital amplifier. Although it is not limited to such an internal configuration, in any case, in this embodiment, since the voice synthesis circuit 42 and the digital amplifier 46 are connected by a serial line, the bit length of the PCM data (voice data) is increased. Even if the sound quality is improved, it is not necessary to change the wiring cable and the like, and the circuit configuration can be simplified.

  In addition, the effect interface board 27 is provided with buffer circuits 47 and 48 for outputting serial data output from the one-chip microcomputer 40. Here, the output buffer 47 transfers the lamp driving signal (serial signal) transmitted from the one-chip microcomputer 40 to a shift register circuit disposed on the lamp driving substrate 29. A shift register circuit (not shown) on the lamp driving substrate 29 converts the lamp driving signal into a parallel signal and drives the LED lamp group.

  The other buffer circuit 48 functions as an input / output buffer and transfers the serial signal transmitted from the one-chip microcomputer 40 to the motor / lamp drive board 30 as it is, while the origin of the group of effect motors M1 to Mn. An origin sensor signal (serial signal) indicating the position is transferred to the one-chip microcomputer 40.

  In the case of the present embodiment, the serial signal transmitted from the one-chip microcomputer 40 to the buffer circuit 48 includes a lamp driving signal (serial signal) for lighting the lamp group and a motor driving signal (serial) for rotating the effect motor. Signal) is continuous. The motor / lamp drive board 30 divides the series of serial signals into 16-bit lengths and converts each 16-bit length into a parallel signal to execute a lamp effect and a movable notice effect. Specifically, a series of lamp effects is executed as the effect operation determined by lottery in response to the control command CMD, and when a motor drive signal is received, the effect motors M1 to Mn are rotated to appropriately A movable notice effect is being executed.

  FIG. 6A is a block diagram specifically showing the circuit configuration of the motor / lamp drive board 30. As shown in the figure, the motor / lamp drive board 30 includes a PS converter 50 that serially converts the origin sensor signals of the effect motors M1 to Mn, and an input buffer 51 that receives a control signal for the PS converter 50 from the one-chip microcomputer 40. A step-down unit 52 that steps down the DC voltage 13V to 12V, an input buffer 53 that receives a lamp drive signal and a motor drive signal from the one-chip microcomputer 40, and drive control units 54 and 55 that drive and control a lamp group and a production motor group. The sink driver 56 receives the drive current of each effect motor. The PS conversion unit 50, the input buffers 51 and 53, the drive control unit 54, and the sink driver 56 operate using a DC voltage of 5V as a power supply voltage.

  The origin sensor signal is an output of an origin sensor that detects whether or not the production motors M1 to Mn are located at the origin, and each origin sensor uses a DC voltage of 12V or 5V as a power supply voltage. These 1-bit and n-bit origin sensor signals are acquired by the PS converter 51 in synchronization with the hold signal LOAD output from the one-chip microcomputer 40, and the PS converter 51 receives the transfer received from the one-chip microcomputer 40. In synchronization with the clock CK, the origin sensor signal is converted into a serial signal and transmitted to the one-chip microcomputer 40.

  As described above, in this embodiment, the one-chip microcomputer 40 can appropriately grasp whether or not each effect motor M1 to Mn is located at the origin. In addition, the possibility of misjudgment is greatly reduced by using a DC voltage (12V, 5V) of a different system from the power supply line (13V) where electromagnetic noise may be superimposed as the power supply voltage of each origin sensor. I am letting.

  Next, in the step-down unit 52, the input side 13V is used as a driving power source for each lamp, the output side 12V is used as a driving power source for the effect motors M1 to Mn, and the power source lines are separated from each other. Further, as described above, the input buffer 53 and the drive control units 54 and 55 use the DC voltage 5V generated in a completely different system from the DC voltage 13V as the power supply voltage.

  Therefore, even if the large production motor groups M1 to Mn suddenly start operation, there is a very low possibility that the lamp drive signal of each lamp is affected by power supply noise or the like. Similarly, even if the lamps are flashed violently with high luminance, the possibility that the motor drive signals of the effect motors M1 to Mn are affected by power supply noise or the like is extremely low.

  By the way, the drive control unit 54 for the production motor and the drive control unit 55 for the lamp have the same configuration. From the one-chip microcomputer 40, the operation control signal EN, the serial signal DATA, and the transfer clock signal CK Are operating in common. The serial signal DATA includes a lamp driving signal and a motor driving signal.

  The drive control units 54 and 55 have, for example, 5-bit length address terminals (A0 to A4), and are configured so that addresses can be appropriately assigned. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are fixedly assigned in advance to the H level or the L level as a hardware configuration.

  The drive control units 54 and 55 are configured to have a large number of internal control registers R1 to Rm, and by setting (writing) control data Di (8-bit length) in each of the control registers R1 to Rm, Each output of the 16-bit output terminal is appropriately controlled.

  The register numbers of the control registers R1 to Rm are 8 bits long. In this embodiment, the address terminals (A0 to A4) having a 5-bit length are set in advance to the H / L level, and the addresses ADRi of the elements 54 and 55 are fixed values.

  The operation contents realized by setting the control data Di in each control register R1 to Rm include not only the ON / OFF state of each output terminal but also the fade operation (fade in / out) until reaching the ON / OFF state. ) And the duty ratio (0 to 99.6%) in the PWM control of the output terminal in the ON state. Therefore, the one-chip microcomputer 40 does not need to bother to change the lamp drive signal (serial data) for PWM control at the time of brightness control or fade in / out presentation, and simply changes the control data of the corresponding register Ri. As a result, the control burden is greatly reduced.

  Of course, by controlling the lamp drive signal with PWM, it is possible to perform fade-in / out effects different from fixed fade operations. In short, according to this embodiment, various lamp effects are possible. It becomes. When such various lamp effects are executed, there is a concern that considerable high-frequency noise is superimposed on the output signal of the drive control unit 55, but it is difficult to affect the effect motors M1 to Mn as described above. It is.

  FIG. 6B is a time chart showing a communication protocol between the one-chip microcomputer 40 and the plurality of drive control units 54, 55... As shown in the figure, the one-chip microcomputer 40 first sets the operation control signal EN to the ON state (H level), and (1) the address number ADRi () of the drive control units 54 to 55 to which the control data Di is to be written. (8 bits long), (2) the number of control registers R1 to Rm to write control data Di in the drive control unit (8 bits long), (3) control data Di (8 bits) to be written to the control register Ri Is output as a serial signal in synchronization with the transfer clock signal CK.

  If the first register number Ri is designated for a series of control registers R1 to Rm, the subsequent control data (set values) D1, D2, R3... Are represented by Ri, Ri + 1, Ri + 2. The control data is recognized by the drive control units 54 and 55 and automatically acquired. Therefore, it is not always necessary to set a set value in all the control registers Ri. For example, in the case of a write process to a series of M control registers Ri to Ri + M−1, M pieces of control data and two pieces of address data Therefore, a total output process of 8 × (M + 2) bits is sufficient.

  When the output of all data is completed, the one-chip microcomputer 40 may return the operation control signal EN from the ON state to the OFF state, and the drive control unit identified by the address number ADRi corresponds to this operation. The operation corresponding to the control data D1... Acquired in the series of control registers Ri.

  Since the production motors M1 to Mn execute the movable advance notice production, the production motors M1 to Mn normally stand by at the origin position in the concealed state. Accordingly, the drive control unit 54 retains the control data in the OFF state, and normally it is not necessary to receive control data transfer from the one-chip microcomputer 40. However, since the control drive unit of this embodiment specifies the address number ADRi and receives the control data Di, there is no influence on the drive control unit 54 that is not designated by the address number even if the serial signal is repeatedly transferred. Don't give.

  Therefore, according to the configuration of the present invention, the drive control unit 55... 55 for controlling the lamp that continuously repeats the dynamic lamp effect and the drive control unit 54 for the movable notice effect that rarely starts the notice operation. Can have the same configuration. In addition, the one-chip microcomputer 40 can handle the motor drive signal and the lamp drive signal in the same row except for determining whether or not to add the motor drive signal to the lamp drive signal. The burden can be reduced.

  Further, by setting all or a part of the drive control units 55, 55 for lamp control to the same address value, it is possible to collect the lighting data (control data) transfer processing related to a large number of lamps, and to produce the effect control. The control burden on the unit 22 is reduced. For example, when the right and left lamp groups of the gaming machine are always caused to emit light in the same manner, a drive control unit 55R for driving the right lamp group and a drive control unit 55L for driving the left lamp group are provided. Only by setting the same address value, the lighting data transfer process can be completed at once.

  FIG. 7 is a circuit block diagram illustrating in detail the image control unit 23 ′ (the image interface board 28 and the image control board 23) including the surrounding boards. FIG. 8 is a block diagram illustrating the connection relation between the memory (ROM / RAM) and the microprocessor (one-chip microcomputer), in particular, for the effect control board 22 and the image control board 23. As described above, the image control unit 23 'operates by receiving the control command CMD', the strobe signal STB ', and the system reset signal SYS from the effect control unit 22'. In addition, two types of DC voltages 5V and 12V are received via the production control unit.

  As shown in FIG. 7, the image control unit 23 ′ stores a one-chip microcomputer 60 that receives a control command via the effect interface board 27 and executes an image control operation, a control program for the one-chip microcomputer 60, and the like. Work of the flash memory 61, the VDP (Video Display Processor) 62 for driving the display device DS based on the instruction of the one-chip microcomputer 60, the graphic ROM (CGROM) 63 for storing image compression data for image production, and the VDP 62 An SDRAM (Synchronous Dynamic Random Access Memory) 64 functioning as an area (Video RAM) and a watchdog timer WDT for forcibly resetting the one-chip microcomputer 60 are configured. The VDP 62 also includes a VRAM 77 that is used as a work area.

  In detail, the compressed image data of the CGROM 63 is divided into moving image compressed data and still image compressed data. Here, the still image is a so-called sprite image, and is a single image that realizes a background image, a special symbol, a character, or the like. Then, each frame is drawn at a predetermined position on the display device DS in a predetermined posture. On the other hand, a moving image means a set of a plurality of still images (for a plurality of frames) that change continuously, and a plurality of still images are continuously drawn on the display device DS, thereby allowing smooth movement. The behavior is reproduced.

  These compressed data are decoded by the internal circuit of the VDP 62, and the decoded image data are stored in a frame buffer secured in the SDRAM 64 or the built-in VRAM 77 after being subjected to appropriate conversion processing, and output to the display device DS. It has come to be. These drawing operations will be further described later with reference to FIG.

  The VDP62 incorporates an SDRAM interface circuit (SDRAM_I / F), a CGROM interface circuit (ROM_I / F), and a one-chip microcomputer interface circuit (CPU_I / F). (See FIG. 12). Then, the VDP 62 and the SDRAM 64 are connected via a SDRAM interface circuit (SDRAM_I / F) to a 3-bit + 13-bit SDRAM first address bus, a 32-bit SDRAM first data bus, The second address bus for SDRAM of 3 bits + 13 bits and the second data bus for SDRAM of 32 bits are connected.

  Here, among the first and second 16-bit address information, the 3 bits are bank switching signals, and the remaining 13 bits are ROW data (13 bits) and COLUMN recognized by time division. Data (10 bits). Corresponding to this, each memory (SDRAM) is divided into 8 banks, but 3 bits supplied from the VDP 62 to the SDRAM 64 function as a bank switching signal.

  Also, by combining ROW data (13 bits) and COLUMN data (10 bits), the selected address becomes 8192 * 1024 = 8M, and there are 8 banks, so a total of 64M × 16 bits = 1G bits in one memory Become long.

  In the case of the present embodiment, the SDRAM 64 functions as a work area for decompressing moving image compressed data. However, by using a total of 4 DDR2 (double data rate 2) type SDRAMs with a memory capacity of 1 Gbit, a total of 4G The memory capacity is a sufficient amount of bits.

  The data input / output terminal of each memory is 16 bits long, but for a pair of SDRAM 64, the data input / output terminal of one memory is connected to the upper 16 bits of the SDRAM data bus, and the data input / output of the other memory is connected. By connecting the terminal to the lower 16 bits of the SDRAM data bus, high-speed data access in units of 32 bits is possible. Since this is true for the first data bus and the second data bus, when the first and second data buses are combined, data access in 64-bit units is possible. In the present embodiment, in particular, since a DDR2 type SDRAM is used, even high-quality moving image data can be smoothly reproduced without any trouble, and an advanced image effect can be achieved.

  Next, the CGROM 63 will be described. The CGROM 63 is a memory that stores, in a compressed state, image data for generating a high-quality still image, an effect moving image that changes at high speed, and the like. Therefore, there is little possibility that an arbitrary address is randomly accessed like the SDRAM 64, and it is considered that there are many sequential accesses that sequentially access consecutive addresses.

  Therefore, in this embodiment, paying attention to this operation content, all data is transmitted by the ROM data bus without using the ROM address bus prepared in the interface circuit (ROM_I / F) for CGROM. It adopts a configuration that realizes the read operation. According to the configuration of the present embodiment, not only the wiring on the substrate can be suppressed and the component space can be secured, but also the manufacturing cost can be suppressed.

  FIG. 9A illustrates an internal configuration of a memory (8 Gbit ROM) suitable for the configuration of the present embodiment. As shown in the figure, this memory has a 32-bit data input / output terminals IO0 to IO31, a chip enable terminal CE, a read clock terminal RE, an operation state output terminal R / B, And a reset terminal RES. Note that the storage capacity of one element is 256M × 32 bits = 8 Gbit length.

  As shown in FIGS. 7 to 8, the CGROM 63 of the present embodiment is configured by arranging the above-mentioned 8 Gbit length memories (CG1 to CG4), and the VDP 62 and the CGROM 63 are interface circuits ( ROM_I / F) and a 64-bit ROM data bus. As described above, in this embodiment, the ROM address bus is not used.

  Of the four CGROMs, the lower 32 bits of the 64-bit ROM data bus are connected to the memory CG1 and the memory CG3, and the upper 32 bits of the 64-bit ROM data bus are connected to the memory CG2 and the memory CG4. It is connected. A common chip enable signal CE0 and read clock signal RE0 are supplied to the memory CG1 and the memory CG2 (see FIG. 8).

  Therefore, the memory CG1 and the memory CG2 perform a memory read operation at the same timing, and the 32-bit data output from the memories CG1 and CG2 are connected via the ROM data bus. Thus, a memory read operation in units of 64 bits is realized. Similarly, a common chip enable signal CE1 and a read clock signal RE1 are supplied to the memory CG3 and the memory CG4, thereby realizing a memory read operation in units of 64 bits.

  FIG. 10A illustrates the internal configuration of the memory CG1 and the memory CG2, and shows the state after address 0X0000 —0000 for convenience. Note that 0X means hexadecimal notation. For example, a usable final address 0X0FAF_FFFF of this memory corresponds to decimal numbers 263, 192, and 575.

  The VDP 62 of this embodiment manages the data of the CGROM 63 in units of 1 byte, and addresses are assigned in units of 1 byte. Further, the same chip enable signal CE0 and the read clock signal RE0 are commonly supplied to the memory CG1 and the memory CG2, and the same address information is always supplied to the memory CG1 and the memory CG2. It is configured.

  For this reason, the 32 bits of the memory CG1 and the 32 bits of the memory CG2 can be consecutively numbered, and 0, 1, 2, 3, 4, 5, 6, 7 · shown in FIG. ... 4095 means 0 address, 1 address, 2 addresses,... 4095, numbered in units of 1 byte.

  FIG. 9B is a time chart showing the operation content of each memory (CG1, CG2), and illustrates a memory read operation in which the VDP 62 reads image data from the memory CG1 and the memory CG2 in units of 64 bits. Show.

  The VDP 62 first asserts the chip enable signal CE0 to L level, and then outputs the read clock signal RE0. The VDP 62 also assigns the same address to the lower 32 bits and upper 32 bits of the ROM data bus. Information AD0 to AD2 is output. Here, the address information AD0 to AD2 is 21-bit data for specifying a base address (start address) of a series of sequential accesses. In these memories CG1 to CG4, since the lower 9 bits (bit8 to bit0) of the base address need to be all 0, the base address becomes a value of 0X200 skip (see FIG. 10A).

  As shown in FIG. 9B, the address information AD0 to AD2 is output in the order of AD0.fwdarw.AD1.fwdarw.AD2 in three steps following the start key data S (= 0XBFBF_BFBF). The output address information AD0 to AD2 is acquired in the memories CG1 and CG2 in synchronization with the rising edge of the read clock signal RE0.

  In this embodiment, the upper 32 bits of the ROM data bus are connected to the memory CG2, and the lower 32 bits of the ROM data bus are connected to the memory CG1 (see FIG. 7). Address information AD0 to AD2 is output in duplicate on the upper 32 bits and lower 32 bits of the ROM data bus. Therefore, for example, when the base address 0X0000_0000 is accessed, the addresses 0 to 3 of the memory CG1 and the addresses 4 to 7 of the memory CG2 shown in FIG. 10A are accessed together.

  In any case, the address information AD0 is 5 bits of Bit24 to Bit28 out of the 32-bit length address, and the same 5-bit data is also output to Bit8 to Bit12 and Bit16 to Bit20 in duplicate. Therefore, even if bit corruption occurs during data transmission, correct bit data can be acquired in the memory by majority logic or the like.

  On the other hand, the address information AD1 is 8 bits from Bit16 to Bit23 out of the 32-bit length address, and the same 8-bit data is also output to Bit8 to Bit15 and Bit24 to Bit31. Further, the address information AD2 is 8 bits from Bit 8 to Bit 15 in the 32-bit length address, and the same 5-bit data is also output to Bit 16 to Bit 23 and Bit 24 to Bit 31 in duplicate.

  Thus, after outputting the address information AD0 to AD2 in three steps, the VDP 62 outputs the end key data E (= 0X0000 _0000), thereby completing the transmission of the address information AD0 to AD2. Thereafter, when the decoding operation is completed in the memories CG1 and CG2 having received the same address information, the operation state output terminals R / B of the memories CG1 and CG2 are asserted at L level, and then the data in the memories CG1 and CG2 are respectively Are output to the ROM data bus in units of 32 bits. In FIG. 9B, HiZ means a high-impedance state in the three-state output, and-means that the value of the data bus at that timing has no influence on the VDP 62 and the memories CG1 and CG2. Means.

  Since the falling edge of the read clock RE0 output from the VDP 62 is a data output instruction to the memories CG1 and CG2, the VDP 62 acquires data on the ROM data bus after a predetermined timing has elapsed from the falling edge of the read clock RE0. As a result, a memory read operation is executed. Such a memory read operation can be executed continuously as long as the read clock RE0 is continued. According to the configuration of this embodiment, sequential access that accesses consecutive addresses in the order of addresses can be executed quickly. it can.

  When the necessary sequential access is completed, the VDP 62 may return the chip enable signal CE0 to the H level, and as a result, the subsequent ROM data bus is in the HiZ state.

  In addition, if new address information (AD0 to AD2) is output following the start key data S (= 0XBFBF_BFBF), a memory read of another address can be started, but the base address is 0X0000_0000 Thus, the value is a value that is a multiple of 0X200. As shown in FIG. 10A, since the interval between the base address and the next base address is 0X200 = 512, 512 * 64 corresponding to the output of 512 read clocks RE0. Bit data is obtained.

  As described above, according to the configuration of the present embodiment, new data is transferred to the memory CG1 and the memory CG2 by data transmission of the start KEY data S → address information AD0 → address information AD1 → address information AD2 → start KEY data E. After designating the same base point address, 64 bits of data (32 bits of CG1 + 32 bits of CG2) (data for 8 addresses) can be read out together with one read clock, and the read clock is output after that Since 64-bit data can be acquired each time, a quick memory read operation is realized. This relationship is the same for the memory CG3 and the memory CG4.

  By the way, the CGROM configured in this way stores CG data that realizes various types of sprites related to still images and moving images with the data structure shown in FIG. A sprite means a group of images such as a character design and a background image, for example. CG data that realizes such a sprite is divided into pattern attributes and pattern data.

  Here, the pattern data is a bitmap that determines the pattern of the sprite. For example, for a sprite having N × M pixels, each pixel is expressed by, for example, RGB three primary colors (RGB color space) with a 24-bit gradation. In this case, the length is N × M × 3 × 24 bits.

  On the other hand, the pattern attribute is variable length data indicating an attribute value unique to the pattern data, and is composed of a 4-byte length essential attribute area and a variable length extended attribute area (see FIG. 9C). . In addition to the 3-byte data that specifies the vertical and horizontal sizes of the sprite, the essential attribute area includes pattern data information (number of bits per pixel, color space type, etc.), alpha data Includes several bits that specify the storage format, whether or not a checksum value is stored in the extended attribute area, or whether or not an alpha table or palette table exists in the pattern data area It is.

  In this embodiment, by storing predetermined bit data in the essential attribute area, the check attribute value is stored in the extended attribute area. Correspondingly, the 1-byte area of the extended attribute area is stored in the 1-byte area. In addition, a checksum value is stored that, when added to the 8-bit total value of the sprite data, results in an addition of zero.

  When reading the sprite data (CG data), the VDP 62 accompanies the checksum operation, and the addition result obtained by adding the checksum value to the total value at the time of reading all the data does not become zero. In this case, a ROM error interrupt is generated. In response to the ROM error interrupt, the one-chip microcomputer 60 executes predetermined error processing, which will be described later.

  Returning to FIG. 7 and continuing the description, the one-chip microcomputer 60 and the VDP 62 of the image control unit 23 'are connected by a 21-bit CPU address bus and a 32-bit CPU data bus. When evaluated from the one-chip microcomputer 60, the VDP 62 is an I / O device that can be arbitrarily accessed from the one-chip microcomputer 60, and a large number of registers R1 to Rn built in the VDP 62 are targets of READ / WRITE. That is, by writing the information output to the CPU data bus to the predetermined register Ri specified by the address information of the CPU address bus, the VDP 62 can be instructed to execute a predetermined operation, and the predetermined register Rj By reading this information, it is possible to grasp the operation state and operation result of the VDP 62.

  The register Ri built in the VDP includes, for example, (1) a register Rx that defines an operation start address, (2) a register Ry that defines an operation end address, and (3) an operation content when executing a checksum operation. A register Rz to be defined and (4) two result storage registers RsL and RsH are included. Therefore, in this embodiment, by utilizing these registers Rx, Ry, Rz, RsL, and RsH, the VDP 62 is allowed to execute a checksum calculation in an arbitrary area of the CGROM 63, and the one-chip microcomputer 60 stores the calculation result in the register. It is obtained from RsL and RsH.

  This checksum calculation is started when the one-chip microcomputer 60 receives an inspection control command from the upstream one-chip microcomputer 40, from the calculation start address specified in the register Rx to the calculation end address specified in the register Ry. The addition operation defined by the register Rz is executed for the data of.

  More specifically, for the address data in 1-byte units of the CGROM 63, an addition operation in 8-bit units is executed for every 4 bytes, that is, for each memory element, and the calculation results are stored in the two registers RsL and RsH, respectively. Stored in 16-bit length. The arrows in FIG. 10 (b) and FIG. 10 (c) indicate the procedure of this checksum calculation. For a given memory element CGi, 8 bytes for 4 bytes for each byte from the execution start address. When the bit addition operation is completed, the 8-bit addition operation is continued for the continuous addresses of the same memory element CGi. When the addition operation up to the operation end address is completed, the 16-bit operation result is stored in the register RsL and the register RsH. Is done.

  In the illustrated example, the checksum operation is collectively performed on the memories CG1 and CG2, the addition result of the memory CG1 is stored in the register RsL, and the addition result of the memory CG2 is stored in the register RsH. This is the same for the memories CG3 and CG4. For the memories CG3 and CG4, the checksum operation is collectively performed, the addition result of the memory CG3 is stored in the register RsL, and the addition result of the memory CG4 is stored in the register RsH. Is saved.

  In this embodiment, although 64-bit data can be acquired by one access to the CGROM 63, an 8-bit addition operation is executed every 4 bytes, and the result is obtained in 2-byte length. Since the data is stored, the garbled data can be detected for each memory element CGi. That is, unlike the present embodiment, if 64-bit data is continuously added, even if bit corruption can be detected, the memory element in which bit corruption has occurred cannot be specified.

  The SDRAM 64 and the CGROM 63 have been described above. Next, the flash memory 61 of the image control unit 23 'will be described. The one-chip microcomputer 60 and the flash memory 61 are connected by a 23-bit CPU address bus and a 16-bit CPU data bus. The flash memory 61 has a memory capacity of 8M (= 223) × 16 bits, but the control program includes a program that executes the same checksum operation as the VDP 62 executes for the entire control program including constant data. Has been. That is, the entire flash memory 61 is also subjected to an addition operation in units of 1 byte, and the operation result is stored in a 16-bit length.

  Incidentally, the output of the watchdog timer WDT shown in FIG. 7 is supplied to the OR circuit together with the system reset signal SYS, and when one of the input signals to the OR circuit becomes an active level, the one-chip microcomputer 60 and the VDP 62 It is reset synchronously. Therefore, when the control operation is initialized due to the program runaway of the one-chip microcomputer 60, the operation of the VDP 62 is initialized correspondingly, and the contradictory and unnatural image effect is executed. It will not be done.

  In this embodiment, the power supply voltage of each element is minimized in order to suppress the power consumption as much as possible. The power supply voltage of each element is (1) the one-chip microcomputer 60 is 3.3V and 1.25V. (2) Flash memory 61 is 1.25V, (3) VDP62 is 3.3V, 1.8V and 1.1V, (4) CGROM 63 is 3.3V, and (5) SDRAM 64 is 1.8V. .

  As described above, in this embodiment, a large number of DC voltages are required to save power, and the supply timings of circuit elements having a plurality of power supply voltages need to be optimized. On the other hand, only two types of direct current voltages are distributed for the purpose of suppressing the number of wiring cables between the effect control unit 22 'and the image control unit 23'.

  Therefore, by arranging a plurality of DC / DC converters having control terminals and providing a power sequencer 65, a large number of DC voltages are supplied to each element at an optimal timing. FIG. 11 shows an internal configuration (a) of LM3881 (national semiconductor) as an example of the power sequencer 65 and an operation time chart (b) executed even when the power sequencer 65 is used.

  In the case of the power sequencer 65 in FIG. 11A, when the INV terminal is at the L level, the operation starts in response to the operation start command EN at the H level, and a clock defined by the capacitance connected to the TADJ terminal. The first control signal PCNT1 rises after nine cycles of the signal Clock, the second control signal PCNT2 rises after eight cycles of the clock signal, and the third control signal PCNT3 rises after another eight cycles of the clock signal.

  On the other hand, when the operation start command EN transitions to the L level, the third control signal PCNT3 falls after 9 cycles of the clock signal, the second control signal PCNT2 falls after 8 cycles of the clock signal, and further 8 cycles after the clock signal. The third control signal PCNT3 falls.

  In the present embodiment, as shown in FIG. 7, the operation start command EN is an AND logic output of two types of DC voltages supplied from the effect control unit 22 '(effect interface board 27). The first control signal PCNT1 is supplied to the operation enable terminal EN of the DC / DC converter V1 for generating 1.1V, and the second control signal PCNT2 is an operation enable for the DC / DC converter V2 for generating 3.3V. It is supplied to terminal EN.

  The third control signal PCNT3 is converted into an AND logic output with 3.3V and supplied to the operation enable terminal EN of the DC / DC converter V3 for generating 1.8V. Each DC / DC converter described above starts the voltage conversion operation on condition that the operation enable terminal EN becomes H level.

  Therefore, as shown in FIG. 11 (b), the DC / DC converter V1 first functions based on 5V distributed from the effect control unit 22 'to generate the DC voltage 1.1V. This DC voltage 1.1V is a power supply voltage for the digital circuit and the built-in VRAM built in the VDP 62, and the normal operation start sequence of the VDP 62 after the power is turned on by starting the operation before other built-in circuits. Is secured.

  After the above operation, since the second control signal PCNT2 becomes H level, the DC / DC converter V2 that receives 12V distributed from the effect control unit 22 'functions to generate the DC voltage 3.3V. The DC voltage 3.3V is supplied to the DC / DC converter V4 for 1.25V. Since this converter V4 does not have an operation enable terminal, the DC voltage 1.V is started immediately. 25V is generated.

  The two types of DC voltages 3.3V and 1.25V generated by being controlled by the second control signal PCNT2 are supplied to the one-chip microcomputer 60, the flash memory 61, and the CGROM 63 at almost the same timing. Each of the circuit elements is ready for operation start without delay after power-on. At this timing, the system reset signal SYS is at the L level, and after this level has been maintained for a while, the power supply circuit of the power supply board is operating so as to change to the H level. The power will be reset.

  Finally, when the third control signal PCNT3 changes to H level, the AND logic output of the third control signal PCNT3 and 3.3V is supplied to the DC / DC converter V3 to generate a DC voltage of 1.8V. This DC voltage 1.8 V is supplied to the VDP 62, SDRAM 64, and SDRAM power supply circuit 68 at almost the same timing, so that the SDRAM 64 and the SDRAM interface circuit in the VDP 62 can be operated in synchronization. Become. Therefore, when the system reset signal SYS changes to the H level, the VDP 62 can smoothly start the initial setting operation.

  FIG. 12A is a block diagram showing the internal configuration of the VDP 62, including the connection relationship between the VDP 62, the CGROM 63, the DDR2-type SDRAM 64, and the one-chip microcomputer 60 (hereinafter referred to as the host CPU 60). ing. 12B is a functional block diagram showing the operation of the VDP 62, and FIG. 12C is a drawing showing the operation procedure of the VDP 62.

  As shown in FIG. 12 (b), a VBlank interrupt signal is transmitted from the VDP 62 to the host CPU 60. Based on the VBlank interrupt signal that normally occurs every 1/60 seconds, the host CPU 60 performs one frame of the display device DS. It is configured so that it can be understood that the display operation has been completed.

  As shown in FIG. 12A and FIG. 12B, the VDP 62 includes a command memory 70 in which a command list is written by the host CPU 60, a system control register 71 accessed from the host CPU 60, and a command for analyzing the command list. A parser (syntax analyzer) 72, a still picture decoder 73 for decoding still picture compression data, a moving picture decoder 74 for decoding moving picture compression data, and an image decoded (expanded) by the decoder A geometry engine 80 that performs affine transformation such as movement and projection transformation, a rendering engine 81 that generates image data that can be output to the display device DS, and a display controller 82 that generates various signals of an LCD (Liquid Crystal Display). 83 and a signal output unit (LVDS transmission unit 7 5 and the DRGB transmission unit 76).

  The system control register 71 is roughly divided into an input register group in which instruction data for the VDP 62 is written, and an output register group in which the host CPU 60 reads out information indicating the operating state of the VDP 62. Then, the host CPU 60 knows the operating state of the VDP 62 by appropriately operating the VDP 62 by writing a necessary set value in an appropriate input register and referring to the value of the required output register.

  The drawing operation of the VDP 62 is executed for each frame as the command parser 72 analyzes the command list written in the command memory 70 by the host CPU 60. For this rendering operation, in the present embodiment, a sprite buffer SPB that decodes and temporarily stores still image compression data is secured in the built-in RAM 77, and a movie buffer MVB that decodes (decompresses) moving image compression data and primarily stores it. , Reserved in the SDRAM 64. That is, the still image decoder 73 decodes predetermined still image compressed data based on the analysis result of the command list by the command parser 72, and stores the decoded result in the sprite buffer SPB (built-in RAM 77). The moving picture decoder 74 decodes predetermined moving picture compression data based on the command list analysis result by the command parser 72 and stores the decoding result in the movie buffer MVB (SDRAM 64).

  The still image expanded in this way and the still image for one frame of the moving image are enlarged, reduced, rotated, or rotated by the geometry engine 80 based on the contents specified in the command list in the sprite buffer SPB or movie buffer MVB. Processing such as affine transformation such as movement and projection transformation is performed. Thereafter, the rendering engine 81 functions, and the data of the sprite buffer SPB and the movie buffer MVB is collected in the SDRAM 64 or the frame buffer FLB secured in the built-in RAM 77.

  In this embodiment, the frame buffer FLB is secured in the built-in RAM 77. However, since the DDR2 type SDRAM 64 is used, there is no problem in processing speed even if the frame buffer FLB is secured in the SDRAM 64.

  Whichever memory 64, 77 is secured, the frame buffer FLB has a double buffer structure, one functioning as a display bank and the other functioning as a drawing bank, and the function is applied to each frame. It works by switching every time. The image data of the display bank is output to the display device DS, and the image data is written into the drawing bank by the rendering engine 81.

  Next, the above description is organized based on FIGS. 12 (b) to 12 (c). The host CPU 60 writes the command list in the command memory 70 due to, for example, the VBlank interrupt (t1) (t2). Next, the host CPU 60 starts the drawing operation of the VDP 62 by setting the start address of the command list and other control information in the system control register 71 (t3).

  Then, the still picture decoder 73 and the moving picture decoder 74 operate in response to the drawing start instruction, the compressed data of the CGROM 63 is read based on the command list of the command memory 70, and the decoding result is converted into the sprite buffer SPB, Then, it is expanded in the movie buffer MVB (t4, t4 ′).

  Next, the geometry engine 80 performs a coordinate operation on the data of the sprite buffer SPB and the movie buffer MVB based on the command list, and the rendering engine 81 executes a drawing operation based on the calculation result. Then, the drawing result is written into the drawing bank of the frame buffer FLB (t5).

  Next, when the drawing bank and the display bank of the frame buffer FLB are switched (t6), the display controller 82 functions thereafter, and an output signal is generated based on the image data of the frame buffer FLB (display bank). It is output to DS (t7). In the present embodiment, the display device DS as an LCD is driven via the LVDS_I / F unit 75.

  The operation procedure of VDP has been described above. Next, the command list will be described with reference to FIG. The command list is a command sequence that lists commands for the VDP 62 (command parser 72). However, the description content and description order are slightly different between the case of instructing drawing of a still image and the operation of instructing drawing of a moving image. To do.

  In the case of a command list for instructing the VDP to draw a still image, as shown in FIG. 13A, first, the memory areas of the frame buffer FLB and the sprite buffer SPB are specifically set (S1). As described above, in this embodiment, the sprite buffer SPB and the frame buffer FLB are set in the built-in VRAM 77, and the buffer size is set corresponding to the screen size (for example, 640 × 320).

  Next, the decoding of the still image is instructed (S2). Specifically, the decode instruction is an instruction of which still image compressed data is to be decoded, and is executed by instructing the head address of the CGROM 63 storing the target sprite, the data size, and the like. In this embodiment, the memory area of the sprite buffer SPB can be set as appropriate. For example, still images that are frequently used can be decoded in advance into a special sprite buffer area.

  In this way, after a decoding instruction for a predetermined still image (sprite) is given, the decoded decompressed data is displayed at any coordinate position on the display device DS and in any manner (rotation angle, reduction / enlargement, etc.). Whether to draw is instructed (S3). Then, if an end processing command such as bank flip is entered (S4), the command list for the specific sprite is completed. Note that the bank flip means switching between the drawing bank and the display bank (see t6 in FIG. 12C).

  By the way, when there are a plurality of sprites to be drawn, the decoding instruction (S2) and the drawing instruction (S3) are repeatedly executed for the plurality of sprites. In such a case, although the drawing positions may overlap, the priority of the image drawn first is the lowest, and the image drawn last is the highest priority. Further, as described above, the decompressed data decoded into a special sprite buffer area that is not overwritten can be repeatedly used based on a drawing instruction for a decoded still image.

  In the case of a command list for instructing the VDP to draw a moving image, the initial command list in FIG. 13B and the steady command list in FIG.

  As shown in FIG. 13B, even in the case of a moving image, first, the memory areas of the frame buffer FLB and the movie buffer MVB are specifically set (S11). As described above, in this embodiment, the movie buffer MVB is set in the SDRAM 74 and the frame buffer FLB is set in the built-in VRAM 77. Note that the buffer size of the frame buffer FLB is set to be the same as that of the still image corresponding to the screen size (for example, 640 × 320).

  Next, the decoding of the moving image is instructed (S12). The decoding instruction is specifically an instruction of which moving image compressed data is to be decoded. The start address of the CGROM 63 storing the corresponding moving image, the movie ID for specifying the moving image, the total number of frames of the moving image, and the like. With instructions. Then, an end processing command is entered to complete the initial command list (S13).

  When this initial command list is executed, the compressed moving image data including a series of still images is decoded, and the decompressed data is expanded in the movie buffer MVB. Therefore, after the decoding of the frame number to be drawn is completed, the host CPU 60 issues the steady command list of FIG.

  The steady command list (FIG. 13C) is composed of drawing instructions for a series of still images that make up a moving image. Specifically, for each moving image identified by a movie ID, which frame number of decompressed data is stored. Is drawn at which coordinate position of the display device DS (S14). Then, if the end processing command is entered (S14), the steady command list for the specific moving image is completed.

  Thereafter, the host CPU 60 may repeatedly issue a steady command list with the updated frame number to the command memory 70 for the same movie ID, and the reproduction of the moving image is performed with a command list (initial command list) for the first time, This is realized by a command list (stationary command list) that is executed a plurality of times for the number of frames.

  FIG. 14 illustrates the LVDS transmission unit 75 in more detail with respect to the connection relationship between the display device DS and the VDP 62 that generates the image data by performing the above-described operation. As shown in the figure, the display device DS of the present embodiment is configured to include an LVDS reception unit (LVDS_I / F) 81 corresponding to the LVDS transmission unit (LVDS_I / F) 75 of the VDP 62.

  As shown in FIG. 14A, the LVDS_I / F unit (LVDS transmission unit) 75 is a part that converts parallel data including 24 bits of RGB data into a low voltage differential signaling (LVDS) signal. LVDS means a low-voltage differential transmission system for high-speed transmission of RGB data and the like with low noise and low power. In this embodiment, several mA is applied to a pair of signal transmission lines (one twisted pair line). While a low level signal current is supplied from the transmission side, this signal current is received by a terminating resistor of about 100Ω provided on the reception side. Therefore, although the voltage amplitude is a low level of about several hundred mV, reliable signal transmission is realized by changing the current direction corresponding to the logic level (H / L).

  In this embodiment, as shown in FIG. 14A, a total of 28-bit parallel data (TA0 to TA0) including all 24-bit RGB signals (each 8 bits long) and horizontal / vertical synchronization signals. TA6, TB0 to TB6, TC0 to TC6, TD0 to TD6) are converted into four pairs of differential signals in the LVDS transmission unit 75. Then, a differential signal of a pair of transfer clocks is added to this and transmitted to the display device DS through five twisted pair lines.

  In FIG. 7 and FIG. 14A, these four pairs of differential signals are evaluated from the standpoint of the display device DS, and (RXIN0 +, RXIN0−), (RXIN1 +, RXIN1−), (RXIN2 +, RXIN2−). ), (RXIN3 +, RXIN3 +), (RXCLK +, RXCLK−).

  As shown in FIG. 14 (b), G0 → R5 → R4 → R3 → R2 → R1 → R0 is serially transferred on the twisted pair lines (RXIN0 +, RXIN0−) during one cycle of the transfer clock RXCLK, and the twisted pair line is transmitted. In (RXIN1 +, RXIN1-), B1 → B0 → G5 → G4 → G3 → G2 → G1 are serially transferred, and in the twisted pair lines (RXIN2 +, RXIN2-), DE → (VS) → (HS) → B5 → B4 → B3 → B2 is serially transferred, and NA → B7 → B6 → G7 → G6 → R7 → R6 is serially transferred on the twisted pair line (RXIN3 +, RXIN3-).

  Here, R0 to R7 are 8-bit length data indicating the luminance of the red pixel, G0 to G7 are 8-bit length data indicating the luminance of the green pixel, and B0 to B7 are 8-bit length data indicating the luminance of the blue pixel. It is. In addition, (VS) and (HS) indicate vertical synchronization timing and horizontal synchronization timing, and DE means DATA ENABLE. Note that NA is unused.

  The display device DS that receives the four pairs of differential signals is provided with an LVDS receiver 81 corresponding to the LVDS transmitter 75 of the VDP 62. A series of serial data is converted into parallel data, and four sets of parallel data RA0 to RA6, RB0 to RB6, RC0 to RC6, and RD0 to RD6 are obtained. As is apparent from the serial data string shown in FIG. 14B, the parallel data RA0 to RA6 are specifically 7 bits of R0 to R5 and G0, and other parallel data are also shown in FIG. 14B. This corresponds to the serial data shown.

  The display device DS realizes screen display based on the RGB gradation data extracted from these. In this way, in this embodiment, the pixel data is 8 bits for each RGB (256 gradations), and a full color image effect can be realized.

  Moreover, since the LVDS signal is used for signal transmission between the VDP 62 and the display device DS, the voltage amplitude is low enough (several hundred mV), and the rise time and fall time of the digital signal are correspondingly short, so high-speed communication is possible. It can be realized, and an image effect transitioning to a high speed can be realized smoothly. Moreover, since it is not affected by common mode noise, an unnatural pixel does not occur.

  Further, since the number of cables is small, space saving and cost reduction are realized, and signal transmission can be performed with a low level voltage, so that power saving can be achieved. Therefore, by utilizing these advantages, it is possible to enrich game effects by arranging more movable effects bodies.

  Since the twisted pair lines (RXIN3 +, RXIN3-) are configured to serially transfer NA → B7 → B6 → G7 → G6 → R7 → R6, the twisted pair lines (RXIN3 +, RXIN3-) are not used, or In addition, by serially transferring NULL data through the twisted pair lines (RXIN3 +, RXIN3-), it is easy to suppress 64 gradations of 6 bits for each of RGB.

  Incidentally, as shown in FIG. 7, in addition to the above-described LVDS signal, two types of DC voltages (12V, 3.3V) and a PWM control signal VBR are transmitted to the display device DS from the image interface board 28. ing.

  Here, the direct-current voltage 3.3V is a power supply voltage of the electronic circuit of the display device DS including the LVDS receiver 81, and the power is reduced by the low power supply voltage. On the other hand, the DC voltage 12V is a power supply voltage of the liquid crystal backlight unit BL composed of LED lamps. In this embodiment, the backlight unit BL is configured by a plurality of LED lamps connected in series, and the cold cathode tube is not used. Therefore, the circuit configuration can be simplified, the power can be reduced, and the performance can be improved. .

  On the other hand, in order to use a cold cathode tube, an inverter circuit that converts a high voltage of about 32 V DC to an AC voltage of about 1000 V at a frequency of about 30 kHz to 45 kHz is necessary, a large installation space, and high power consumption. Although it has become a noise source on the top (about several watts), all of these problems are solved in this embodiment.

  That is, since the backlight unit BL of this embodiment is a DC drive of 12V, it does not become a noise source, an inverter circuit is unnecessary, and power consumption is reduced to half or less.

  Further, the display device DS of this embodiment has a built-in drive circuit that receives a DC voltage of 12 V and supplies a drive current of about 40 to 65 mA to a plurality of LED lamps. This drive circuit is configured so that the dimming of the LED lamp can be controlled by the PWM control signal VBR. For example, for a gaming machine in which a player is not seated, the backlight can be turned off. But power saving is realized.

  Note that the PWM control signal VBR of the embodiment has a voltage amplitude of 3.3 V and is configured so that the duty ratio can be arbitrarily set in the range of 0 to 100%. And the brightness | luminance of a backlight can be changed to a desired level by changing a duty ratio suitably in the state which sent regulation current (40-65mA) to LED of an energized state.

  As described above, the hardware configuration of the image control unit 23 ′ has been mainly described. Subsequently, the image control operation executed by the image control unit 23 ′ will be specifically described.

  In the gaming machine of the embodiment, the series of image effects executed by the image control unit 23 ′ that has received the effect command CMD ″ is the effect progress table provided corresponding to the effect commands CMD1 ″ to CMDn ″ for image effects. It is managed by Pr_TBL1 to Pr_TBLn.

  Here, the effect progress table Pr_TBL defines the start times Ti for the segment effects ENi (EN1 to ENn) obtained by appropriately dividing a series of image effects on the time axis. The effect progress table Pr_TBL is, for example, as shown in FIG. 15A, and for each segmented effect ENi, an effect table that defines the start timing Ti from the start of a series of effect operations and specific effect contents. Index information INXxy for specifying Di_xy is stored. The elapsed time from the start of a series of effect operations is measured by the effect timer TMR.

  FIGS. 15B and 15C exemplify an image effect that is executed when a specific effect command CMD ″ is received, and is realized based on the effect progress table Pr_TBL shown in FIG. Is done.

  The series of image effects shown in FIG. 15 (b) includes a segment effect EN1 (start variation effect of T0 to T4) from the start of the variation of the three symbols until the left and right symbols stop in the reach state, and the subsequent segment. The production EN2 (normal reach production from T4 to T5), the division production EN3 (T5 to T6 super reach production) continued in the promoted state, and the division production EN4 (final production from T6 to T7) indicating the winning state It is divided into a division effect EN5 (swing fluctuation effect after T7) in which the design floats. In addition, in the Example, although the production time of the division | segmentation productions 1-5 is comprised so that it may not mutually overlap, it is not specifically limited.

  As shown in FIG. 15 (c), the image control unit 23 that has received the predetermined effect command CMD "starts, for example, in the order of the left symbol“ 7 ”→ the middle symbol“ 8 ”→ the right symbol“ 4 ”from the timing T0. Then, the rotation of each symbol is started, and thereafter, after three symbols are rotated at high speed from timing T1, a notice effect is executed at timing T1 + β. Then, at the timing T2, the left symbol “2” is stopped, and at the timing T3, the right symbol “2” is stopped.

  Thereafter, as a series of image effects, a normal reach effect is started from timing T4, and the timing is promoted to a super reach effect with a high expectation. Then, the final effect indicating the winning state is started from the timing T6, and then the fluctuation variation effect is executed from the timing T7 with the stopped symbols “3”, “3”, and “3” in the winning state. Note that the fluctuation variation effect ends when the stop command CMD "is received.

  FIG. 16A illustrates the data structure of the effect table Di_xy for realizing the above-described segmented effect ENi. As shown in the figure, the effect table Di_xy is for each of the table header information HDt that comprehensively specifies the segment effect ENi defined by itself, and one or more unit effects (UT1 to UTn) that realize the segment effect ENi. Each unit effect UTi is composed of actual frame data 1 to n for specifying the contents of the effect. That is, in this embodiment, the effect table Di_xy specifying the segment effect ENi has a relationship of Di_xy = HDt + n frame actual data.

  As shown in FIG. 16A, the table header information HDt includes, in addition to the index information INXi of the effect table Di_TBL, the total number of frames TLF realizing the segmented effect ENi, the total data size TLD, and the like. ing. Here, the number of frames TLF is the number of display screens drawn in time sequence on the display device. In this embodiment in which an image is displayed every 1/60 seconds, for example, a section effect EN of 5 minutes is realized. The total number of frames to be performed is 5 × 60 × 60. Therefore, the total frame number TLF means the effect duration time of the segment effect EN.

  The actual frame data 1 to n are data for specifying the content of the effect for each unit effect UTi that realizes the segmented effect ENx. As shown in FIG. 16B, the effect header information HDe and an arbitrary number of scenes It consists of information SNk. That is, in this embodiment, the actual frame data specifying the unit effect UTi has a relationship of HDe + SN1 + SN2 +.

  Here, the effect header information HDe includes the start time of the unit effect UTi, the frame size used for the unit effect UTi, and the number of scenes (k, l, m) that realize the unit effect UTi. The number (k, l, m) of scene information is specified by the effect header information HDe (see FIG. 16B).

  As shown in FIG. 16C, each of the scene information SN1 to SNk is composed of scene header information HDs and scene data DATA composed of a combination of duration and sprite information. The scene data DATA is variable length data, and the data range is specified by the END data.

  The scene header information HDs includes (1) overall information of the image constituting the scene information SNk, (2) size information indicating the vertical and horizontal sizes of the image, and (3) a memory location indicating the storage location of the CGROM 63 of the image. Information, data size, and the like are included (see FIG. 16C).

  The overall image information includes information on whether the image constituting the scene information SNk is a group of moving images or a single or a plurality of still images (sprites), a drawing channel CHi to be drawn, and the scene information. After the execution, LOOP information or the like indicating whether the rendering operation is finished or re-executed from the beginning is specified.

  When the unit effect UTi is realized by a moving image, the data size of the scene header information HDs includes the number of frames for realizing the moving image. That is, a moving image is realized by a series of a plurality of still images being continuous, and the scene header information HDs relating to the moving image includes the continuous number of still images (the number of frames) that realize the moving image.

  The drawing channel CHi defines the priority order of a plurality of images drawn in duplicate. In this embodiment, the command list for the image of the minimum channel number CH0 is written first, followed by the command list for the image of the next channel CH1, and thereafter the command list for the maximum channel number CHm is similarly written. It is structured to write. Since the VDP describes the image data in the frame buffer FLB in the order of the command list, the image of the largest channel CHm written last is given the highest priority in the overwritten image. .

  FIG. 16D and FIG. 17A show the arrangement of the segment effect EN1 (start variation effect of T0 to T4) in an organized manner. As shown in FIG. 17A, the segment effect EN1 is composed of eight unit effects UT1 to UT8. Specifically, the segment effect EN1 = unit effect UT1 (frame actual data 1) + unit effect UT2 (Frame actual data 2) +... + Unit effect UT8 (frame actual data 8) is established.

  Here, the unit effects UT1 to UT4 and the unit effects UT6 to 8 are each composed of single scene information SN1... SN1, and the scene information SN1 of the unit effect UT1 means a background image. ing. On the other hand, the other six pieces of scene information SN1... SN1 all specify a motion effect by moving images, and start rotation A1, start rotation A2, start rotation A3, stop operation A5, stop operation A6, and notice effect, respectively. B1 is specified.

  On the other hand, the unit effect UT5 is composed of three scene information SN1 to SN3, and each scene information SN1 to SN3 specifies the effect operation by the moving image, and the left symbol, the middle symbol, and the right symbol, respectively. The high-speed rotation (A41, A42, A43) is specified.

  The same applies to the segment effects EN2 to EN5, as shown in FIGS. 16 (e) to 16 (h) and FIGS. 17 (b) to 17 (e), respectively.

  For example, the segment effect EN2 (normal reach effect) and the segment effect EN3 (super reach effect) are each composed of one unit effect (UT1). Then, the segment effect EN2 (normal reach effect) = unit effect UT1, which is composed of scene information SN1 for specifying the reach effect C1 and scene information SN2 for specifying the reach symbol (symbol 2) (UT1 = SN1 + SN2). ). Similarly, section effect EN3 (super reach effect) = unit effect UT1, and is composed of scene information SN1 that specifies the super reach effect D1 and scene information SN2 that specifies the promoted reach symbol (symbol 3) ( UT1 = SN1 + SN2).

  The segment effect EN5 (final effect) and the segment effect EN6 (swing fluctuation effect) are each composed of one unit effect UT1, but the unit effect UT1 of the segment effect EN5 (final effect) has three scene information. The scene information SN1 to SN3 is composed of SN1 to SN3, and specifies anomalous variation effects (E1 to E3) by moving images.

  On the other hand, the scene information SN1 to SN3 of the segment effect EN5 (final effect) respectively specifies fluctuation fluctuations (F1 to F3) due to still images.

  As is apparent from the above configuration, in this embodiment, each segmented effect ENi is composed of a single or a plurality of unit effects UT1 to UTn each having a start time defined (that is, not necessarily common). . Then, the start timing of the division effect is managed by the effect timer TMR.

  On the other hand, each unit effect UTi is composed of single or a plurality of scene information SN1 to SNk with a specified start time (that is, a common start time). The start timing of the scene information is also managed by the effect timer TMR. The display continuation time of individual sprites constituting the scene information is managed by continuation timers TM0 to TMm provided for the drawing channels CH0 to CHm.

  FIG. 18 is a flowchart showing the operation contents of the main processing of the one-chip microcomputer (host CPU) 60 of the image control unit 23. When the host CPU 60 is reset, a series of main processing (ST82 to 89) is performed in an infinite loop after appropriate initial setting processing (ST81) is executed including each part of the one-chip microcomputer and various registers 71 of the VDP. Repeated.

  In the main process, first, it waits for a VBlank interrupt from VDP (ST82). Here, the Vblank interrupt occurs at the timing when the VDP 62 finishes drawing one frame on the display device DS, for example, every 1/60 seconds.

  As described above, the VDP 62 of the embodiment adopts the double buffer method, and is configured to store image data for one frame of the display device DS in the display bank and the drawing bank, respectively. The functions of the two frame buffers FLB are alternately switched, and the image data of the display bank is output to the display device DS, while the next image data is drawn in the drawing bank.

  Therefore, if there is a Vblank interrupt (ST82), it is determined whether there is a new received command (ST83). If a new control command is received, processing corresponding to this is executed (ST84). ). For example, when the production command CMD "is received, the production progress table Pr_TBL corresponding to the production command is specified.

  In the process of step ST84, in order to start the image effect operation, the effect flag FLG is set, and an effect timer TMR for managing the progress of the image effect is started. The effect timer TMR is incremented in the process of step ST89 and executes a time measuring operation.

  As described with reference to FIG. 15A, the effect progress table Pr_TBL includes one or a plurality of effect tables Di_xy for realizing a series of image effect operations and image effects defined by the effect tables Di_xy. The effect start timing is specified, and the effect table Di_xy is indicated by table index data INXi.

  Next, the value of the production flag FLG is determined (ST85), and if this is in the set state, the value of the production timer TMR is compared with the production start timing defined in the production progress table Pr_TBL to start production. If the timing has been reached, the effect table Di_xy specified by the table index INXi is stored in the effect table buffer BUF1 (ST86).

  In this embodiment, since the new effect table Di_xy is stored in the effect table buffer BUF1, the old effect table Di_xy ′ that has been stored until then is virtually lost. That is, since the END data exists at the final position of the new effect table Di_xy, it is the same as the data after that has disappeared. However, it is not necessarily limited to such a configuration, an effect table to be stored from the top address of the effect table buffer BUF1, an effect table to be additionally stored in the empty area of the effect table buffer BUF1, For example, the unit effect UT8 for the notice operation (B1) can be separated from the effect table Di_10 for the start variation effect.

  Aside from the above points, FIG. 19A shows an effect table Di_10 acquired at the timing of the effect timer TMR = T0 for this embodiment. As described above, the effect table Di_10 specifies the start variation operation that is the segment effect EN1, and the start variation operation EN1 is configured by eight unit effects UT1 to UT8 (FIG. 16A). )reference). Therefore, information including the production start timing of each of the unit productions UT1 to UT8 is stored in the production table buffer BUF1 based on the storage contents of the production table Di_10 (see FIG. 16A). (See FIG. 17A).

  When the process of step ST86 as described above is completed, next, the presence table unit UTx that has reached the effect start timing is determined based on the value of the effect timer TMR with reference to the data of the effect table buffer BUF1, If the corresponding unit effect UTx exists, the actual frame data is developed in the scene information buffer BUF2 (ST87).

  The scene information buffer BUF2 is a storage area referred to for generating a command list to be output to the VDP 62, and is divided for each drawing channel from the minimum channel CH0 to the maximum channel CHm (FIG. 19B). .

  As described above, in this embodiment, the start timing of the unit effect UTx is defined as the effect header information HDe, and the moving image or still image drawing channel CH that realizes the unit effect is specified as the scene header information HDs. Has been. Therefore, in the process of step ST87, with respect to the unit effect UTx that has reached the start timing, the scene information SN1 to SNi that realizes the unit effect UTx is represented by a scene corresponding to the drawing channel CH defined for each. It is stored in the information buffer BUF2.

  As shown in FIG. 19B, at the timing T0, “scene information relating to the background image A0” is stored in the drawing channel CH0, and “scene information relating to the starting rotation A1 of the left symbol” is stored in the drawing channel CH1. After that, at the timing T0 + α, “scene information relating to the starting rotation A3 of the middle symbol” is stored in the drawing channel CH3, and “scene information relating to the starting rotation A3 of the right symbol” is stored in the drawing channel CH2 at the timing T0 + 2α.

  Note that the left symbol, middle symbol, and right symbol at this time are stop symbols at the end of the previous fluctuation operation, and the host CPU 60 stores each symbol. You can identify videos. Thereafter, at timing T1 + β, “scene information related to the notice effect B1” is stored in the drawing channel CH4.

  In the present embodiment, the drawing channels CH0 to CHm indicate the order in which the command list is generated, and the VDP 62 executes the drawing operation in the order of the command list. The priority increases in the order of right symbol → middle symbol → notice image.

  The subsequent operations are also the same. At timing T1, “scene information relating to the high-speed rotations A41 to A43” is stored in the drawing channels CH1 to CH3, and at the timings T2 and T3, “stop operation A5 and "Scene information relating to the stop operation A6" is stored. Similarly, the contents of the drawing channels CH1 to CH4 are updated. Finally, at the timing T7, “scene information regarding the fluctuations F1 to F3” is stored in the drawing channels CH1 to CH3.

  In this embodiment, many effects are realized with moving images. However, which still image is drawn for a plurality of still images constituting one moving image is managed by the effect counter CT. An effect counter CTi is provided for each drawing channel CHi.

  On the other hand, the “drawing of stop symbols C2 to D2” of the drawing channel CH5 and the “production of shaking fluctuations F1 to F3” of the drawing channels CH1 to CH3 are realized by still images, but are produced by still images (sprites). The operation is managed by continuation timers TM0 to TMm provided for the drawing channels CH0 to CHm and effect counters CT0 to CTm. That is, as shown in FIG. 17, the scene data DATA is composed of a duration and sprite information. When the duration for the predetermined sprite information measured by the duration timer TMi is over, the effect counter CTi is updated. Then, the next sprite information is moved to the effect, and thereafter, when the duration of the last sprite information ends, the effect is finished or the first effect operation is returned (LOOP).

  Note that the scene information SNi that has been produced is deleted based on the values of the continuation timer TMj and the production counter CTj, but is not necessarily required. If new scene information SNj is stored in the scene information buffer BUF2, the scene information SNi is old. The scene information SNi is automatically deleted.

  When the processing in step ST87 having the above contents is completed, a command list is generated based on the contents of the scene information buffer BUF2 at that time (ST88).

  As described with reference to FIG. 13, the command list decodes which sprite's compressed data for a still image (S2), draws the decompressed data at which coordinate position (S2), or which video of which This is an instruction for which coordinate position to draw the decompressed data of the frame number (S14).

  Since all information for generating a command list is stored in the scene information buffer BUF2, the host CPU 60 moves the scene information buffer BUF2 from the lowest drawing channel CH0 to the highest drawing channel CHm. In the case of a still image, a necessary command list is generated based on the values of the effect counter CTi and the continuation timer TMi at that time. On the other hand, in the case of a moving image, the value of the effect counter CTi at that time means the frame number of the moving image. Therefore, a necessary command list is generated based on the value of the effect counter CTi at that time.

  The command list generated in this way is written into the command memory 70 of the VDP 62. As described above, the command list of the drawing channel CH0 is registered at the head of the command memory 70, and each command list is registered in the order of the drawing channel CH1 → the drawing channel CH2 →. The priority level of the command list of channel CH0 is the lowest level.

  Thereafter, the host CPU 60 starts the drawing operation of the VDP 62 by setting the start address of the command list and other control information in the system control register 71 (ST88).

  Since the VDP 62 starts the decoding process by the above processing, the host CPU 60 updates the presentation timer TMR, the continuation timer TM, etc., executes other necessary processing, and then waits for a V Blank interrupt ( ST89).

  As described above, in this embodiment, the host CPU 60 and the VDP 62 cooperate to realize the image effect operation, so that complex and advanced image effects can be executed smoothly. In addition, since it has a special memory configuration, it is possible to smoothly change high-quality images, and even if there is a defect in the memory, the memory can be specified and replaced in units of memory elements. Is also possible.

  As mentioned above, although the Example of this invention was described in detail, the concrete description content does not specifically limit this invention. In other words, the application of the present invention is not limited to the ball game machine, and it is needless to say that the present invention can be suitably applied to a spinning machine (slot machine).

  In the above-described embodiment, the host CPU 60 starts the drawing operation of the VDP 62 by setting the start address of the command list and other control information in the system control register 71. It is preferable that the VDP 62 automatically starts the drawing operation.

  Furthermore, in the above embodiment, the effect control unit 22 ′ and the image control unit 23 ′ are configured by a separate circuit board, and the control command CMD ′ is transmitted in parallel with the strobe signal STB ′. It is also preferable to omit the parallel transmission path (wiring cable) by configuring the unit 22 ′ and the image control unit 23 ′ with an integrated substrate.

  In addition, if the control operations of the one-chip microcomputer 40 and the one-chip microcomputer 60 are executed by a single CPU, it is possible to enhance the rendering operation such as accurately synchronizing various rendering operations. Furthermore, in order to further enrich the image effects, it is also preferable to add a small liquid crystal display device DS 'or to permanently store game results and notify the player as necessary. The liquid crystal display device DS 'is configured to be movable at the time of a notice effect as a kind of movable accessory.

  FIG. 20 shows a circuit configuration that realizes such an advanced operation. The production integrated board 90 and the production interface board 91 use a wiring cable through a male connector and a female connector. It is laminated without doing.

  As shown in the figure, a speech synthesis circuit 42, a sound memory 43, a VDP 62, a CGROM 63, an SDRAM 64, and the like are arranged on the effect integrated substrate 90. The effect control substrate 22 shown in FIG. 4 and the effect control substrate 22 shown in FIG. All the main circuit elements of the image control board 23 are mounted.

  In this embodiment, the lamp effect, the motor effect, the sound effect, and the image effect are controlled by a single one-chip microcomputer 92, which eliminates the need for the transmission path for the control command CMD 'and is described above. Each performance operation can be accurately synchronized.

  When these points are specifically confirmed, the one-chip microcomputer 92 receives a control command CMD from the main control board 21 at its parallel input port Pi, and receives an operation enable signal EN, a holding signal LOAD, etc. from the parallel output port Po ( Various control signals are output.

  Further, the one-chip microcomputer 92 transmits control data (control data) to the LED driver and motor driver control registers R1 to Rm mounted on the lamp driving board 29 and the motor lamp control board 30 through the built-in serial input / output port Si of a plurality of channels. Parameter) and a serial signal indicating the origin position.

  The data bus D_BUS and address bus A_BUS of the one-chip microcomputer 92 are connected to a program ROM 93 that stores a control program for uniformly realizing a lamp effect, a motor effect, a sound effect, and an image effect, and is connected to the VDP 62. Is also connected. Therefore, in this embodiment, the image control shown in FIGS. 13 and 18 is executed by the one-chip microcomputer 92.

  Similarly, the data bus D_BUS and address bus A_BUS of the one-chip microcomputer 92 are also connected to the speech synthesis circuit 42. Here, the voice synthesizing circuit 42 accesses the voice memory 43 based on an instruction (set value by the voice command SND) received from the one-chip microcomputer 92 to the voice control registers RG0 to RGn which are built-in registers. This circuit reproduces and outputs an audio signal. Note that the audio memory 43 stores compressed audio data and SAC data, which are original data of an audio signal to be reproduced.

  In the case of the present embodiment, the compressed audio data stored in the audio memory 43 is phrase compressed data specified by a phrase number (000H to 1FFFH) having a 13-bit length, and is a sequence of background music. (BGM), a group of effect sounds (notice sounds), and the like are stored in a maximum of 8192 types (= 213), each corresponding to a phrase number. The phrase number is specified by the set value of the voice command SND transmitted from the one-chip microcomputer 92 to the voice control registers RG0 to RGn of the voice synthesis circuit 42.

  The voice command SND has a plurality of (2 or 3) bytes and is used for a write application in which a predetermined set value is transmitted to any one of the many voice control registers RG0 to RGn built in the voice synthesis circuit 42. Is done. However, the voice command SND of the present embodiment is used not only for a write application for writing a set value such as a phrase number, but also for a read application for reading status information (error information) STS from a predetermined voice control register RGi. The predetermined audio control register RGi to be accessed is specified by a 1-byte register address.

  By the way, setting (Write) of the set value to the audio control register RGi is not necessarily performed individually for each audio control register, and a group of SAC data stored in the audio memory 43 is designated. A series of setting operations for the voice control registers RGi to RGj can be completed.

  Here, the SAC data is an aggregate of a maximum of 512 pieces (up to 1024 bytes) in which the register address (1 byte) of the voice control register RGi is associated with the set value (multiple bytes) in the voice control register RGi. Means. In the present embodiment, only a necessary set of such SAC data is stored in the audio memory 43 in advance, and a set of SAC data is specified by a SAC number of about 13 bits that is a single ID information. It is like that.

  Therefore, in the case of the present embodiment, the voice command SND for write use specifies a SAC number and specifies a set of SAC data, or specifies a set value and a register address individually.

  Next, FIG. 20B illustrates the connection relationship between the above-described speech synthesis circuit 42 and the one-chip microcomputer 92. As shown in the figure, the one-chip microcomputer 92 and the speech synthesis circuit 42 include parallel signal lines (data buses) CD0 to CD7 that can transmit and receive 1-byte data, and a 2-bit-long operation management data line that can transmit operation management data ( Address buses A0 to A1, 2 bit control signal lines WR and RD capable of controlling read / write operations, and a chip select signal line CS for selecting the speech synthesis circuit 42 are connected.

  The parallel signal lines CD0 to CD7 are realized by the data bus D_BUS of the one-chip microcomputer 92, and the operation management data lines A0 to A1 are realized by the address bus A_BUS of the one-chip microcomputer 92. It is connected. When the CPU executes, for example, an IOREAD operation or an IOWRITE operation by program processing, the control signals WR and RD and the chip select signal CS are appropriately changed, and the audio control register specified by the parallel signal lines CD0 to CD7. Read / write (R / W) operation with RGi is realized.

  Specifically, as shown in FIG. 20B, the register address of the audio control register RGi and the write data to the audio control register RGi are transmitted in parallel through the parallel signal lines CD0 to CD7, respectively. Whether the 1 byte transmitted in parallel is a register address or write data (write data) is specified by the operation management data A0 to A1.

  Therefore, as shown in FIG. 20B, the operation management data (address data A0 to A1) is changed from [00] to [01], while 1-byte data on the data bus is changed to [voice control register RGi. A predetermined voice command SND is transmitted by transiting from “register address” → [write data to voice control register RGi]. When the write data is a plurality of bytes long as in the case of transmitting the SAC number (13 bits), the operation management data A0 to A1 of [01] are changed from [00] → [01] → [01]. → Send the data of multiple bytes while repeating [01].

  The voice command transmitted in this way is subsequently validated as long as there is no communication abnormality. However, if a communication error is recognized, such as data having a plurality of bytes inconsistent with each other, the voice command SND is not activated. Then, an error flag of the voice control register RGn is set. This error flag (status information STS) is set by moving the address bus operation management data A0 to A1 from [01] to [10]. The chip microcomputer 92 can receive data by the READ operation.

  As described above, in this embodiment, error information (abnormality of a plurality of bits) is obtained in the final cycle in which the operation management data A0 to A1 are changed from [00] → [01] →... [01] → [10]. FFH) can be obtained. Then, by retransmitting the voice command SND that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of FIG. 20B, the unnaturalness that the sound effect suddenly stops can be surely eliminated.

  In the configuration of FIG. 20B, the one-chip microcomputer 92 receives the status information STS including error information in parallel from the speech synthesis circuit 42. However, the configuration is not limited to this configuration. . That is, it is also preferable to adopt a configuration in which an interrupt signal is output to the one-chip microcomputer 92 when the voice synthesis circuit 42 recognizes a communication error. In this case, in the interrupt processing program of the one-chip microcomputer 92, a communication error is detected. The generated voice command may be retransmitted. If such a configuration is adopted, an error flag (status information STS) acquisition process that is a useless process in most cases, that is, a process of transitioning the operation management data A0 to A1 to [10] may be omitted. it can.

  Next, FIG.20 (c) shows the applicable part (76,96,97) of FIG.20 (a) in detail about the connection relation between VDP62 and sub display apparatus DS2. As shown in the figure, in this embodiment, the transmission unit 96 disposed on the effect interface board 91 is connected to the DRGB_I / F unit 76 of the VDP 62, and the reception unit 97 is disposed corresponding to the transmission unit 96. Here, the transmission unit 96 and the reception unit 97 are connected by a differential one-pair cable, and the RGB signal, the synchronization signal, and other signals are transmitted to the V-by-One with a single differential line. (Registered trademark) system.

  As shown in FIG. 20 (a), the DRGB_I / F unit 76 of the VDP 62 has an 18-bit digital RGB data (6 bits × 3), a 3-bit control signal SYC such as a horizontal / vertical synchronization signal, and an enable signal. The signal DE is output. Here, the enable signal DE indicates that the digital RGB data is being output when it is at the H level, and indicates that the control signal SYC is being output when the enable signal DE is at the L level. .

  Each of the RGB data is 6 bits long (64 gradations), suppresses the amount of transmission data, stabilizes the operation, and simplifies the device configuration such as the wiring between the VDP 62 and the transmission unit 96. . Since the sub display device DS ′ is in charge of the notice effect and the effect effect, there is no problem even if the gradation level is lowered. By adopting the above configuration, it is possible to enrich other game members. .

  FIG. 20C shows the internal configuration of the transmission unit 96 (for example, THCV 213) and the reception unit 97 (for example, THCV 214), and the connection relationship between the two elements. As shown in the figure, the transmission unit 96 and the reception unit 97 realize transmission of pixel data by only one pair of twisted pair lines (TXOUT +, TXOUT−), and do not transmit a transfer clock. Therefore, the number of cable wires and the number of connector terminals can be reduced, and cost reduction and space saving can be realized. In addition, there is an advantage that high-frequency noise associated with transmission of the transfer clock does not occur.

  In this embodiment, the handshake function is automatically realized by taking the LOCKN output of the receiving unit 97 and the INIT terminal of the transmitting unit 96 as input. That is, in a state where data transmission is not in progress, the LOCKN output becomes L level to notify the transmission unit 96 that a predetermined number of serial data should be transmitted, and in response to this, the transmission unit 96 performs transmission processing. Run.

  The transmission process is realized by serially converting the RGB data and control signal SYC received from the VDP 62, adding an enable signal DE thereto, and serially outputting the twisted pair lines (TXOUT +, TXOUT-). Upon receiving this serial signal, the receiving unit 97 converts the RGB data and the control signal SYC into parallel signals and outputs them together with the enable signal DE to the sub display device DS 'to execute an appropriate image effect.

In this embodiment, it is sufficient to transmit RGB data (8 bits each) of 64 gradations, so that high-speed transmission is not necessary, and stable serial communication can be realized by the above-described handshake operation. Therefore, there is no fear that the character is unnaturally deformed or noise is displayed on the display screen of the sub display device DS2 in the notice effect. In addition, the receiving unit 97 has a clock data recovery (CDR) function, and specifically, by detecting the edge of serial data to be transferred, each serial can be used without using a transfer clock. Since data is acquired accurately, stable serial communication is realized in this sense.

  Incidentally, as shown in FIGS. 20A and 21, in this embodiment, the data bus D_BUS and the address bus A_BUS of the one-chip microcomputer 92 can permanently store the real-time clock RTC and necessary presentation data. A memory element (Static Random Access Memory) 94 is also connected. Here, the real-time clock RTC is a clock IC that measures the current date and time, and operates permanently with the memory element 94 and the secondary battery BT charged with the power supply voltage of the effect interface board 91. ing. That is, the secondary battery BT is charged while the gaming machine is powered on, and after the gaming machine is powered off, the real-time clock RTC is based on the charged secondary battery BT. Timekeeping operation is continued, and production data is also permanently stored (backup operation).

  As shown in FIG. 21, the real-time clock RTC of the embodiment is connected to the CPU of the one-chip microcomputer 92 through the 4-bit data bus A_BUS, the 4-bit data bus D_BUS, and the control bus RD + WR for Read / Write operation. Has been. Then, the CPU stores important game information and abnormality information related to the game operation in the memory element 94 by adding date information, day information and time information acquired from the real-time clock RTC.

  This real-time clock RTC has two types of chip select terminals, CS1 and CS0 bars, and permits access from the CPU on condition that the input voltage to each terminal is at a normal level. Yes. Here, the CS0 bar terminal is a normal chip select terminal that receives the output of the address decoder. On the other hand, the CS1 terminal receives the output (voltage drop signal) Vo of the power supply abnormality detecting unit ER, and when the CS1 terminal receives the abnormal level output Vo, the abnormality detection flag Fos of the real-time clock RTC is automatically set. To be set.

  In the case of the present embodiment, this abnormality detection flag Fos is determined by the CPU of the one-chip microcomputer 92 together with other abnormality detection flags TEMP when the power is turned on. If the abnormality detection flag Fos is set, the year at that time The date and time are notified. Therefore, if an abnormality in the clock function is recognized, it can be dealt with quickly.

  Even if the voltage of the secondary battery BT drops when the power is shut down, the voltage level of the secondary battery BT is quickly recovered by power recovery and the CS1 terminal returns to the normal level, so that access from the CPU is permitted. It will be. Therefore, when the configuration of the present embodiment in which the determination processing of the abnormality detection flag Fos is not adopted, there is a possibility that the abnormality of the real time clock RTC cannot be detected permanently.

  The real-time clock RTC of the embodiment is configured to output the interrupt signal IRQ once a week, for example, every Friday at 21:50. In the CPU that has received the interrupt signal IRQ, The game information and abnormality information stored in the memory element 94 are appropriately tabulated.

  The game information to be aggregated is a summary of history information related to the big hit state. For example, (1) the number of winnings to the symbol start opening required to become the big hit state, (2) the symbol of the big hit state, Total value and statistical value of jackpot state whether or not it is probable, (3) type of notice effect or reach effect that reached the big hit state, (4) number of consecutive chants, (5) number of balls thrown out by consecutive chans Increasing trends are included. And these total information and statistical information are alert | reported suitably according to a player's request | requirement. The player's instruction is specified by, for example, pressing the chance button 11 during the demonstration effect, and the notification content is displayed on the display device DS.

  On the other hand, the abnormal information to be tabulated includes, for example, (1) the number of times the door is opened, (2) the detection type, the number of detection times and the detection time of the detection sensor for detecting illegal activities, This includes the number of detections, detection frequency, detection time, etc. of an act of forcibly opening the winning opening 16 with a wire or the like. The total information is displayed on the display device DS in response to a special operation by an attendant.

  As shown in FIGS. 21B to 21D, the real-time clock RTC of the embodiment has three internal register tables Bank0 to Bank2. Each register table is composed of 4 bytes × 16 registers, and the current date and time measured by the internal circuit are written in the register table of Bank 0 (FIG. 21C). Yes. Note that the Bank2 register table relates to time setting and date setting, and is not shown in FIG.

  As shown in FIG. 21C, in the register table of Bank0, bit 3 of the first register is an abnormality detection flag Fos, and bit 2 of the 14th register indicates that the built-in temperature sensor has detected an abnormal temperature. This is a temperature abnormality flag TEMP shown. In this embodiment, when the CPU of the effect control unit 22 is reset, the value of the abnormality detection flag Fos is determined, thereby preventing the abnormal timekeeping operation from continuing. In addition, the real-time clock RTC is disposed close to the one-chip microcomputer 92, and the temperature abnormality flag TEMP is repeatedly determined at appropriate time intervals to quickly detect the temperature abnormality of the one-chip microcomputer 92.

  In the register table of Bank0, bit 0 of the 15th register is a Busy flag indicating that the register table is being updated. In this embodiment, the current date and time are acquired from the register table of Bank 0 on the condition that the Busy flag is in a non-Busy state (update completion). Therefore, in this embodiment, there is no possibility of acquiring halfway during the update operation or irrational clock information, and the validity of the clock information stored in the memory element 94 is ensured. For example, if clock information that is being updated from 1:59:59 to 2: 00: 00: 00 is acquired, there is a possibility that the clock information of 1: 0: 0 is acquired.

  Further, the register table of Bank 1 is configured so that the generation time of the interrupt signal IRQ can be set. Therefore, in this embodiment, an interrupt generation is instructed by setting 1 to bit 0 of the register No. 1 of Bank 1 (Interrupt Enable), and the day of the week of Friday is designated in the registers 0 to 8 of Bank 1. Time information of 30:30 hours is set.

GM gaming machine 92 computer element 90 effect control means 91 effect control means 93 memory element RTC real time clock 94 memory element

Claims (1)

A main control means for executing a lottery process caused by a predetermined switch signal and outputting a control command for specifying a lottery result by the lottery process, and a series of image effects corresponding to the lottery result specified by the control command, An effect control means that executes using a display device, and a gaming machine configured to have,
The effect control means is composed of a single computer element that controls a sound effect and / or a lamp effect synchronized with an image effect,
The data bus and address bus of the computer element are:
Connected to a memory element that stores a control program that controls the sound effect and / or lamp effect synchronized with the image effect, and can store the required effect data in a non-volatile manner, as well as a real-time clock capable of grasping the necessary timing information Connected to a memory device ,
Provided with an abnormality detection unit that is charged when the power is turned on and that can detect an abnormal drop in the power supply voltage of the secondary power supply that drives the real-time clock after the power is turned off.
2. The gaming machine according to claim 1, wherein the real-time clock is configured such that access from the computer element is permitted on condition that the abnormality detection unit has not detected an abnormal drop in power supply voltage .