JP5941394B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present specification relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device used in a motor.

  Patent Document 1 discloses a piezo motor that starts, stops, and intermittently operates with a short pulse for noise reduction in FIGS. 1 and 2 and related portions thereof. 3 and 4 and related portions disclose a piezo motor that starts, stops, and intermittently operates by PDM (pulse density modulation) for noise reduction.

  In this Patent Document 1, since the magnitude of the voltage amplitude supplied to the gates of the MOSFETs Q1 to Q4 for driving the piezomotor is large even in the short pulse control and the PDM control, the MOSFETs Q1 to Q4 The piezo element receives a potential difference between the power supply of the H bridge circuit configured by the above and GND (ground). Therefore, since the piezo element (piezoelectric element) is activated, stopped, and intermittently controlled in response to a large potential difference, it cannot be sufficiently silenced.

JP 2011-182577 A

A piezo motor driven by applying a voltage to a piezo element has a movement amount proportional to the amount of voltage change applied to the piezo element per unit time. When the gate voltage of a driving transistor such as an H-bridge driven by the power supply voltage VM and the ground voltage GND is controlled using a PWM (pulse width modulation) control method that can be easily controlled, the transistor is completely Turns on. Under such conditions, when the stopped piezo motor is started by the PWM control method, the driving transistor such as the H bridge is completely turned on, so that the piezo element is connected between the power supply voltage VM and the ground voltage GND. The potential difference is applied, and a large voltage change is applied, which causes a sudden operation and noise.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  The PWM wave for driving the piezo motor is such that a signal having an amplitude smaller than the potential difference between the power supply voltage of the output stage and the ground voltage is output from the drain of the MOS transistor of the output stage during start-up or stop control. The second pulse width is larger than the first pulse width so that a signal having an amplitude between the power supply voltage and the ground voltage is output from the drain of the MOS transistor in the output stage during normal driving. It is said.

  According to the present invention, since the PWM wave at the time of starting or stopping control has the first pulse width, a signal having an amplitude smaller than the potential difference between the power supply voltage and the ground voltage is output from the MOS transistor in the output stage. Therefore, since a large voltage change due to a large potential difference is not given to the piezo element, the operation can be started gradually and noise can be prevented.

1 is an overall view of a semiconductor integrated circuit device according to a first embodiment. 1 is a configuration diagram of a motor driver according to a first embodiment. 2 shows a configuration and operation waveform diagram of a PWM wave generation circuit. It is a figure showing the structure of a table and the data stored in this table. It is a figure showing the time change of a pulse width setting value. It is a figure showing the drive waveform of the motor driver when the pulse width setting value is generated by the period set in the table and the individual pulse width value. It is a figure showing the drive waveform of a motor driver from the time of starting to the time of stop control through normal driving. FIG. 8 is a waveform diagram corresponding to full amplitude driving in FIG. 7. FIG. 2 shows various configuration diagrams of a pre-driver.

Hereinafter, embodiments will be described in detail with reference to the drawings.
In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation, timing chart, element step, operation step, etc.) are specifically indicated unless otherwise specified and considered to be clearly essential in principle. Not necessarily essential. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Note that portions or members having the same function are denoted by the same or related reference numerals throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
FIG. 1 is an overall view of the semiconductor integrated circuit device according to the first embodiment.

  The semiconductor integrated circuit device IC includes a central processing unit CPU, a random access memory RAM, a nonvolatile memory FLASH, an AD conversion circuit ADC, an input / output circuit I / O, an oscillation circuit OSC, a bus BUS, and a motor driver MTD. And have.

  The central processing unit CPU controls the entire semiconductor integrated circuit device IC according to a program. The random access memory RAM is used as a work area for the central processing unit CPU, and is a storage area for storing various data, instructions, and the like. In the nonvolatile memory FLASH, stored data can be rewritten, and various programs used in the central processing unit CPU are stored. The input / output circuit I / O is a circuit that performs input / output control of various ports. The AD conversion circuit ADC is a circuit that converts an analog signal into a digital signal. The motor driver MTD is a circuit for driving various motors. The bus BUS exchanges various data, commands, and addresses with the central processing unit CPU, random access memory RAM, nonvolatile memory FLASH, input / output circuit I / O, motor driver MTD, and oscillation circuit OSC. A plurality of signal lines. The oscillation circuit OSC receives various clock signals used in the central processing unit CPU, random access memory RAM, nonvolatile memory FLASH, input / output circuit I / O, motor driver MTD, and oscillation circuit OSC based on an external clock signal. Generate.

  FIG. 2 is a configuration diagram of the motor driver according to the first embodiment.

  The motor driver MTD includes a driver DR, a PWM wave generation circuit PWM-GC, a sequencer SQC, and a table TBL.

  The sequencer SQC generates the pulse width setting signal PWS1 and the pulse width setting signal PWS2 based on the command value IV for determining the number of PWM wave drive pulses from the central processing unit CPU and the data DATA stored in the table TBL. The pulse width setting signal PWS1 and the pulse width setting signal PWS2 are output to the PWM wave generation circuit PWM-GC. The PWM wave generation circuit PWM-GC generates the PWM wave PWM1 and the PWM wave PWM2 based on the pulse width setting signal PWS1, the pulse width setting signal PWS2, and the clock CLK of the cycle CT from the oscillation circuit OSC. The driver DR includes a PMOS transistor (P-channel MOS field effect transistor) PMOS1, an NMOS transistor (N-channel MOS field effect transistor) NMOS1, a PMOS transistor PMOS2, an NMOS transistor NMOS2, a predriver PreDRV1, and a predriver PreDRV2. , Pre-driver PreDRV3 and pre-driver PreDRV4. The PMOS transistor PMOS1, the NMOS transistor NMOS1, the PMOS transistor PMOS2, and the NMOS transistor NMOS2 constitute an H bridge as an output stage. The power supply voltage VM is supplied to the source of the PMOS transistor PMOS1, the drain of the PMOS transistor PMOS1 is connected to the drain of the NMOS transistor NMOS1, and the ground voltage GND lower than the power supply voltage VM is supplied to the source of the NMOS transistor NMOS1. A pre-driver PreDRV3 is connected to the gate of the transistor PMOS1, and a pre-driver PreDRV4 is connected to the gate of the NMOS transistor NMOS1. A PWM wave PWM1 is supplied to the pre-driver PreDRV3 and the pre-driver PreDRV4, and an output based on the PWM wave PWM1 is output from the pre-driver PreDRV4 to the NMOS transistor NMOS1, and is output from the pre-driver PreDRV3 to the PMOS transistor PMOS1. The power supply voltage VM is supplied to the source of the PMOS transistor PMOS2, the drain of the PMOS transistor PMOS2 is connected to the drain of the NMOS transistor NMOS2, the ground voltage GND lower than the power supply voltage VM is supplied to the source of the NMOS transistor NMOS2, and the PMOS transistor The pre-driver PreDRV1 is connected to the PMOS2 gate, and the pre-driver PreDRV2 is connected to the gate of the NMOS transistor NMOS2. The PWM wave PWM2 is supplied to the pre-driver PreDRV1 and the pre-driver PreDRV2, and an output based on the PWM wave PWM2 is output from the pre-driver PreDRV2 to the NMOS transistor NMOS2, and is output from the pre-driver PreDRV1 to the PMOS transistor PMOS2. Therefore, the PMOS transistor PMOS1 and the NMOS transistor NMOS1 are driven by the PWM wave PWM1, and the PMOS transistor PMOS2 and the NMOS transistor NMOS2 are driven by the PWM wave PWM2.

  A piezo motor PZ having a piezo element is provided so that the drain of the PMOS transistor PMOS1 is connected to the terminal PZT1, and the drain of the PMOS transistor PMOS2 is connected to the terminal PZT2.

  FIG. 3 shows a configuration and operation waveform diagram of the PWM wave generation circuit PWM-GC.

  FIG. 3A shows the configuration of the PWM wave generation circuit PWM-GC.

  The PWM wave generation circuit PWM-GC has a counter CNT and a comparator CMP.

  FIG. 3B shows an operation waveform diagram of the PWM wave generation circuit PWM-GC.

  The sequencer SQC outputs a pulse width setting signal PWS1 and a pulse width setting signal PWS2. The pulse width setting signal PWS1 includes an instruction signal IS11 and an instruction signal IS12, and the pulse width setting signal PWS2 includes an instruction signal IS21 and an instruction signal IS22. The instruction signal IS22 and the instruction signal IS12 are fixed values, and the instruction signal IS21 and the instruction signal IS11 are variable according to the control of the sequencer SQC based on the instruction value IV and the data DATA stored in the table TBL. The counter CNT counts up the counter value CNT-V at every rising or falling edge of the clock CLK. The counter value CNT-V is counted up from the value 0 to the value XM, and is reset to the value 0 when it reaches the value XM. A period until the counter value CNT-V changes from the value 0 to the value XM is a PWM cycle PWM-T that is a cycle of the PWM wave PWM1 and the PWM wave PWM2. The PWM wave PWM1 is set to the high level when the instruction signal IS11> the counter value CNT-V> the instruction signal IS12. PWM cycle PWM-T = value XM × cycle CT. The PWM wave PWM2 is set to the high level when the instruction signal IS21> the counter value CNT-V> the instruction signal IS22. The difference between the instruction signal IS21 and the instruction signal IS22 and the difference between the instruction signal IS11 and the instruction signal IS12 are the pulse width setting value Xp. Therefore, the pulse width setting value Xp is proportional to the period during which the PWM wave PWM1 or PWM wave PWM2 is at a high level, and the pulse width setting value Xp is proportional to the duty of the PWM wave PWM1 or PWM wave PWM2. Since the instruction signal IS22 and the instruction signal IS12 are fixed values, the PWM period PWM-T of the PWM wave PWM1 and the PWM wave PWM2 becomes constant.

  FIG. 4 is a diagram showing a table configuration and data stored in the table.

  FIG. 4A shows a table structure and data stored in the table.

  The table TBL stores periods T0 to Tk and individual pulse width values X0 to Xk. The individual pulse width value during the period T0 is X0, and the individual pulse width value during the period T1 is X1. The same applies to the following, and the individual pulse width value during the period Tk is Xk. Here, k is a natural number. The period T0 is a period immediately after the time TCS when the correction value IV is output, and the period T1 is a period after the period T0. Similarly, the period Tk is a period after the period Tk-1. Each of the periods T0 to Tk is LK times the PWM cycle PWM-T that is the cycle of the PWM wave PWM1. Here, LK is a natural number. The individual pulse width values X0 to Xk are the pulse width setting values Xp in the corresponding periods T0 to Tk, respectively. The individual pulse width values X0 to Xk are each a multiple of D. Here, a multiple does not necessarily mean an integer, but also includes a fraction and a decimal. D is a value of a pulse width setting value that allows the H-bridge to perform full amplitude operation. The full amplitude operation of the H bridge is an operation in which a potential difference between the power supply voltage VM and the ground voltage GND is applied between the terminal PZT1 and the terminal PZT2. The value D, the periods T0 to Tk, and the individual pulse width values X0 to Xk can be set from the outside of the semiconductor integrated circuit device IC through the input / output circuit I / O.

  Since each of the periods T0 to Tk is LK times the PWM period PWM-T, which is the period of the PWM wave PWM1, as a result, the table TBL has a pulse width which is determined by the number of times defined by the command value IV. Determines whether to use individual values.

  FIG. 4B shows an example of data set in the table.

  2 × PWM cycle PWM-T is set as the period T0, D / 5 is set as the pulse width individual value X0, 2 × PWM cycle PWM-T is set as the period T1, and 2D / 5 is set as the pulse width individual value X1. Is set, 2 × PWM cycle PWM-T is set as the period T2, 3D / 5 is set as the pulse width individual value X2, 2 × PWM cycle PWM-T is set as the period T3, and the individual pulse width value X3 4D / 5 is set, 2 × PWM cycle PWM-T is set as the period T4, and D is set as the pulse width individual value X4.

  When the command value IV is 40, the pulse width setting value Xp is as follows. Since the command value IV is 40, the total of the periods T0 to T4 set in the table TBL for the PWM wave PWM1 and the PWM wave PWM2 is 10 × PWM cycle PWM-T. The individual pulse width value becomes the pulse width setting value Xp. The first and second pulses follow the period T0 and the individual pulse width value X0, and the pulse width setting value Xp is D / 5. The third and fourth pulses follow the period T1 and the individual pulse width value X1, and the pulse width setting value Xp is 2D / 5. The fifth and sixth pulses follow the period T2 and the individual pulse width value X2, and the pulse width setting value Xp is 3D / 5. The seventh and eighth pulses follow the period T3 and the individual pulse width value X3, and the pulse width setting value Xp is 4D / 5. The ninth and tenth pulses follow the period T4 and the individual pulse width value X4, and become D as the pulse width setting value Xp. The subsequent pulses of the PWM wave PWM1 and PWM wave PWM2 from the 11th to the 30th become D as the pulse width setting value Xp. The remaining 10 pulses are also pulses according to the table TBL, and are used sequentially from those corresponding to the period T4 which is a pulse in the subsequent period. The 31st and 32nd pulses follow the period T4 and the individual pulse width value X4, and become D as the pulse width setting value Xp. The 33rd and 34th pulses follow the period T3 and the individual pulse width value X3, and the pulse width setting value Xp is 4D / 5. The 35th and 36th pulses follow the period T2 and the individual pulse width value X2, and the pulse width setting value Xp is 3D / 5. The 37th and 38th pulses follow the period T1 and the individual pulse width value X1, and the pulse width setting value Xp is 2D / 5. The 39th and 40th pulses follow the period T0 and the individual pulse width value X0, and the pulse width setting value Xp is D / 5. Of the command value IV, the initial number and end number corresponding to the total period of the periods T0 to Tk divided by the PWM cycle use the individual pulse width values corresponding to the table TBL as the pulse width setting value Xp. For other intermediate times, D is used as the pulse width setting value Xp. As described above, when the table setting value as shown in FIG. 4B and the command value IV is 40, the 1st to 10th and 31st to 40th pulses are the periods T0 to T4 and the individual pulse width values X0 to X4. The other 11th to 30th pulses use D as the pulse width setting value Xp. The command value IV can be a negative value. When the command value IV is negative, D becomes a negative value, and accordingly, the pulse width setting value Xp also becomes negative. When D is negative, the PWM wave PWM1 is supplied to the pre-driver PreDRV1 and the pre-driver PreDRV2, and the PWM wave PWM2 is supplied to the pre-driver PreDRV3 and the pre-driver PreDRV4. When D is negative, the instruction signal IS21 is obtained by adding the instruction signal IS22 to the absolute value of the pulse width setting value Xp, and the instruction signal IS11 is obtained by adding the instruction signal IS12 to the absolute value of the + pulse width setting value Xp. Become. Otherwise, it is the same as when the command value IV is positive.

  FIG. 4C shows the relationship between the time when the data shown in FIG. 4B is set and the individual pulse width values.

  The vertical axis represents the individual pulse width values X0 to Xk, and the horizontal axis represents time. The origin of the horizontal axis is time TCS. When D is a positive value, the individual pulse width values X0 to Xk change so as to gradually increase from the period T0 to the period T4.

  FIG. 5 is a diagram showing the time change of the pulse width setting value.

  Since the command value IV is not output in the period TA, the pulse width setting value Xp is 0. Therefore, the output stage of the H bridge is not driven as shown in (1) when stopped. The piezo motor PZ is also stopped.

  The time TCS is reached at the beginning of the period TB. At this time, the command value IV1 is output from the central processing unit CPU. The pulse width setting value Xp is changed so as to increase in the form according to the setting value of the data DATA of the table TBL as in the pulse width changing part Xp-V1. This pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described with reference to FIG. At this time, as indicated by the arrow in (2), the voltage output is applied to the output stage of the H-bridge every PWM cycle PWM-T in the direction in which the current flows from the PMOS transistor PMOS1 to the NMOS transistor NMOS2, and from the PMOS transistor PMOS2 to the NMOS transistor. A voltage is applied in the direction in which the NMOS 1 is energized. The applied voltage is smaller than the potential difference between the power supply voltage VM and the ground voltage GND, which is the potential difference between the power supply voltages of the H bridge. This is because the pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described in FIG. 4, and the pulse widths of the PWM wave PWM1 and the PWM wave PWM2 are narrow. Therefore, the output stage transistor is not sufficiently turned on, and the potential difference between the power supply voltage VM and the ground voltage GND is not applied to the terminals PZT1 and PZT2. In this way, the piezo motor PZ gradually moves at a higher speed.

  After the pulse width changing portion Xp-V1, the driving is performed in such a manner that the pulse width Xp becomes D. Here, during normal driving, the output stage of the H bridge applies a voltage in the direction in which the PMOS transistor PMOS1 energizes the NMOS transistor NMOS2 every PWM cycle PWM-T, as indicated by the arrow in (3). A voltage is applied in the direction in which the transistor PMOS2 energizes the NMOS transistor NMOS1. The normal driving time is when the piezo motor PZ moves at a constant speed, and the moving speed at this time is faster than that at the time of starting or stopping control. The applied voltage is the same as the potential difference between the power supply voltage VM and the ground voltage GND, which is the potential difference between the power supply voltages of the H bridge. This is because the pulse width setting value Xp is D and the pulse widths of the PWM wave PWM1 and PWM wave PWM2 are wide, so that the transistors in the output stage can be sufficiently turned on, and the power supply voltage VM is applied to the terminals PZT1 and PZT2. This is because a potential difference between the ground voltage GND and the ground voltage GND is applied.

  After the portion indicated by the arrow in (3), a pulse width changing portion Xp-V2 at the time of stop control is obtained. At this time, the pulse width setting value Xp is changed so as to decrease in accordance with the setting value of the data DATA of the table TBL. This pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described with reference to FIG. At this time, as indicated by the arrow in (2), a voltage is applied to the output stage of the H-bridge every PWM cycle PWM-T in the direction in which the current flows from the PMOS transistor PMOS1 to the NMOS transistor NMOS2, and from the PMOS transistor PMOS2 to the NMOS transistor. A voltage is applied in a direction in which the NMOS 1 is energized. The period TB is obtained by multiplying the PWM cycle PWM-T by the command value IV1. In this way, the piezo motor PZ gradually stops at a reduced speed.

  After the period TB, the drive period of the number of pulses based on the command value IV1 has ended, so the pulse width setting value Xp is 0 in the period TC. Therefore, the output stage of the H bridge is not driven as shown in (1) when stopped. The piezo motor PZ is also stopped.

  Time TCS is reached again at the beginning of period TD. At this time, a command value IV2 which is a negative value is output from the central processing unit CPU. First, the pulse width setting value Xp is changed so as to decrease in the form according to the setting value of the data DATA of the table TBL as in the pulse width changing part Xp-V3 of (4). This pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described with reference to FIG. At this time, as indicated by the arrow in (4), the output voltage of the H bridge is applied to the NMOS transistor NMOS1 from the PMOS transistor PMOS2 to the NMOS transistor NMOS1 every PWM cycle PWM-T. A voltage is applied in the direction in which the NMOS 2 is energized. The order of application is opposite to that in (2) and (3), and opposite to when the moving direction of the piezo motor PZ is driven based on the command value IV1. This is because when driven based on the command value IV1, the PWM wave PWM1 is supplied to the pre-driver PreDRV3 and the pre-driver PreDRV4, and the PWM wave PWM2 is supplied to the pre-driver PreDRV1 and the pre-driver PreDRV2, whereas D is This is because the PWM wave PWM1 is supplied to the pre-driver PreDRV1 and the pre-driver PreDRV2, and the PWM wave PWM2 is supplied to the pre-driver PreDRV3 and the pre-driver PreDRV4 when driven based on the command value IV2 because it is negative. The applied voltage is smaller than the potential difference between the power supply voltage VM and the ground voltage GND, which is the potential difference between the power supply voltages of the H bridge. This is such that the pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described in FIG. 4, and the pulse widths of the PWM wave PWM1 and the PWM wave PWM2 are narrow. Therefore, the output stage transistor is not sufficiently turned on, and the potential difference between the power supply voltage VM and the ground voltage GND is not applied to the terminals PZT1 and PZT2.

  After the pulse width changing portion Xp-V3, the pulse width Xp is driven in the form of D. Here, during normal driving, the output stage of the H bridge applies a voltage in the direction in which the PMOS transistor PMOS2 energizes the NMOS transistor NMOS1 every PWM cycle PWM-T, as indicated by the arrow in (5). A voltage is applied in the direction in which the transistor PMOS1 energizes the NMOS transistor NMOS2. The applied voltage is the same as the potential difference between the power supply voltage VM and the ground voltage GND, which is the potential difference between the power supply voltages of the H bridge. This is because the pulse width setting value Xp is D and the pulse widths of the PWM wave PWM1 and PWM wave PWM2 are wide, so that the transistors in the output stage can be sufficiently turned on, and the power supply voltage VM is applied to the terminals PZT1 and PZT2. This is because a potential difference between the ground voltage GND and the ground voltage GND is applied.

  After the portion indicated by the arrow in (5), a pulse width changing portion Xp-V4 is obtained. At this time, the pulse width setting value Xp is changed so as to increase in accordance with the setting value of the data DATA of the table TBL. This pulse width setting value Xp is determined by the relationship between the periods T0 to Tk and the individual pulse width values X0 to Xk as described with reference to FIG. At this time, as indicated by the arrow in (4), the output voltage of the H bridge is applied to the NMOS transistor NMOS1 from the PMOS transistor PMOS2 to the NMOS transistor NMOS1 every PWM cycle PWM-T. A voltage is applied in the direction in which the NMOS 2 is energized. The period TD is obtained by multiplying the PWM cycle PWM-T by the absolute value of the command value IV2.

FIG. 6 is a diagram showing a driving waveform of the motor driver when the pulse width setting value is generated by the period set in the table and the individual pulse width value.
When the command value IV is output from the central processing unit CPU, first, the motor driver MTD is driven according to the data DATA set in the table TBL. In the PWM wave PWM1 and the PWM wave PWM2, a narrow pulse is output in accordance with the period T0, the pulse width individual value X0, and the period T1, the pulse width individual value X1. According to the two pulses of the PWM wave PWM1 in the period T0, the gate voltages of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 slightly decrease from the power supply voltage VM toward the ground voltage GND. Similarly, according to the two pulses of the PWM wave PWM2 in the period T0, the gate voltages of the PMOS transistor PMOS2 and the NMOS transistor NMOS2 slightly decrease from the power supply voltage VM toward the ground voltage GND. By controlling the gate voltage in this way, a voltage is applied in the direction in which the PMOS transistor PMOS1 is supplied to the NMOS transistor NMOS2, and a voltage is applied in the direction in which the PMOS transistor PMOS2 is supplied to the NMOS transistor NMOS1. The voltage change in this application is smaller than the potential difference between the power supply voltage VM and the ground voltage GND.

  Next, according to the two pulses of the PWM wave PWM1 in the period T1, the gate voltages of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 are slightly lowered from the power supply voltage VM toward the ground voltage GND. The fall width of the gate voltage becomes larger because the pulse width of the PWM wave PWM1 is larger than that in the period T0. Similarly, according to the two pulses of the PWM wave PWM2 in the period T1, the gate voltages of the PMOS transistor PMOS2 and the NMOS transistor NMOS2 slightly decrease from the power supply voltage VM toward the ground voltage GND. The decrease width of the gate voltage becomes larger because the pulse width of the PWM wave PWM2 is larger than that in the period T0. By controlling the gate voltage in this way, a voltage is applied in the direction in which the PMOS transistor PMOS1 is supplied to the NMOS transistor NMOS2, and a voltage is applied in the direction in which the PMOS transistor PMOS2 is supplied to the NMOS transistor NMOS1. The voltage change in this application is smaller than the potential difference between the power supply voltage VM and the ground voltage GND, but is larger than in the period T0.

  Thus, basically, when the pulse width setting value Xp is generated by the periods T0 to Tk and the individual pulse width values X0 to Xk set in the table TBL, the pulse widths of the PWM wave PWM1 and the PWM wave PWM2 are The narrower the width, the lower the gate voltage drop of the H-bridge transistor, and the wider the PWM wave PWM1 and PWM wave PWM2 pulse widths, the larger the gate voltage drop of the H-bridge transistor. Accordingly, a voltage is applied in a direction in which the PMOS transistor PMOS1 is supplied to the NMOS transistor NMOS2, and a voltage change when the voltage is applied in a direction in which the PMOS transistor PMOS2 is supplied to the NMOS transistor NMOS1 changes the power supply voltage VM and the ground voltage GND. The potential difference is smaller than the voltage difference between them, and is proportional to the decrease in the gate voltage of the H-bridge transistor. However, this is not the case when the individual pulse width values X0 to Xk are D or more.

  FIG. 7 is a diagram showing the drive waveform of the motor driver from the time of startup to the time of stop control through normal driving.

When the command value IV is output from the central processing unit CPU, first, the motor driver MTD is driven according to the data DATA set in the table TBL. In the PWM wave PWM1 and the PWM wave PWM2, a narrow pulse is output in accordance with the period T0, the pulse width individual value X0, and the period T1, the pulse width individual value X1. This case is the same as that described in FIG.
Next, in the period T2, the gate voltages of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 slightly decrease from the power supply voltage VM toward the ground voltage GND. The decrease width of the gate voltage is larger than that in the period T1. This is because the pulse width of the PWM wave PWM1 in the period T2 is larger than the pulse width of the PWM wave PWM1 in the period T1. Similarly, in the period T2, the gate voltages of the PMOS transistor PMOS2 and the NMOS transistor NMOS2 slightly decrease from the power supply voltage VM toward the ground voltage GND. The decrease width of the gate voltage is larger than that in the period T1. This is because the pulse width of the PWM wave PWM2 in the period T2 is larger than the pulse width of the PWM wave PWM2 in the period T1. By controlling the gate voltage in this way, a voltage is applied in the direction in which the PMOS transistor PMOS1 is supplied to the NMOS transistor NMOS2, and a voltage is applied in the direction in which the PMOS transistor PMOS2 is supplied to the NMOS transistor NMOS1. The voltage change in this application is smaller than the potential difference between the power supply voltage VM and the ground voltage GND, but is larger than in the period T1.

Next, in the period T3, the gate voltages of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 slightly decrease from the power supply voltage VM toward the ground voltage GND. The decrease width of the gate voltage is larger than that in the period T2. This is because the pulse width of the PWM wave PWM1 in the period T3 is larger than the pulse width of the PWM wave PWM1 in the period T2. Similarly, in the period T3, the gate voltages of the PMOS transistor PMOS2 and the NMOS transistor NMOS2 slightly decrease from the power supply voltage VM toward the ground voltage GND. The decrease width of the gate voltage is larger than that in the period T2. This is because the pulse width of the PWM wave PWM2 in the period T3 is larger than the pulse width of the PWM wave PWM2 in the period T2. By controlling the gate voltage in this way, a voltage is applied in the direction in which the PMOS transistor PMOS1 is supplied to the NMOS transistor NMOS2, and a voltage is applied in the direction in which the PMOS transistor PMOS2 is supplied to the NMOS transistor NMOS1. The voltage change in this application is smaller than the potential difference between the power supply voltage VM and the ground voltage GND, but is larger than in the period T2.
Thereafter, the gate voltage of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 is lowered from the power supply voltage VM to the ground voltage GND, and the gate voltage of the PMOS transistor PMOS2 and NMOS transistor NMOS2 is lowered from the power supply voltage VM to the ground voltage GND. As a result, a voltage is applied in the direction in which the PMOS transistor PMOS1 energizes the NMOS transistor NMOS2, and a voltage is applied in the direction in which the PMOS transistor PMOS2 energizes the NMOS transistor NMOS1. The voltage change in this application is a potential difference between the power supply voltage VM and the ground voltage GND. In this specification, full-amplitude driving expresses that the H bridge transistor is applied with a drive that changes from the power supply voltage VM, which is the power supply potential difference of the H bridge, to the ground voltage GND and is applied to the energization. ing. The waveform of this full amplitude drive will be described later.

  After full-amplitude driving, control in the period T3 is executed, control in the period T2 is executed next, control in the period T1 is executed next, and control in the period T0 is executed next. Control during these periods is as described above in the description of FIG.

  FIG. 8 is a waveform diagram corresponding to the full amplitude drive in FIG.

  Actually, there are far more pulses, but in the figure, the gate voltage of the PMOS transistor PMOS1 and the NMOS transistor NMOS1 is lowered from the power supply voltage VM to the ground voltage GND four times in accordance with the four PWM waves PWM1. A voltage is applied in a direction in which the PMOS 1 and the NMOS transistor NMOS2 are energized. This applied voltage is a potential difference between the power supply voltage VM and the ground voltage GND. Similarly, the voltage is applied in the direction of energization from the PMOS transistor PMOS2 to the NMOS transistor NMOS1 by reducing the gate voltage of the PMOS transistor PMOS2 and NMOS transistor NMOS2 from the power supply voltage VM to the ground voltage GND four times in accordance with the four PWM waves PWM2. The This applied voltage is a potential difference between the power supply voltage VM and the ground voltage GND.

  FIG. 9 shows various configuration diagrams of the pre-driver.

  FIG. 9C shows the parasitic capacitance of the power MOS transistor that receives the output of the pre-driver.

  The power MOS transistor PW-MOS is any one of a PMOS transistor PMOS1, an NMOS transistor NMOS1, a PMOS transistor PMOS2, and an NMOS transistor NMOS2 constituting an H bridge. A parasitic capacitance Cgs exists between the gate G and the source S of the power MOS transistor PW-MOS, and a parasitic capacitance Cgd exists between the gate G and the drain D of the power MOS transistor PW-MOS. The power MOS transistor PW-MOS has a large gate area, and these parasitic capacitances cannot be ignored in driving.

  FIG. 9A shows an example of the pre-drivers PreDRV1 to PreDRV4.

  The pre-driver PreDRV-A has an input terminal IN, an output terminal OUT, a PMOS transistor PMOS3, an NMOS transistor NMOS3, and a resistor R. The input terminal IN is connected to the gates of the PMOS transistor PMOS3 and the NMOS transistor NMOS3, the source of the PMOS transistor PMOS3 is supplied with the power supply voltage VM, the drain of the PMOS transistor PMOS3 is connected to one terminal of the resistor R, and the NMOS transistor NMOS3 The drain is connected to one terminal of the resistor R, the source of the NMOS transistor NMOS3 is supplied with the ground voltage GND, and the output terminal OUT is connected to the other terminal of the resistor.

  A filter having a certain time constant is constituted by the parasitic capacitance and the resistance R described above. Therefore, even if the input terminal IN changes from the high level to the low level, the gate G of the power MOS transistor PW-MOS connected to the output terminal OUT does not immediately switch from the low level to the high level. Similarly, even when the input terminal IN changes from the low level to the high level, the gate G of the power MOS transistor PW-MOS connected to the output terminal OUT does not immediately switch from the high level to the low level. When the motor driver MTD is driven with a pulse width individual value such that the pulse width of the PWM wave PWM1 or PWM wave PWM2 is short, as described with reference to FIGS. Therefore, before the gate G of the power MOS transistor PW-MOS changes from the power supply voltage VM to the ground voltage GND due to the change of the PWM wave PWM1 or PWM wave PWM2 from the low level to the high level, the PWM wave PWM1 or PWM wave. When the PWM2 returns from the high level to the low level, the gate G of the power MOS transistor PW-MOS returns from the intermediate voltage between the power supply voltage VM and the ground voltage GND to the power supply voltage VM. On the contrary, when the motor driver MTD is driven by D having a long width of the PWM wave PWM1 or PWM wave PWM2, the power MOS is generated by changing the PWM wave PWM1 or PWM wave PWM2 from the low level to the high level. The gate G of the transistor PW-MOS changes from the power supply voltage VM to the ground voltage GND. Next, when the PWM wave PWM1 and the PWM wave PWM2 return from the high level to the low level, the gate G of the power MOS transistor PW-MOS returns from the ground voltage GND to the power supply voltage VM.

  FIG. 9B is an example of the pre-drivers PreDRV1 to PreDRV4.

The pre-driver PreDRV-B is different from the pre-driver PreDRV-A in the following.
There is no resistor R, and the output terminal OUT is connected to the drain of the PMOS transistor PMOS3. There is a current source IS-P between the source of the PMOS transistor PMOS3 and the supply terminal of the power supply voltage VM. There is a current source IS-N between the source of the NMOS transistor NMOS3 and the supply terminal of the ground voltage GND.
The current source IS-P passes a constant current i from the supply terminal of the power supply voltage VM toward the source of the PMOS transistor PMOS3. The constant current i flowing toward the source of the PMOS transistor PMOS3 flows until the drain potential of the PMOS transistor PMOS3 becomes the power supply voltage VM when the PMOS transistor PMSO3 is turned on. The current source IS-N flows a constant current i from the source of the NMOS transistor NMOS3 toward the supply terminal of the ground voltage GND. The constant current i flowing from the source of the NMOS transistor NMOS3 flows until the drain potential of the NMOS transistor NMOS3 becomes the ground voltage GND when the NMOS transistor NMSO3 is turned on.

  The gate voltage of the power MOS transistor PW-MOS is determined depending on the time during which the constant current i flows in and out of the parasitic capacitance. Therefore, even if the input terminal IN changes from the high level to the low level, the gate G of the power MOS transistor PW-MOS connected to the output terminal OUT does not immediately switch from the low level to the high level. Similarly, even when the input terminal IN changes from the low level to the high level, the gate G of the power MOS transistor PW-MOS connected to the output terminal OUT does not immediately switch from the high level to the low level. When the motor driver MTD is driven with a pulse width individual value such that the pulse width of the PWM wave PWM1 or PWM wave PWM2 is short, as described in FIGS. 6 and 7, the PWM wave PWM1 or PWM wave PWM2 Is changed from the low level to the high level, before the gate G of the power MOS transistor PW-MOS changes from the power supply voltage VM to the ground voltage GND, the charge extraction from the parasitic capacitance due to the constant current i of the current source IS-N is stopped. When the PWM wave PWM1 and the PWM wave PWM2 return from the high level to the low level, charge supply to the parasitic capacitance due to the constant current i of the current source IS-P starts, and the gate G of the power MOS transistor PW-MOS becomes the power supply voltage VM. The intermediate voltage between the ground voltage GND and the power supply voltage VM is restored. On the contrary, when the motor driver MTD is driven by D having a long width of the PWM wave PWM1 or PWM wave PWM2, the power MOS is generated by changing the PWM wave PWM1 or PWM wave PWM2 from the low level to the high level. The gate G of the transistor PW-MOS changes from the power supply voltage VM to the ground voltage GND. Next, when the PWM wave PWM1 and the PWM wave PWM2 return from the high level to the low level, the gate G of the power MOS transistor PW-MOS returns from the ground voltage GND to the power supply voltage VM.

  In this way, the resistor R is connected to the output terminal OUT of the pre-driver, and the current supply and extraction to the output terminal OUT is performed by the constant current i of the current source IS-P and the current source IS-N. The gate voltage of the power MOS transistor PW-MOS does not change from the power supply voltage VM to the ground voltage GND unless there is a duty of the PWM wave PWM1 or PWM2 to the extent based on D.

  In the present embodiment, the PWM wave (PWM wave PWM1 or PWM wave PWM2) for driving the piezo motor is an output stage MOS transistor (PMOS transistor PMOS1, NMOS transistor NMOS1, PMOS transistor PMOS2, The first pulse width is such that a signal having an amplitude smaller than the potential difference between the power supply voltage VM of the output stage and the ground voltage GND is output from the drain of the NMOS transistor NMOS2), and is output during normal driving. The second pulse width is larger than the first pulse width such that a signal having an amplitude between the power supply voltage VM and the ground voltage GND is output from the drain of the MOS transistor in the stage. As described above, the signal output from the drain of the MOS transistor at the time of starting or stopping control has the amplitude of the intermediate voltage and the power supply voltage VM. As a result, the amount of voltage change applied to the piezo motor PZ is reduced, and suddenly no large voltage change amount is applied to the piezo motor PZ at the time of start-up or stop control.

A PWM wave is generated based on a command value IV that determines the number of pulses of the PWM wave from the central processing unit CPU, and has a sequencer SQC that generates a pulse width setting value Xp based on the command value IV.
The PWM wave generation circuit PWM-GC determines the duty of the PWM wave based on the pulse width setting value Xp. As a result, the central processing unit CPU can easily control the piezo motor PZ simply by determining the number of pulses based on the command value IV.

  The table TBL used in the sequencer SQC has a period T0 to Tk and individual pulse width values X0 to Xk. During startup, the period Tk and the individual pulse width value Xk are sequentially used from the period T0 and the individual pulse width value X0 stored in the table TBL, so that the pulse width set value Xp is changed and the piezo motor PZ is controlled to start and stop. During control, the period T0 and the pulse width individual value X0 are sequentially used from the period Tk and the pulse width individual value Xk stored in the table TBL, whereby the pulse width set value Xp is changed and the piezo motor PZ is controlled to stop. The central processing unit CPU determines the number of pulses based on the command value IV by determining the pulse width setting value Xp using the period T0 and the pulse width individual value X0 stored in the table TBL at the time of starting and stopping control. The control at the time of start-up and stop control for noise reduction can be easily performed.

  During normal driving, D is set as the pulse width setting value Xp, the pulse width individual values X0 to Xk are multiples of D, the periods T0 to Tk are natural multiples of the PWM period PWM-T, and D and pulse width are individually Values X0 to Xk and periods T0 to Tk can be set from the outside of the semiconductor integrated circuit device IC through the input / output circuit I / O. In this way, D, individual pulse width values X0 to Xk, and periods T0 to Tk can be set from the outside of the semiconductor integrated circuit device IC through the input / output circuit I / O, so as to match the characteristics of the piezo motor PZ. These parameters can be set. Since the period T0 to Tk is a natural number multiple of the PWM cycle PWM-T, the number of times determined by the command value IV according to the individual pulse width values X0 to Xk and the periods T0 to Tk stored in the table TBL. It is possible to determine which individual pulse width value is used for each pulse.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

IC Semiconductor integrated circuit device CPU Central processing unit FLASH Nonvolatile memory RAM Random access memory ADC AD conversion circuit MTD, MTD1 Motor driver OSC Oscillation circuit BUS Bus DR driver PWM-GC PWM wave generation circuit SQC Sequencer TBL Table IV Command value DATA Data PWM1 , PWM2 PWM wave T0 to Tk period Xp pulse width setting value X0 to Xk individual pulse width value PWM-T PWM period

Claims (5)

A PWM wave generation circuit for generating a PWM wave;
An output stage for driving a piezo motor driven by the PWM wave from the PWM wave generation circuit, the first MOS transistor;
As for the PWM wave, a signal having an amplitude smaller than the potential difference between the power supply voltage of the output stage and the ground voltage is output from the drain of the first MOS transistor of the output stage when the piezo motor is started or stopped. The first pulse width so that a signal having an amplitude between the power supply voltage and the ground voltage is output from the drain of the first MOS transistor of the output stage during normal driving. A semiconductor integrated circuit device having a larger pulse width than the second pulse width. A central processing unit,
The PWM wave is generated based on a command value that determines the number of pulses of the PWM wave from the central processing unit,
The output stage includes the first MOS transistor, the second MOS transistor, a third MOS transistor, and a fourth MOS transistor, and the gates of the first and second MOS transistors receive the PWM wave, The sources of the first and third MOS transistors are supplied with the power supply voltage, the sources of the second and fourth MOS transistors are supplied with the ground voltage, and the drains of the first and second MOS transistors are connected to the piezoelectric motor. Connected to one terminal, drains of the third and fourth MOS transistors are connected to the other terminal of the piezo motor, and a PWM wave different from the PWM wave is applied to the gates of the third and fourth MOS transistors. It is an H-bridge type configured to receive,
The semiconductor integrated circuit device according to claim 1, wherein a potential difference between the power supply voltage and the ground voltage is applied to one terminal and the other terminal of the piezo motor during the normal driving. A sequencer for generating a pulse width setting value based on the command value;
The semiconductor integrated circuit device according to claim 2, wherein the PWM wave generation circuit determines a duty of the PWM wave based on the pulse width setting value. Having a table used in the sequencer;
The table stores the first period, the second period, the first pulse width individual value of the first period, and the pulse width individual value of the second period,
The pulse width setting value is the first pulse width individual value in the first period, and the second pulse width individual value in the second period,
The PWM based on the second pulse width individual value in the second period after the piezo motor is driven by the PWM wave based on the first pulse width individual value in the first period from the stopped state at the time of starting Driven by waves,
During the stop control, the piezo motor is driven from the moving state by the PWM wave based on the second pulse width individual value in the second period, and then based on the second pulse width individual value in the first period. 4. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is stopped after being driven by a PWM wave. The pulse width setting value is set to a predetermined value such that a potential difference between the power supply voltage and the ground voltage is applied to one terminal and the other terminal of the piezoelectric motor during the normal driving,
The first and second pulse width individual values are multiples of the predetermined value,
The first period and the second period are a natural number times the period of the PWM wave,
5. The semiconductor integrated circuit device according to claim 4, wherein the predetermined value, the first and second individual pulse width individual values, and the first and second periods can be set from the outside.

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