JP5935538B2 - Mixer circuit and mixing device - Google Patents

Description

  The disclosed technology relates to a mixer circuit and a mixing device.

  In a radio communication device, a mixer circuit including a differential amplifier circuit is frequently used for orthogonal modulation / demodulation, frequency conversion, and the like. For example, in a direct conversion type or low IF (Intermediate Frequency) type receiver, a mixer circuit including a differential amplifier circuit is used when a baseband signal is obtained from a high-frequency input signal. In the differential amplifier circuit included in the mixer circuit, two transistors each supplied with a power supply voltage are grounded via a common constant current source. In the mixer circuit, a switching transistor is connected to each of the two transistors of the differential amplifier circuit, and the switching transistor is switched by a local oscillation signal. As a result, the mixer circuit mixes the input signal and the local oscillation signal and outputs a baseband signal.

  The mixer circuit includes a pair of common source amplifier circuits and a Gilbert cell type mixer circuit in which two sets of transistors are provided for each of the common source amplifier circuits. The mixer circuit operates a transistor provided in each of the transistor groups based on a control signal generated according to the template signal, and obtains an output signal obtained by multiplying the template signal and the differential signal.

  By the way, in a mixer circuit including a differential amplifier circuit, when the input signal to the differential amplifier circuit is zero, the output signal is preferably zero. From this, for the mixer circuit that performs frequency conversion by mixing the input signal and the local signal, the DC offset of the output signal with respect to the input signal to the differential amplifier circuit is detected, and the differential amplifier circuit based on the detection result There have been proposals for correcting the input signal to.

  Here, it is preferable to detect the DC offset of the output signal in the mixer circuit with high accuracy. For this purpose, when performing DC offset detection, it is necessary to increase the voltage amplification gain of the mixer circuit to obtain an output signal.

  However, in the mixer circuit, when the voltage amplification gain is increased, the frequency conversion gain when performing the frequency conversion is also increased, and there is a problem that the quality of the output signal is deteriorated such that the output signal is distorted.

JP 2009-218637 A JP 2009-232445 A JP 2011-119886 A

  In one aspect, the disclosed technology obtains a high-quality output signal in which a DC offset is suppressed in a mixer circuit including a differential amplifier circuit.

In the disclosed technique, the first differential input signal is input to the first differential pair. The second differential input signal is input to the plurality of buffer circuits. Each of the plurality of second differential pairs is connected to the first differential pair, and the differential input internal signals output from the plurality of buffer circuits are input to each of the plurality of second differential pairs. An output internal signal is output, and the output unit combines the plurality of differential output internal signals to output a differential output signal. Here, at the time of the first operation, all of the plurality of buffer circuits are stopped, and a reference voltage is input to one or the other of the active elements that form a pair in each of the plurality of second differential pairs. sometimes, the at least one non-stop of a plurality of buffer circuits, the reference voltage is input to the second differential pair connected to said stop has been the buffer circuit.

In one aspect, the disclosed technology stops all of the plurality of buffer circuits and sequentially operates one and the other of the paired active elements in each of the second differential pairs with high accuracy. detection can, high-quality output signal with reduced distortion by stopping the addition of at least one of the plurality of buffer circuits is obtained, an effect that.

It is a functional block diagram of the frequency converter which concerns on 1st Embodiment. 1 is a circuit diagram illustrating an example of a mixer circuit according to a first embodiment. FIG. It is a circuit diagram which shows the principal part of the mixer circuit which concerns on 1st Embodiment. It is a circuit diagram which shows the mixer circuit equivalent to the mixer circuit which concerns on this embodiment. It is a functional block diagram which shows an example of a DC offset detection part. It is a circuit diagram which shows the operation state of the mixer circuit in the case of DC offset detection in 1st Embodiment. It is a circuit diagram which shows the operation state of the mixer circuit in the case of performing frequency conversion in 1st Embodiment. It is a functional block diagram of the frequency converter which concerns on 2nd Embodiment. It is a circuit diagram which shows an example of the mixer circuit which concerns on 2nd Embodiment. It is a circuit diagram which shows the principal part of the mixer circuit which concerns on 2nd Embodiment. It is a diagram which shows the outline of the frequency conversion gain with respect to the frequency in a mixer circuit. It is a functional block diagram of the frequency converter which concerns on 3rd Embodiment. It is a circuit diagram which shows an example of the mixer circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows the principal part of the mixer circuit which concerns on 3rd Embodiment. It is a circuit diagram which shows an example of the mixer circuit used as a comparative example. It is a functional block diagram which shows an example of the frequency conversion part in which the mixer circuit of a comparative example is used.

[Comparative Example]
Prior to the description of embodiments of the disclosed technology, a comparative example of the disclosed technology will be described. FIG. 15 shows a mixer circuit 200 as a comparative example. The mixer circuit 200 includes a pair of transistors M202 and M204. In the transistors M202 and M204, a constant current source 206 is connected to the source S, and a differential amplifier 208 that differentially amplifies signals in and xin input to the gate G is formed.

In the mixer circuit 200, the sources S of the transistors M210 and M212 are connected to the drain D of the transistor M202, and the sources S of the transistors M216 and M218 are connected to the drain D of the transistor M204. The transistor M210 is supplied with the power supply voltage V _DD via the bias resistor 214a to the drain D, and the transistor M212 is supplied with the power supply voltage V _DD via the bias resistor 214b. The transistor M216 is supplied with the power supply voltage V _DD through the bias resistor 214b to the drain D, and the transistor M218 is supplied with the power supply voltage V _DD through the bias resistor 214a. Thereby, the mixer circuit 200 is a double balanced mixer (DBM) which is a Gilbert cell type mixer.

  FIG. 16 shows a frequency converter 220 in which the mixer circuit 200 is provided. The frequency converting unit 220 removes high frequency components from the signals in and xin output from the baseband unit 222 by the LPF 224 a, amplifies the signals by the buffer amplifier 224 b, and inputs the amplified signals to the mixer circuit 200. The frequency converter 220 includes a local oscillator 226 that oscillates and outputs a signal Lo that is a signal having a predetermined frequency as a carrier wave and a signal xLo obtained by inverting the signal Lo. The frequency conversion unit 220 amplifies the signals Lo and xLo output from the local oscillation unit 226 by the buffer amplifiers 228a and 228b, and inputs the amplified signals to the mixer circuit 200 via the capacitors 230a and 230b.

As shown in FIG. 15, the mixer circuit 200 supplies the reference voltage V _REF to the gates G of the transistors M210 and M216 via the switch 232a and the bias resistor 234a. Moreover, the mixer circuit 200 supplies a reference voltage _{V REF} to the gates G of the transistors M212, M218 via a switch 232b and a bias resistor 234b. In addition, a signal Lo is input to each gate G of the transistors M210 and M216, and a signal xLo is input to each gate G of the transistors M212 and M218. Further, the drains of the transistors M210 and M218 are connected to the output terminal 238a via the capacitor 236a, and the drains D of the transistors M212 and M216 are connected to the output terminal 238b via the capacitor 236b.

  Accordingly, the mixer circuit 200 performs frequency conversion by mixing the signals in and xin and the signals Lo and xLo, and outputs the output signals rf and xrf from the pair of output terminals 238a and 238b. As shown in FIG. 16, the frequency converter 220 amplifies and outputs the output signals rf and xrf of the mixer circuit 200 by the buffer amplifier 240.

  In such a mixer circuit 200, when the signals in and xin are zero, the output signals rf and xrf are preferably zero. However, a DC offset may occur in the signals in and xin input to the mixer circuit 200 due to variations in the manufacturing process of the semiconductor integrated circuit. For example, when the mixer circuit 200 is used in a communication terminal or the like, if a DC offset occurs in the signals in and xin, a signal having a frequency component equal to the signals Lo and xLo causes a carrier leak to be output as the output signals rf and xrf. generate. This carrier leak causes an error during signal reproduction in the demodulator on the receiving side. The mixer circuit 200 can prevent carrier leakage due to the DC offset if the DC offset of the signals in and xin is suppressed.

  From here, the frequency conversion unit 220 includes a DC offset detection unit 240 and a controller 242. The DC offset detector 240 receives the output signal rf when the switch 244a is turned on, and receives the output signal xrf when the switch 244b is turned on. The DC offset detector 240 detects a DC offset from the input output signals rf and xrf.

As shown in FIG. 15, the mixer circuit 200, the power supply voltage _{V DD} to the buffer amplifier 228a via the switch 246a is supplied, the power supply voltage _{V DD} to the buffer amplifier 228b through the switch 246a is supplied. In the mixer circuit 200, the operation of the buffer amplifiers 228a and 228b is stopped when the switches 246a and 246b are turned off.

  The mixer circuit 200 includes a switch 248a having one contact connected between the switch 232a and the bias resistor 234a, and a switch 248b having one contact connected between the switch 232b and the bias resistor 234b. . In the mixer circuit 200, the other contacts of the switches 248a and 248b are grounded, and when the switches 248a and 248b are turned off, the gates G of the transistors M210, M212, M216, and M218 are grounded.

  When the mixer circuit 200 functions as a frequency conversion circuit, the controller 242 turns on the switches 232a and 232b and the switches 246a and 246b, and turns off the switches 248a and 248b. Further, when the frequency converter 220 detects the DC offset of the output signals rf and xrf of the mixer circuit 200, the controller 242 turns off the switches 246a and 246b, and inputs the signals Lo and xLo to the mixer circuit 200. Stop.

  In this state, the controller 242 turns on the switches 232a and 248b, turns off the switches 232b and 248a, and operates the transistors M210 and M216 as a differential amplifier. In addition, the controller 242 turns on the switches 232b and 248a, turns off the switches 232a and 248b, and causes the transistors M212 and M218 to operate as a differential amplifier. As a result, the DC offset detector 240 detects the DC offset of the output signals rf and xrf.

  The controller 242 performs control so that the baseband unit 222 corrects and outputs the signals in and xin based on the detection result of the DC offset with respect to the output signals rf and xrf. Thereby, in the mixer circuit 200, output signals rf and xrf in which the DC offset of the signals in and xin output from the baseband unit 222 and the DC offset generated in the mixer circuit 200 are suppressed are obtained.

  Here, when detecting a DC offset, it is preferable that the voltage amplification gains of the transistors M210 and M216 of the mixer circuit 200 operated as a differential amplifier are high. In general, the carrier leak is desirably −20 dB or less. When the transistors M210 and M216 are operated as a differential amplifier, when the voltage amplification factor is increased to accurately detect a small DC offset, the mixer circuit 200 performs frequency conversion when functioning as a frequency conversion circuit. Gain also increases.

  When performing frequency conversion, if the frequency conversion gain is increased too much, the output waveform is distorted and the output signals rf and xrf are degraded. Therefore, it is preferable to suppress the voltage amplification gain of the mixer circuit 200 when performing frequency conversion. As a method of increasing the detection accuracy of the DC offset and suppressing the quality deterioration of the output signals rf and xrf in the mixer circuit 200, a method of switching the voltage amplification gain between the DC offset detection and the frequency conversion is conceivable.

  As a method of switching the voltage amplification gain in the mixer circuit 200, a method applied to a general variable gain amplifier, such as a method of switching the current of the constant current source 206 and a method of switching the resistance values of the bias resistors 214a and 214b, can be considered.

  However, in any of the above methods, since the bias voltages of the source S, gate G, and drain D in the transistors M202 and 204 of the differential amplifying unit 208 change, the output signal is detected when DC offset is detected and when frequency conversion is performed. The DC offset of rf and xrf changes, and the DC offset at the time of frequency conversion cannot be suppressed accurately.

[First Embodiment]
Next, an example of an embodiment of the disclosed technology will be described in detail with reference to the drawings. In FIG. 1, the principal part of the frequency converter 10 which concerns on 1st Embodiment is shown. The frequency conversion device 10 functions as an example of a mixing device according to the disclosed technology. The frequency conversion device is used in a transmission system, a reception system, a communication system including a transmission system and a reception system, and the frequency conversion device 10 used in the transmission system is described as an example in this embodiment.

  The frequency conversion device 10 includes a baseband unit 12, a mixer unit 14, and a local oscillation unit 16. Further, the mixer unit 14 includes a mixer circuit 18. The baseband unit 12 generates and outputs a signal to be transmitted such as an audio signal and an image signal. At this time, the signal output from the baseband unit 12 is a differential signal based on the signal IN and the signal xIN obtained by inverting the polarity of the signal IN, and the baseband unit 12 outputs the signals IN and xIN. The signals IN and xIN are examples of a first differential input signal in the disclosed technique, and the baseband unit 12 functions as a first signal generation unit in the disclosed technique.

  The frequency converter 10 removes high-frequency components from the signals IN and xIN output from the baseband unit 12 by an LPF (Low Pass Filter) 20, amplifies the signals by a buffer amplifier 22, and inputs the amplified signals to the mixer circuit 18.

  The local oscillating unit 16 oscillates a signal having a predetermined frequency F serving as a carrier wave of a signal output from the frequency conversion device 10. At this time, the local oscillation unit 16 generates a differential signal based on the signal Lo of the frequency F and the signal xLo obtained by inverting the signal Lo. In the disclosed technology, the signals Lo and xLo are examples of the second differential input signal, and the local oscillation unit 16 functions as an example of the second signal generation unit in the disclosed technology. The frequency converter 10 amplifies the signals Lo and xLo of the local oscillator 16 by the operation of the buffer amplifier 24 and inputs the amplified signals Lo and xLo to the mixer circuit 18 via the capacitor 26.

  The mixer circuit 18 performs frequency conversion by mixing the input signals Lo and xLo and the signals IN and xIN, and outputs an output signal RF and an output signal xRF obtained by inverting the output signal RF as output signals. The frequency conversion device 10 includes a capacitor 28 and a buffer amplifier 30. The output signals RF and xRF are input to the buffer amplifier 30 through the capacitor 28, and the output signals RF and xRF are amplified by the buffer amplifier 30 and output. The output signals RF and xRF are examples of differential output signals in the disclosed technology, and the buffer amplifier 30 functions as an example of an output unit in the disclosed technology.

  FIG. 2 shows the mixer unit 14 according to the present embodiment. The mixer circuit 18 provided in the mixer unit 14 is formed on a semiconductor integrated circuit such as an LSI (Large-scale Integrated circuit) made of CMOS (Complementary Metal Oxide Semiconductor), for example.

  The mixer circuit 18 includes a pair of transistors Ma and Mb. The transistors Ma and Mb function as an example of the first differential pair in the disclosed technology. In addition, the transistors Ma and Mb function as an example of an active element that forms the first differential pair in the disclosed technique. The transistors Ma and Mb have their sources S connected to the constant current source 32. In the mixer circuit 18, the signal IN is input to the gate G of one transistor Ma, and the signal xIN is input to the gate G of the other transistor Mb. Hereinafter, the transistors Ma and Mb and the constant current source 32 are collectively referred to as a differential amplifier 34. The differential amplifier 34 functions as an example of the differential amplifier in the disclosed technology.

  The mixer circuit 18 includes eight transistors Mc, Md, Me, Mf, Mg, Mh, Mi, and Mj. The transistors Mc, Md, Me, Mf, Mg, Mh, Mi, and Mj function as an example of an active element in the disclosed technique. In the disclosed technique, a plurality of second differentials are formed by the transistors Mc to Mj as an example. Pairs are formed. In the mixer circuit 18, the sources S of the transistors Mc, Md, Mg, and Mh are connected to the drain D of the transistor Ma, and the sources S of the transistors Me, Mf, Mi, and Mj are connected to the drain D of the transistor Mb. ing.

The mixer circuit 18 includes bias resistors 36a and 36b and bias resistors 38a and 38b. The bias resistor 36a is connected to the drains D of the transistors Mc and Mi, and the bias resistor 36b is connected to the drains D of the transistors Md and Md. The bias resistor 38a is connected to the drains D of the transistors Me and Mg, and the bias resistor 38b is connected to the drains D of the transistors Mf and Mh. Thus, in the mixer circuit 18, a voltage corresponding to the power supply voltage V _DD is applied to each drain D of the transistors Mc to Mh.

  As shown in FIGS. 1 and 2, the frequency conversion apparatus 10 includes four buffer amplifiers 24 a, 24 b, 24 c, and 24 d as the buffer amplifier 24, and four capacitors 26 a, 26 b, 26 c, and 26 d as the capacitors 26. Prepare. The buffer amplifiers 24a, 24b, 24c, and 24d function as an example of a plurality of buffer circuits in the disclosed technology.

  As shown in FIG. 2, in the mixer circuit 18, the signal Lo is input to the gates G of the transistors Mc and Me through the buffer amplifier 24a and the capacitor 26a, and the transistors Md and Mf are input through the buffer amplifier 24b and the capacitor 26b. Input to gate G. Further, the mixer circuit 18 inputs the signal xLo to the gates G of the transistors Mg and Mi via the buffer amplifier 24c and the capacitor 26c, and inputs the signals xLo to the gates G of the transistors Mh and Mj via the buffer amplifier 24d and the capacitor 26d. .

  As shown in FIGS. 1 and 2, the frequency conversion device 10 includes four capacitors 28 a, 28 b, 28 c, and 28 d as the capacitors 28. As shown in FIG. 2, the capacitor 28a has one end connected to the drains D of the transistors Mc and Mi, and the capacitor 28b has one end connected to the drains D of the transistors Md and Mj. The other ends of the capacitors 28a and 28b are connected to each other. Capacitor 28c has one end connected to each drain D of transistors Me and Mg, and capacitor 28d has one end connected to each drain D of transistors Mf and Mh. The other ends of the capacitors 28c and 28d are connected to each other.

  Thus, in the mixer circuit 18, a single balanced mixer (hereinafter referred to as SBM) 40a is formed by the transistor Ma of the differential amplifier 34 and the pair of transistors Mc and Mg. In the mixer circuit 18, an SBM 40 b is formed by the transistor Mb of the differential amplifier 34 and the pair of transistors Me and Mi. Therefore, the mixer circuit 18 includes a Gilbert cell type double balanced mixer (hereinafter referred to as DBM) 42 formed by the SBMs 40a and 40b.

  In the mixer circuit 18, the SBM 44a is formed by the transistor Ma and the pair of transistors Md and Mh of the differential amplifier 34, and the SBM 44b is formed by the transistor Mb and the pair of transistors Mf and Mj of the differential amplifier 34. Yes. Therefore, the mixer circuit 18 includes a Gilbert cell type DBM 46 formed by the SBMs 44 a and 44 b in addition to the DBM 42. Each of the transistor Mc and the transistor Mg, the transistor Me and the transistor Mi, the transistor Md and the transistor Mh, and the transistor Mf and the transistor Mj functions as an example of a plurality of second differential pairs in the disclosed technology. The pair of transistors Mc and Mg and the pair of transistors Me and Mi, and the pair of transistors Md and Mh and the pair of transistors Mf and Mj function as an example of two pairs of active elements in the disclosed technology.

  The DSBs 42 and 46 can operate independently of each other, and the DSB 42 performs frequency conversion by inputting the signals IN and xIN, the signal Lo, and the signal xLo, and outputs an output signal RFa and an output signal xRFa. Further, the DSB 46 performs frequency conversion by inputting the signals IN and xIN and the signals Lo and xLo, and outputs an output signal RFb and an output signal xRFb. Signals corresponding to the signals Lo and xLo inputted to the DSBs 42 and 46 from the buffer amplifiers 24a to 24d function as an example of differential input internal signals in the disclosed technique. In the following description, the second differential input signal and the differential input internal signal are not distinguished from each other and are described as signals Lo and xLo.

  The mixer circuit 18 outputs the output signal RFa of the DBM 42 and the output signal RFb of the DBM 46 as the output signal RF, and outputs the output signal xRFa and DBM46 output signal xRFb of the DBM 42 to the buffer amplifier 30 as the output signal xRF. In the disclosed technique, the output signals RFa, xRFa, RFb, and xRFb function as an example of differential output internal signals.

  As described above, the mixer circuit 18 according to the present embodiment includes the two DBMs 42 and 46 that share the differential amplification unit 34, and forms a DSB 46 and a transistor group that forms the DBM 42 for the differential amplification unit 34. A transistor group is connected in parallel. In the following description, a circuit including the transistor group (transistors Mc, Me, Mg, Mi) of the DBM 42 is generically referred to as a mixing unit 48a except for the differential amplifier 34 (transistors Ma, Mb) shared by the DBMs 42, 46. To do. A circuit including a transistor group (transistors Md, Mf, Mh, Mj) of the DBM 46 is generically referred to as a mixing unit 48b except for the differential amplifier 34 (transistors Ma, Mb) shared by the DBMs 42, 46. The mixing unit 48a and the mixing unit 48b function as an example of a plurality of mixing units in the disclosed technology.

  In the mixer circuit 18, the characteristics of the respective transistors of the mixing units 48 a and 48 b are aligned so as to form a double balanced modulation circuit with the differential amplification unit 34.

  Incidentally, in the mixer circuit 18 according to the first embodiment, the transistor Mc to which the signal Lo is input corresponds to the transistor Md, and the transistor Me and the transistor Mf correspond to each other between the mixing unit 48a and the mixing unit 48b. To do. In the mixer circuit 18, the transistor Mg to which the signal xLo is input corresponds to the transistor Mh, and the transistor Mi and the transistor Mj correspond to each other between the mixing unit 48a and the mixing unit 48b. Further, in the mixer circuit 18, between the mixing unit 48a and the mixing unit 48b, the bias resistor 36a and the bias resistor 36b correspond, and the bias resistor 38a and the bias resistor 38b correspond.

  In general, the voltage amplification gain Av of a transistor such as a MOSFET is the input voltage Vin when the voltage Vgs between the source S and the gate G is slightly changed, and the voltage Vds between the source S and the drain D at this time. Assuming that the change in the output voltage is Vout, Av = Vout / Vin = gm · Rd. Further, when the transconductance of the transistor is gm and the bias resistance connected to the drain D is Rd, the drain current Id is Id = gm · Vgs.

Further, when the size of the gate G between the drain D and the source S and the gate length, the dimension of the gate G in the direction intersecting the gate length to the gate width W, mutual conductance gm gate width It is proportional to W. That is, when the gate width W is 1/2, the transconductance gm is 1/2 and the voltage amplification gain Av is also 1/2.

FIG. 3 shows transistors Mc and Md as an example of transistors corresponding to each other in the mixer circuit 18. Here, in the first embodiment, the resistance values of the bias resistors 36a and 36b are 2r, and the gate widths W of the transistors Mc and Md are W = d / 2. Accordingly, in the mixer circuit 18, when the drain current Id ₁ in the transistor Mc and _Id 1 = i / 2, the drain current Id ₂ of the transistor Md becomes _Id 2 = i / 2.

  As shown in FIG. 2, in the mixer circuit 18, mixing units 48a and 48b are connected in parallel to the local oscillation unit 16 (see FIG. 1), the differential amplification unit 34, and the buffer amplifier 30 (see FIG. 1). . Thus, the transistors Mc and Md are arranged in parallel with the local oscillation unit 16, the differential amplification unit 34, and the buffer amplifier 30.

  Therefore, in FIG. 3, the drains D of the transistors Mc and Md are connected via the capacitors 28a and 28b, so that the combined resistance value of the bias resistors 36a and 36b becomes the resistance value r. The transistors Mc and Md corresponding to each other can be regarded as transistors having a gate width W of W = d (= 2 · d / 2) when viewed from the local oscillation unit 16 side. That is, the mixer circuit 18 can be regarded as one transistor that includes the transistors Mc and Md. At this time, the drain current Id of the virtual transistor including the transistors Mc and Md is Id = i (= 2 · i / 2).

  In the mixer circuit 18 in the first embodiment, the resistance values of the bias resistor 36a and the bias resistor 36b are 2r, and the bias resistor 38a and the bias resistor 38b are 2r. In the mixer circuit 18, the gate widths W of the transistors Ma to Mj are d / 2.

  FIG. 4 shows a general mixer circuit 50 that forms a Gilbert cell type mixer (double balanced mixer: DBM). In the mixer circuit 50, a mixing unit 56 is formed by the bias resistors 52 and 54 and the transistors MA, MB, MC, and MD. That is, the mixer circuit 50 receives the signal IN and the signal xIN input to the differential amplifier 34, the signal Lo input to the gate G of the transistors MA and MB, and the signal xLo input to the gate G of the transistors MC and MD. Mix.

  At this time, the mixer circuit 50 sets the resistance value of the bias resistor 52 as the resistance value r which is the combined resistance value of the bias resistors 36a and 36b, and sets the resistance value of the bias resistor 54 as the combined resistance value of the bias resistors 38a and 38b. Let r. In addition, the mixer circuit 50 sets the gate width W of the transistors MA to MD to W = d with respect to the gate width W = d / 2 of the transistors Mc to Mj in the mixer circuit 18. Thereby, for example, the drain current Id of the transistor MA becomes Id = i.

  That is, in the mixer circuit 50, the transistor MA corresponds to the set of transistors Mc and Md of the mixer circuit 18, and the transistor MB corresponds to the set of transistors Me and Mf of the mixer circuit 18. In the mixer circuit 50, the transistor MC corresponds to the set of transistors Mg and Mh of the mixer circuit 18, and the transistor MD corresponds to the set of transistors Mi and Mj of the mixer circuit 18.

  Therefore, in the first embodiment, the two mixing sections 48a and 48b provided in the mixer circuit 18 shown in FIG. 2 are equivalent to one mixing section 56 of the mixer circuit 50 shown in FIG. 18 is equivalent to the mixer circuit 50. In the disclosed technology, the mixing unit 56 functions as an example of one mixing unit including a plurality of mixing units.

  Since the mixer circuit 18 is equivalent to the mixer circuit 50, the voltage amplification gain when the mixing units 48 a and 48 b are operated becomes the voltage amplification gain in the mixer circuit 50.

  On the other hand, as shown in FIG. 1, the frequency conversion device 10 includes a controller 58 and a DC offset detection unit 60. The DC offset detection unit 60 functions as an example of the offset detection unit in the disclosed technology. The controller 58 functions as an example of a correction unit in the disclosed technology. The DC offset detector 60 detects the DC offset of the output signals RF and xRF output from the mixer circuit 18. The controller 58 controls the DC offset detection included in the output signals RF and xRF of the mixer circuit 18 by the DC offset detection unit 60. Further, the controller 58 controls the baseband unit 12 to correct and output the signals IN and xIN based on the detection result of the DC offset detection unit 60.

  As shown in FIGS. 1 and 2, the frequency conversion device 10 includes four switches 62 a, 62 b, 62 c, and 62 d corresponding to the signals RFa, RFb, xRFa, and xRFb output from the mixer circuit 18.

  The switch 62a has one contact point connected between the drain D of the transistors Mc and Mi and the capacitor 28a, and the switch 62b has one contact point connected between the drain D of the transistors Md and Mj and the capacitor 28b. Yes. The switches 62 a and 62 b are connected to the DC offset detection unit 60 with the other contacts connected to each other. The switch 62c has one contact point connected between the drain D of the transistors Me and Mg and the capacitor 28c, and the switch 62d has one contact point connected between the drain D of the transistors Mf and Mh and the capacitor 28d. Yes. The switches 62c and 62d are connected to the DC offset detector 60 with the other contacts connected to each other. As a result, the DC offset detector 60 receives the output signals RF and xRF output from the mixer circuit 18 when the switches 62a to 62d are turned on.

The frequency conversion device 10 includes a switch 64 for each buffer amplifier 24. A switch 64a is connected to the buffer amplifier 24a, and the power supply voltage V _DD is supplied through the switch 64a. A switch 64b is connected to the buffer amplifier 24b, and the power supply voltage V _DD is supplied through the switch 64b. A switch 64c is connected to the buffer amplifier 24c, and the power supply voltage V _DD is supplied through the switch 64c. A switch 64d is connected to the buffer amplifier 24d, and the power supply voltage V _DD is supplied through the switch 64d.

The buffer amplifier 24 (24a to 24d) operates when the switch 64 (64a to 64d) is turned on and the power supply voltage V _DD is supplied, and the switch 64 (64a to 64d) is turned off to supply the power supply voltage V _DD. The operation is stopped by stopping the supply. Thereby, the frequency converter 10 can be operated by separately inputting the signals Lo and xLo to the DBMs 42 and 46.

  As shown in FIGS. 1 and 2, the mixer section 14 includes bias resistors 66a and 66b and switches 68a and 70a on the input side of the signal Lo, and bias resistors 72a and 72b and a switch 68b on the input side of the signal xLo. 70b.

  As shown in FIG. 2, one end of the bias resistor 66a is connected to the gates G of the transistors Mc and Me, and one end of the bias resistor 66b is connected to the gates G of the transistors Md and Mf. One end of the bias resistor 72a is connected to the gates G of the transistors Mg and Mi, and one end of the bias resistor 72b is connected to the gates G of the transistors Mh and Mj.

The switch 68a has one contact connected to the other end of the bias resistor 66a and the bias resistor 66b, and the switch 68b has one contact connected to the other end of the bias resistor 72a and the bias resistor 72b. In the switches 68a and 68b, the reference voltage _VREF is applied to the other contact. The reference voltage V _REF is an example of a reference voltage in the disclosed technology.

In the mixer circuit 18, when the switch 68a is turned on, a bias voltage corresponding to the reference voltage _VREF is applied to the gates G of the transistors Mc and Me and the transistors Md and Mf. Further, in the mixer circuit 18, when the switch 68b is turned on, a bias voltage corresponding to the reference voltage _VREF is applied to the gates G of the transistors Mg and Mi and the transistors Mh and Mj. In the mixer circuit 18, when the bias voltage is applied to each gate G, the transistors Mc to Mj operate.

  In the switch 70a, one contact is connected to the switch 68a side of the bias resistors 66a and 66b, and the other contact is grounded. The switch 70b has one contact point connected to the switch 68b side of the bias resistors 72a and 72b and the other contact point grounded.

  Accordingly, in the mixer circuit 18, when the switch 70a is turned on, the gates G of the transistors Mc to Mf are grounded, and the transistors Mc to Mf stop operating. Further, in the mixer circuit 18, when the switch 70b is turned on, the gates G of the transistors Mg to Mj are grounded, and the transistors Mg to Mj stop operating.

  The controller 58 functions as a control unit, and controls on / off of the switches 62a to 62d, the switches 64a to 64d, the switches 68a and 68b, and the switches 70a and 70b. Thus, the controller 58 performs DC offset detection and frequency conversion using the mixer circuit 18.

  The frequency conversion device 10 performs frequency conversion using one of the DBMs 42 and 46 of the mixer circuit 18. At this time, the controller 58 functions as an example of a selection unit. When frequency conversion is performed using the DBM 42, the switches 64b, 64d, 70a, and 70b are turned off, and the switches 64a, 64c, 68a, and 68b are turned on.

  Thereby, in the mixer circuit 18, the transistors Mc to Mj can operate, and the signals Lo and xLo are input to the DBM 42. Therefore, in the mixer circuit 18, frequency conversion is performed in the DBM 42. The mixer circuit 18 can use a DBM 46 instead of the DBM 42. In this case, the controller 58 stops the operation of the DBM 42 and operates the DBM 46 by turning on the switches 64b and 64d instead of the switches 64a and 64c.

  On the other hand, when the controller 58 detects the DC offset from the output signals RF and xRF of the mixer circuit 18, the controller 58 turns on the switches 62 a to 62 d and inputs the output signals RF and xRF of the mixer circuit 18 to the DC offset detector 60. . Further, the controller 58 stops the input of the signals Lo and xLo to the mixer circuit 18 by turning off the switches 64a to 64d.

  In addition, the controller 58 performs DC offset detection in each of the state in which the switches 68b and 70a are turned off and the switches 68a and 70b are turned on, and the switches 68a and 70b are turned off and the switches 68b and 70a are turned on. .

  In the mixer circuit 18, when the switches 68b and 70a are turned off and the switches 68a and 70b are turned on, the gates G of the transistors Mg to Mj are grounded, and a bias voltage is applied to the gates G of the transistors Mc to Mf. Applied. Thereby, the mixer circuit 18 operates as a differential amplifier using the transistors Mc to Mf with respect to the signals IN and xIN.

  In the mixer circuit 18, when the switches 68a and 70b are turned off and the switches 68b and 70a are turned on, the gates G of the transistors Mc to Mf are grounded, and the gates G of the transistors Mg to Mj are biased. A voltage is applied. As a result, the mixer circuit 18 operates as a differential amplifier using the transistors Mg to Mj with respect to the signals IN and xIN.

  As such a controller 58, a computer in which memories such as a CPU, ROM, RAM, and HDD are connected by a bus can be used. At this time, the CPU may perform various processes by reading and executing the programs stored in the ROM and the memory.

  On the other hand, FIG. 5 shows an example of the DC offset detector 60. For the DC offset detection, various configurations for detecting the DC offset of the output signal RF (output signals RFa, RFb) and the output signal xRF (output signals xRFa, xRFb) of the mixer circuit 18 can be applied.

  The DC offset detection unit 60 includes a comparator unit 74 and a differential amplification unit 76. The differential amplifier 76 includes a pair of input terminals 78 a and 78 b and a differential amplifier 80. The switches 62a and 62b are connected to the input terminal 78a. When the switches 62a and 62b are turned on, the output signal RFa and the output signal RFb are input as the output signal RF of the mixer circuit 18. Further, the switches 62c and 62d are connected to the input terminal 78b, and the output signal xRFa and the output signal xRFb are input as the output signal xRF of the mixer circuit 18 by turning on the switches 62c and 62d.

  In the differential amplifier 80, one input terminal 80a is connected to the input terminal 78a through the capacitor 82a, and the other input terminal 80b having a signal inversion function (inverter function) is connected to the input terminal 78b through the capacitor 82b. ing. Thereby, in the differential amplifier 80, a signal corresponding to the output signal RF is input to the input terminal 80a, and a signal corresponding to the output signal xRF is inverted and input to the input terminal 80b.

  The differential amplifier 76 includes a switch 84 provided between the input terminal 78a and the input terminal 78b. In the differential amplifying unit 76, when the switch 84 is turned on, the capacitors 82a and 82b have the same potential, whereby the input terminals 80a and 80b of the differential amplifier 80 have the same potential.

  The differential amplifier 80 differentially amplifies signals input to the input terminals 80a and 80b and outputs the signals from the output terminals 80c and 80d. The differential amplifying unit 76 includes switches 86a and 86b. The switch 86a connects the input terminal 80a and the output terminal 80c of the differential amplifier 80, and the switch 86b connects the input terminal 80b and the output terminal 80d of the differential amplifier 80. In the differential amplifying unit 76, when the switches 86a and 86b are turned on, signals output from the output terminals 80c and 80d of the differential amplifier 80 are fed back to the input terminals 80a and 80b.

  The comparator unit 74 includes a comparator 88. One input end 88 a of the comparator 88 is connected to the output end 80 d of the differential amplifier 80, and the other input end 88 b of the comparator 88 is an output having a signal inverting function (inverter function) of the differential amplifier 80. It is connected to the end 80c. As a result, the signal output from the differential amplifier 80 is input to the comparator 88. The comparator unit 74 includes a switch 90, and the synchronization signal CK output from the controller 58 is input via the switch 90.

  When detecting the DC offset, the controller 58 turns on the switches 62a to 62d and controls on / off of the switch 84, the switches 86a and 86b, and the switch 90. At this time, the converter 88 outputs a binary comparison signal of “0 (Low)” and “1 (High)” corresponding to the input signals of the pair of input terminals 88a and 88b based on the synchronization signal CK to the output terminal. The data is output from 88c to the controller 58.

  The operation of the first embodiment will be described below.

  The frequency conversion device 10 inputs the signals IN and xIN output from the baseband unit 12 and the signals Lo and xLo output from the local oscillation unit 16 to the mixer circuit 18 of the mixer unit 14. The mixer circuit 18 outputs the output signals RF and xRF by performing frequency conversion based on the input signals IN and xIN and the signals Lo and xLo.

  The frequency converter 10 detects DC offsets of the output signals RF and xRF of the mixer circuit 18 prior to frequency conversion. Further, the controller 58 corrects the signals IN and xIN output from the baseband unit 12 based on the detection result of the DC offset detection unit 60. Thereby, when the frequency conversion is performed, the frequency conversion apparatus 10 can obtain the output signals RF and xRF in which the DC offset due to the signals IN and xIN is suppressed and the occurrence of carrier leakage is prevented.

  When the controller 58 performs DC offset detection of the output signals RF and xRF of the mixer circuit 18, the controller 58 turns off the switches 64 a to 64 d and stops the input of the signals Lo and xLo to the mixer circuit 18. At this time, the baseband unit 12 operates to output signals IN and xIN having predetermined values (for example, zero).

  Further, the controller 58 operates the switches 62a to 62d, 68a, 68b, 70a, and 70b of the mixer unit 14. At this time, the controller 58 performs DC offset detection in the state where the switches 68a and 70b are turned on and the switches 68b and 70a are turned off, and the state where the switches 68a and 70b are turned off and the switches 68b and 70a are turned on.

  FIG. 6 shows a state where the switches 68a and 70b of the mixer unit 14 are turned on and the switches 68b and 70a are turned off as an example of DC offset detection. In FIG. 6, the circuit wiring through which the electric signal flows is indicated by a solid line, and the circuit wiring in which the electric signal flow stops is indicated by a dotted line.

In the mixer circuit 18, when the switch 68b is turned off and the switch 70b is turned on, the gates G of the transistors Mg to Mj are grounded, and the operations of the transistors Mg to Mj are stopped. Further, the mixer circuit 18 operates with the bias voltage (reference voltage V _REF ) applied to the gate G by turning on the switch 68a and turning off the switch 70a.

  Thereby, in the mixer circuit 18, the transistors Mc, Md, Me, and Mf operate as differential amplifiers for the signals IN and xIN. The output of the transistor Mc is input to the DC offset detection unit 60 as the output signal RFa, and the output of the transistor Md is input as the output signal RFb. Further, the output of the transistor Me is input to the DC offset detection unit 60 as the output signal xRFa, and the output of the transistor Mf is input as the output signal xRFb.

In the mixer circuit 18, the drains D of the transistors Mc and Md are short-circuited when the switches 62a and 62b are turned on, and the drains D of the transistors Me and Mf are short-circuited when the switches 62c and 62d are turned on. Become. Thereby, the mixer circuit 18 is equivalent to a differential amplifier using the transistors MA and MB in the mixer circuit 50 shown in FIG. That is, the transistors Mc and Md having the gate width W = d / 2 operate as the transistors MA having the gate width W = d, and the transistors Me and Mf having the gate width W = d / 2 are the transistors MB having the gate width W = d. Works as.

The mixer circuit 18 uses the transistors MC and MD in the mixer circuit 50 when the switches 68a and 70b are turned off and the switches 68b and 70a are turned on to operate the transistors Mg to Mj to perform DC offset detection . Equivalent to a differential amplifier . Therefore, also in this case, the mixer circuit 18 operates with a high voltage amplification gain equivalent to that of the differential amplifier using the transistors MA and MB in the mixer circuit 50.

  The DC offset detector 60 detects the difference between the output signal RF obtained from the transistors Mc and Md and the output signal xRF obtained from the transistors Me and Mf.

  As shown in FIG. 5, first, the output signals RF and xRF are input to the DC offset detector 60 when the switches 62a to 62d are turned on. Further, the DC offset detector 60 is configured such that the outputs of the differential amplifier 80 are fed back to the input side when the switches 86a and 86b are turned on, and the charges accumulated in the capacitors 82a and 82b are equalized when the switch 84 is turned on. Is done. Thereby, the DC offset detection unit 60 removes the DC offset of the differential amplifier 80, and makes the capacitors 82a and 82b equal to the offset reference voltage by the accumulated charge.

  Thereafter, when the switches 84, 86a, and 86b are turned off, the DC offset detection unit 60 accumulates charges according to the output signal RF in the capacitor 82a, and accumulates charges according to the output signal xRF in the capacitor 82b. . As a result, a voltage (DC offset voltage) corresponding to the potential difference between the output signal RF and the output signal xRF is input to the differential amplifier 80 at the input ends 80a and 80b.

  The differential amplifier 80 differentially amplifies the DC offset voltage and outputs it to the comparator 88. The comparator 88 outputs a binary signal of “H” or “L” according to the DC offset voltage input to the input terminals 88a and 88b. Thereby, for example, the DC offset detection unit 60 outputs the “H” level signal when the output signal RF is higher than the output signal xRF, and the comparator 88 when the output signal RF is lower than the output signal xRF. Outputs an “L” level signal.

When detecting the DC offset in this way, it is preferable that the voltage (potential difference between the input terminals 88a and 88b) input to the comparator 88 is large. At this time, the mixer circuit 18 can obtain a high voltage amplification gain when one of the paired transistors in each of the DBMs 42 and 46 operates as a differential amplifier, so that the differential amplifier 88 of the DC offset detection unit 60 can be obtained. Without increasing the gain, the comparator 88 can generate a potential difference with which a desired accuracy can be obtained. Therefore, in the frequency conversion device 10, the power consumption of the differential amplifier 80 of the DC offset detection unit 60 can be suppressed by using the mixer circuit 18.

  The controller 58 corrects the signals IN and xIN output from the baseband unit 12 so that the DC offset voltage is reduced from the output of the DC offset detection unit 60. For example, the controller 58 sets correction values for the signals IN and xIN based on the detection result of the DC offset detection unit 60. At this time, if the output signal RF is higher than the output signal xRF, the controller 58 sets the correction value so as to lower the output signal RF and raise the output signal xRF, so that the signals IN and xIN are canceled. Correct.

  The controller 58 operates each of the transistors Mc to Mf and the transistors Mg to Mj of the mixer circuit 18, for example, correction values of the signals IN and xIN so that the DC offset voltage detected by the DC offset detector 60 is minimized. Set.

  When the frequency converter 10 performs frequency conversion, the baseband unit 12 corrects and outputs the signals IN and xIN based on the correction value set by the controller 58.

  On the other hand, when the frequency conversion device 10 performs frequency conversion, the controller 58 turns on the switches 68a and 68b and turns off the switches 70a and 70b. Thereby, a bias voltage is applied to each gate G of the transistors Mc to Mj. In the frequency conversion device 10, the controller 58 turns on the switches 64a and 64c and turns off the switches 64b and 64d. Thereby, in the mixer circuit 18, the signals Lo and xLo are input to the DBM 42, and the DBM 42 operates as a mixer circuit that performs frequency conversion.

  FIG. 7 shows the mixer circuit 18 when the DBM 42 operates. In FIG. 7, a circuit wiring through which an electric signal contributing to frequency conversion flows is shown by a solid line, and a circuit wiring at which the electric signal flow stops is shown by a dotted line. In FIG. 7, the circuit wiring in which the flow of the signal Lo or the signal xLo is stopped is indicated by a broken line.

  In the mixer circuit 18, the switches Mc to Mj can be operated by turning off the switches 70a and 70b and turning on the switches 68a and 68b. In the mixer circuit 18, when the switches 64a and 64c are turned on, the signal Lo is input from the buffer amplifier 24a to the transistors Mc and Me, and the signal xLo is input from the buffer amplifier 24c to the transistors Mg and Mi.

  As a result, in the mixer circuit 18, the signals IN and xIN input to the transistors Ma and Mb are subjected to frequency conversion in the DBM 42, the transistors Mc and Mi output the output signal RFa, and the transistors Me and Mg output signals. xRFa is output.

Since the mixer circuit 18 performs frequency conversion using only the DBM 42 of the DBM 42 and DBM 46, the frequency conversion is performed in comparison with the case where DC offset detection is performed (when the frequency conversion is performed using both the DBM 42 and the DBM 46 ). Gain is lowered. Therefore, since the mixer circuit 18 can operate in a linear region of the output characteristics, it is possible to suppress degradation in quality such as distortion in the output signals RF and xRF.

  On the other hand, the mixer circuit 18 suppresses DC offset in a state where the transistors Mc to Mj are operated. Here, the mixer circuit 18 applies a bias voltage to each gate of the transistors Md, Mf, Mh, and Mj included in the DBM 46.

  As described above, in the mixer circuit 18, the transistors Mg to Mj of the DBM 46 are operating in addition to the transistors Mc to Mf of the DBM 42 in a no-signal state in which the signals IN and xIN output from the baseband unit 12 are zero. Thereby, the bias conditions of the transistors Ma and Mb can be kept equal to the bias conditions when the mixer circuit 18 is operated to detect the DC offset. Therefore, in the frequency conversion device 10, the DC offset is suppressed, and the occurrence of carrier leak in the output signals RF and xRF is suppressed.

  In the first embodiment, when performing the frequency conversion, the DBM 42 included in the mixer circuit 18 is used. However, the DBM 46 may be used instead of the DBM 42, and the DBM 42 and the DBM 46 are used alternately. May be. When the DBM 42 and the DBM 46 are alternately used, the frequency conversion apparatus 10 may switch the DBM 42 and the DBM 46 at a timing such as when the signals RF and xRF are not output when the signals IN and xIN are off. As a result, the frequency conversion device 10 can extend the lifetime of the transistors Mc to Mj provided in the mixer circuit 18.

[Second Embodiment]
Next, a second embodiment will be described. The basic configuration of the second embodiment is the same as that of the first embodiment. In the second embodiment, the same reference numerals are given to the same functions as those of the first embodiment. The description is omitted.

  As shown in FIGS. 8 and 9, in the second embodiment, the frequency converter 10 </ b> A is provided with a mixer circuit 18 </ b> A instead of the mixer circuit 18. The mixer circuit 18A uses bias resistors 36c and 36d instead of the bias resistors 36a and 36b, and uses bias resistors 38c and 38d instead of the bias resistors 38a and 38b.

  As shown in FIG. 9, in the mixer circuit 18A, a DBM 42A is formed by the transistors Ma and Mb and the transistors Mc, Me, Mg, and Mi of the differential amplifier 34. In the mixer circuit 18A, the DBM 46A is formed by the transistors Ma and Mb and the transistors Md, Mf, Mh, and Mj of the differential amplifier 34.

  Here, in the mixer circuit 18A, the resistance values of the bias resistors 36c and 38c are 4r / 3, and the resistance values of the bias resistors 36d and 38d are 4r. Further, the mixer circuit 18A sets the gate width W between the paired transistors in accordance with the resistance value 4r / 3 of the bias resistors 36c and 38c and the resistance value 4r of the bias resistors 36d and 38d. That is, in the mixer circuit 18A, the gate width W of the transistors Mc, Me, Mg, and Mi is W = 3d / 4, and the gate width W of the transistors Md, Mf, Mh, and Mj is W = d / 4.

FIG. 10 shows transistors Mc and Md as an example of a set of transistors in the mixer circuit 18A. In the mixer circuit 18A, the bias resistor 36c has a resistance value 4r / 3, the bias resistor 36d has a resistance value 4r, the gate width W of the transistor Mc is W = 3d / 4, and the gate width W of the transistor Md is W = d / 4. Yes. Thus, in the mixer circuit 18A, when the drain current Id ₁ in the transistor Mc and _Id 1 = 3i / 4, the drain current Id ₂ of transistor Md becomes _Id 2 = i / 4.

  As described above, in the mixer circuit 18A, the voltage amplification gain is different between the DBMs 42A and 46A. At this time, in the mixer circuit 18A, the voltage amplification gain of the DBM 42A is set higher than the voltage amplification gain of the DBM 46A.

Thus, the mixer circuit 18A is equivalent to the mixer circuit 50 (see FIG. 4). That is, the combined resistance value of the bias resistors 36c and 36d is r, and the sum of the gate widths W of the paired transistors Mc and Md is W = d (W = 3d / 4 + d / 4). Therefore, the mixer circuit 18A can detect a DC offset with a high voltage amplification gain equivalent to that of the mixer circuit 50.

On the other hand, as shown in FIG. 8, the frequency conversion device 10 </ b> A includes local oscillation units 16 </ b> A and 16 </ b> B instead of the local oscillation unit 16. The local oscillators 16A and 16B output signals Lo and xLo having different frequencies F. Here, as an example, the local oscillation unit 16A outputs the signals Lo ₁ and xLo ₁ having the frequency F ₁ (for example, F ₁ = 400 MHz) as the signals Lo and xLo. The local oscillator 16B outputs signals Lo ₂ and xLo ₂ having a frequency F ₂ (for example, F ₂ = 800 MHz) higher than the frequency F ₁ as the signals Lo and xLo.

The local oscillator 16A is provided with switches 92a and 92b, and the local oscillator 16B is provided with switches 94a and 94b. As shown in FIGS. 8 and 9, the signal Lo ₁ output from the local oscillator 16A is input to the buffer amplifiers 24a and 24b via the switch 92a, and the signal xLo ₁ is input to the buffer amplifier 24c and the buffer amplifier 24c via the switch 92b. 24d. The signal Lo ₂ output from the local oscillator 16B is input to the buffer amplifiers 24a and 24b via the switch 94a, and the signal xLo ₂ is input to the buffer amplifiers 24c and 24d via the switch 94b.

The controller 58 switches the frequency F of the signals RF and xRF to the frequency F ₁ or the frequency F ₂ by controlling on / off of the switches 92a and 92b and the switches 94a and 94b in the frequency conversion device 10A. That is, the frequency conversion device 10A has a multiband function for outputting the output signals RF and xRF in different frequency bands.

  Further, the controller 58 selects one of the DBM 42A and the DBM 46A for the mixer circuit 18A by operating the switches 64a to 64d according to the switched frequency F.

Here, the frequency conversion device 10A reduces the frequency conversion gain of the mixer circuit 18A when the frequency F of the signals Lo and xLo is low, and increases the frequency conversion gain of the mixer circuit 18A when the frequency F of the signals Lo and xLo is high. Make it high. That is, in the frequency conversion device 10A, the DBM 46A is operated for the signals Lo ₁ and xLo ₁ output from the local oscillator 16A, and the DBM 42A is output for the signals Lo ₂ and xLo ₂ output from the local oscillator 16B. To work.

  As shown in FIG. 11, generally, in a mixer circuit, the frequency conversion gain varies according to the frequency F of the signals Lo and xLo. At this time, in the mixer circuit, the frequency conversion gain decreases as the frequency F increases.

From this point, in the frequency conversion device 10A, the mixer circuit 18A is provided with DBM 42A and DBM 46A having different voltage amplification gains, and frequency conversion is performed using one of the DBM 42A or DBM 46A according to the frequency of the signals Lo and xLo. At this time, in the mixer circuit 18A, the voltage amplification gain of the DBM 42A is set higher than the voltage amplification gain of the DBM 46A. The frequency converter 10A includes a frequency _F 1, _F signal _Lo 1 of low frequencies _{F 1} within the _2, relative XLO _1, using a low voltage amplification gain DBM46A, high frequency _{F 2} of the signal _Lo 2, against XLO _2, using a high voltage amplification gain DBM42A.

When the controller 58 outputs the output signals RF and xRF based on the signals Lo ₁ and xLo ₁ of the local oscillator 16A, the controller 58 turns on the switches 92a and 92b and turns off the switches 94a and 94b. The controller 58 turns off the switches 64a and 64c and turns on the switches 64b and 64d.

Thereby, in the frequency conversion device 10A, the signals Lo ₁ and xLo ₁ of the local oscillating unit 16A are input to the DBM 46A of the mixer circuit 18A, frequency-converted by the DBM 46A, and the output signals RF and RF corresponding to the signals Lo ₁ and xLo ₁ xRF is output.

When the controller 58 outputs the output signals RF and xRF based on the signals Lo ₂ and xLo ₂ of the local oscillator 16B, the controller 58 turns on the switches 94a and 94b and turns off the switches 92a and 92b. The controller 58 turns off the switches 64b and 64d and turns on the switches 64a and 64c.

Thereby, in the frequency conversion device 10A, the signals Lo ₂ and xLo ₂ of the local oscillating unit 16B are input to the DBM 42A of the mixer circuit 18A, frequency-converted by the DBM 42A, and the output signals RF and RF corresponding to the signals Lo ₂ and xLo ₂ xRF is output.

Therefore, in the frequency conversion device 10A, when output signals RF and xRF of different frequencies F (F ₁ and F ₂ ) are output, the frequency conversion gain is suppressed from decreasing even if the frequencies of the signals Lo and xLo are high. The

[Third Embodiment]
Next, a third embodiment will be described. The basic configuration of the third embodiment is the same as that of the first embodiment. In the third embodiment, the same functions as those of the first embodiment are denoted by the same reference numerals and description thereof is omitted. To do.

  12 and 13 show a frequency conversion device 10B according to the third embodiment. The frequency conversion device 10B includes a mixer unit 14B instead of the mixer unit 14. As shown in FIG. 12, the mixer circuit 18B provided in the mixer unit 14B includes three sets of DBMs (double balanced mixers) 96A, 96B, and 96C.

As shown in FIG. 13, the DBM 96A includes a differential amplifier 34 and transistors Mc, Me, Mg, and Mi. DBM96A the transistor Mc, the drain D of Mg, is supplied power supply voltage _{V DD} via a bias resistor 36f, the transistors Me, the power supply voltage _{V DD} via a bias resistor 38f to the drain D of Mi is supplied. The DBM 96B is formed to include the differential amplifier 34 and the transistors Md, Mf, Mh, and Mj. DBM96B the transistor Md, the drain D of the Mh, the power supply voltage _{V DD} is supplied through a bias resistor 36 g, transistors Mf, the power supply voltage _{V DD} via a bias resistor 38g is supplied to the drain D of the Mj.

  The mixer circuit 18A includes transistors Mk, Ml, Mm, and Mn and bias resistors 36h and 38h. The DBM 96C is formed to include a differential amplifier 34 and transistors Mk, Ml, Mm, and Mn.

In the transistors Mk and Mm, the source S is connected to the drain D of the transistor Ma, and in the transistors Ml and Mn, the source S is connected to the drain D of the transistor Mb. The transistors Mk and Mm are supplied with the power supply voltage V _DD to the drain D through the bias resistor 36h, and the transistors Ml and Mn are supplied with the power supply voltage V _DD through the bias resistor 38h to the drain D.

  In the mixer circuit 18B, the transistors Mc, Me, Mg, and Mi of the DBM 96A and the bias resistors 36f and 38f form a mixing unit 98a, and the transistors Md, Mf, Mh, and Mj of the DBM 96B and the bias resistors 36g and 38g include the mixing unit 98b. Form. In the mixer circuit 18B, the transistors Mk, Ml, Mm, and Mn of the DBM 96C and the bias resistors 36h and 38h form a mixing unit 98c.

In the mixer circuit 18B, the gates G of the transistors Mk and Ml and the switch 68a are connected via the bias resistor 68c, and the gates G of the transistors Mm and Mn and the switch 68b are connected via the bias resistor 72c. ing. In addition, the mixer unit 14B includes a buffer amplifier 24e that operates based on the power supply voltage V _DD supplied when the switch 64e is turned on, and a buffer amplifier 24F that operates based on the power supply voltage V _DD supplied when the switch 64f is turned on. Prepare.

  In the mixer circuit 18B, the signal Lo is input to the transistors Mk and Ml via the buffer amplifier 24e and the capacitor 26e, and the signal xLo is input to the transistors Mk and Ml via the buffer amplifier 24f and the capacitor 26f. The transistors Mk and Mm have the drain D connected to the buffer amplifier 30 via the capacitor 28e, and the transistors Ml and Mn have the drain D connected to the buffer amplifier 30 via the capacitor 28f.

  Thereby, the output signal RFa of DBM 96A, the output signal RFb of DBM 96B, and the output signal RFc of DBM 96C are input to the buffer amplifier 30 as the output signal RF. Further, the output signal xRFa of the DBM 96A, the output signal xRFb of the DBM 96B, and the output signal xRFc of the DBM 96C are input to the buffer amplifier 30 as the output signal xRF.

  On the other hand, the output signal RFc of the DBM 96C is input to the DC offset detection unit 60 when the switch 62e is turned on, and the output signal xRFc of the DBM 96C is input when the switch 62F is turned on. The DC offset detection unit 60 captures the output signals RFa, RFb, and RFc as the output signal RF, captures the output signals xRFa, xRFb, and xRFc as the output signal xRF, and detects the DC offset from the output signals RF and xRF.

  Here, in the mixer circuit 18B, the resistance values of the bias resistors 36f and 38f are 2r, and the resistance values of the bias resistors 36g and 38g and the bias resistors 36h and 38h are 4r. Further, the mixer circuit 18B sets the gate width W between the paired transistors in accordance with the resistance value 2r of the bias resistors 36f and 38f and the resistance value 4r of the bias resistors 36g, 36h, 38g, and 38h. That is, in the mixer circuit 18B, the gate width W of the transistors Mc, Me, Mg, and Mi is W = d / 2, and the gate width W of the transistors Md, Mf, Mh, and Mj and the transistors Mk, Ml, Mm, and Mn is W = d / 4.

FIG. 14 shows transistors Mc, Md, and Mk as an example of a set of transistors in the mixer circuit 18B. In the mixer circuit 18B, the bias resistor 36f has a resistance value 2r, the bias resistors 36g and 36h have a resistance value 4r, the gate width W of the transistor Mc is W = d / 2, and the gate widths W of the transistors Md and Mk are W = d / Four. Thus, in the mixer circuit 18B, when the drain current Id ₁ of the transistor Mc is Id ₁ = i / 2, the drain current Id ₂ of the transistor Md is Id ₂ = i / 4, and the drain current Id _{3 of the} transistor Mk is Id ₃ = i / 4.

  Thereby, in the mixer circuit 18B, the voltage amplification gain is made different between the DBMs 96A, 96B, and 96C. At this time, in the mixer circuit 18B, the voltage amplification gain of the DBM 96A is set higher than the voltage amplification gains of the DBMs 96 and 96C. That is, in the mixer circuit 18B, the voltage conversion gain of the DBM 96A is higher than the voltage amplification gains of the DBMs 96B and 96C for the signals Lo and xLo of the same frequency F. In the mixer circuit 18B, the voltage amplification gain becomes higher than the voltage amplification gain of any one of the DBM 96B and the DBM 96C by combining with the DBM 96A and one of the DBM 96B or the DBM 96C.

The mixer circuit 18B is equivalent to the mixer circuit 50 (see FIG. 4). That is, in the mixer circuit 18B, the combined resistance value of the bias resistors 36f, 36g, and 36h is r, and the sum of the gate widths W of the paired transistors Mc, Md, and Mk is W = d (W = d / 2 + d / 4 + d / 4). Therefore, the mixer circuit 18B can detect a DC offset with a high voltage amplification gain equivalent to that of the mixer circuit 50.

On the other hand, as illustrated in FIG. 12, the frequency conversion device 10 </ b> B includes a local oscillation unit 16 </ b> C instead of the local oscillation unit 16. The local oscillating unit 16C varies the oscillating frequency F and outputs signals Lo and xLo. Accordingly, the frequency conversion device 10B has a multiband function. Here, as an example, the local oscillating unit 16C has a signal Lo of a frequency F ₁ (for example, 400 MHz), a frequency F ₂ (for example, 800 MHz), and a frequency F ₃ (for example, 600 MHz, F ₁ <F ₃ <F ₂ ). Oscillate xLo. Hereinafter, the signals Lo and xLo of the frequency F ₁ are the signals Lo ₁ and xLo ₁ , the signals Lo and xLo of the frequency F ₂ are the signals Lo ₂ and xLo ₂ , and the signals Lo and xLo of the frequency F ₃ are the signals Lo ₃ and xLo _3. Is written.

  In the frequency converter 10B, the controller 58 selects and turns on the switches 64a to 64f according to the frequency F oscillated by the local oscillator 16C. Thereby, in the frequency conversion device 10B, at least one of the DBMs 96A, 96B, and 96C is selected according to the frequencies of the signals Lo and xLo, and the frequency conversion is performed.

Here, in the frequency conversion device 10B, the DBM 96A and DBM 96B (or DBM 96A and 96C) are selected and operated for the signals Lo ₁ and xLo ₁ output from the local oscillation unit 16B. Further, in the frequency conversion device 10B, the DBM 96A is selected for the signals Lo ₃ and xLo ₃ output from the local oscillator 16B, and the DBM 96B (or the signal Lo ₂ and xLo ₂ output from the local oscillator 16B is selected. DBM 96C) is selected and operated.

  That is, when DC offset detection is performed, the mixer circuit 18B operates as the mixer circuit 50 in which the bias resistors 52 and 54 have the resistance value r and the gate width W of the transistors MA to MD is W = d.

  In contrast, when DBM 96A is selected, mixer circuit 18B operates as a mixer circuit having a bias resistance of 2r and a transistor gate width W of W = d / 2 to perform frequency conversion. Further, when DBM 96B (or DBM 96C) is selected, mixer circuit 18B operates as a mixer circuit having a bias resistance of 4r and a transistor gate width W of W = d / 4 to perform frequency conversion.

  Furthermore, in the mixer circuit 18B, for example, when DBM 96A and DBM 96B are selected, the combined resistance value of the bias resistors 36f and 36g is 4r / 3, and the sum of the gate widths of the transistors Mc and Md is 3d / 4. Therefore, the mixer circuit 18B operates as a mixer circuit having a bias resistance of 4r / 3 and a transistor gate width W of W = 3d / 4, and performs frequency conversion.

  As a result, when the frequency converter 10B performs DC offset detection, the mixer circuit 18B operates with a high voltage amplification gain. In addition, when the frequency conversion device 10B performs frequency conversion, the voltage amplification gain of the mixer circuit 18B is lower than when DC offset is detected. At this time, in the frequency conversion device 10B, the voltage amplification gain of the mixer circuit 18B increases as the frequencies of the signals Lo and xLo increase. Therefore, in the frequency conversion device 10B, even if the frequencies of the signals Lo and xLo are high, the frequency conversion gain is suppressed from decreasing.

  In the present embodiment described above, the mixer circuits 18, 18A and 18B including two or three DBMs as mixer circuits have been described as examples. However, the number of DBMs included in the mixer circuit may be four or more. good. That is, the mixer circuit can include two or more sets of mixing units.

  In the present embodiment, the frequency conversion device provided in the transmission system has been described as an example, but the present invention can also be applied to the frequency conversion device provided in the reception system. The disclosed technique can be applied not only to the frequency conversion circuit but also to a mixer circuit including a differential amplifier circuit.

  In addition, all patent applications and technical documents disclosed in patent applications mentioned in this specification include specific and individual cases where individual documents, patent applications and technical standards are incorporated by reference. To the same extent, it is incorporated herein by reference.

The disclosed technology includes the following supplementary notes.
(Appendix 1)
A first differential pair (Ma, Mb) to which a first differential input signal (IN, xIN) is input;
A plurality of buffer circuits (24a to 24d) to which a second differential input signal (LO, xLO) is input;
The differential input internal signals (RFa, xRFa, RFb,..., RFb, RFb, RFb,. a plurality of second differential pairs (Mc and Mg, Me and Mi, Md and Mh, Mf and Mj) that output xRFb),
An output unit (28a to 28d) for synthesizing the plurality of differential output internal signals and outputting a differential output signal (RF, xRF);
Have
During the first operation (offset detection), all of the plurality of buffer circuits are stopped, and a reference voltage (V _REF ) is input to the plurality of second differential pairs,
At the time of the second operation (normal operation), at least one of the plurality of buffer circuits is stopped, and the reference voltage (V _REF ) is input to the second differential pair connected to the stopped buffer circuit. A mixer circuit (18).

(Appendix 2)
And an offset detector (60) for detecting a potential difference between the plurality of differential output internal signals,
The mixer circuit according to appendix 1, wherein the offset detection unit is operated during the first operation.

(Appendix 3)
The mixer circuit according to appendix 1 or appendix 2, wherein at least one of the plurality of buffer circuits is operated based on the frequency of the second differential input signal during the second operation.

(Appendix 4)
A first signal generator (12) for generating a first differential input signal (IN, xIN);
A second signal generator (16) for generating a second differential input signal (LO, xLO);
A first differential pair (Ma, Mb) to which the first differential input signal is input;
A plurality of buffer circuits (24a to 24d) to which the second differential input signal is input;
The differential input internal signals (RFa, xRFa, RFb,..., RFb, RFb, RFb,. a plurality of second differential pairs (Mc and Mg, Me and Mi, Md and Mh, Mf and Mj) that output xRFb),
An output unit (28a to 28d) for synthesizing the plurality of differential output internal signals and outputting a differential output signal (RF, xRF);
Including
During a first operation (offset detection), all of the plurality of buffer circuits are stopped, and a reference voltage (V _REF ) is input to the plurality of second differential pairs,
During a second operation (normal operation), at least one of the plurality of buffer circuits is stopped, and the reference voltage (V _REF ) is input to a second differential pair connected to the stopped buffer circuit. (58), mixing device (10).

(Appendix 5)
And an offset detector (60) for detecting a potential difference between the plurality of differential output internal signals,
The mixing apparatus according to appendix 4, wherein the offset detection unit is operated during the first operation (58).

(Appendix 6)
The mixing apparatus according to appendix 5, wherein the first differential input signal is corrected by the first signal generation unit in accordance with a detection result of the offset detection unit during the first operation (58).

(Appendix 7)
The mixing device according to any one of appendix 4 to appendix 6, wherein at least one of the plurality of buffer circuits is operated based on the frequency of the second differential input signal during the second operation (58).

(Appendix 8)
A differential amplifier (34) for differentially amplifying and outputting a first differential input signal (IN, xIN);
When the second differential input signal (Lo, xLo) is input by including two pairs of active elements (Mc and Mg, Me and Mi, or Md and Mh, Mf and Mj), the second differential input Each of which outputs a differential output internal signal (RFa, xRFa, or RFb, xRFb) by mixing a signal and a signal corresponding to the first differential input signal output from the differential amplifier. Connected to the amplifying unit, and the second differential input signal is input to each of them, so that the active elements corresponding to each other are paired to operate as two pairs of active elements (MA to MD). The differential output internal signals (RFa, xRFa, RFb, xRFb) are mixed by mixing the second differential input signal and a signal corresponding to the first differential input signal output from the differential amplifier. A plurality of mixing sections (48a, 48b) for outputting
Each of the plurality of mixing units is connected, and an output unit (30) that outputs a pair of output signals by combining the signals output from each of the plurality of mixing units;
A mixer circuit (18).

(Appendix 9)
Each of the plurality of mixing units differentially amplifies the first differential input signal in accordance with the gate width of the active element (Mc to Mj), and each mixing unit between at least two mixing units. 9. The mixer circuit according to appendix 8, wherein the mixer circuit operates as one mixing unit (56) including active elements (MA to MD) having a gate width corresponding to a sum of gate widths of the active elements.

(Appendix 10)
The mixer circuit according to appendix 8 or appendix 9, wherein a reference voltage (V _REF ) is applied _{instead of} the second differential input signal to a gate of the active element of at least one of the plurality of mixing units.

(Appendix 11)
A differential amplifier (34) that differentially amplifies and outputs the first differential input signal (IN, xIN), two pairs of active elements (Mc and Mg, Me and Mi, or Md and Mh, Mf and Mj) ) Including the second differential input signal (Lo, xLo), and the second differential input signal and the signal corresponding to the first differential input signal output from the differential amplifier To output differential output internal signals (RFa, xRFa, or RFb, xRFb) are connected to the differential amplifier, and the second differential input signal is input to each of them. Each of the active elements corresponding to each other is paired to operate as two pairs of active elements (MA to MD), and the second differential input signal and the first differential amplifier output the first differential The differential output internal signal (RFa, xR) is mixed with a signal corresponding to the differential input signal. a, RFb, xRFb) and a plurality of mixing sections (48a, 48b), and each of the plurality of mixing sections is connected, and the signals output from each of the plurality of mixing sections are combined to output a pair of outputs. A mixer circuit (18) including an output unit (30) for outputting a signal;
A signal generator (16) for generating the second differential input signal;
A selection unit (58, 64) for selecting at least one mixing unit for inputting the second differential input signal generated by the signal generation unit from the plurality of mixing units;
Including mixing equipment.

(Appendix 12)
Each of the plurality of mixing units differentially amplifies the first differential input signal in accordance with the gate width of the active element (Mc to Mj), and each mixing unit between at least two mixing units. The mixing device according to claim 11, wherein the mixing device operates as a single mixing unit (56) including active elements (MA to MD) having a gate width corresponding to a sum of gate widths of the active elements of the unit.

(Appendix 13)
The signal generation unit oscillates a signal having a predetermined frequency as the second differential input signal, and the selection unit outputs at least one signal from the plurality of mixing units based on the frequency of the second differential input signal. The mixing device according to appendix 11 or appendix 12, wherein the mixing unit is selected.

(Appendix 14)
An offset detection unit (60) for detecting a DC offset from the output signal obtained by differentially amplifying a signal corresponding to the first signal by each of the plurality of mixing units, and detected by the offset detection unit; 14. The mixing apparatus according to any one of appendix 11 to appendix 13, including a correction unit (58) that corrects the first differential input signal input to the differential amplification unit based on the DC offset.

10, 10A, 10B Frequency converter 12 Baseband unit 14, 14A, 14B Mixer unit 16, 16A, 16B, 16C Local oscillator unit 18, 18A, 18B Mixer circuit 34 Differential amplifier units 36a-36d, 36f-36h, 38a -38d, 38f-38h Bias resistor 42, 42A, 46, 46A, 96A-96C DBM
48a, 48b, 98a to 98c Mixer 58 Controller 60 DC offset detectors 64a to 64f Switches 68a to 68c, 72a to 72c Bias resistance Ma, Mb Transistors Ma to Mn Transistors MA to MD transistors

Claims (7)

A first differential pair to which a first differential input signal is input;
A plurality of buffer circuits to which a second differential input signal is input;
Each is connected to the first differential pair, and a plurality of second output signals that output a plurality of differential output internal signals are input to the differential input internal signals output from the plurality of buffer circuits. A differential pair of
An output unit that combines the plurality of differential output internal signals and outputs a differential output signal;
Have
During the first operation, all of the plurality of buffer circuits are stopped, and a reference voltage is input to one or the other of the active elements paired in each of the plurality of second differential pairs,
During the second operation, the at least one non-stop of a plurality of buffer circuits, the reference voltage is input to the second differential pair connected to the buffer circuits the stop, the mixer circuit. Furthermore, an offset detection unit for detecting a potential difference between the plurality of differential output internal signals,
The mixer circuit according to claim 1, wherein the offset detection unit is operated during the first operation.   3. The mixer circuit according to claim 1, wherein at the time of the second operation, at least one of the plurality of buffer circuits is operated based on a frequency of the second differential input signal. A first signal generator for generating a first differential input signal;
A second signal generator for generating a second differential input signal;
A first differential pair to which the first differential input signal is input;
A plurality of buffer circuits to which the second differential input signal is input;
Each is connected to the first differential pair, and a plurality of second output signals that output a plurality of differential output internal signals are input to the differential input internal signals output from the plurality of buffer circuits. A differential pair of
An output unit that combines the plurality of differential output internal signals and outputs a differential output signal;
Including
During the first operation, all of the plurality of buffer circuits are stopped, and a reference voltage is input to one or the other of the active elements paired in each of the plurality of second differential pairs,
During the second operation, stop the addition of at least one of said plurality of buffer circuits, and inputs the reference voltage into a second differential pair connected to the buffer circuits the stop, the mixing device. Furthermore, an offset detection unit for detecting a potential difference between the plurality of differential output internal signals,
The mixing apparatus according to claim 4, wherein the offset detection unit is operated during the first operation.   The mixing apparatus according to claim 5, wherein the first differential input signal is corrected by the first signal generation unit according to a detection result of the offset detection unit during the first operation.   7. The mixing device according to claim 4, wherein at the time of the second operation, at least one of the plurality of buffer circuits is operated based on a frequency of the second differential input signal. 8.

Images