JP5920049B2 - Liquid crystal display element - Google Patents

Description

  The present invention relates to a liquid crystal display element such as LCOS (Liquid Crystal On Silicon).

  Projection-type display devices that enlarge and project an image using a liquid crystal display element such as LCOS are widely used. Conventionally, an analog driving method that mainly expresses gradation by inputting an analog signal to a liquid crystal display element has been used. However, in recent years, a PWM (Pulse Width Modulation) digital signal is input to a liquid crystal display element. A digital drive system that expresses gradation has been widely used.

  In the digital driving method, each digital signal having a pulse width corresponding to the gradation is used as subframe data, and the gradation is expressed by, for example, data of 64 subframes.

  In recent years, the number of pixels of video data input to a liquid crystal display element has been increasing. In some cases, video data having the number of pixels called 4K2K is input to the liquid crystal display element. 4K2K refers to the number of pixels such as 4096 × 2400, 4096 × 2160, 3840 × 2160, for example, using the notation of the number of pixels in the horizontal direction × the number of pixels in the vertical direction.

JP 2001-51643 A

  For example, when the area of the image projected by the projection display device is narrowed, the outer portion of the narrowed image is black. In order to make the outer portion of the video black, generally, a digital signal corresponding to black data is written to the pixel of the liquid crystal display element. In this case, black data is generated outside the liquid crystal display element and supplied to the liquid crystal display element.

  By the way, if 4K2K 44-bit video data is input in the number of subframes of 64 subframes to a liquid crystal display element corresponding to the number of 4K2K pixels, the required data rate of the input video data is about 1 Gbps. If the data rate of the video data increases, the circuit scale increases and the power consumption increases.

  If the data supplied from the outside to the liquid crystal display element is only video data other than black data, the data rate can be lowered. If the data rate is lowered, the circuit scale can be reduced and the power consumption can be reduced.

  Further, if the data supplied from the outside to the liquid crystal display element is only video data other than black data and the data rate is not changed, the number of subframes can be increased to, for example, 65 subframes or 66 subframes. Become. If the number of subframes is increased, the number of gradations that can be expressed increases, so that high image quality can be achieved.

  As described above, it is various advantages that the data supplied from the outside to the liquid crystal display element is only the video data other than the black data. Therefore, a liquid crystal display element capable of displaying black using a peripheral circuit included in the liquid crystal display element without supplying black data from the outside is desired.

  In order to meet such a demand, an object of the present invention is to provide a liquid crystal display element capable of displaying black using a peripheral circuit included in the liquid crystal display element.

In order to solve the above-described problems of the related art, the present invention includes a plurality of pixels arranged in a matrix in the horizontal direction and the vertical direction, and a pixel electrode provided in each pixel and a facing surface facing the pixel electrode. A liquid crystal panel having an electrode, and a liquid crystal sealed between the pixel electrode and the counter electrode, and low and high for each subframe of video data applied to the counter electrode and displayed on the liquid crystal panel. In synchronization with the alternately repeated voltage, a low voltage is applied to the pixel electrode if the voltage applied to the counter electrode is low, and a high voltage is applied if the voltage applied to the counter electrode is high. A black data generating unit for generating black data for displaying black on the liquid crystal panel, and displaying the video data or the black data on a pixel at a predetermined position in the horizontal direction of the liquid crystal panel. A horizontal driving circuit for driving the video data, and a vertical driving circuit for driving the video data or the black data to be displayed on a predetermined line in the vertical direction of the liquid crystal panel. A parallel D flip-flop with a data selector that selects a column at a horizontal position in which the pixel data constituting the video data is written based on a mode signal corresponding to the number of pixels in the horizontal direction; the flop, said generated by the black data generating unit, the so that the black data is displayed at a predetermined pixel in the horizontal direction of the liquid crystal panel or pixel data constituting the image data according to the number of pixels, is supplied The horizontal drive circuit is output from the parallel D flip-flop with the data selector. A pixel position adjustment shift register that adjusts a horizontal position for displaying the input video data or the black data on the liquid crystal panel. also the first stage of adjusting the shift register, the black data generated by the black data generation unit to provide a liquid crystal display element characterized by being configured to be supplied.

In the liquid crystal display element, the horizontal driving circuit further includes a horizontal signal driver that supplies the video data or the black data output from the pixel position adjustment shift register to each pixel of the liquid crystal panel, wherein in the horizontal direction signal driver, it is preferable that the black data generated by the black data generation unit is configured to be supplied.

  In the liquid crystal display element, it is preferable that the vertical driving circuit includes an address decoder that is connected to each line of the liquid crystal panel and generates an address in the vertical direction.

  According to the liquid crystal display element of the present invention, black can be displayed using a peripheral circuit included in the liquid crystal display element.

It is a block diagram which shows one Embodiment of the liquid crystal display element of this invention. It is a block diagram which shows the specific structural example of the parallel D flip-flop 4 with a data selector in FIG. FIG. 3 is a diagram for explaining the operation of a specific configuration example of a parallel D flip-flop 4 with a data selector shown in FIG. 2. FIG. 2 is a block diagram illustrating a specific configuration example of a pixel position adjustment shift register 5 in FIG. 1. It is a timing chart for demonstrating the production | generation method of the black data in one Embodiment. FIG. 2 is a block diagram illustrating a specific configuration example of a horizontal direction signal driver 6 in FIG. 1. FIG. 7 is a diagram for explaining the operation of a specific configuration example of the horizontal signal driver 6 shown in FIG. 6. FIG. 7 is a diagram for explaining the operation of a specific configuration example of the horizontal signal driver 6 shown in FIG. 6. FIG. 2 is a block diagram showing a specific configuration example of address decoders 8a and 8b in FIG. It is a figure which shows the example of a display of the video data and black data by one Embodiment.

  Hereinafter, an embodiment of a liquid crystal display element of the present invention will be described with reference to the accompanying drawings. In FIG. 1, the liquid crystal panel 1 has a plurality of pixels Px arranged in a matrix. The liquid crystal panel 1 has the number of pixels corresponding to 4K2K. In FIG. 1, for the convenience of illustration, the number of pixels Px is smaller than the number of 4K2K pixels.

  In the present embodiment, the number of pixels in the horizontal direction of the liquid crystal panel 1 is the number of pixels corresponding to 4096 pixels. Specifically, it is assumed that there are 4104 adjustment pixels each having 4 adjustment pixels on the left and right sides of 4096 pixels. The number of lines in the vertical direction of the liquid crystal panel 1 is the number of lines corresponding to 2400 lines. Similarly, it is assumed that there are 4408 adjustment lines at the top and bottom, and 2408 lines.

  The liquid crystal panel 1 includes a pixel electrode provided corresponding to each pixel Px, and a counter electrode that faces the pixel electrode and is provided in common for all the pixel electrodes. The counter electrode is made of, for example, ITO (Indium Tin Oxide). The liquid crystal panel 1 has liquid crystal sealed between the pixel electrode and the counter electrode.

  Video data to be displayed on the liquid crystal panel 1 is supplied to the digital signal bus 3 via a high-speed interface (high-speed I / F) 2. Pixel data for one line in the video data is input to a parallel D flip-flop 4 with a data selector (parallel DFF with data selector). The parallel DFF 4 with data selector is a horizontal drive circuit.

  The control unit 7 may generate black data Dblk to be displayed on predetermined pixels in the horizontal direction on the liquid crystal panel 1 and supply the black data Dblk to the digital signal bus 3 in some cases. The black data Dblk is data generated by the control unit 7 which is a peripheral circuit of the liquid crystal display element, and is not data supplied from the outside of the liquid crystal display element. A method for generating the black data Dblk will be described later.

  As described above, there are a plurality of 4K2K pixel numbers such as 4096 × 2400, 4096 × 2160, and 3840 × 2160. In the present embodiment, video data of all these pixels can be displayed. Further, not video data of 4K2K but video data of 1920 × 1080 pixels called so-called full HD can be displayed.

  That is, any one of 4096, 3840, and 1920 video data is input to the liquid crystal display element of this embodiment as the number of pixels in the horizontal direction. The data selector in the parallel DFF 4 with data selector is provided to display the video data corresponding to each of the horizontal number of pixels of the video data of 4096, 3840, and 1920.

  A specific configuration example of the parallel DFF 4 with a data selector will be described with reference to FIG. FIG. 2 shows a configuration for one column provided corresponding to one pixel in the parallel DFF 4 with data selector. In the parallel DFF 4 with data selector, the configuration shown in FIG. 2 is provided in parallel for 4104 columns.

  In FIG. 2, data d1 is data of one pixel constituting video data having 1920 pixels in the horizontal direction, data d2 is data of one pixel constituting video data having 3840 pixels in the horizontal direction, and data d3 is data in the horizontal direction. It is assumed that the data is one pixel constituting video data having 4096 pixels.

  Data d1 and data selected by the data selector 42 are input to the data selector 41. Data d2 and d3 are input to the data selector. The data selector 43 receives the enable signal EN1 and the enable signal selected by the data selector 44. The data selector 44 receives enable signals EN2 and EN3.

  A mode signal M1 is input to the data selectors 41 and 43, and a mode signal M2 is input to the data selectors 42 and 44. The mode signals M1 and M2 are “0” or “1”, respectively. The mode signals M1 and M2 are input from the control unit 7.

  The data selectors 41 to 44 select the data or enable signal input to the terminal 0 if the mode signals M1 and M2 are “0”, and are input to the terminal 1 if the mode signals M1 and M2 are “1”. Data or enable signal to be selected.

  Therefore, the selection signal SEL and the input signal DIN input to the data selector 45 become the enable signal EN3 and the data d3 if the mode signals M1 and M2 are both “0” as shown in FIG. When the mode signal M1 is “0” and the mode signal M2 is “1”, the selection signal SEL and the input signal DIN are the enable signal EN2 and the data d2. When the mode signal M1 is “1” and the mode signal M2 is “0”, the selection signal SEL and the input signal DIN are the enable signal EN1 and the data d1.

  The data selector 45 outputs the input signal DIN input to the terminal 1 if the selection signal SEL is “1”, and does not output the input signal DIN if the selection signal SEL is “0”. Therefore, as shown in FIG. 3, the output of the data selector 45 is in a state of holding the previous data indicated as Q if the enable signals EN3, EN2, and EN1 are “0”, and the enable signals EN3, EN2, and EN1 are If “1”, the data is d3, d2, d1.

  The output of the data selector 45 is temporarily held by the DFF 46 and input to the DFF constituting the pixel position adjustment shift register 5 at the subsequent stage. A clock CLK is input to the DFF 46. The clock CLK is supplied from the control unit 7 to the DFF 46.

  As described above, the parallel DFF 4 with a data selector selects any of the data d1 to d3 by setting the mode signals M1 and M2 and the enable signals EN1 to EN3 in the respective columns. By selecting the data d1 to d3, the pixel data can be written in the column at an appropriate horizontal position regardless of the number of pixels in the horizontal direction of the video data, ie, 4096, 3840, and 1920.

  If the number of pixels of the input video data is fixed, the data selector may be omitted and only the DFF 46 may be used.

  The pixel data for one line output from the parallel DFF 4 with data selector is input to the pixel position adjustment shift register 5. The pixel position adjustment shift register 5 can be configured by a parallel input shift register. The pixel position adjustment shift register 5 is a horizontal drive circuit.

  As shown in FIG. 4, the pixel position adjustment shift register 5 receives the clock CLK and data Dload for transferring the data held in the parallel DFF 4 with data selector to the pixel position adjustment shift register 5. The Further, black data Dblk generated by the control unit 7 is input to the pixel position adjustment shift register 5.

  The pixel position adjustment shift register 5 can adjust the horizontal position of one line of pixel data output from the parallel DFF 4 with data selector. As described above, since the liquid crystal panel 1 has four adjustment pixels on each side of 4096 pixels, even when video data of 4096 pixels in the horizontal direction is input, 4096 pixels for one line. It is possible to adjust the position of the pixel data between a state in which is moved to the leftmost side and a state in which is moved to the rightmost side.

  The pixel position adjustment shift register 5 can hold the black data Dblk in addition to the pixel data of the video data by shifting the black data Dblk serially input from the control unit 7 in the horizontal direction. The pixel position adjustment shift register 5 can also hold black data Dblk for all of one line.

  Here, a method of generating the black data Dblk will be described with reference to FIG. In FIG. 5, (a) shows the voltage applied to the counter electrode. As for the voltage applied to the counter electrode, low (L) and high (H) are alternately repeated for each subframe (SF). In FIG. 5, (b) shows the voltage applied to the pixel electrode. If the voltages applied to the pixel electrodes are set to L and H in synchronization with the voltages L and H applied to the counter electrode shown in FIG. 5A, black is displayed.

  Therefore, as shown in FIG. 5 (c), at the timing of the previous subframe, L, H and L are set so that the voltage applied to the counter electrode is H when the voltage is L and L when the voltage is H. Is generated black data Dblk. The black data Dblk shown in (c) of FIG. 5 is collectively transferred to the pixels at the timing of the pulse that becomes H at the head of each subframe shown in (d) of FIG.

  The control unit 7 is applied to the counter electrode and is applied to the pixel electrode and the voltage applied to the counter electrode in synchronization with a voltage in which low and high are alternately repeated for each subframe of video data displayed on the liquid crystal panel 1. The black data generation unit generates black data for displaying black on the liquid crystal panel 1 by applying a low voltage when the voltage applied to the counter electrode is high, and a high voltage when the voltage applied to the counter electrode is high.

  The pixel data for one line output from the pixel position adjustment shift register 5 is input to the horizontal direction signal driver 6. The horizontal signal driver 6 is a horizontal drive circuit.

  A specific configuration example of the horizontal direction signal driver 6 will be described with reference to FIG. FIG. 6 shows a configuration for one column provided corresponding to one pixel in the horizontal signal driver 6. The horizontal signal driver 6 is provided in parallel with the configuration shown in FIG. 6 for 4104 columns.

  In FIG. 6, the pixel data output from the DFF of the pixel position adjustment shift register is input to the terminal 00 of the data selector 61. The L fixed data output from the control unit 7 is input to the terminal 01 of the data selector 61. The fixed H data output from the control unit 7 is input to the terminal 10 of the data selector 61. The data fixed at L or H corresponds to the black data Dblk.

The data selector 61 receives a 2-bit selection signal S _Lsel for selecting the terminals 00, 01, and 10 in line units. As shown in FIG. 7, if the selection signal S _Lsel is “00”, the data selector 61 selects the terminal 00 as the normal state. The data selector 61 selects the L-fixed terminal 01 if the selection signal is “01”, and selects the H-fixed terminal 10 if the selection signal is “10”.

The output of the data selector 61 is input to one input terminal of the NAND circuit 62. The output control signal S _OUTctl is input to the other input terminal of the NAND circuit 62. As shown in FIG. 8, the output control signal S _OUTctl is “1” or “0”.

The configuration shown in FIG. 1 can stop writing to the liquid crystal panel 1 in order to test the liquid crystal display element. If the output control signal S _OUTctl is “0”, the impedance becomes high impedance, and the output of the horizontal signal driver 6 does not drive the horizontal signal line. In a normal operation state, the output control signal S _OUTctl is “1”, so that pixel data is output to the output of the horizontal direction signal driver 6.

The output of the data selector 61 is inverted and input to one input terminal of the AND circuit 63. The output control signal S _OUTctl is inverted by the NOT circuit 64, and further, the output of the NOT circuit 64 is inverted and input to the other input terminal of the AND circuit 63.

  The output of the NAND circuit 62 is input to the p-type MOSFET 65, and the output of the AND circuit 63 is input to the n-type MOSFET 66. The output of the CMOS circuit of the p-type MOSFET 65 and the n-type MOSFET 66 is supplied to the pixel Px of the liquid crystal panel 1. In this circuit configuration, when the output is set to high impedance, the p-type MOSFET 65 and the n-type MOSFET 66 are turned off. Further, in the normal state, both the p-type MOSFET 65 and the n-type MOSFET 66 are in the state of performing the inverter operation in which they are turned on.

  The liquid crystal display element of this embodiment includes address decoders 8 a and 8 b as a vertical drive circuit of the liquid crystal panel 1. In the configuration example shown in FIG. 1, address decoders 8a and 8b are provided so that the liquid crystal panel 1 can be driven from the left-right direction. Only the left address decoder 8a and the right address decoder 8b may be used. Address decoders 8a and 8b are collectively referred to as address decoder 8.

  Although the shift register is generally used as a vertical drive circuit, in this embodiment, the address decoder 8 that can reduce the writing time even when black is displayed on a plurality of lines is used as the vertical drive circuit.

  A specific configuration example of the address decoder 8 will be described with reference to FIG. FIG. 9 shows a configuration for one line provided corresponding to one line in the address decoder 8. In the address decoder 8, the configuration shown in FIG. 9 is provided in parallel for 2408 lines.

  The control circuit 7 has an m-bit count 71. The vertical address decoder 81 receives the count output of the m-bit count 71 and the inverted count output. The vertical address decoder 81 outputs “1” when the counter value coinciding with the vertical address becomes “0”. Different m-bit counts 71 are connected to the vertical address decoder 81 for each line.

The output of the vertical address decoder 81 is inverted and input to one input terminal of the NAND circuit 82. The other input terminal of the NAND circuit 82 is inverted and inputted with a black write signal S _{BW that} is set to “1” when displaying black in line units. The output of the NAND circuit 82 is input to one input terminal of the AND circuit 83. The other input terminal of the AND circuit 83 receives a pulse width signal S _PW that determines the width of time for driving one line.

  As a result, it is possible to write to the correct pixel at the correct timing by matching the timing of the effective data time of the pixel output to the row scanning line that drives the pixel in the horizontal direction and the line selection time.

The output of the AND circuit 83 is a line selection signal S _VLsel for selecting the row scanning line in the vertical direction.

  The address decoder 8 can select a line for displaying the black data Dblk. The address decoder 8 can select a plurality of lines for displaying the black data Dblk.

  When the data written in the liquid crystal panel 1 is read for testing, a start pulse Pstt is input to the shift register 9. The shift register 9 supplies the data read from the liquid crystal panel 1 to the test comparator 10 as serial data.

  As described above, according to the liquid crystal display element of the present embodiment, as an example, as shown in FIG. 10, black data generated by the peripheral circuit of the liquid crystal display element around the video data shown in white. Black by Dblk can be displayed. In FIG. 10, for the sake of illustration, the number of pixels Px is smaller than the number of 4K2K pixels.

  In the example shown in FIG. 10, only the video data shown in white needs to be supplied to the liquid crystal display element, and it is not necessary to supply the surrounding black data from the outside. Therefore, the data rate of video data can be reduced, the circuit scale can be reduced, and power consumption can be reduced. When the data rate is not changed, the number of subframes can be increased, and the number of gradations that can be expressed can be increased to achieve high image quality.

  The present invention is not limited to the embodiment described above, and various modifications can be made without departing from the gist of the present invention. In the present embodiment, the black data Dblk is supplied to any of the parallel D flip-flop 4 with data selector, the pixel position adjustment shift register 5 and the horizontal signal driver 6. You may make it supply with respect to 1 or 2.

1 LCD panel 2 High-speed interface 3 Digital signal bus 4 Parallel D flip-flop with data selector (horizontal drive circuit)
5 Pixel position adjustment shift register (horizontal drive circuit)
6 Horizontal signal driver (horizontal drive circuit)
7 Control unit (black data generation unit)
8a, 8b Address decoder (vertical drive circuit)
9 Shift register 10 Comparison section

Claims (3)

A plurality of pixels are arranged in a matrix in the horizontal direction and the vertical direction, and are enclosed between a pixel electrode provided in each pixel, a counter electrode facing the pixel electrode, and the pixel electrode and the counter electrode. A liquid crystal panel having a liquid crystal
The voltage applied to the counter electrode is applied to the pixel electrode in synchronization with a voltage alternately applied to low and high for each subframe of video data to be displayed on the liquid crystal panel. If the voltage applied to the counter electrode is high, a black data generation unit that generates black data for displaying black on the liquid crystal panel by applying a high voltage if the voltage applied to the counter electrode is high;
A horizontal driving circuit for driving the video data or the black data to be displayed on a pixel at a predetermined position in the horizontal direction of the liquid crystal panel;
A vertical driving circuit for driving the video data or the black data to be displayed on a predetermined line in the vertical direction of the liquid crystal panel;
With
The horizontal driving circuit includes a parallel D flip-flop with a data selector for selecting a column at a horizontal position in which pixel data constituting the video data is written based on a mode signal corresponding to the number of pixels in the horizontal direction of the video data. Have
The data selector with parallel D flip-flop, said generated by the black data generation unit, constituting the video data to which the corresponding to the black data or the number of the pixels is displayed in a predetermined pixel in the horizontal direction of the liquid crystal panel Configured to be supplied with pixel data ,
The horizontal driving circuit receives the video data or the black data output from the parallel D flip-flop with the data selector, and displays the input video data or the black data on the liquid crystal panel. A pixel position adjustment shift register for adjusting
A liquid crystal display device wherein in the first stage of the pixel position adjustment shift register, the black data generated by the black data generation unit is configured to be supplied. The horizontal drive circuit further includes a horizontal signal driver that supplies the video data or the black data output from the pixel position adjustment shift register to each pixel of the liquid crystal panel,
The liquid crystal display device according to claim 1, wherein in the horizontal direction signal driver, the black data generated by the black data generation unit is characterized in that it is configured to be supplied.   The liquid crystal display element according to claim 1, wherein the vertical driving circuit includes an address decoder that is connected to each line of the liquid crystal panel and generates an address in a vertical direction.

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