JP5919834B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a semiconductor memory device.

  Generally, in a flash memory, data is stored in a memory cell by injecting or not injecting electrons into the floating gate, that is, by programming or not. On the contrary, the data in the memory cell is erased by extracting electrons from the floating gate, that is, erasing. Normally, in a flash memory that stores 1-bit data in a memory cell, the state of the programmed memory cell is associated with “0” and the state of the erased memory cell is associated with “1”. In the state, the threshold voltage of the memory cell is at a high voltage level, and in the state “1”, the threshold voltage of the memory cell is at a low voltage level.

  When reading data from the memory cell, the drain current and reference current of the read memory cell are calculated using the current of the reference cell set to the threshold voltage as an intermediate voltage between the threshold voltage in the programmed state and the threshold voltage in the erased state. Compare. Then, data “0” or “1” is determined depending on whether the drain current of the read memory cell is larger or smaller than the reference current. However, since the threshold voltage of the memory cell has a distribution having a certain extent, there is a memory cell in which a sufficient threshold margin with the reference cell cannot be secured, and data may not be read correctly.

  In order to cope with this, Patent Documents 2 to 5 adopt a method (hereinafter referred to as a complementary cell mode) in which positive and negative logic states that are always complementarily paired are stored in a pair of memory cells. Yes. By storing data in a pair of memory cells in the complementary cell mode, when reading data from the flash memory, a sufficient threshold margin can be ensured by using one of the memory cells as a reference cell.

JP 2007-257109 A JP 2005-92915 A JP 2008-84426 A JP-A-6-236687 JP 2005-141908 A

  In particular, for data that requires reliability, it is effective to store all memory areas in memory cells in the complementary cell mode. However, since 1-bit data is stored in a pair of memory cells, it can be used as compared with a conventional method (hereinafter referred to as single-phase cell mode) in which 1-bit data is stored in one memory cell. The capacity is halved and it is not suitable for storing large volumes of data. The data stored in the flash memory has different reliability levels depending on the data, and it is not always necessary to store all the data in the complementary cell mode, and data with a low reliability level is stored in the single-phase cell mode. Sometimes it is better.

  Accordingly, an object of the present invention is to provide a semiconductor memory device that supports not only data that requires reliability but also large-capacity data.

The first aspect of the semiconductor memory device is
A plurality of sectors each having a plurality of memory cells, each pair of sectors forming a plurality of sector groups,
As each operation of the plurality of sector groups, a single-phase cell mode in which 1-bit data is stored in one memory cell of one sector or the 1-bit data is included in a pair of sectors of the sector group, respectively. A mode determination unit that outputs a selection result of a complementary cell mode stored as complementary data in a pair of the memory cells;
A semiconductor memory device comprising: an operation control unit that operates the sector group in the single-phase cell mode or the complementary cell mode based on the selection result.

  According to the first aspect of the semiconductor memory device, not only data requiring reliability but also large-capacity data can be handled.

FIG. 1 is a diagram showing a memory cell array of a flash memory according to the present embodiment. FIG. 2 is a block diagram showing the configuration of the flash memory in the present embodiment. FIG. 3 is a flowchart showing a write operation of the semiconductor memory device according to the first embodiment. FIG. 4 is a diagram showing sector states of the lower sector and the upper sector in the first embodiment. FIG. 5 is a diagram illustrating a write mode determination operation according to the first embodiment. FIG. 6 is a waveform diagram of a flag signal when a write request is made in the order of the lower sector and the upper sector when both the lower and upper sectors of the flash memory in the first embodiment are in the batch erase state. FIG. 7 is a waveform diagram of a flag signal when a write request and a batch erase request are sequentially issued to the lower sector when both the lower and upper sectors of the flash memory in the first embodiment are in a batch erase state. . FIG. 8 is a waveform diagram showing the rise of each signal when the external power supply in the first embodiment is turned on. FIG. 9 is a block diagram showing generation of an internal ERS command in the first embodiment. FIG. 10 is a waveform diagram showing waveforms of the flag signal and the internal flag signal when the flash memory is turned on in the first embodiment. FIG. 11 is a flow chart for determining whether to execute the batch erase operation for inverted data in the first embodiment. FIG. 12 is a diagram showing a sector control circuit (decoder) in the first embodiment. FIG. 13 is a diagram showing the memory cell array according to the first embodiment. FIG. 14 is a diagram showing a lead path in the first embodiment. FIG. 15 is a diagram showing a program path in the first embodiment. FIG. 16 is a diagram illustrating an amplifier control circuit according to the first embodiment. FIG. 17 is a diagram illustrating a truth table of the amplifier control signal in the first embodiment. FIG. 18 is a flowchart showing the operation of the semiconductor memory device according to the second embodiment. FIG. 19 is a diagram illustrating sector states of the lower sector and the upper sector in the second embodiment. FIG. 20 is a diagram illustrating a write mode determination operation according to the second embodiment. FIG. 21 is a waveform diagram of a flag signal when a write request is made in the order of the lower sector and the upper sector when both the lower and upper sectors of the flash memory in the second embodiment are in the batch erase state. FIG. 22 is a waveform diagram showing the rise of each signal when the external power supply in the second embodiment is turned on. FIG. 23 is a block diagram illustrating generation of an internal ERS command according to the second embodiment. FIG. 24 is a diagram showing a sector control circuit (decoder) in the second embodiment. FIG. 25 is a diagram showing a read path in the second embodiment. FIG. 26 is a diagram illustrating a program path in the second embodiment. FIG. 27 is a diagram illustrating an amplifier control circuit for an upper sector in the second embodiment. FIG. 28 is a diagram illustrating an amplifier control circuit for a lower sector in the second embodiment. FIG. 29 is a diagram illustrating a truth table of amplifier control signals in the second embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a memory cell array of a flash memory according to the present embodiment.

  The memory cell array 10 has eight sectors Sector 0 to 7 having a plurality of memory cells and four sector groups SG0 to SG3 obtained by grouping two sectors. Sectors Sector 0 to 7 have sector numbers 0 to 7, respectively. Hereinafter, sectors Sector 0 to 3 having sector numbers 0 to 3 are referred to as lower sectors, and sectors Sector 4 to 7 having sector numbers 4 to 7 are referred to as upper sectors. I will do it. Sector groups SG0 to SG3 are formed by combining sectors Sector 0, 1, 2, and 3 and Sector 7, 6, 5, and 4, respectively. That is, the sector groups SG0 to SG3 are obtained by combining the lower sector and the upper sector.

  When the data writing method is the single-phase cell mode, one memory cell of one sector is selected from the eight sectors Sector 0 to 7, and 1-bit data is written. On the other hand, in the complementary cell mode, when one memory cell of one sector among the eight sectors Sector 0 to 7 is selected, not only 1-bit data is written to the selected memory cell but also the same sector group. The inverted data is written to one memory cell of the other sector in the memory. That is, in the complementary cell mode, complementary data is written in a pair of sectors.

  In addition, when erasing data written in a memory cell, the data is erased collectively in sector units. Specifically, after selecting a sector having data to be erased and setting all the memory cells in the sector to the program state “0”, the data in all the memory cells in the sector is erased and the memory is erased. All the cell states are set to the erased state “1”.

  Note that data writing and batch erasure are performed when an external write request or batch erase request is made to the flash memory 10. Further, the data writing means that the data “0” is written from the erased state “1” to the programmed state “0”, and the data “1” is written in the erased state “1”. It is. In addition, the state of the sector selected by each request is called a write state and a batch erase state, respectively.

  The semiconductor memory device according to the present embodiment performs data writing by determining either the single-phase cell mode or the complementary cell mode based on the state of the sector.

  FIG. 2 is a block diagram showing the configuration of the flash memory in the present embodiment.

  The command generation circuit 201 is supplied with commands such as a chip enable signal CEX and a write enable signal WEX from the outside, reads data from the memory cell, writes data to the memory cell, or batch erases the data in the memory cell in the sector. In response to such a request, a command signal such as a read command RD, a write command PGM, or a batch erase command ERS is output.

  Address input circuit 202 receives external address signals FA00-20 and outputs address signal AD to address selection circuit 210.

  The data input / output circuit 203 inputs the write data DI via the data terminals DIN00-15 and outputs the read data DO via the data terminals DO00-15.

  The operation control circuit 208 is responsive to command signals such as a read command RD, a write command PGM, and a batch erase command ERS, and a timing signal such as a memory core control signal for controlling a read operation, a write operation, a batch erase operation, etc. An internal ERS command for erasing inverted data written in the memory cell is output. Further, input data is input from the data input / output circuit 203 and output data DO is input from the read amplifier 220 for the verify operation.

  The internal address generation circuit 209 generates a verify operation internal address signal IA in response to the timing signal from the operation control circuit 208.

  Address selection circuit 210 receives address signal AD and internal address signal IA, and outputs row address signal RA and column address signal CA.

  The sector state memory 206, the sector state memory access control circuit 207, and the flag signal generation circuit 211 constitute a mode determination unit that determines the operation mode (single-phase cell mode or complementary cell mode) of each sector group.

  The sector status memory 206 is a non-volatile memory that stores the sector status of each sector. That is, sector state data for identifying whether a write request is input to a sector of the memory cell array or a batch erase state in which a batch erase request is input is held. A sector status memory is provided for each sector, and each sector status memory outputs a sector status signal based on the sector status data of the corresponding sector. Further, the sector state memory 206 stores the operation mode (single-phase cell mode or complementary cell mode) of each sector group.

  The sector state memory access control circuit 207 receives the command signal, the row address signal RA, the column address signal CA, the timing signal, and the flag signal twins output from the flag signal generation circuit 211, and inputs the sector state data to the sector state memory 206. Controls memory operation. Further, the sector state memory access control circuit 207 determines the operation of each sector group to the single-phase cell mode or the complementary cell mode based on the sector state signal output from the sector state memory 206. Then, the sector state memory access control circuit 207 stores the determination result in the sector state memory 206.

  The internal voltage generation circuit 204 generates a plurality of types of internal power supply voltages used in each circuit in the flash memory such as the X control circuit 213 according to the external power supply voltage.

  The power-on reset circuit 205 detects that the power supply VDD is supplied from the outside, and outputs a power-on reset signal POR to the operation control circuit 208 and the flag signal generation circuit 211.

  The flag signal generation circuit 211 latches the determination result (single-phase cell mode or complementary cell mode) stored in the sector state memory 206 for each sector and outputs a flag signal twins.

  The memory cell array 217 includes a plurality of word lines and source lines extending in the row direction (horizontal direction), and a plurality of global bit lines and a plurality of local bit lines extending in the column direction (vertical direction). The detailed configuration will be described later with reference to FIG.

  The sector control circuit 212, the write amplifier 219, and the read amplifier 220 are operation control units that control the operation of the memory cell array 217 based on the flag signal twins.

  The sector control circuit 212 outputs a signal SS for selecting a sector to be read, written or batch erased based on the flag signal twins, the memory core control signal, the row address signal RA, and the column address signal CA. .

  The X control circuit 213 decodes the row address signal RA and outputs a drive signal WLSEL for a word line and a drive signal SLS for a source line of the memory cell array.

  The Y control circuit 214 decodes the column address signal CA and outputs a local bit line selection signal LBSEL.

  The Y control circuit 215 decodes the column address signal CA and outputs a global bit line selection signal YSEL.

  Based on the memory core control signal, the flag signal twins, the row address signal RA, and the write command PGM, the amplifier control circuit 216 receives the upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, the reference cell selection signal / Twin, complementary output control signal / RAoutH, read amplifier enable signal RAen, write command PGM, and write clock signal / PGMCK are output.

  The write amplifier 219 receives the write data DI, and based on the write command PGM, the write clock signal / PGMCK, the upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, and the reference cell selection signal / twin, Write data to.

  The read amplifier 220 receives read data DO based on the upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, the reference cell selection signal / twin, the complementary output control signal / RAoutH, and the read amplifier enable signal RAen. Output.

  The column switch 218 selects a predetermined global bit line in the memory cell array 217 in response to the global bit line selection signal YSEL and connects it to the write amplifier 219 or the read amplifier 220.

[First Embodiment]
In the first embodiment, external address signals FA00 to 20 are input to the address input circuit 202 so that the sector order to be used is ascending order of sector numbers, and write data DI is input to the data input / output circuit 203. Write data DI is written in each sector. Specifically, first, the writing of input data is started sequentially from the sector Sector 0 to the sector Sector 3 in the complementary cell mode, and the inverted data of the input data is written to all the upper sectors Sector 7 to 4 corresponding to the sectors Sector 0 to 3 . When data is continuously written, data is written in the single-phase cell mode from the sector Sector 4 to the sector Sector 7 in order. However, when data writing is started from the sector Sector 4, since the inverted data of the lower sectors Sector 3 to 0 is written in the upper sectors Sector 4 to 7, the inverted data before starting writing in the single-phase cell mode. Perform batch erase.

  FIG. 3 is a flowchart showing a write operation of the semiconductor memory device according to the first embodiment.

  In the flash memory at the time of shipment, all the memory cells are in the erased state (data “1”), and the sector status data of each sector in the sector status memory 206 is in the batch erased state. Hereinafter, the fact that the sector state data of the two sectors of the sector group is in the batch erase state is referred to as an initial state.

  When all the sector groups are in the initial state, the write data DI is input to the data input / output circuit 203, and when the command generation circuit 201 outputs the write command PGM in response to an external write request, the external address signals FA00 to 20 Based on the above, the sector control circuit 212 selects the sector Sector0 by the row address signal RA generated by the address selection circuit 210 (S301). Then, the sector state memory access control circuit 207 determines the complementary cell mode based on the sector state data of the sectors Sector 0 and 7, and the write data DI is written to the sector Sector 0 and the inverted data is written to the sector Sector 7. (S302). After this determination, based on the external address signals FA00 to FA20 and the write command PGM, the sector state data of the sector Sector0 written in the sector state memory 206 is in a write state.

  Next, when there is no free space in the sector Sector0 and the write command PGM is output from the command generation circuit 201 in response to the write request, the sector Sector1 is based on the external address signal FA00-20 input to the address input circuit 202. Are selected (S303). Then, the sector state memory access control circuit 207 determines the complementary cell mode based on the sector state data of the sectors Sector 1 and 6, and the write data DI is written to the sector Sector 1 and its inverted data is written to the sector Sector 6. (S304). After this determination, the sector state data of sector Sector1 is in a write state. Thereafter, the write data DI is sequentially written in the same manner up to the sector Sector 3 (S305 to S308).

  Thus, when step S308 is completed, all sectors Sector0-7 are written in the complementary cell mode, sectors Sector0-3 are written with data DI, and sectors Sector4-7 are written with inverted data.

  Further, when writing the write data DI, when the command generation circuit 201 outputs the write command PGM in response to the write request, the memory of the sector Sector 4 is based on the external address signal FA00-20 input to the address input circuit 202. A cell is selected (S309). Then, the sector state memory access control circuit 207 determines the single-phase cell mode based on the sector state data of the sectors Sectors 3 and 4. Based on the determination result of the sector state memory access control circuit 207, the write command PGM is output from the command generation circuit 201 to the sector Sector4, and all the memory cells in the erased state “1” are set to the program state “0” in the sector Sector4. Writing is performed. Then, an internal ERS command for the sector Sector 4 is output from the operation control circuit 207 to the memory core 207, and all the memory cells in the sector Sector 4 are collectively erased from the program state “0” to the erase state “1”. Thereafter, write data DI is written in the sector Sector 4 in the single-phase cell mode based on the write command PGM output from the command generation circuit 201 (S310). In addition, after the determination by the sector state memory access control circuit 207, the sector state data of the sector Sector4 is in a write state. Thereafter, the write data DI is sequentially written in the same manner for the sectors Sectors 5 to 7 (S311 to S316).

  As described above, in the first embodiment, the sectors Sector0 and Sector7 of the sector group SG0 are finally switched from the complementary cell mode to the single-phase cell mode. Therefore, high-reliability data is written with priority over the sector Sector0. It is effective to leave

  As described above, the sector state memory access control circuit 207 determines the complementary cell mode or the single-phase cell mode. The sector state memory access control circuit 207 determines the complementary cell mode or the single-phase cell mode based on the logic levels of the sector state signals of the two sectors. The sector status signal is at the H level when the sector status data is in the write state and at the L level when in the batch erase state. On the other hand, in the first embodiment, external address signals FA00-20 are input so that the sector numbers corresponding to the input addresses are in ascending order, that is, the sector numbers are 0, 1,. When the write data DI is input, the write data DI is first written in the complementary cell mode. When the writing to the sector Sector 3 is completed, the sector Sector 4 is switched to the single-phase cell mode, and the write data DI is written. Therefore, in the first embodiment, on the assumption that the write data DI is written in this way, the sector status memory access control circuit 207 has the sector status signals of the lower sector and the upper sector at the L level. Only when there is a write command PGM for the lower sector, the complementary cell mode is determined.

  Therefore, the transition of the determination result of the sector state memory access control circuit 207 in the lower sector and the upper sector of one sector group (for example, the lower sector Sector0 and the upper sector Sector7 of the sector group SG0) will be described with reference to FIG. .

  FIG. 4 is a diagram showing sector states of the lower sector and the upper sector in the first embodiment. Specifically, FIG. 4 shows the logical level of the sector status signal and the sector status memory access control when there is a write request or batch erase request for each of the lower sector and the upper sector in one sector group. The logic level of the flag signal twins output from the flag signal generation circuit 211 based on the determination result of the circuit 207 is shown. When the flag signal twins is at the H level, it means that the determination result is the complementary cell mode, and when it is at the L level, it means that the determination result is in the single-phase cell mode.

  In FIG. 4, the initial state is the starting point (S401). In the initial state, since the state of all the memory cells in each sector is the erased state “1”, that is, the batch erased state, both the sector status memories of the lower sector and the upper sector output an L level sector status signal. In this state, the sector state memory access control circuit 207 determines the single-phase cell mode, stores the determination result in the sector state memory 206, and the flag signal generation circuit 211 outputs the L level flag signal twins.

  When the write command PGM is generated for the lower sector from the state of step S401 (S402), the sector status data of the lower sector is changed from the batch erase state to the write state, and the sector status memory of the lower sector is set to the H level sector. A status signal is output. As described above, when the sector status signal of the lower sector is switched from the L level to the H level and the sector status signal of the upper sector remains at the L level, the sector status memory access control circuit 207 determines the complementary cell mode. The determination result is stored in the sector state memory 206, and the flag signal generation circuit 211 outputs an H level flag signal twins.

  When the write command PGM is generated for the upper sector from the state of step S402 (S403), the sector state data of the upper sector changes from the batch erase state to the write state, and the sector status memory of the upper sector A status signal is output. As described above, when the lower sector and the upper sector are in the H level from the state in which the lower sector is at the H level and the sector status signal is at the H level, the sector state memory access control circuit 207 determines that the single-phase cell mode is set. Then, the determination result is stored in the sector state memory 206, and the flag signal generation circuit 211 outputs an L level flag signal twins.

  When the batch erase command ERS is generated for the lower sector from the state of step S403 (S404), the sector status data of the lower sector changes from the write state to the batch erase state, and the sector status signal of the sector status memory of the lower sector becomes L level. In this case, the sector state memory access control circuit 207 determines the single-phase cell mode, and the output flag signal twins remains at the L level.

  When the write command PGM is generated for the lower sector from the state of step S404 (S405), the sector status data of the lower sector is changed from the batch erase state to the write state, and the sector status signal of the sector status memory of the lower sector is H. Become a level. In this case, the sector state memory access control circuit 207 determines that the mode is the single-phase cell mode, and the output flag signal twins remains at the L level.

  When the batch erase command is generated for the upper sector from the state of step S405 (S406), the sector status data of the upper sector changes from the write state to the batch erase state, and the sector status signal of the sector status memory of the upper sector is L Become a level. In this case, the sector state memory access control circuit 207 determines the single-phase cell mode, and the output flag signal twins remains at the L level.

  When the batch erase command is generated in the lower sector from the state of step S406 (S407), the sector state of the lower sector changes from the write state to the batch erase state, and the sector status signal of the sector status memory of the lower sector becomes L level. . In this case, the sector state data of the lower sector and the upper sector are the same as the initial state, the sector state memory access control circuit 207 determines that the single-phase cell mode, and the output flag signal twins remains at the L level. .

  If a write command is generated for the upper sector and the lower sector in this order from the state of step S407 (S408, S409), the sector status data of the upper sector and the lower sector changes from the batch erase state to the write state in order. Then, the sector status signals in the sector status memories of the upper sector and the lower sector sequentially become H level. In both S408 and S409, the sector state memory access control circuit 207 determines the single-phase cell mode, and the output flag signal twins remains at the L level.

  When the batch erase command is generated in order for the upper sector and the lower sector from the state of step S409 (S410, S411), the sector status of the upper sector and the lower sector changes from the batch erase state to the write state in order, The sector status signal in the sector status memory of the lower sector sequentially becomes H level. In both S410 and S411, the sector state memory access control circuit 207 determines the single-phase cell mode, and the output flag signal twins remains at the L level. Note that the sector status memories of the lower sector and the upper sector are initialized by S411.

  When a write command is generated in the lower sector from the state of step S411 (S412), similarly to S402, the sector state memory access control circuit 207 determines the complementary cell mode and stores the determination result in the sector state memory 206. The flag signal generation circuit 211 outputs an H level flag signal twins.

  When a batch erase command is generated in the upper sector from the state of step S412 (S413), inversion data is actually written, but apparently no write data DI is written to the upper sector. This is a case where batch erasure is about to be performed. In the state of step S412, since data is written to the lower and upper sectors in the complementary cell mode in which highly reliable data is written, a batch erase command is generated for the upper sector where the write data DI is not written. However, the complementary cell mode needs to be maintained. Therefore, in step S413, the operation control circuit 208, which detects that the flag signal twins is at the H level in step S412 even when the command generation circuit 201 generates the batch erase command ERS, performs the batch erase operation on the memory core 221. The inverted data written in the upper sector is maintained. The sector status data of the upper sector is maintained in the batch erase state. Therefore, the flag signal twins output from the flag signal generation circuit 211 remains at the H level.

  When the batch erase command is generated in the lower sector from the state of step S413 (S414), the sector status data of the lower sector changes from the write state to the batch erase state, and the sector status signal of the sector status memory of the lower sector becomes L level. Become. In this case, the sector state memory access control circuit 207 determines the single-phase cell mode, stores the determination result in the sector state memory 206, and the flag signal generation circuit 211 outputs the L level flag signal twins.

  Thus, when both the lower and upper sector sector status data are at the L level, the sector status memory access control circuit 207 determines that the complementary cell mode is used only when the write command PGM is issued for the lower sector. Further, if the batch erase command ERS is issued for the upper sector in the complementary cell mode, the sector status data of the upper sector maintains the batch erase state, so the judgment result of the sector state memory access control circuit 207 is the complementary cell. Remain in mode. Then, data is written in ascending order of sector numbers, and the lowest sector stores data in the complementary cell mode until the highest sector is written. Therefore, the lowest sector ensures the reliability of stored data. Can be high.

  FIG. 5 is a diagram showing the determination operation of the write method in the first embodiment. FIG. 5 shows a sector state memory access control circuit 207, a lower sector state memory 501, an upper sector state memory 502, a sector state memory 206 having a lower sector single-phase complementary memory 504, and a flag signal generation circuit 211. . The sector state memory 206 and the flag signal generation circuit 211 are provided for each sector group.

  The lower sector state memory 501 is a sector state memory of any one of the lower sectors Sector 0 to 3, and the upper sector state memory 502 is a sector state memory of an upper sector in the same sector group as the lower sector of the lower sector state memory 501. It is. The sector state data in both sector state memories 501 and 502 are rewritten to the respective states in response to the write command PGM and the batch erase command ERS. The sector state signal c1outL output from the lower sector state memory 501 and the sector state signal c1outU output from the upper sector state memory 502 are supplied to the sector state memory access control circuit 207. Further, a program enable signal c2PGmen for single-phase complementary memory, which is a negative OR of the sector status signals c1outL and c1outU, is supplied to the sector status memory access control circuit 207 via the NOR gate 503.

  The lower sector single-phase complementary memory 504 is based on the sector state data of the lower sector state memory 501 and the upper sector state memory 502 when the address signal AD and the write command PGM batch erase command ERS are supplied from the operation control circuit 208. , A memory for storing single-phase complementary determination data indicating a determination result of the single-phase cell mode or the complementary cell mode, and a single-phase complementary determination signal c2outL of H level (complementary cell mode) or L level (single-phase cell mode) Output.

  For example, when the write command PGM is generated for the lower sector in the initial state (sector state signals c1outL and c1outU are both at L level (batch erase state)), that is, the program enable signal c2PGMan is at H level, The memory access control circuit 207 changes the single-phase complementary determination data of the lower sector single-phase complementary memory 504 from the L level (single-phase cell mode) to the H level (complementary cell mode). The sector state signal c1outL becomes H level (write state) in response to the write command PGM. From this state, when either the batch erase command ERS is generated for the lower sector or the write command PGM is generated for the upper sector, the sector state memory access control circuit 207 The single-phase complementary determination data in the lower sector single-phase complementary memory 504 is changed from H level (complementary cell mode) to L level (single-phase cell mode).

  The flag signal generation circuit 211 latches the single-phase complementary determination signal c2outL of the lower sector single-phase complementary memory 504 by the latch circuit 504 in response to the rising edge of the control clock signal ControlCLK, and outputs the flag signal twins. If the single-phase complementary determination data in the lower sector single-phase complementary memory 504 is H level (complementary cell mode), the flag signal twins is H level (complementary cell mode), and the single-phase complementary determination data is L level (single-phase (Cell mode), the flag signal twins is at L level (single-phase cell mode).

  The flag signal twins is output for each sector group. Therefore, when the flag signal that determines the writing method of the sector Sector 7 to the sector Sector 0 of the sector group SG0 is described, the flag signal is expressed as twins <7>. Similarly, in the sector group SG1, the flag signal that determines the writing method of the sector Sector6 for the sector Sector1 is twins <6>, and in the sector group SG2, the flag signal that determines the writing method of the sector Sector5 for the sector Sector2 is twins <5>, In the sector group SG3, the flag signal for determining the writing method of the sector Sector 4 with respect to the sector Sector 3 is expressed as twins <4>.

  The control clock signal ControlCLK is generated by the operation control circuit 208 in response to an OR signal obtained by ORing the write command PGM and the batch erase command ERS generated by the command generation circuit 201. The latch circuit 504 is reset in response to a power-on reset signal POR that is output from the power-on reset circuit 205 and becomes H level during activation of the external power supply VDD.

  FIG. 6 is a waveform diagram of a flag signal when a write request is made in the order of the lower sector and the upper sector when both the lower and upper sectors of the flash memory in the first embodiment are in the batch erase state. In FIG. 6, after the write command PGM is generated at the times T0 and T1 in the order of the lower sector and the upper sector in the same sector group, the batch erase command ERS is generated at the times T2 and T3 in the order of the lower sector and the upper sector. At T4 and T5, the write command PGM is generated again in the order of the lower sector and the upper sector.

  Based on the rising edge of the write command PGM for the lower sector at time T0 and the program enable signal c2PGMen (H level) for the single phase complementary memory immediately before that, the single phase complementary determination data in the lower sector single phase complementary memory 504 is at the L level. From (single phase cell mode) to H level (complementary cell mode). As a result, the single-phase complementary determination signal c2outL output from the lower sector single-phase complementary memory 504 is also changed from the L level (single-phase cell mode) to the H level (complementary cell mode). In response to the rise of the write command PGM for the lower sector at time T0, the sector status signal c1outL of the sector status memory 501 of the lower sector becomes H level, and the sector status data is in the write status. The control clock signal ControlCLK falls in response to the rise of the OR signal at time T0, and becomes H level at time C0 after time tcc from time T0. The latch circuit 504 latches the single-phase complementary determination signal c2outL in response to the rise of the control clock signal ControlCLK at time C0, and outputs an H level (complementary cell mode) flag signal twins.

  In response to the rise of the write command PGM for the upper sector at time T1, the single-phase complementary determination data in the lower-sector single-phase complementary memory 504 changes from H level (complementary cell mode) to L level (single-phase cell mode). As a result, the single-phase complementary determination signal c2outL also changes from the H level (complementary cell mode) to the L level (single-phase cell mode). At this time, the sector status signal c1outU of the upper sector becomes H level, and the sector status data in the sector status memory 502 is in the write status. The control clock signal ControlCLK becomes H level at time C1 after time T1. In response to this, the latch circuit 504 latches the single-phase complementary determination signal c2outL and outputs an L-level (single-phase cell mode) flag signal twins.

  In response to the rise of the batch erase command ERS for the lower sector at time T2, the sector status signal c1outL of the lower sector becomes L level, and the sector status data in the sector status memory 501 enters the batch erase state. At this time, the single-phase complementary determination data in the lower sector single-phase complementary memory 504 maintains the L level (single-phase cell mode). The control clock signal ControlCLK becomes H level at time C2. In response to this, the single-phase complementary determination signal c2outL latched by the latch circuit 504 is at the L level, and the output flag signal twins remains at the L level (single-phase cell mode).

  In response to the rise of the batch erase command ERS for the upper sector at time T3, the sector status signal c1outU of the upper sector becomes L level, and the sector status data in the sector status memory 502 enters the batch erase state. At this time, the single-phase complementary determination data in the lower sector single-phase complementary memory 504 maintains the L level (single-phase cell mode). The control clock signal ControlCLK becomes H level at time C3. In response to this, the single-phase complementary determination signal c2outL latched by the latch circuit 504 is at the L level, and the output flag signal twins remains at the L level (single-phase cell mode).

  After time T4, the operation from time T0 to time T2 is repeated.

  Thus, when both the lower sector and the upper sector are in the batch erase state, the write command PGM is generated in the lower sector, so that the determination result of the lower sector single-phase complementary memory 504 is from the single-phase cell mode to the complementary cell. Switch to mode. When the write command PGM is further generated in the upper sector, the determination result of the lower sector single-phase complementary memory 504 is switched to the single-phase cell mode.

  FIG. 7 is a waveform diagram of a flag signal when a write request and a batch erase request are sequentially issued to the lower sector when both the lower and upper sectors of the flash memory according to the first embodiment are in a batch erase state. In FIG. 7, the write command PGM and the batch erase command ERS are generated in the lower sector at times T0 and T1, and then the write command PGM and the batch erase command ERS are generated in the upper sector at times T2 and T3.

  The operation in response to the write command PGM to the lower sector starting from the time T0 is performed in the same manner as in FIG. 6, and the flag signal twins becomes H level (complementary cell mode).

  In response to the rise of the batch erase command ERS to the lower sector at time T1, the single-phase complementary determination data in the lower-sector single-phase complementary memory 504 changes from the H level (complementary cell mode) to the L level (single-phase cell mode). . As a result, the single-phase complementary determination signal c2outL also changes from the H level (complementary cell mode) to the L level (single-phase cell mode). Further, the sector status signal of the lower sector becomes L level, and the sector status data in the sector status memory 501 is in a batch erase state. The latch circuit 504 latches the single-phase complementary determination signal c2outL and outputs an L-level (single-phase cell mode) flag signal twins.

  In response to the rise of the write command PGM for the upper sector at time T2, the sector status signal in the sector status memory of the upper sector becomes H level, and the sector status data is in the write status. The single-phase complementary determination data is maintained at the L level (single-phase cell mode). The single-phase complementary determination signal c2outL latched by the latch circuit 504 at time C2 is at L level, and the output flag signal twins remains at L level (single-phase cell mode).

  The operation after the time T3 is performed in the same manner as the operation after the time T3 in FIG. 6, and the batch erase command to the upper sector, the write command to the lower sector, the write command to the upper sector at the times T3, T4 and T5. On the other hand, the flag signals twins at times C3, C4, and C5 are at L level (single phase cell mode), H level (complementary cell mode), and L level (single phase cell mode), respectively.

  As described above, when the write command PGM is generated in the lower sector when both the lower sector and the upper sector are in the batch erase state, the determination result of the lower sector single-phase complementary memory 504 is switched to the complementary cell mode. Further, when the batch erase command ERS is generated in the lower sector, the determination result of the flag signal generation circuit 210 is switched to the single-phase cell mode.

  FIG. 8 is a waveform diagram showing the rise of each signal when the external power supply in the first embodiment is turned on. FIG. 8 (1) shows waveforms when the sector status signals c1outL and c1outU are at the H level (write state) and the single-phase complementary determination signal c2outL is at the L level (single-phase cell mode) in both the lower sector and the upper sector. 8 (2) shows that the sector status signal c1outL of the lower sector is H level (write state), the sector status signal c1outU of the upper sector is L level (batch erase state), and the single-phase complementary determination signal c2outL is H level. It is a waveform in the case of (complementary cell mode).

  In FIG. 8A, the external power supply VDD that has been turned off is turned on at time T1 and rises to H level at time T2. As the external power supply VDD rises, the sector status signals c1outL and c1outU of the lower and upper sectors also rise. Further, in response to the rise of the external power supply VDD, the power-on reset signal POR becomes H level between times T1 and T2, and the operation control circuit 208 and the latch circuit 504 are reset. Therefore, the control clock signal ControlCLK generated by the operation control circuit 208 and the flag signal twins output from the latch circuit 504 are at the L level until time T2.

  When the control clock signal ControlCLK becomes H level at time T2, the latch circuit 504 latches the single-phase complementary determination signal c2outL. At this time, since the single-phase complementary determination signal c2outL is at the L level (single-phase cell mode), the output flag signal twins remains at the L level (single-phase cell mode).

  On the other hand, in FIG. 8B, the sector status signal c1outL of the lower sector and the single-phase complementary determination signal c2outL rise with the rise of the external power supply VDD from time T1. Further, the control clock signal ControlCLK and the flag signal twins output from the latch circuit 504 are set to the L level during the time T1 to T2 by the power-on reset signal POR.

  When the control clock signal ControlCLK becomes H level at time T2, the latch circuit 504 latches the H-level (complementary cell mode) single-phase complementary determination signal c2outL and outputs the H-level (complementary cell mode) flag signal twins. Output.

  Thus, in the first embodiment, when the external power supply is turned on, the flag signal twins is reset by the power-on reset signal. When the external power supply rises, the latch circuit 504 latches the single-phase complementary determination signal c2outL and outputs the flag signal twins having the same voltage level as that immediately before the external power supply is turned off.

  FIG. 9 is a block diagram showing generation of an internal ERS command in the first embodiment.

  In the first embodiment, in the complementary cell mode in the circuit configuration of FIG. 5, when the write command PGM for the upper sector or the batch erase command ERS for the lower sector is generated, Batch erase is performed. Along with this, the flag signal twins becomes L level (single-phase cell mode), the sector state data in the sector state memory 206 is rewritten, and at the same time, batch erase of the inverted data written in the upper sector is started. . Then, after the batch erase of the inverted data is completed, the operation of the generated command signal is started. Here, if the flash memory power is turned off during the batch erase operation of complementary cell data in the upper sector, the batch erase is interrupted halfway. However, when the power supply of the flash memory is turned on, even though the flag signal twins is at the L level (single-phase cell mode), a part of the inverted data is still held in the upper sector. End up.

  Therefore, in the first embodiment, the flag signal twins before the generation of the command signal for generating the batch erase operation of the inverted data is set as the internal flag signal int-twins, and the ERS is executed until the batch erase operation is completed. The sector state memory 901 holds it. When the power of the flash memory is turned on, even if the flag signal twins is at L level (single phase cell mode), if the internal flag signal int-wins is at H level (complementary cell mode), the batch erase is still performed. Is not completed, the batch erase operation of inverted data is performed after the power is turned on. As a result, even if the power of the flash memory is turned off during the batch erase operation of the complementary cell data of the upper sector, the batch erase operation of the inverted data of the upper sector is completed when the power is turned on thereafter. be able to.

  The operation of erasing the inverted data written in the upper sector at once will be described first. As an example, the operation when the write command PGM is sequentially generated for the lower sector and the upper sector of the sector group in the initial state will be described.

  First, when the write command PGM for the lower sector is generated, the complementary cell mode is determined by the sector state memory access control circuit 207 based on the sector state data of the lower and upper sectors, and the flag signal output from the flag signal generation circuit 211 Twins changes from L level (single phase cell mode) to H level (complementary cell mode). Then, the sector status data of the lower sector changes from the batch erase state to the write state. The sector state memory access control circuit 207 outputs an internal flag control signal int-tc to the ERS sector state memory 901 in response to the rise of the flag signal twins. The ERS sector state memory 901 changes the internal flag signal int-twins from the L level (single phase cell mode) to the H level (complementary cell mode) in response to the internal flag control signal int-tc.

  Next, when the write command PGM is generated for the upper sector, the flag signal twins changes from H level (complementary cell mode) to L level (single phase cell mode). The sector status data of the upper sector changes from the batch erase state to the write state in response to the write command PGM for the upper sector. Then, the sector state memory access control circuit 207 outputs an ERS start signal, which is a batch erase start command for the upper sector, to the operation control circuit 208 in response to the fall of the flag signal twins. The operation control circuit 208 generates an internal ERS command in response to the ERS start signal and outputs it to the memory core 221. As a result, collective erasure of the upper sector and its verify operation are performed. After completion, the operation control circuit 208 outputs an ERS completion signal to the sector state memory access control circuit 207. The sector state memory access control circuit 207 outputs an internal flag control signal int-tc to the ERS sector state memory 901 in response to the ERS completion signal. The ERS sector state memory 901 changes the internal flag signal int-twins from the H level (complementary cell mode) to the L level (single phase cell mode) in response to the internal flag control signal int-tc.

  In this way, in the complementary cell mode, inversion written in the upper sector in response to the generation of the write command PGM for the upper sector or the batch erase command ERS for the lower sector. Even if the power is accidentally turned off while the data is being erased at once, it will be erased normally. Next, the operation when the power of the flash memory is turned on after the power of the flash memory is turned off during the batch erase operation of the inverted data of the upper sector will be specifically described.

  FIG. 10 is a waveform diagram showing the waveforms of the flag signal and the internal flag signal when the flash memory is turned on in the first embodiment. FIG. 10 shows a waveform when the power supply is turned on from the state where the power supply of the flash memory is turned off during the batch erase operation of the inverted data of the upper sector, as described above.

  The power supply VDD starts to rise at time T10, and the power supply VDD becomes H level at time T11. In response to this, the control clock signal ControlCLK, the power-on control clock signal, and the internal flag signal int-twins also become H level at time T11. In FIG. 10, the flag signal twins is at the L level (single phase cell mode) at the start of batch erasure of the upper sector before the power of the flash memory is turned off. Therefore, the flag signal twins remains at the L level at time T11.

  In response to the rising edge of the power-on control clock signal output from the operation control circuit 208 to the sector state memory access control circuit 207 at time T11, the sector state memory access control circuit 207 sets the flag signal twins to the L level (single-phase cell mode). ), It is detected that the internal flag signal int-twins is at the H level (complementary cell mode).

  Then, the sector state memory access control circuit 207 sets the ERS start signal to the H level at time T12. Thereby, the batch erase operation of the inverted data of the upper sector which has been interrupted is resumed at time T12.

  When batch erase of inverted data is completed in the memory core 221 and the ERS completion signal output from the operation control circuit 208 rises at time T13, the internal flag signal int-twins falls in response to this at time T14. In other words, the resume operation of the complementary cell data that has been resumed is completed, and the sector status data of the upper sector is such that all the cells are in the erased state “1” (collective erase state), and the flag signal twins and the internal flag signal int-twins. Both become L level (single phase cell mode).

  When the write command PGM is output from the command generation circuit 201 to the lower sector at time T15, the control clock ControlCLK rises at time T16. At time T16, the flag signal twins output from the flag signal generation circuit 211 based on the sector status signals of the lower and upper sectors output from the sector status memory changes from L level (single phase cell mode) to H level (complementary). Cell mode). At this time, the sector state memory access control circuit 207 detects that the flag signal twins is H level (complementary cell mode) and the internal flag signal int-twins is L level (single phase cell mode), and at time T17. Internal flag signal int-twins is set to H level (complementary cell mode).

  When the write command PGM is output from the command generation circuit 201 to the upper sector at time T18, the control clock ControlCLK rises at time T19. At time T19, the flag signal twins output from the flag signal generation circuit 211 changes from the H level (complementary cell mode) to the L level (single phase cell mode). In response to the fall of the flag signal twins, the ERS start signal becomes H level at time T20. Thereby, the batch erase operation of the inverted data of the upper sector is started. When batch erase of the inverted data of the upper sector is completed and the ERS completion signal output from the operation control circuit 208 rises at time T21, the internal flag signal int-twins falls at time T22 in response to this. At this time, the batch erasure of the inverted data of the upper sector is completed, and the sector status data of the upper sector is in the erased state “1” (batch erased state) for all the cells.

  In this way, even if the flash memory power is turned off during batch erase of the inverted data of the upper sector and the batch erase operation of the inverted data of the upper sector is interrupted, the flag signal twins and the internal flag are turned on when the power is turned on. Based on the signal int-twins, the batch erase operation of the inverted data is resumed, and the consistency of the data written in each sector is ensured.

  FIG. 11 is a flow chart for determining whether to perform the batch erase operation for inverted data in the first embodiment. That is, FIG. 11 is a flowchart for determining whether or not to execute the correction data batch erasing operation performed in FIG.

  First, when the flash memory is powered on or when the write command PGM or the batch erase command ERS is output from the command generation circuit 201, the flag signal twins is at the L level (single-phase cell mode) or the H level (complementary cell mode). ) Is determined (S1101).

  If the flag signal twins is at L level (single phase cell mode) in step S1101, it is determined whether the internal flag signal int-wins is at H level or L level (S1102). When the internal flag signal int-twins is at L level, both the flag signal twins and the internal flag signal int-twins are at L level (single phase cell mode). This means that the batch erase operation of the inverted data in the upper sector is not interrupted, and the flash memory performs a normal operation. On the other hand, when the internal flag signal int-twins is at the H level (complementary cell mode), the flag signal twin (L level, single-phase cell mode) and the internal flag signal int-twins (H level, complementary cell mode) The logic level is different. This means that the batch erase operation of the inverted data of the upper sector is interrupted or the batch erase command ERS is generated for the upper sector. Therefore, an internal ERS signal is generated for the upper sector, and a batch erase operation of the inverted data of the upper sector is performed (S1103). Then, after the verify operation (S1104) is completed, in response to the internal ERS completion signal, the internal flag signal int-twins becomes L level, and both the flag signal twins and the internal flag signal int-twins are at L level (single-phase cell mode). ) (S1105, S1106). After the program for setting the ERS sector state memory 901 to the L level is completed, both the flag signal twins and the internal flag signal int-twins are set to the L level (single-phase cell mode), and the flash memory performs a normal operation (S1107).

  On the other hand, if the flag signal twins is at the H level (complementary cell mode) in step S1101, it is determined whether the internal flag signal int-twins is at the H level (complementary cell mode) (S1108).

  When the internal flag signal int-twins is at L level (single phase cell mode), the flag signal twins is at H level (complementary cell mode), and the internal flag signal int-twins is at L level (single phase cell mode). This means that the write mode is switched from the single-phase cell mode state to the complementary cell mode. That is, the write command PGM is generated for the lower sector from the state where the lower and upper sectors are in the batch erase state, and the lower sector is switched to the write state. In this case, in order to match the internal flag signal int-twins to the logic level of the flag signal twins, the sector state memory access control circuit 207 performs an erasing operation to set the ERS sector state memory 901 to the H level (S1109). Then, after the verify operation (S1110) of the ERS sector state memory 901 is completed, the flag signal twins and the internal flag signal int-twins are both at the H level (complementary cell mode), so the normal operation is performed.

  If the internal flag signal int-twins is at the H level (complementary cell mode) in step S1108, the flag signal twins and the internal flag signal int-twins are both at the H level (complementary cell mode), so that normal operation is performed.

  As described above, when the power source of the flash memory is activated or when a command signal is generated, the batch of inverted data written in the upper sector is based on the logic levels of the flag signal twins and the internal flag signal int-twins. Determination of the erase operation status is performed. When the flag signal twins is at the L level (single-phase cell mode) and the internal flag signal int-wins is at the H level (complementary cell mode), the batch data erase operation of the upper sector is performed. This is because, in this case, (A) the flash memory is turned off and the batch erase operation of the inverted data is interrupted, and (B) the write command PGM is generated in the upper sector in the complementary cell mode. This is because it is necessary to perform a batch erase operation.

  In the first embodiment, when the lower sector is selected in the complementary cell mode, the upper sector of the same sector group as the lower sector is also selected. Therefore, the sector control circuit 212 will be described.

  FIG. 12 is a diagram showing a sector control circuit (decoder) in the first embodiment. 12 (1) is a circuit diagram of the sector control circuit 212 for the sector Sector0, and FIG. 12 (2) is a circuit diagram of the sector control circuit 212 for the sector Sector7 belonging to the same sector group SG0 as the sector Sector0.

  The circuit of FIG. 12A is supplied with 3-bit sector address signals Sector Address <0>, <1>, <2> from the address selection circuit 210. The 3-bit sector address signal is input to the NAND gate 1204 via the inverters 1201 to 1203, respectively, and is output via the inverter 1205 as a 1-bit sector selection signal Sector Select <0> for the sector Sector0. Therefore, when the address signal “000” of the sector Sector0 is supplied, the sector selection signal Sector Select <0> of the sector Sector0 is output at the H level.

  In the circuit of FIG. 12B, when the address “000” of the sector Sector0 is supplied in the complementary cell mode, the sector selection signal Sector Select <7> of the sector Sector7 becomes H level and the sector Sector7 is also selected. It is a thing. The circuit of FIG. 12B includes inverters 1206 to 1208, 1216 and 1218, transfer gates 1210 to 1215, and NAND gate 1217, and the 3-bit sector address signal Sector Address <0 output from the address selection circuit 210. >, <1>, <2> and the flag signal twins <7> output from the flag signal generation circuit 211 are input. The gates of the transfer 1210 to 1215 are driven by the flag signal twins <7> to control the path of the sector selection signal.

  In the complementary cell mode, that is, when the flag signal is at the H level, the sector address signal “000” is input to the NAND gate 1217 via the inverters 1206 to 1208 and the transfer gates 1211, 1213 and 1215, and as a result, the inverter The sector selection signal Sector Select <7> of the sector Sector 7 output from 1218 becomes H level. That is, when the sector address signal “000” is input to the circuits of FIGS. 12A and 12B, in the complementary cell mode, the sector Sector 0 is selected and the sector Sector 7 is also selected.

  On the other hand, in the single-phase cell mode, that is, when the flag signal is at the L level, the sector address signal “000” is input to the NAND gate 1217 via the transfer gates 1210, 1212, and 1214, and as a result, from the inverter 1218. The sector selection signal Sector Select <7> of the sector Sector 7 to be output becomes L level. That is, in the single-phase cell mode, the sector Sector 7 is not selected.

  In the first embodiment, the sector control circuit 212 for the sectors Sectors 1 to 3 is set when the combination of sector address signals corresponding to each sector is input to the sector control circuit 212 in FIG. In this circuit, the presence or absence of the inverters 1201 to 1203 is changed so that all the input signals of the NAND gate 1204 are at the H level. The sector control circuit 212 for the sectors Sectors 4 to 6 has the flag signal twins set to H when the sector address signal of the lower sector of the sector group to which each sector belongs is input to the sector control circuit 212 in FIG. When the level (complementary cell mode), all the input signals of the NAND gate 1217 are H level, and when the flag signal twins is L level (single phase cell mode), the input signals of the NAND gate 1217 are all L level. This is a circuit in which the arrangement (inverter or lower side) of the inverters in the regions 1224 to 1226 is changed.

  In this way, when the lower sector is selected in the complementary cell mode, the corresponding upper sector is simultaneously selected.

  Next, the memory cell array in the first embodiment will be described. FIG. 13 is a diagram showing the memory cell array in the first embodiment.

  FIG. 13 (1) shows that a plurality of global bit lines GBL that vertically traverse each sector Sector 0 to 7 of the memory cell array 217 are connected to the write amplifier 219 and the read amplifier 220 via the column switch 218. . The global bit lines GBL can be roughly divided into two types, those connected to the local bit lines of the lower sector and those connected to the local bit lines of the upper sector, and are arranged alternately on the memory cell array. As described with reference to FIG. 2, the column switch 218 selects the corresponding global bit line GBL based on the global bit line selection signal YSEL output from the Y control circuit 215, and sends it to the write amplifier 219 or the read amplifier 220. Connecting.

  FIG. 13B is an enlarged view of a part of the configuration of the sectors Sector 3 and 4 included in the area 1301 of FIG. The memory cell array 217 has a stack / gate type memory cell 1302 as one unit and is arranged in a matrix in the row direction and the column direction. The memory cell array 217 includes a plurality of global bit lines GBL, a plurality of local bit lines LBL, a plurality of word lines WL, a source line SL, and a column selection line SSEL. The global bit line GBL is connected to the local bit line LBL via transistor groups 1303 and 1304 whose gates are the column selection line SSEL driven by the local bit line selection signal LBSEL. The memory cell 1302 has a control gate, a floating gate, a drain, and a source. The word line WL is connected to the control gate, the drain is connected to the local bit line LBL, and the source is connected to the source line SL. . For example, when programming the memory cell 1302, the source line SL is grounded, a high voltage (about 9V) is applied to the word line BL, a write voltage (about 5V) is applied to the local bit line, and electrons are injected into the floating gate. The program state is set to “0”. When erasing the memory cell 902, a low voltage (about -9V) is applied to the word line WL, a high voltage (about 9V) is applied to the well of the memory cell, and the local bit line and the source line are brought into a floating state. , Electrons are extracted from the floating gate, and the erased state is set to “1”.

  As described above, the memory cell array 217 has a plurality of global bit lines GBL, local bit lines LBL, source lines SL, and word lines WL, and data is written to or erased from the stacked gate type memory cells.

  As shown in FIG. 2, the write amplifier 219 performs a program operation for writing data to the memory cell array 217 and batch erasing, and the read amplifier 220 reads data from the memory cell array 217. The write amplifier 219 and the read amplifier 220 receive data by the upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, the reference cell selection signal / twin, and the complementary output control signal / RAoutH output from the amplifier control circuit 216. The path is controlled. Therefore, the read amplifier 220, the write amplifier 219, and the amplifier control circuit 216 will be described below with reference to FIGS.

  FIG. 14 is a diagram showing a lead path in the first embodiment. FIG. 14 shows a read path when reading from the memory cell 1401 of the sector Sector3 or the memory cell 1402 of the sector Sector4.

  The read amplifier 220 is connected to the column switch 218 via the data bus DB, and includes a read path switching circuit 1411 and a comparator circuit 1416.

  The read path switching circuit 1411 includes a transistor 1407 whose gate is driven by a lower sector selection signal LSEL, a transistor 1408 whose gate is driven by an upper sector selection signal USEL, and a transistor 1409 whose gate is driven by a complementary path selection signal twin. , A transistor 1410 whose gate is driven by a reference cell selection signal / twin. The upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, and the reference cell selection signal / twin will be described later with reference to FIG. The transistor 1410 is a reference in which an intermediate voltage between the threshold voltage in the programmed state and the threshold voltage in the erased state of the memory cell is set to the threshold voltage via the transistor 1406 that is turned on with a predetermined voltage applied to the gate. A reference cell RC1 having a memory cell 1403 is connected.

  The comparator circuit 1416 includes a comparator 1412, a transistor 1413 whose gate is driven by a read amplifier enable signal RAen, and transistors 1414 and 1415 whose gates are driven by a complementary output control signal / RAoutH. The complementary output control signal / RAoutH will be described later with reference to FIG.

  The column switch 218 is connected to the sector sectors Sector 3 and 4 through the global bit line GBL.

  The local bit line LBL which is the drain of the memory cells 1401 and 1402 of the sectors Sector 3 and 4 is connected to the global bit line GBL via the transistors 1404 and 1405 whose gate is the column selection line SSEL driven by the local bit line selection signal LBSEL. Connecting.

  When reading the memory cell 1401 in the sector Sector3, in the single-phase cell mode, the column selection line SSEL of the gate of the transistor 1404 in the sector Sector3 is set to H level, and the transistor 1404 is turned on. In addition, the lower sector selection signal LSEL is set to the H level, the upper sector selection signal USEL is set to the L level, the complementary path selection signal twin is set to the L level, and the reference cell selection signal / twin is set to the H level by the amplifier control circuit of FIG. As a result, the transistor 1407 of the lead path switching circuit 1411 is turned on, the drain of the memory cell 1401 is connected to the negative terminal of the comparator 1412, the transistor 1406 of the reference cell RC1 and the transistor 1410 of the lead path switching circuit 1411 are turned on, and the memory cell The drain of 1403 is connected to the plus terminal of the comparator 1412. As described above, in the single-phase cell mode, the comparator 1412 compares the current of the memory cell in the sector Sector3 with the current of the reference cell RC1.

  On the other hand, in the complementary cell mode, the column selection line SSEL of the gate of the transistor 1404 in the sector Sector 3 is H level and the transistor 1404 is turned on, and the column selection line SSEL of the gate of the transistor 1405 in the sector Sector 4 paired with the sector Sector 3 is also H level. The transistor 1405 is turned on. In addition, the lower sector selection signal LSEL is set to the H level, the upper sector selection signal USEL is set to the L level, the complementary path selection signal twin is set to the H level, and the reference cell selection signal / twin is set to the L level by the amplifier control circuit of FIG. As a result, the transistor 1407 of the lead path switching circuit 1411 is turned on, and the drain of the memory cell 1401 is connected to the negative terminal of the comparator 1412. Further, the transistor 1405 of the sector Sector 4 and the transistor 1409 of the read path switching circuit 1411 are turned on, and the drain of the memory cell 1402 is connected to the plus terminal of the comparator 1412. As described above, in the complementary cell mode, the current of the memory cell in the sector Sector 3 is compared with the current of the memory cell in the sector Sector 4 by the comparator 1412.

  When the memory cell 1401 in the sector Sector 3 is read, the complementary output control signal / RAoutH is set to the H level by the amplifier control circuit shown in FIG. 16 described later in both the single-phase cell mode and the complementary cell mode. Therefore, when the read enable signal becomes H level, the comparison result is output from the comparator 1412.

  When reading the memory cell 1402 of the sector Sector4, the transistor 1405 is turned on in the single-phase cell mode. In addition, the lower sector selection signal LSEL is at the L level, the upper sector selection signal USEL is at the H level, the complementary path selection signal twin is at the L level, the reference cell selection signal / twin is at the H level, and the complementary output by the amplifier control circuit of FIG. Control signal / RAoutH is at H level. That is, the comparator 1412 outputs a comparison result between the current of the memory cell in the sector Sector4 and the current of the reference cell RC1.

  On the other hand, in the complementary cell mode, the complementary output control signal / RAoutH becomes L level by the amplifier control circuit of FIG. Therefore, regardless of the comparison result between the sectors Sector 3 and 4 by the comparator 1412, the output becomes the H level. This is because the output is always set to the H level because reading the upper sector in the complementary cell mode is an erroneous reading.

  As described above, in FIG. 14, in the single-phase cell mode, the lower sector selection signal LSEL or the upper sector selection signal USEL is H level, the complementary path selection signal twin is L level, and the reference cell selection signal / twin is H level. , The lower sector or the upper sector is compared with the reference cell.

  On the other hand, in the complementary cell mode, the lower sector selection signal LSEL is at the H level, the upper sector selection signal USEL is at the L level, the complementary path selection signal twin is at the H level, and the reference cell selection signal / twin is at the L level. The sector is compared. However, in the complementary cell mode, when the upper sector is read, it is an erroneous reading, so the complementary output control signal / RAoutH is set to L level and the comparison result is always set to H level.

  FIG. 15 is a diagram showing a program path in the first embodiment. FIG. 15 shows a program path for programming the memory cell 1501 in the sector Sector3 or the memory cell 1502 in the sector Sector4.

  The write amplifier 219 includes a program path switching circuit 1511 and a program amplifier 1512 that amplifies the write data DI, and is connected to the column switch 218 via the data bus DB.

  Program amplifier 1512 receives the output of NOR gate 1513 that receives write data DI and program clock signal / PGMCK.

  The program path switching circuit 1511 is driven by an inverter 1510, transistors 1508 and 1509 for driving gates by a write command PGM, a transistor 1505 for driving gates by a lower sector selection signal LSEL, and a gate by an upper sector selection signal USEL. And a transistor 1507 whose gate is driven by a complementary path selection signal twin.

  The column switch 218 is connected to the sector sectors Sector 3 and 4 via the global bit line GBL, as in FIG.

  The local bit line LBL which is the drain of the memory cells 1501 and 1502 of the sectors Sector 3 and 4 is connected to the global bit line GBL via the transistors 1503 and 1504 whose gates are the column selection lines SSEL driven by the local bit line selection signal LBSEL. Connecting.

  In the single-phase cell mode, when programming the memory cell 1501 of the sector Sector3, the lower sector selection signal LSEL is H level, the upper sector selection signal USEL is L level, and the complementary path selection signal is L level. Then, the transistor 1503 in the sector Sector 3 and the transistor 1505 in the program path switching circuit 1505 are turned on, the transistors 1506 and 1507 are turned off, and the program amplifier 1512 writes the write data DI (0 or 1) to the drain of the memory cell 1501 in the sector Sector 3. ), A high potential or a low potential is applied and the program or erase state is left. On the other hand, when programming the memory cell 1502 of the sector Sector4, the lower sector selection signal LSEL is L level, the upper sector selection signal USEL is H level, and the complementary path selection signal is L level. Then, the transistor 1504 in the sector Sector 4 and the transistor 1506 in the program path switching circuit 1505 are turned on, the transistors 1505 and 1507 are turned off, and the program amplifier 1512 writes the write data DI (0 or 1) to the drain of the memory cell 1502 in the sector Sector 4. ), A high potential or a low potential is applied and the program or erase state is left.

  In the complementary cell mode, the lower sector selection signal LSEL is H level, the upper sector selection signal USEL is L level, and the complementary path selection signal twin is H level. Then, the transistor 1503 of the sector Sector 3 and the transistors 1505 and 1507 of the program path switching circuit 1505 are turned on, the transistor 1506 is turned off, and not only the memory cell 1501 but also the memory cell 1502 is connected to the program amplifier 1512. As a result, the memory cells 1501 and 1502 are left in the programmed or erased state according to the write data DI (0 or 1).

  As described above, in FIG. 15, in the complementary cell mode, the lower sector selection signal LSEL and the complementary path selection signal twin become H level, and the write data DI is programmed in the lower sector and the inverted data is programmed in the upper sector. In the single-phase cell mode, the lower sector selection signal LSEL or the upper sector selection signal USEL becomes H level, and the write data DI is programmed in the lower or upper sector.

  FIG. 16 is a diagram illustrating an amplifier control circuit according to the first embodiment. An amplifier control circuit 216 is provided for each of the sectors Sectors 4-7. In FIG. 16, an amplifier control circuit for the sector Sector4 is shown.

  The amplifier control circuits of the sectors Sector 4 to 7 receive the sector address signals Sector Address <0> to <2> and the flag signals twins <4> to <7>, respectively. Then, through the circuit shown in FIG. 16, the amplifier control circuit 216 receives the upper sector selection signal USEL, the lower sector selection signal LSEL that is an inverted version of the upper sector selection signal USEL, the complementary path selection signal twin, and the complementary path selection. A reference cell selection signal / twin, which is a negative OR of the signal twin and the write command PGM, and a complementary output control signal / RAoutH are output. These signals are used for program path / read path control by the write amplifier 219 and the read amplifier 220 as described with reference to FIGS.

  The amplifier control circuit of the sector Sector 4 in FIG. 16 includes inverters 1601 to 1602, 1604 to 1606, 1608, 1609, 1617, and 1619, NAND gates 1603, 1607, 1610 to 1616, and a NOR gate 1618. Among these, NAND gates 1614 to 1616, inverters 1617 and 1619, and NOR gate 1618 are shared among the amplifier control circuits of Sectors 4 to 7.

  The amplifier control circuits of sectors Sectors 5 to 7 have the same circuit configuration as inverters 1604 to 1606, 1608, and 1609 and NAND gates 1603, 1607, and 1610 to 1613, and sector addresses for selecting the respective sectors. When signals Sector Address <0> to <2> are input to amplifier control circuit 216, inverters are arranged in regions 1620 and 1621 so that all three inputs of the NAND gate corresponding to NAND gate 1603 are at H level. Or a circuit that does not. For example, in the case of sector Sector 4, since the sector address signal is “100”, inverters 1601 and 1602 are provided for sector address signals Sector Address <0> and <1>.

  The NAND gate 1614 outputs a negative logical product of the output of the NAND gate 1611 and the outputs from the NAND gates of the sectors Sectors 5 to 7 corresponding to the NAND gate 1611 as the upper sector selection signal USEL.

  Similarly, the NAND gates 1615 and 1616 complement the NAND of the outputs of the NAND gates 1612 and 1613 and the outputs from the NAND gates of the sectors Sectors 5 to 7 corresponding to the NAND gates 1612 and 1613 with the complementary path selection signal twin. Output as an inverted signal of the output control signal / RAoutH.

  As an example, the output of each signal when the sector address signal “100” of the sector Sector4 is input to the amplifier control circuit 216 shown in FIG. 16 will be described below.

  When SectorAddress <0> = “0”, SectorAddress <1> = “0”, SectorAddress <2> = “1” is input, the sector address signal corresponding to the amplifier control circuit for sector Sector4 is input. , The output of the inverter 1608 becomes H level. Therefore, it can be considered that the output of the NAND gate 1611 is controlled by the flag signal twins <4>. Specifically, if flag signal twins <4> is at L level (single-phase cell mode), the output of NAND gate 1611 is H level, and if flag signal twins <4> is at H level (complementary cell mode), L Become a level. On the other hand, the outputs of the NAND gates corresponding to the NAND gate 1611 in the amplifier control circuits of the sectors Sectors 5 to 7 are all at the H level. Therefore, when the sector address signal “100” is input to the amplifier control circuit 216, if the flag signal twins <4> is L level (single-phase cell mode), the upper sector selection signal USEL is H level and the lower sector selection signal LSEL becomes L level. On the other hand, when the flag signal twins <4> is at the H level (complementary cell mode), the upper sector selection signal USEL is at the L level and the lower sector selection signal LSEL is at the H level.

  The NAND gate 1612 receives the output of the NAND gate 1610 and the flag signal twins <4>. When the sector address signal “100” is input, the output of the NAND gate 1610 becomes the H level, so that the output of the NAND gate 1612 can be regarded as being controlled by the flag signal twins <4>. Specifically, if the flag signal twins <4> is L level (single-phase cell mode), the output of the NAND gate 1609 is H level, and if the flag signal twins <4> is H level (complementary cell mode), L Become a level. On the other hand, the outputs of the NAND gates corresponding to the NAND gate 1612 in the amplifier control circuits of the sectors Sectors 5 to 7 are all at the H level. Therefore, when the sector address signal “100” is input to the amplifier control circuit 216, if the flag signal twins <4> is at L level (single phase cell mode), the complementary path selection signal twin is at L level. Conversely, when the flag signal twins <4> is at the H level (complementary cell mode), the complementary path selection signal twin is at the H level.

  The output of the inverter 1608 and the flag signal twins <4> are input to the NAND gate 1613. When the sector address signal “100” is input, since the output of the inverter 1608 is at the H level, the output of the NAND gate 1613 can be regarded as being controlled by the flag signal twins <4>. Specifically, if flag signal twins <4> is at L level (single-phase cell mode), the output of NAND gate 1613 is H level, and if flag signal twins <4> is at H level (complementary cell mode), NAND is output. The output of gate 1610 is at L level. On the other hand, the outputs of the NAND gates corresponding to the NAND gate 1613 in the amplifier control circuits of the sectors Sectors 5 to 7 are all at the H level. Therefore, when the sector address signal “100” is input to the amplifier control circuit 216, if the flag signal twins <4> is L level (single-phase cell mode), the output of the NAND gate 1616 is L level, that is, complementary output control. Signal / RAoutH is at H level. On the other hand, when flag signal twins <4> is at the H level (complementary cell mode), the output of NAND gate 1616 is at the H level, that is, complementary output control signal / RAoutH is at the L level. The above output results are summarized in FIG. 17 together with the output of each signal when the sector address signal “011” of the sector Sector3 is input.

  FIG. 17 is a diagram illustrating a truth table of the amplifier control signal in the first embodiment. When sector Sector 3 is selected, the lower sector selection signal LSEL is H level and the reference cell selection signal / twin is H level in the single-phase cell mode, and the lower sector selection signal LSEL is H level in the complementary cell mode. The complementary path selection signal twin becomes H level. On the other hand, when sector Sector 4 is selected, the upper sector selection signal HSEL is H level and the reference cell selection signal / twin is H level in the single-phase cell mode, which is an undesirable access in the complementary cell mode. Complementary output control signal / RAoutH is at L level. That is, as described with reference to FIG. 14, when the flag signal twins <4> is at the H level (complementary cell mode), when there is a read request for the sector Sector4 (sector address signal “100”), the request is made. Is an erroneous read request, the transistor 1414 is turned off and the transistor 1415 is turned on by the L level complementary output control signal / RAoutH, so that the output of the read amplifier 220 is always set to the erased state “1”.

  As described above, the amplifier control circuit 216 complements the upper sector selection signal USEL, the lower sector selection signal LSEL, the complementary path selection signal twin, the cell selection signal / twin based on the input sector address signal. Output control signal / RAoutH is output. Further, the program path and the read path are controlled as shown in FIGS. 14 and 15 in the write amplifier 219 and the read amplifier 220 by these signals.

  As described above, in the first embodiment, when the addresses are input in ascending order of sector numbers, the input data DI is first written in the complementary cell mode sequentially to the lower sector and the upper sector of the pair, and the upper sector is then written. After the writing occurs, the mode is switched to the single-phase cell mode, and the input data is written to the upper sector. Until the input data DI is written in the highest sector, data is stored in the complementary cell mode with the lowest sector of the pair, so data that requires reliability must be written in the lowest sector. Is effective.

[Second Embodiment]
In the second embodiment, the order of writing is not the ascending order of the sector numbers, and the lower order belonging to the sector group corresponding to the input external address signals FA00 to 20 regardless of the order of writing. According to the sector status data of the upper sector, writing is performed in either the complementary cell mode or the single-phase cell mode. And in response to a write request to the upper sector, writing is performed in the complementary cell mode or single-phase cell mode. Therefore, when high reliability is required for the data, the write data DI is written in the complementary cell mode to any sector of the sector group in which both the lower and upper sectors are in the batch erase state. Thereafter, the flash memory can hold highly reliable data by not making a write request to the sector in which the inverted data is written.

  FIG. 18 is a flowchart showing the operation of the semiconductor memory device according to the second embodiment. In FIG. 18, as an example, write requests are made to the flash memory at the time of shipment in the order of sectors Sector 6, 3, 7, 2, 4, 0, 1, 5.

  When a write request is made to the sector Sector 6 which is the upper sector of the sector group SG1 (S1801), the sector state memory access control circuit 207 determines the complementary cell mode based on the sector state data of the sectors Sector 6 and 1, and As a result, the write data DI is written in the sector Sector6 and the inverted data is written in the sector Sector1 (S1802). Then, the sector state data of the sector Sector 6 held in the sector state memory 206 is in a write state.

  Similarly, by performing the write operation of the write data DI on the sectors Sector 3, 7 and 2 in order (S1803 to S1808), the write data DI is stored in the sectors Sector 3, 7 and 2, and the Sectors 4, 0 and 5 are stored. The inverted data is written.

  Thus, when step S1808 is completed, write data is written in the lower sectors Sector 2 and 3 and upper sectors Sector 6 and 7, and inverted data is written in the lower sectors Sector 0 and 1 and upper sectors 4 and 5.

  Following step S1808, when there is a write request to sector Sector4, which is the upper sector of sector group 3 (S1809), sector state memory access control circuit 207 determines the single-phase cell based on the sector state data of sectors Sector4,3. The mode is determined. As a result, a write operation for setting all memory cells in the erase state “1” to the program state “0” and a batch erase operation for setting all memory cells to the erase state “1” are performed on the sector Sector4. Then, based on the write command PGM output from the command generation circuit 201, the write data DI is written to the sector Sector4 in the single-phase cell mode (S1810). Then, the sector state data of the sector Sector 4 stored in the sector state memory 205 is in a write state.

  Thereafter, the write operation is performed in the same manner for the sectors Sector 0, 1, 5 (S1811-1816), whereby the write data DI is stored in the sectors Sector 0-7 in the single-phase cell mode.

  As described above, in the second embodiment, sectors can be selected in an arbitrary order, and the write method of the write data DI is determined based on the sector status data of the lower and upper sectors. Therefore, unlike the first embodiment, the inverted data of the write data DI may be written in the lower sector.

  Then, the transition of the determination result of the sector state memory access control circuit 207 in the lower sector and the upper sector of one sector group will be described with reference to FIG.

  FIG. 19 is a diagram illustrating sector states of the lower sector and the upper sector in the second embodiment.

  FIG. 19 starts from the initial state (S1901). Up to step 1907, as in steps S402 to S407 in FIG. 4, a write request and batch erase request are made to the lower and upper sectors, and the write method is determined (S1902 to S1907).

  Subsequent to step S1907 in which both the lower and upper sectors are in the initial state, when a write command PGM is generated for the upper sector (S1908), the sector state memory access control circuit 207 determines the sector status signals of the lower and upper sectors. And the flag signal generation circuit 211 outputs an H level flag signal twins. Then, the sector status data of the upper sector changes from the batch erase state to the write state, the sector status signal of the upper sector outputs an H level sector status signal, and the lower sector outputs an L level sector status signal. .

  Next, when the write command PGM is generated for the lower sector (S1909), the sector state memory access control circuit 207 determines that the mode is the single-phase cell mode, and the flag signal generation circuit 211 outputs the L level flag signal twins. The Then, the sector status data of the lower sector changes from the batch erase state to the write state, and a sector status signal of H level is output from the sector status memory of the lower sector, and an H level sector status signal is output from the sector status memory of the upper sector.

  When the batch erase command ERS is generated for the upper sector and the lower sector from the state of step S1909 (S1910, S1911), the sector state memory access control circuit 207 determines that the single-phase cell mode is used in both S1910 and S1911. The flag signal twins output from the flag signal generation circuit 211 remains at the L level. Then, the sector status data of the upper sector and the lower sector sequentially change from the write state (H level) to the batch erase state (L level).

  Further, when the write command PGM is generated for the lower sector from the state of step S1911 (both the output of the sector state memory is at L level) in which both the lower and upper sectors are in the initial state (S1912), the sector state memory access control The circuit 207 determines the complementary cell mode, and the flag signal twins is switched to the H level. Then, the sector status data of the lower sector changes from the batch erase state to the write state, and the sector status signal of the sector status memory of the lower sector becomes H level.

  Thus, in the second embodiment, one of the sector status signals is changed to the H level (write state) from the state where the sector status signals of the lower sector and the upper sector are both at the L level (collective erase state). In this case, the sector state memory access control circuit 207 determines that the complementary cell mode is selected, and the flag signal twins output thereby becomes H level. That is, the write method is determined based on the sector status data of the sector and the paired sector. Therefore, reliable data is written in an arbitrary sector in complementary cell mode, and thereafter, writing to that sector and its paired sector is not performed, so that reliable data is retained in an arbitrary sector. It is possible.

  Next, the write method determination operation in the second embodiment will be described. FIG. 20 is a diagram illustrating a write mode determination operation according to the second embodiment. In the second embodiment, as described in FIG. 19, when a lower sector and an upper sector belonging to the same sector group are in a batch erase state, if there is a write request in either the lower or upper sector, Writing to the lower and upper sectors is performed in the complementary cell mode. Therefore, in FIG. 20, an upper sector single-phase complementary memory 2005 and a latch circuit 2007 are further provided as compared with FIG. As in the first embodiment, in the second embodiment, the sector state memory 206 and the flag signal generation circuit 211 are provided for each sector group.

  The sector state data in both sector state memories 2001 and 2002 are rewritten to the respective states in response to the write command PGM and the batch erase command ERS. The sector status signals c1outL and c1outU output from the sector status memories 2001 and 2002 are supplied to the sector status memory access control circuit 207. Similarly to FIG. 5, the program enable signal c2PGMan for the single-phase complementary memory is supplied to the sector state memory access control circuit 207.

  The lower sector single-phase complementary memory 2004 and the upper sector single-phase complementary memory 2005 are stored in both the sector state memories 2001 and 2002 when the address signal AD and the write command PGM or the batch erase command ERS are supplied from the operation control circuit 208. A memory for storing single-phase complementary determination data indicating a determination result of the single-phase cell mode or the complementary cell mode based on the sector state data. Both single-phase complementary memories 2004 and 2005 output single-phase complementary determination signals c2outL and c2outU of H level (complementary cell mode) or L level (single-phase cell mode).

  For example, when the write command PGM is generated for the lower sector in the initial state (sector state signals c1outL and c1outU are both at L level (batch erase state)), that is, the program enable signal c2PGMan is at H level, The memory access control circuit 207 changes the single-phase complementary determination data of the lower sector single-phase complementary memory 2004 from L level (single-phase cell mode) to H level (complementary cell mode). On the other hand, the upper sector single-phase complementary memory 2005 maintains the L level (single-phase cell mode). Then, the sector state signal c1outL of the lower sector state memory 2001 becomes H level (write state) in response to the write command PGM. From this state, when either the batch erase command ERS is generated for the lower sector or the write command PGM is generated for the upper sector, the sector state memory access control circuit 207 The single-phase complementary determination data in the sector single-phase complementary memory 2004 is changed from H level (complementary cell mode) to L level (single-phase cell mode). At this time, the single-phase complementary determination data in the upper sector single-phase complementary memory 2005 remains L (single-phase cell mode).

  Contrary to the above example, when the write command PGM is generated for the upper sector in the initial state, the single-phase complementary determination data in the upper-sector single-phase complementary memory 2005 changes from L level (single-phase cell mode) to H Although the level (complementary cell mode) is set, the single-phase complementary determination data in the lower sector single-phase complementary 2004 memory maintains the L level (single-phase cell mode). Then, the sector state signal c1outU of the upper sector state memory 2002 becomes H level (write state) in response to the write command PGM. From this state, when either the batch erase command ERS is generated for the upper sector or the write command PGM is generated for the lower sector, the single unit of the upper sector single-phase complementary memory 2005 is stored. The phase complement determination data changes from H level (complementary cell mode) to L level (single phase cell mode). At this time, the single-phase complementary determination data in the lower sector single-phase complementary memory 2004 remains L (single-phase cell mode).

  In response to the rise of the control clock signal ControlCLK, the flag signal generation circuit 211 latches the single-phase complementary determination signals c2outL and c2outU of the single-phase complementary memories 2004 and 2005 by the latch circuits 2006 and 2007, and each flag signal twins is latched. Output. The control clock signal ControlCLK is generated by the operation control circuit 208 in response to the OR signal, as in FIG. The latch circuits 2006 and 2007 are reset in response to the power-on reset signal POR, as in FIG.

  The flag signal twins is output as two types of signals for each sector group. The flag signals twins <4> to <7> output from the latch circuit 2006 represent the writing schemes of the sectors Sector 4, 5, 6, and 7 for the sectors Sector 3, 2, 1, and 0, respectively. Further, flag signals twins <0> to <3> output from the latch circuit 2007 represent the writing methods of the sectors Sector 0, 1, 2, and 3 with respect to the sectors Sector 7, 6, 5, and 4, respectively.

  For example, when the sector status signals of the sectors Sector0 and Sector7 are at the L level (batch erase status), if there is a write request to the sector Sector0, the single-phase complementary determination signal c2outL of the lower sector single-phase complementary memory 2004 is H Level (complementary cell mode). As a result, the flag signal twins <7> of the sector Sector7 changes from the L level (single phase cell mode) to the H level (complementary cell mode). At this time, the flag signal twins <0> of the sector Sector0 remains at the L level (single phase cell mode).

  On the other hand, when the sector status signals of the sectors Sector0 and Sector7 are at the L level (batch erase state), if there is a write request to the sector Sector7, the single-phase complementary determination signal c2outU of the upper sector single-phase complementary memory 2005 is H Level (complementary cell mode). As a result, the flag signal twins <0> of the sector Sector0 changes from the L level (single phase cell mode) to the H level (complementary cell mode). At this time, the flag signal twins <7> of the sector Sector 7 remains at the L level (single phase cell mode).

  In this manner, the sector state memory access control circuit 207 determines the single-phase or complementary cell mode based on the sector state data of the lower sector and the upper sector.

  FIG. 21 is a waveform diagram of a flag signal when a write request is made in the order of the lower sector and the upper sector when both the lower and upper sectors of the flash memory in the second embodiment are in the batch erase state. In FIG. 21, after the write command PGM is generated at times T0 and T1 in the order of the lower sector and the upper sector in the same sector group, the batch erase command ERS is generated at times T2 and T3 in the order of the lower sector and the upper sector. At T4 and T5, the write command PGM is generated in the order of the upper sector and the lower sector.

  Regarding times T0 to T3, the waveforms of the lower and upper sector status signals c1outL and c1outU, the lower sector single-phase complementary determination signal c2outL, and the flag signals twins <4> to <7> are the same as those in FIG. Further, the upper sector single-phase complementary determination signal c2outU and the flag signals twins <0> to <3> are maintained at the L level. At time T3, both sector state memories 2001 and 2002 are in the initial state.

  Based on the rise of the write command PGM for the upper sector at time T4 and the program enable signal c2PGMen (H level) for the single-phase complementary memory immediately before that, the single-phase complementary determination data in the upper sector single-phase complementary memory 2005 is at the L level. From (single phase cell mode) to H level (complementary cell mode). As a result, the single-phase complementary determination signal c2outU output from the upper sector single-phase complementary memory 2005 also changes from the L level (single-phase cell mode) to the H level (complementary cell mode). Further, in response to the rise of the write command PGM for the upper sector at time T4, the sector state signal c1outU of the sector state memory 2002 of the upper sector becomes H level, and the sector state data is in the write state. The latch circuit 2007 latches the single-phase complementary determination signal c2outL in response to the rise of the control clock signal ControlCLK at time C4, and outputs H level (complementary cell mode) flag signals twins <0> to <3>. To do.

  In response to the rise of the write command PGM for the lower sector at time T5, the single-phase complementary determination data in the upper sector single-phase complementary memory 2005 changes from H level (complementary cell mode) to L level (single-phase cell mode). As a result, the single-phase complementary determination signal c2outU also changes from the H level (complementary cell mode) to the L level (single-phase cell mode). At this time, the sector status signal c1outL of the lower sector becomes H level, and the sector status data in the lower sector status memory 2001 is in the write state. The latch circuit 2007 latches the single-phase complementary determination signal c2outL in response to the fall of the control clock signal ControlCLK at time C5, and outputs an L-level (single-phase cell mode) flag signal twins <0> to <3>. To do.

  As described above, when both the lower sector and the upper sector are in the batch erase state, the write command PGM is generated in the upper sector, so that the determination result of the upper sector single-phase complementary memory 2005 is changed from the single-phase cell mode to the complementary cell mode. Switch to Further, when the write command PGM is generated in the lower sector, the determination result of the upper sector single-phase complementary memory 2005 is switched to the single-phase cell mode. On the other hand, if the write command PGM is generated in the lower sector when both sectors are in the batch erase state, the operation is reversed.

  FIG. 22 is a waveform diagram showing the rise of each signal when the external power supply in the second embodiment is turned on. FIG. 22 (1) shows waveforms when the sector status signals c1outL and c1outU are at the H level (write state) and the single-phase complementary determination signals c2outL and c2outU are at the L level (single-phase cell mode) in both the lower sector and the upper sector. . 22 (2) shows that the sector status signal c1outL of the lower sector is H level (write state), the sector status signal c1outU of the upper sector is L level (batch erase state), and the single-phase complementary determination signal c2outL is H level ( Complementary cell mode) and c2outU are in the L level (single phase cell mode).

  22 (1) and 22 (2), as in FIGS. 8 (1) and 8 (2), when the external power supply is turned on, the flag signal twins is reset by the power-on reset signal. When the external power supply is turned on, the sector state signals c1outL and c1outU and the single-phase complementary determination signals c2outL and c2outU are in a state immediately before the external power supply is turned off. At this time, the latch circuits 2006 and 2007 latch the single-phase complementary determination signals c2outL and c2outU, respectively, and output the flag signal twins having the same voltage level as that immediately before the external power supply is turned off.

  In the second embodiment, as in the first embodiment, when inverted data is written in the complementary cell mode, the write command PGM is issued for the sector in the batch erase state or the sector in the write state. On the other hand, when the batch erase command ERS is generated, the flag signal twins becomes L level (single phase cell mode). For example, steps S1903 and 1904 in FIG. Then, after the inverted data written in the sector on the side of the sector state memory 2001, 2002 that changes from the batch erase state to the write state is erased collectively, the operation of the generated command signal is started. Therefore, as in the first embodiment, when the power of the flash memory is turned off during batch erase of inverted data, it is necessary to complete the batch erase operation of inverted data even when the power is turned on. Become. Therefore, the batch erase operation for inverted data will be described next.

  FIG. 23 is a block diagram showing generation of an internal ERS command in the second embodiment. Similarly to FIG. 9, when the flash memory is turned on, any one of the flag signals twins <0> to <7> is at the L level (single-phase cell mode), and the corresponding internal flag signal int-twins <0> If .about. <7> is at the H level (complementary cell mode), the sector state memory access control circuit 207 outputs an ERS start signal for the corresponding sector in order to resume the interrupted batch erase operation. When the batch erase operation is completed, an ERS completion signal is output from the operation control circuit 208, and the internal flag signal int-twins in the ERS sector state memory 2301 becomes L level (single phase cell mode). When the power is turned on, the sector state memory access control circuit 207 determines whether or not to output the ERS start signal based on the flag signal and the internal flag signal in response to the power-on control clock signal.

  For example, when both of the sectors Sector0 and Sector7 are in the batch erase state, the flag signal twins <0> changes from the L level (single-phase cell mode) to the H level (complementary cell mode) when there is a write request to the sector Sector7. On the other hand, the flag signal twins <7> and the internal flag signals int-twins <0>, <7> remain at the L level (single-phase cell mode). In addition, the sector state memory 2002 of the sector Sector7 switches from the batch erase state to the write state, but the sector state memory 2001 of the sector Sector0 remains in the batch erase state. Then, based on the flag signals twins <0>, <7> and the internal flag signals int-twins <0>, <7>, the sector state memory access control circuit 207 generates the internal flag control signal int-tc <0>. Output. In response to the internal flag control signal int-tc <0>, the ERS sector state memory 2301 sets the internal flag signal int-twins <0> to the H level (complementary cell mode). In response to the write request, the flash memory writes the write data DI in the sector Sector7 and the inverted data in the sector Sector0. This operation is the same as the operation at time T16 and T17 in FIG.

  Next, when there is a batch erase request in the sector Sector 7 from the complementary cell mode, the flag signal twins <0> is changed from H level (complementary cell mode) to L level (single phase cell mode). On the other hand, the flag signal twins <7> is at the L level (single phase cell mode), the internal flag signal int-wins <0> is at the H level (complementary cell mode), and the internal flag signal int-wins <7> is at the L level (single cell mode). Phase cell mode). Further, the sector state memory 2002 of the sector Sector7 is switched from the write state to the batch erase state. At this time, the inverted data in the sector Sector0 is not yet erased at once, and the inverted data is held in the sector Sector0. Therefore, the sector state memory access control circuit 207 is based on the flag signals twins <0>, <7> and the internal flag signals int-twins <0>, <7> in order to erase all the inverted data of the sector Sector0. , ERS start signal for sector Sector0 is output. Thereafter, as in FIG. 9 of the first embodiment, when the batch erase of the inverted data is completed, the operation control circuit 208 outputs an ERS completion signal for the sector Sector0 to the sector state memory access control circuit 207. In response to the ERS completion signal, the ERS sector state memory 2301 changes the internal flag signal int-twins <0> from the H level (complementary cell mode) to the L level (single phase cell mode). This is the same operation at times T11 to T14 and T19 to T22 in FIG. Further, the flash memory performs batch erase of the sector Sector 7 as a normal operation, and all cells in the sector Sector 7, 0 are in the erased state “1”.

  Contrary to the above example, in the complementary cell mode state when sector Sector0 is in the write state and sector Sector7 is in the batch erase state, the operation when there is a batch erase request to sector Sector0 has been described with reference to FIG. The operation is the same. In this case, the flag signals twins <7> and <0> and the internal flag signal int-twins <0> are at L level (single-phase cell mode), and the internal flag signal int-wins <7> is at H level (complementary cell mode). ) At this time, the inverted data in the sector Sector 7 is not yet erased at once, and the inverted data is held in the sector Sector 7. For this reason, after the inverted data of sector Sector7 is erased at once, the flash memory performs batch erase of sector Sector0 as a normal operation, and the cells in sector Sector0 and sector Sector7 are all in the erased state “1”.

  As described above, when the paired sector pair is in the complementary cell mode and the batch erase is requested for the sector in the paired sector pair, the flash memory stores the inverted data of the other sector of the pair. After all are deleted, the batch erase operation is performed on the sector for which batch erase is requested. The operation of deleting the inverted data is performed when the flag signal twins is at the L level and the internal flag signal int-twins is at the H level. Accordingly, not only in the above example, but also in the second embodiment, as in the first embodiment, (1) in the complementary cell mode, a write request is made to the sector in which inverted data is written. (2) When the power is turned off while the inverted data is being deleted and then the power is turned on, the inverted data is collectively erased in each case.

  In the second embodiment, as in the first embodiment, the sector to be written is determined based on the input sector address signal and the single-phase complementary determination result. In the single-phase cell mode, the sector corresponding to the input sector address signal is selected, and in the complementary cell mode, the paired sector is further selected. A decoder for selecting a sector will be described with reference to FIG.

  FIG. 24 is a diagram showing a sector control circuit (decoder) in the second embodiment. The circuit of FIG. 24 (1) is a circuit diagram of the sector control circuit 212 for the sector Sector0. FIG. 24 (2) is a circuit diagram of the sector control circuit 212 for the sector Sector 7 belonging to the same sector group SG0 as the sector Sector0, and is the same circuit as FIG. 12 (2). The circuit shown in FIG. 24A is a circuit obtained by changing the arrangement of the inverters 2421 to 2423 in the circuit shown in FIG.

  For example, when the input sector address signal is “111” and the flag signals twins <0>, <7> are both at the L level (single-phase cell mode), the sector selection signals Sector of the sectors Sector0, 7 Select <0> and <7> are L level and H level, respectively, and only sector Sector 7 is selected. On the other hand, that is, when the flag signals twins <0> and <7> are at the H level (complementary cell mode) and the L level (single phase cell mode), respectively, the sector selection signals Sector Select <0>, Both <7> are at the H level, and both sectors Sector 0 and 7 are selected.

  As described above, in the complementary cell mode, when one sector is selected, the paired sector is also selected simultaneously.

  As in the first embodiment, the sector control circuit 212 for the sectors Sectors 1 to 3 has a NAND cell 2411 input in the complementary cell mode (corresponding flag signal twins <1>) in the circuit of FIG. ~ <3> is at H level) and inverters in regions 2413 to 2415 are all at L level in single-phase cell mode (corresponding flag signals twins <1> to <3> are at L level). The circuit is arranged on the upper side or the lower side. Similarly, in the sector control circuit 212 for the sectors Sector 4 to 6, in the circuit of FIG. 24 (2), the input of the NAND gate 2431 is in the complementary cell mode (the corresponding flag signals twins <4> to <6> are at the H level. ) In all regions 2433 to 2435 so that they are all at the H level and in the single-phase cell mode (the corresponding flag signals twins <4> to <6> are at the L level) are all at the L level. Circuit.

  As shown in FIG. 2, the write amplifier 219 and the read amplifier 220 are similar to the first embodiment in that the upper sector selection signal USEL, the lower sector selection signal LSEL, and the complementary path selection signal twin output from the amplifier control circuit. The program path and the read path are controlled by the reference cell selection signal / twin and the complementary output control signal / RAoutH. However, in the second embodiment, the complementary path selection signal twin is classified into an upper complementary path selection signal twinU and a lower complementary path selection signal twinL. The upper complementary path selection signal twinU is a signal for controlling a read path and a program path to the lower sector when inverted data is held in the lower sector. The lower complementary path selection signal twinL is a signal for controlling a read path and a program path to the upper sector when inverted data is held in the upper sector. The description of each signal will be described later with reference to FIGS. Hereinafter, the read amplifier 220, the write amplifier 219, and the amplifier control circuit 216 will be described in order with reference to FIGS.

  FIG. 25 is a diagram showing a lead path in the second embodiment. FIG. 25 shows a read path when reading from the memory cell 2501 of the sector Sector3 or the memory cell 2502 of the sector Sector4.

  Similar to FIG. 14 of the first embodiment, the read amplifier 219 is connected to the column switch 218 via the data bus DB, and includes a read path switching circuit 2512 and a comparator circuit 2517. However, unlike FIG. 14, the read path switching circuit 2512 includes a transistor 2509 whose gate is driven by the upper complementary path selection signal twinU and a transistor 2510 whose gate is driven by the lower complementary path selection signal twinL. Because of the presence of these two transistors 2509 and 2510, when the write data DI is written to the memory cell 2501, not only the memory cell 2501 is read in the complementary cell mode, but also the write data DI is written to the memory cell 2502. In addition, the memory cell 2502 can be read in the complementary cell mode. The operation in the complementary cell mode will be specifically described below with two examples.

  First, the write data DI is written in the memory cell 2501 of the sector Sector 3 and the inverted data is written in the memory cell 2502 of the sector Sector 4 in the complementary cell mode. When reading the memory cell 2501, the lower sector selection signal LSEL is H level, the upper sector selection signal USEL is L level, the upper complementary path selection signal twinU is L level, the lower complementary path selection signal twinL is H level, and the reference cell selection signal / Twin is at L level and the complementary output control signal / RAoutH is at H level. That is, in the lead switching circuit 2512, the transistors 2507 and 2510 are turned on, and the transistors 2508, 2509, and 2511 are turned off. Sectors Sector 3 and 4 are connected to the negative input terminal and the positive input terminal of comparator 2513, respectively, and the currents of memory cells 2501 and 2502 are compared by comparator 2513.

  Next, in the complementary cell mode, the write data DI is written in the memory cell 2502 in the sector Sector4 and the inverted data is written in the memory cell 2501 in the sector Sector3. When reading the memory cell 2502, the lower sector selection signal LSEL is L level, the upper sector selection signal USEL is H level, the upper complementary path selection signal twinU is H level, the lower complementary path selection signal twinL is L level, and the reference cell selection signal / Twin is at L level and the complementary output control signal / RAoutH is at H level. That is, in the lead switching circuit 2512, the transistors 2508 and 2509 are turned on, and the transistors 2507, 2510, and 2511 are turned off. The sectors Sector 3 and 4 are connected to the plus terminal and the minus terminal of the comparator 2513, respectively, and the currents of the memory cells 2501 and 2502 are compared by the comparator 2513.

  In any case, in the comparator circuit 2517, the transistor 2515 is turned on, the transistor 2516 is turned off, and the transistor 2514 is turned on when the read enable signal becomes H level, and the comparison result is output from the comparator 2513.

  In the above two cases, when reading the memory cell in which the inverted data of the write data DI is written in the complementary cell mode, the complementary output control signal / RAoutH becomes L level, the transistor 2516 is turned on, and the transistor 2514 is turned on. Since it is turned off, the output of the comparator circuit 2517 becomes H level. This is because reading the inverted data in the complementary cell mode is an erroneous reading, so that the output is always at the H level, that is, the erased state “1”.

  On the other hand, in the case of the single-phase cell mode, the comparator 2513 compares the current of the memory cell in the selected sector with the current of the reference cell RC1, as in FIG. Specifically, when reading the memory cell 2501 of the sector Sector3, the transistors 2507 and 2511 are turned on, the memory cell 2501 is connected to the negative terminal of the comparator 2513, and the transistor 2503 of the reference cell RC1 is connected to the comparator 2513 as a positive terminal. Connect to. Then, the current of the memory cell 2501 in the sector Sector3 is compared with the current of the reference cell RC1. When reading the memory cell 2502 of the sector Sector4, the transistors 2508 and 2511 are turned on, the memory cell 2502 is connected to the negative terminal of the comparator 2513, and the transistor 2503 of the reference cell RC1 is connected to the positive terminal of the comparator 2513. . Then, the current of the memory cell 2502 in the sector Sector4 is compared with the current of the reference cell RC1.

  As described above, in FIG. 25, the paired lower sector and the upper sector are compared in the complementary cell mode, and the lower sector or the upper sector and the reference cell are compared in the single-phase cell mode. However, in the complementary cell mode, when the sector holding the inverted data is read out, it is an erroneous reading, so the comparison result is always at the H level.

  FIG. 26 is a diagram illustrating a program path in the second embodiment. FIG. 26 shows a program path for programming the memory cell 2601 of the sector Sector3 or the memory cell 2602 of the sector Sector4.

  The write amplifier 219 includes a program path switching circuit 2612 and a program amplifier 2613 that amplifies the write data DI, and is connected to the column switch 218 via the data bus DB, as in FIG. 15 of the first embodiment. . However, unlike FIG. 15, the program path switching circuit 2612 has a transistor 2607 whose gate is driven by the upper complementary path selection signal twinU and a transistor 2608 whose gate is driven by the lower complementary path selection signal twinL. Yes.

  In the complementary cell mode, when programming into the memory cell 2601 of the sector Sector3, the lower sector selection signal LSEL and the lower complementary path selection signal twinL become H level. That is, the transistors 2605 and 2608 are turned on, and the memory cells 2601 and 2602 are connected to the program amplifier 2613. Then, write data is programmed in the memory cell 2601 and inverted data of the write data is programmed in the memory cell 2602. When programming the memory cell 2602 of the sector Sector4, the upper sector selection signal USEL and the upper complementary path selection signal twinU become H level. That is, the transistors 2606 and 2607 are turned on, and the memory cells 2601 and 2603 are connected to the program amplifier. The memory cell 2601 is programmed with the inverted data of the write data, and the memory cell 2602 is programmed with the write data.

  On the other hand, the case of the single-phase cell mode is the same as FIG. That is, the transistor 2605 is turned on when programming into the memory cell 2601 in the sector Sector3, and the transistor 2606 is turned on when programming into the memory cell 2602 in the sector Sector4.

  As described above, in FIG. 26, in the complementary cell mode, the paired lower sector memory cell and upper sector memory cell are connected to the program amplifier, and the write data is stored in one memory cell, and the other memory cell. The inverted data is programmed in On the other hand, in the single-phase cell mode, the memory cell of the selected sector is connected to the program amplifier, and the write data is programmed.

  FIG. 27 is a diagram showing an amplifier control circuit for the upper sector in the second embodiment. FIG. 28 is a diagram illustrating an amplifier control circuit for a lower sector in the second embodiment. FIG. 27 shows an amplifier control circuit for the sector Sector4 in the upper sector, and FIG. 28 shows an amplifier control circuit for the sector Sector3 which is a pair of the sector Sector4.

  The amplifier control circuit of FIG. 27 has the same configuration as the amplifier control circuit of FIG. However, the output of the NAND gate 2715 corresponding to the NAND gate 1615 of FIG. 16 becomes the lower complementary path selection signal twinL. Further, the NOR gate 2718 corresponding to the NOR gate 1618 in FIG. 16 receives the lower complementary path selection signal twinL, the write command PGM, and the output of the NAND gate 2811 of the amplifier control circuit of the sector Sector 3 described later, and receives the complementary cell selection signal. / Twin is output. Further, a NOR gate 2719 corresponding to the NOR gate 1619 in FIG. 16 includes an upper sector complementary output control signal noU that is an output of the NAND 2716 corresponding to the NAND gate 1616 in FIG. 16 and a NAND gate 2812 of the amplifier control circuit of the sector Sector 3 described later. The lower sector complementary output control signal noL, which is the output of No. 1, is input, and the complementary output control signal / RAoutH is output.

  Similarly to FIG. 16, the amplifier control circuits of the sectors Sector 5 to 7 have NAND gates corresponding to the NAND gate 2703 when the corresponding sector address signals Sector Address <0> to <2> are input to the amplifier control circuit 216. In this circuit, inverters are arranged or not arranged in the areas 2720 and 2721 so that all three inputs are at the H level. For example, in the case of sector Sector 4, since the sector address signal is “100”, inverters 2701 and 2702 are provided for sector address signals Sector Address <0> and <1>.

  The amplifier control circuits of sectors Sector 3 to 0 in FIG. 28 receive sector address signals Sector Address <0> to <2> and flag signals twins <3> to <0>, and upper sector complementary path selection signal twinU and lower A sector complementary output control signal noL is output.

  The amplifier control circuit of sector Sector 3 in FIG. 28 has inverters 2801, 2803 to 2805, 2807 and NAND gates 2802, 2806, 2808 to 2812, and NAND gates 2811 and 2812 are connected between the amplifier control circuits of Sectors 0 to 3. Shared on.

  Also, the amplifier control circuits of sectors Sector 0 to 2 have three inputs of the NAND gate corresponding to NAND gate 2802 when the corresponding sector address signals Sector Address <0> to <2> are input to amplifier control circuit 216. In this circuit, inverters are arranged or not arranged in the regions 2820 and 2821 so that all become H level. For example, in the case of sector Sector 3, since the sector address signal is “011”, no inverter is provided in the areas 2820 and 2821 for the sector address signals Sector Address <0> and <1>.

  Here, as an example, the output of each signal when the sector address signal “100” of the sector Sector4 is input to the amplifier control signal 216 of FIGS. 27 and 28 will be described below. In the second embodiment, when the sector Sector4 is selected, in the single-phase cell mode, the flag signal twins <4> is at L level and twins <3> is at L level. In the complementary cell mode, when the flag signal twins <4> is L level and twins <3> is H level (hereinafter referred to as complementary cell mode 1), or twins <4> is H level and twins <3. > Is L level (hereinafter referred to as complementary cell mode 2).

  When SectorAddress <0> = “0”, SectorAddress <1> = “0”, and SectorAddress <2> = “1” are input, the sector address signal “100” corresponding to the amplifier control circuit for sector Sector4 in FIG. "Is input, the output of the inverter 2708 is at the H level. Therefore, in the single-phase cell mode and the complementary cell mode 1, the upper sector selection signal USEL is at the H level, and in the complementary cell mode 2 is at the L level.

  The output of the NAND gate 2710 and the flag signal twins <4> are input to the NAND gate 2712. When the sector address signal “100” is input, the output of the NAND gate 2710 becomes H level. Therefore, in the single-phase cell mode and the complementary cell mode 1, the lower sector complementary path selection signal twinL is at L level, and in the complementary cell mode 2 is at H level.

  The output of the inverter 2708 and the flag signal twins <4> are input to the NAND gate 2713. When the sector address signal “100” is input, the output of the inverter 2708 becomes H level. Therefore, the upper sector complementary output control signal noU output from the NAND gate 2716 is L level in the single-phase cell mode and the complementary cell mode 1, and is H level in the complementary cell mode 2.

  When the sector address signal “100” is input to the amplifier control signal of FIG. 28, the output of the inverter 2807 is L level and the output of the NAND gate 2808 is H level. Accordingly, the upper sector complementary path selection signal twinU output from the NAND 2811 is at the L level in the single-phase cell mode and the complementary cell mode 2 and at the H level in the complementary cell mode 1. The lower sector complementary output control signal noL output from the NAND gate 2812 is at the L level in both the single-phase cell mode and the complementary cell modes 1 and 2.

  27 and 28, the reference cell selection signal / twin output from the NOR gate 2718 is at the H level in the single-phase cell mode and at the L level in the complementary cell modes 1 and 2. Complementary output control signal / RAoutH output from NOR gate 2719 is at H level in single-phase cell mode and complementary cell mode 1, and is at L level in complementary cell mode 2. The above output results are summarized in FIG. 29 together with the output of each signal when the sector address signal “011” of the sector Sector 3 is input.

  FIG. 29 is a diagram illustrating a truth table of amplifier control signals in the second embodiment. When sector Sector 3 is selected, in the single-phase cell mode, the lower sector selection signal LSEL is H level and the reference cell selection signal / twin is H level. In the complementary cell mode 2, the lower sector selection signal LSEL is H level. Since the level and lower sector complementary path selection signal twinL is at H level and the complementary cell mode 1 is not preferable access, the complementary output control signal / RAoutH is at L level. When sector Sector 4 is selected, the upper sector selection signal USEL is H level and the reference cell selection signal / twin is H level in the single-phase cell mode, and the upper sector selection signal USEL is H level in the complementary cell mode 1. Since the upper sector complementary path selection signal twinU is at the H level and the complementary cell mode 2 is an undesirable access, the complementary output control signal / RAoutH is at the L level. As described above, the complementary output control signal / RAoutH becomes L level in the sector Cell3 in the complementary cell mode 1 and in the sector Sector4 in the complementary cell mode 2. In the complementary cell mode 1, when there is a read request for the sector Sector 3 (sector address signal “011”), the request is an erroneous read request, so the L level complementary output control signal / RAoutH Thus, the transistor 2515 is turned off and the transistor 2516 is turned on so that the output of the read amplifier 220 is always in the erased state “1”. The same applies to a read request for sector Sector 4 (sector address signal “100”) in the complementary cell mode 2.

  As described above, the amplifier control circuit 216 performs the upper sector selection signal USEL, the lower sector selection signal LSEL, the upper sector complementary path selection signal twinU, and the lower sector complementary path selection signal based on the input sector address signal. TwinL, a cell selection signal / twin, and a complementary output control signal / RAoutH are output. Further, the program path and the read path are controlled as shown in FIGS. 25 and 26 in the write amplifier 219 and the read amplifier 220 by these signals.

  As described above, in the second embodiment, the complementary cell mode is selected according to the sector status data of the sector of the selected sector and the sector of the pair, regardless of the order in which writing is requested to each sector. Alternatively, writing is performed in either single-phase cell mode. Thereby, the flash memory can hold not only highly reliable data but also a large amount of data in an arbitrary sector.

  The above embodiment is summarized as follows.

(Appendix 1)
A plurality of sectors each having a plurality of memory cells, each pair of sectors forming a plurality of sector groups,
As each operation of the plurality of sector groups, a single-phase cell mode in which 1-bit data is stored in one memory cell of one sector or the 1-bit data is included in a pair of sectors of the sector group, respectively. A mode determination unit that selects one of the complementary cell modes to be stored as complementary data in the pair of memory cells and outputs a selection result;
A semiconductor memory device comprising: an operation control unit that operates the sector group in the single-phase cell mode or the complementary cell mode based on the selection result.

(Appendix 2)
In Appendix 1,
The semiconductor memory device, wherein the mode determination unit determines that a sector group is in a complementary cell mode when a write request is made in one sector when a pair of sectors in the sector group is in an erased state.

(Appendix 3)
In Appendix 2,
The semiconductor memory device, wherein the mode determination unit determines that the sector group is in the single-phase cell mode when there is a write request to the other sector of the sector group in the complementary cell mode.

(Appendix 4)
In Appendix 1,
The mode determination unit holds sector state data for identifying whether the sector is in a write state corresponding to a write request or an erase state corresponding to an erase request, corresponding to each of the plurality of sectors. Sector state memory to be
A semiconductor memory device comprising: a sector state memory access control circuit for outputting the selection result based on the sector state data corresponding to one sector constituting the sector group and the sector state data corresponding to the other sector.

(Appendix 5)
In Appendix 4,
The sector state memory access control circuit, when there is a write request to the one sector of the sector group in which both the sector state data of the one sector and the other sector are in the erased state, A semiconductor memory device that outputs a selection result of the complementary cell mode and changes the sector state data of the one sector to a write state.

(Appendix 6)
In Appendix 5,
The sector state memory access control circuit outputs a selection result of the single-phase cell mode for the sector group when there is a write request to the other sector of the sector group that is in the complementary cell mode, A semiconductor memory device for changing the sector state data of a sector to a write state.

(Appendix 7)
In Appendix 5,
The sector state memory access control circuit outputs the selection result of the single-phase cell mode for the sector group when there is an erasure request in the one sector of the sector group in the complementary cell mode, A semiconductor memory device for changing the sector state data of a sector to an erased state.

(Appendix 8)
In Appendix 6 or 7,
When the operation control unit detects that the selection result is switched from the complementary cell mode to the single-phase cell mode, the operation control unit requests the other sector to be erased.

(Appendix 9)
In Appendix 5,
A semiconductor memory device that does not erase data in the other sector when there is an erase request in the other sector of the sector group in the complementary cell mode.

(Appendix 10)
In Appendix 4,
The semiconductor memory device, wherein the sector state memory access control circuit sets the sector state data in a write state in response to a write request to the sector and sets the sector state data in an erase state in response to an erase request for the sector.

(Appendix 11)
In Appendix 4,
The sector state memory stores an internal flag signal indicating whether or not the erase operation of the other sector performed in response to the selection result of switching from the complementary cell mode to the single-phase cell mode is completed,
When the sector state memory access control circuit has a write request to the other sector or an erase request to the one sector, the selection result is the single-phase cell mode and the internal flag signal is incomplete In this case, the semiconductor memory device outputs an erase command signal for the other sector, and completes the internal flag signal when the erase of the data in the other sector by the erase command signal is completed.

(Appendix 12)
In Appendix 1 or 4,
The operation control unit writes a sector control circuit for selecting a sector to write or read data based on the selection result, and writes complementary data of the write data to a pair of sectors of the sector group based on the selection result Or a write amplifier that writes write data to one sector, and outputs read data based on complementary data from a pair of sectors of the sector group based on the selection result, or outputs data from the one sector And a read amplifier that outputs the read data based on the read data.

(Appendix 13)
In Appendix 12,
The sector control circuit selects the one sector corresponding to the input address signal in the single-phase cell mode, and the same sector as the one sector and the one sector in the complementary cell mode. A semiconductor memory device for selecting the other sector constituting the group.

(Appendix 14)
In Appendix 12,
The write amplifier outputs the write data to the one sector corresponding to the input address signal in the single-phase cell mode, and outputs the write data to the one sector in the complementary cell mode. And a semiconductor memory device for outputting inverted data of the write data to the other sector constituting the same sector group as the one sector.

(Appendix 15)
In Appendix 12,
The read amplifier outputs the read data by comparing the memory cell and the reference cell in the one sector corresponding to the input address signal in the single-phase cell mode, and in the complementary cell mode, A semiconductor memory device that outputs the read data by comparing a memory cell in the one sector with a memory cell in the other sector constituting the same sector group as the one sector.

(Appendix 16)
In Appendix 1,
Each of the plurality of sectors has a sector number;
The plurality of sectors are divided into a first sector group having a sector number smaller than an intermediate value of sector numbers and a second sector group having a larger sector number,
The sector group comprises a pair of sectors in order from a sector with a lower sector number among sectors of the first sector group and a sector with a higher sector number among sectors of the second sector group,
Write requests are input in order from the sector with the smallest sector number. For write requests to the sectors of the first sector group, data is stored in the complementary cell mode, and write requests to the sectors of the second sector group are stored. A semiconductor memory device for storing data in the single-phase cell mode.

(Appendix 17)
In Appendix 1,
After storing data in the complementary cell mode in response to a write request to one of the pair of sectors of the sector group, the write request to the other sector of the sector group in the complementary cell mode A semiconductor memory device that stores data in a single-phase cell mode in response.

RD: Read command PGM: Write command ERS: Batch erase command twins: Flag signal USEL: Upper sector selection signal LSEL: Lower sector selection signal twin: Complementary path selection signal / twin: Reference cell selection signal twinU: Upper complementary path selection signal twinL : Lower complementary path selection signal RAoutH: Complementary output control signal int-twins: Internal flag signal int-tc: Internal flag control signal WL: Word line SL: Source line LBL: Local bit line GBL: Global bit line SSEL: Column selection line LBSEL: Local bit line selection signal YSEL: Global bit line selection signal

Claims (9)

A plurality of sectors each having a plurality of memory cells, each pair of sectors forming a plurality of sector groups,
As each operation of the plurality of sector groups, a single-phase cell mode in which 1-bit data is stored in one memory cell of one sector or the 1-bit data is included in a pair of sectors of the sector group, respectively. A mode determination unit that selects one of the complementary cell modes to store as complementary data in the pair of memory cells and outputs a selection result;
Based on the selection result, it possesses an operation control unit for operating the sector group in the single-phase cell mode or complementary cell mode,
The mode determination unit, a semiconductor memory device for determining the sector group and the complementary cell mode when the pair of sectors of said sector group is a write request to one of the sector during an erase state. In claim 1 ,
The semiconductor memory device, wherein the mode determination unit determines that the sector group is in the single-phase cell mode when there is a write request to the other sector of the sector group in the complementary cell mode. In claim 1,
The mode determination unit holds sector state data for identifying whether the sector is in a write state corresponding to a write request or an erase state corresponding to an erase request, corresponding to each of the plurality of sectors. Sector state memory to be
A semiconductor memory device comprising: a sector state memory access control circuit for outputting the selection result based on the sector state data corresponding to one sector constituting the sector group and the sector state data corresponding to the other sector. In claim 3 ,
The sector state memory access control circuit, when there is a write request to the one sector of the sector group in which both the sector state data of the one sector and the other sector are in the erased state, A semiconductor memory device that outputs a selection result of the complementary cell mode and changes the sector state data of the one sector to a write state. In claim 4 ,
The sector state memory access control circuit outputs a selection result of the single-phase cell mode for the sector group when there is a write request to the other sector of the sector group that is in the complementary cell mode, A semiconductor memory device for changing the sector state data of a sector to a write state. In claim 1 or 3 ,
The operation control unit writes a sector control circuit for selecting a sector to write or read data based on the selection result, and writes complementary data of the write data to a pair of sectors of the sector group based on the selection result Or a write amplifier that writes write data to one sector, and outputs read data based on complementary data from a pair of sectors of the sector group based on the selection result, or outputs data from the one sector And a read amplifier that outputs the read data based on the read data. In claim 6 ,
The sector control circuit selects the one sector corresponding to the input address signal in the single-phase cell mode, and the same sector as the one sector and the one sector in the complementary cell mode. A semiconductor memory device for selecting the other sector constituting the group. In claim 1,
Each of the plurality of sectors has a sector number;
The plurality of sectors are divided into a first sector group having a sector number smaller than an intermediate value of sector numbers and a second sector group having a larger sector number,
The sector group comprises a pair of sectors in order from a sector with a lower sector number among sectors of the first sector group and a sector with a higher sector number among sectors of the second sector group,
Write requests are input in order from the sector with the smallest sector number. For write requests to the sectors of the first sector group, data is stored in the complementary cell mode, and write requests to the sectors of the second sector group are stored. A semiconductor memory device for storing data in the single-phase cell mode. In claim 1,
After storing data in the complementary cell mode in response to a write request to one of the pair of sectors of the sector group, the write request to the other sector of the sector group in the complementary cell mode A semiconductor memory device that stores data in a single-phase cell mode in response.

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