JP5918421B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technology effective when applied to a semiconductor device used for a driver for an LCD (Liquid Crystal Display).

  Japanese Unexamined Patent Application Publication No. 2007-103848 (Patent Document 1) describes a technique that can reduce the size of a semiconductor chip. According to this technique, first, a pad and wiring other than the pad are provided on the insulating film. A surface protective film is formed on the insulating film including the pad and the wiring, and an opening is provided in the surface protective film. The opening is formed on the pad and exposes the surface of the pad. A bump electrode is formed on the surface protective film including the opening. Here, the size of the pad is made sufficiently smaller than the size of the bump electrode. Thus, the wiring is arranged immediately below the bump electrode and in the same layer as the pad. That is, the wiring is arranged in the space of the bump electrode formed by reducing the pad.

JP 2007-103848 A

  In recent years, LCDs using liquid crystals as display elements are rapidly spreading. This LCD is controlled by a driver for driving the LCD. The LCD driver is composed of a semiconductor chip and is mounted on, for example, a glass substrate. A semiconductor chip constituting an LCD driver has a structure in which a plurality of transistors and multilayer wiring are formed on a semiconductor substrate, and bump electrodes are formed on the surface. And the bump electrode formed in the surface and the glass substrate are connected through an anisotropic conductive film. At this time, the semiconductor chip and the glass substrate are connected by the bump electrode. From the viewpoint of improving the adhesive force, the area of the bump electrode is increased to increase the bonding area of the semiconductor chip and the glass substrate. . That is, the bump electrode of the semiconductor chip constituting the LCD driver has a feature that the size is much larger than the bump electrode of the semiconductor chip used for general purposes.

  In the LCD driver, an insulating film serving as a surface protective film (passivation film) is formed under the bump electrode, and a pad formed on the uppermost layer of the multilayer wiring is formed through an opening provided in the insulating film. It is connected. Usually, the opening and the pad are formed to have the same area according to the size of the bump electrode. However, if the pad is formed in accordance with the size of the bump electrode, the occupied area of the pad is increased, and there is a problem that the space for arranging the power supply wiring and the signal wiring disposed in the same layer as the pad is eliminated.

  For this reason, in the LCD driver, the size of the pad is made smaller than the size of the bump electrode. That is, the size of the bump electrode is larger than the size of the pad, and the bump electrode has an overlapping region that overlaps the pad in a planar manner and a non-overlapping region that does not overlap the pad in a planar manner. Therefore, a space is secured in the uppermost layer of the multilayer wiring layer immediately below the non-overlapping region of the bump electrode. Therefore, it is possible to arrange power supply wiring and signal wiring in this space, and it is possible to effectively use the space immediately below the non-overlapping area. As described above, by making the pad smaller than the bump electrode, wiring other than the pad can be arranged under the bump electrode, and thus the semiconductor chip (LCD driver) can be downsized.

  However, when wiring is arranged in the uppermost wiring layer under the bump electrode, the following problems occur. This problem will be described with reference to the drawings. FIG. 36 is a diagram showing a connection relationship between the uppermost layer wiring of the semiconductor chip constituting the LCD driver and the bump electrode. As shown in FIG. 36, a pad PD and wirings L1 and L2 are formed in the uppermost layer on the interlayer insulating film 100. That is, the pad PD and the wirings L1 and L2 are formed in the same layer. A surface protective film 101 is formed so as to cover the uppermost wiring layer on which the pad PD and the wirings L1 and L2 are formed. The surface protective film 101 has irregularities on the surface reflecting the steps of the pad PD and the wirings L1 and L2. Accordingly, the bump electrode BP formed on the surface protective film 101 has a shape reflecting the unevenness due to the surface protective film 101. The bump electrode BP is electrically connected to the pad PD by a plug SIL whose opening is filled with a conductive material. The bump electrode BP formed on the surface protective film 101 is formed larger than the pad PD, and an overlapping region X that overlaps the pad PD in a plan view and a non-overlapping region Y that does not overlap the pad PD in a plan view. Will have. That is, the pad PD is not formed in the uppermost wiring layer immediately below the non-overlapping region Y of the bump electrode BP shown in FIG. 36, and a space is secured. By arranging the wirings L1 and L2 different from the pad PD in this space, the wiring can be efficiently arranged in the uppermost wiring layer, and the semiconductor chip (LCD driver) can be downsized.

  However, when the wirings L1 and L2 are arranged in the uppermost wiring layer immediately below the non-overlapping region Y of the bump electrode BP, the surface protection film 101 is uneven as a result of the step formed by the wirings L1 and L2. Then, the bump electrode BP formed on the surface protective film 101 also has an uneven shape reflecting the unevenness due to the surface protective film 101. If the bump electrode BP has irregularities in this way, inconvenience occurs when the semiconductor chip is mounted on the glass substrate.

  FIG. 37 is a cross-sectional view showing a state in which a semiconductor chip is mounted on a glass substrate. As shown in FIG. 37, in order to mount a semiconductor chip on a glass substrate 103, a bump electrode BP formed on the semiconductor chip and a wiring 103a formed on the glass substrate 103 are connected via an anisotropic conductive film ACF. This is done by connecting them. At this time, if the bump electrode BP has irregularities on the surface, the conductive particles 102 constituting the anisotropic conductive film ACF and the bump electrode BP may not be satisfactorily contacted. As shown in FIG. 37, irregularities are formed on the surface of the bump electrode BP, but the bumps of the bump electrode BP are in good contact with the conductive particles 102. On the other hand, the concave portion of the bump electrode BP cannot be in good contact with the conductive particles 102. That is, since the pressure by the glass substrate 103 is applied to the convex portion of the bump electrode BP, the conductive particles 102 come into contact with the bump electrode BP to ensure conductivity. However, the pressure from the glass substrate 103 is less likely to be applied to the concave portion of the bump electrode BP. For this reason, it becomes difficult to ensure the conductivity between the bump electrode BP and the conductive particles 102.

  For this reason, in order to ensure the connection between the glass substrate 103 and the bump electrode BP via the anisotropic conductive film ACF, even if the bump electrode BP is enlarged, the bump electrode becomes uneven when the surface of the bump electrode BP is generated. It becomes difficult to improve the connection reliability between the BP and the wiring 103 a formed on the glass substrate 103.

  An object of the present invention is to provide a technique capable of improving the connection reliability between a bump electrode of a semiconductor chip and a wiring of a mounting substrate. In particular, even when a wiring is arranged on the uppermost wiring layer under the bump electrode, a technique is provided that can ensure the flatness of the bump electrode and improve the connection reliability between the bump electrode and the wiring formed on the glass substrate. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to a representative embodiment includes (a) a semiconductor substrate, (b) a semiconductor element formed on the semiconductor substrate, (c) a multilayer wiring layer formed on the semiconductor element, d) a pad formed on the uppermost layer of the multilayer wiring layer. (E) a surface protective film formed on the pad and having an opening reaching the pad; and (f) a surface protective film formed on the surface protective film and embedded in the opening to electrically connect with the pad. And a bump electrode to be connected. The bump electrode is formed larger than the pad so as to have an overlapping region that overlaps the pad in a planar manner and a non-overlapping region that does not overlap the pad in a planar manner. Here, in the uppermost layer of the multilayer wiring layer, (g) a first wiring made of a power supply wiring or a signal wiring in addition to the pad, and (h) a dummy pattern different from the first wiring are formed. . The first wiring formed in the same layer as the pad is formed below the non-overlapping region of the bump electrode.

  As described above, by arranging the dummy pattern in addition to the power supply wiring and the signal wiring on the uppermost layer of the multilayer wiring layer, the flatness of the surface protective film formed on the uppermost layer can be improved. In other words, if only the power supply wiring and signal wiring are formed on the uppermost layer of the multilayer wiring layer, the uppermost layer cannot be densely filled with wiring, so the unevenness due to the power supply wiring and signal wiring becomes remarkable. In addition, the flatness of the uppermost layer can be improved by spreading a dummy pattern. For this reason, the flatness of the surface protective film formed on the uppermost layer is ensured, and the flatness of the bump electrode formed on the surface of the surface protective film can be improved.

  A method of manufacturing a semiconductor device according to a representative embodiment includes: (a) a step of forming a semiconductor element on a semiconductor substrate; (b) a step of forming a multilayer wiring layer on the semiconductor element; Forming a conductor film on the uppermost layer of the multilayer wiring layer. Next, (d) patterning the conductor film to form a pad and a first wiring and a dummy pattern made of a power supply wiring or a signal wiring; and (e) the pad, the first wiring and the dummy. Forming a surface protective film so as to cover the pattern. And (f) forming an opening reaching the pad in the surface protective film, and (g) forming a bump electrode larger than the pad on the surface protective film including the opening. Here, in the step (g), the bump electrode is formed so as to have an overlapping region that overlaps the pad planarly and a non-overlapping region that does not overlap the pad planarly. Then, the first wiring formed in the same layer as the pad is formed below the non-overlapping region of the bump electrode formed in the step (g), and is formed below the non-overlapping region. The dummy pattern is formed in a predetermined range adjacent to the first wiring.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By arranging a dummy pattern in addition to the power supply wiring and the signal wiring on the uppermost layer of the multilayer wiring layer, the flatness of the surface protective film formed on the uppermost wiring layer can be improved. In other words, if only the power supply wiring and signal wiring are formed on the uppermost layer of the multilayer wiring layer, the uppermost layer cannot be densely filled with wiring, so the unevenness due to the power supply wiring and signal wiring becomes remarkable. In addition, the flatness of the uppermost wiring layer can be improved by spreading dummy patterns. For this reason, the flatness of the surface protective film formed on the uppermost wiring layer is ensured, and the flatness of the bump electrode formed on the surface of the surface protective film can be improved. Therefore, the connection reliability between the bump electrode of the semiconductor chip and the wiring of the mounting substrate can be improved.

It is a figure which shows the planar structure of the semiconductor chip in embodiment of this invention. It is the figure which expanded the bump electrode vicinity for input signals of the semiconductor chip shown in FIG. FIG. 3 is an enlarged view showing an arrangement of dummy patterns shown in FIG. 2. It is the figure which expanded the bump electrode vicinity of the semiconductor chip shown in FIG. It is sectional drawing cut | disconnected by the AA line of FIG. It is sectional drawing cut | disconnected by the BB line of FIG. It is a figure explaining the relationship between the size of a dummy pattern, and the unevenness | corrugation formed in the silicon oxide film surface which covers a dummy pattern. It is a figure explaining the relationship between the size of a dummy pattern, and the unevenness | corrugation formed in the silicon oxide film surface which covers a dummy pattern. It is the figure which expanded the bump electrode vicinity for the output signals of the semiconductor chip shown in FIG. It is a figure which shows the modification of FIG. It is sectional drawing cut | disconnected by the AA line of FIG. In a semiconductor chip, it is a figure which shows the case where the occupation area of the uppermost wiring layer is 70% or less of the whole semiconductor chip. It is sectional drawing cut | disconnected by the AA line of FIG. In a semiconductor chip, it is a figure which shows the case where the occupation area of the uppermost wiring layer is 70% or more of the whole semiconductor chip. It is sectional drawing cut | disconnected by the BB line of FIG. It is explanatory drawing which shows the initial stage of an etching, when the occupation area of the uppermost wiring layer is 70% or less of the whole semiconductor chip. It is explanatory drawing which shows the completion | finish stage of an etching, when the occupation area of the uppermost wiring layer is 70% or less of the whole semiconductor chip. It is explanatory drawing which shows the initial stage of an etching, when the occupation area of the uppermost wiring layer is 70% or more of the whole semiconductor chip. It is explanatory drawing which shows the completion | finish stage of an etching, when the occupation area of the uppermost wiring layer is 70% or more of the whole semiconductor chip. It is sectional drawing which shows the structure of MISFET formed in a semiconductor chip. It is a flowchart which shows the manufacturing process of MISFET. It is sectional drawing which shows the manufacturing process of the semiconductor device in embodiment. FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 22; FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 23; FIG. 25 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 24; FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 25; FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 26; FIG. 28 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 27; FIG. 29 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 28; FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 29; FIG. 31 is a cross-sectional view showing a manufacturing step of the semiconductor device following that of FIG. 30; FIG. 32 is a cross-sectional view showing the manufacturing process of the semiconductor device, following FIG. 31; It is sectional drawing which shows the state which has mounted the semiconductor chip in embodiment in the glass substrate. It is an enlarged view which shows the state which connects a semiconductor chip and a glass substrate via an anisotropic conductive film. 1 is a diagram illustrating a main configuration of a liquid crystal display device. It is the figure which this inventor examined, Comprising: It is a figure which shows the connection relation of the uppermost layer wiring of a semiconductor chip, and a bump electrode. It is the figure which this inventor examined, Comprising: It is sectional drawing which shows a mode that a semiconductor chip is mounted in a glass substrate.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say.

  Similarly, in the following embodiments, when referring to the shape, positional relationship, etc., of components, etc., unless otherwise specified, and in principle, it is considered that this is not clearly the case, it is substantially the same. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges.

  In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In order to make the drawings easy to understand, even a plan view may be hatched.

  FIG. 1 is a plan view showing a configuration of a semiconductor chip CHP (semiconductor device) in the present embodiment. The semiconductor chip CHP in the present embodiment is an LCD driver. In FIG. 1, a semiconductor chip CHP has a semiconductor substrate 1S formed in, for example, an elongated rectangular shape (rectangular shape), and an LCD driver for driving a liquid crystal display device, for example, is formed on the main surface. Yes. This LCD driver has a function of controlling the direction of liquid crystal molecules by supplying a voltage to each pixel of a cell array constituting the LCD, and includes a gate drive circuit, a source drive circuit, a liquid crystal drive circuit, a graphic RAM (Random Access). Memory) and peripheral circuits. These functions are realized by semiconductor elements and wirings formed on the semiconductor substrate 1S. First, the surface configuration of the semiconductor chip CHP will be described.

  The semiconductor chip CHP has a rectangular shape having a pair of short sides and a pair of long sides, and the bump electrode BP1 is arranged along one long side (the lower side in FIG. 1) of the pair of long sides. Has been. These bump electrodes BP1 are arranged on a straight line. The bump electrode BP1 functions as an external connection terminal connected to an integrated circuit (LCD driver) composed of semiconductor elements and wirings formed inside the semiconductor chip CHP. In particular, the bump electrode BP1 is a bump electrode for a digital input signal or an analog input signal.

  Next, the bump electrode BP2 is disposed along the other long side (the upper side in FIG. 1) of the pair of long sides. These bump electrodes BP2 are arranged in two rows along the long side, and the two rows along the long side are arranged in a staggered manner. Thereby, bump electrode BP2 can be arrange | positioned with high density. These bump electrodes BP2 also function as external connection terminals that connect the integrated circuit formed inside the semiconductor substrate 1S and the outside. In particular, the bump electrode BP2 is a bump electrode for an output signal from the LCD driver.

  Thus, the bump electrodes BP1 and the bump electrodes BP2 are formed on the pair of long sides constituting the outer periphery of the semiconductor chip CHP. At this time, since the number of bump electrodes BP2 is larger than the number of bump electrodes BP1, the bump electrode BP1 is formed in a straight line along the long side, whereas the bump electrode BP2 is formed on the long side. It is arranged in a staggered pattern along. This is because the bump electrode BP1 is a bump electrode for an input signal input to the LCD driver, whereas the bump electrode BP2 is a bump electrode for an output signal output from the LCD driver. That is, since the input signal input to the LCD driver is serial data, the number of bump electrodes BP1 which are external connection terminals does not increase so much. On the other hand, since the output signal output from the LCD driver is parallel data, the number of bump electrodes BP2 which are external connection terminals increases. That is, since the output signal bump electrode BP2 is provided for each cell (pixel) constituting the liquid crystal display element, the bump electrode BP2 corresponding to the number of cells is required. Therefore, the number of bump electrodes BP2 for output signals is larger than that of bump electrodes BP1 for input signals. For this reason, the bump electrodes BP1 for input signals can be arranged in a straight line along the long side, but the bump electrodes BP2 for output signals are arranged in a staggered manner along the long side to increase the number. ing.

  In FIG. 1, the bump electrode BP1 and the bump electrode BP2 are arranged along a pair of long sides constituting the semiconductor chip CHP. Bump electrodes can also be arranged.

  Next, details of the bump electrode BP1 and the bump electrode BP2 will be described. The bump electrode BP1 and the bump electrode BP2 have a rectangular shape (rectangular shape) composed of a short side and a long side, and the long sides of the bump electrode BP1 and the bump electrode BP2 are directed in the short side direction of the semiconductor chip CHP. In this state, the semiconductor chips CHP are arranged side by side in the long side direction. The bump electrode BP1 and the bump electrode BP2 formed on the semiconductor chip CHP are larger in size (area) than the bump electrode used for general purposes. That is, in the semiconductor chip CHP used for the LCD driver, the ratio of the area of the bump electrode BP1 and the bump electrode BP2 occupying the surface is large. This is to ensure connection reliability when the semiconductor chip CHP, which is an LCD driver, is mounted on a glass substrate of a liquid crystal display device via an anisotropic conductive film, as will be described later. Therefore, in the semiconductor chip used for general purposes, the bump electrode is not formed on the active region where the semiconductor element is formed, but in the semiconductor chip CHP used for the LCD driver, the bump electrode BP1 is also formed on the active region. And bump electrode BP2 is formed.

  Next, the bump electrode BP1 is formed on the surface of the semiconductor chip CHP. The arrangement relationship between the uppermost wiring layer formed below the bump electrode BP1 and the bump electrode BP1 will be described. FIG. 2 is an enlarged view of the region R in FIG. In FIG. 2, bump electrodes BP1 are arranged side by side along the long side direction of the semiconductor chip. In FIG. 2, two adjacent bump electrodes BP1 are shown. The bump electrode BP1 is formed on a surface protective film (passivation film) formed on the semiconductor chip, and an uppermost wiring layer is formed below the surface protective film. In FIG. 2, the illustration of the surface protective film is omitted, and the positional relationship between the uppermost wiring layer formed under the surface protective film and the bump electrode BP1 is shown.

  As shown in FIG. 2, the bump electrode BP1 is connected to a pad PD formed in the uppermost wiring layer. The bump electrode BP1 is formed larger than the pad PD, and a wiring L1 other than the pad PD is disposed in the uppermost wiring layer immediately below the bump electrode BP1. That is, the wiring L1 extends along the long side direction of the semiconductor chip immediately below the bump electrode BP1. Thus, the size of the bump electrode BP1 is larger than the size of the pad PD, and a space is secured in the uppermost layer of the multilayer wiring layer immediately below the bump electrode BP1. Thus, the wiring L1 can be arranged in this space, and the space immediately below the bump electrode BP1 can be effectively utilized. As described above, by making the pad PD smaller than the bump electrode BP1, the wiring L1 other than the pad PD can be disposed under the bump electrode BP1, so that the semiconductor chip (LCD driver) can be downsized. be able to. The wiring L1 can be, for example, a power supply wiring or a signal wiring.

  However, as described in the problem to be solved by the invention, when the wiring L1 is formed immediately below the bump electrode BP1, a step due to the wiring L1 and the space is reflected in the surface protective film, and the bumps are formed on the unevenness of the surface protective film. The electrode BP1 is formed. As a result, the surface of the bump electrode BP1 is not flat but has an uneven shape. When the surface of the bump electrode BP1 has an uneven shape, a problem occurs when the semiconductor chip is mounted on the glass substrate. Therefore, it is necessary to flatten the surface of the bump electrode BP1.

  Therefore, in the present embodiment, as shown in FIG. 2, the dummy pattern DP is formed in the uppermost wiring layer that is the same layer as the wiring L1. For example, in FIG. 2, the dummy patterns DP are arranged so as to be spread over an area adjacent to the wiring L1. In particular, the dummy pattern DP is arranged in a space between the plurality of wirings L1. As a result, the space immediately below the bump electrode BP1 can be filled with the dummy pattern DP. That is, the uppermost wiring layer immediately below the bump electrode BP1 is provided with a plurality of wirings L1 and a dummy pattern DP formed between these wirings L1. Therefore, the step between the wiring L1 and the space generated in the lower layer (uppermost wiring layer) of the bump electrode BP1 can be reduced. This is because the dummy pattern DP having the same height as the wiring L1 is formed in the space formed in the lower layer (uppermost wiring layer) of the bump electrode BP1, so that the bump electrode BP1 is formed by the wiring L1 and the dummy pattern DP. This is because the level difference in the lower layer (uppermost wiring layer) is relaxed.

  In the uppermost wiring layer, a dummy pattern DP is arranged immediately below the bump electrode BP1 so as to be parallel to the wiring L1, but the dummy pattern DP is also formed in a region not directly below the bump electrode BP1. Yes. That is, the dummy pattern DP is arranged so as to be adjacent to the wiring L1 even in a region that does not overlap the bump electrode BP1 in a plan view. Forming the dummy pattern DP in the space immediately below the bump electrode BP1 is considered to be a configuration necessary for eliminating the step due to the space between the wiring L1 and the space immediately below the bump electrode BP1. On the other hand, it is questionable whether there is an advantage in forming the dummy pattern DP so as to be adjacent to the wiring L1 even in a region that does not overlap with the bump electrode BP1 in plan view. However, even if the region is not directly under the bump electrode BP1, a step is generated between the wiring L1 and the space. If this step occurs in the vicinity of the bump electrode BP1, the flatness of the bump electrode BP1 is affected. For this reason, not only the lower layer (uppermost wiring layer) of the bump electrode BP1, but also the peripheral area away from the bump electrode BP1 by a predetermined distance is laid down to ensure the flatness of the bump electrode BP1. It is configured as follows.

  Next, the arrangement layout of the dummy patterns DP will be described. FIG. 3 is a diagram showing an arrangement pattern of the dummy patterns DP. As shown in FIG. 3, each dummy pattern DP has a rectangular shape (rectangular shape) having a short side and a long side, and a plurality of dummy patterns DP are arranged in the vertical and horizontal directions on the paper surface. Space). The long side length of each dummy pattern DP is, for example, 5.0 μm, and the short side length is, for example, 0.8 μm. Therefore, considering that the width of the wiring L1 is, for example, 20 μm to 30 μm, it can be seen that both the short side width and the long side width of each dummy pattern DP are smaller than the width of the wiring L1. That is, it can be seen that the size of each dummy pattern DP is very small. Therefore, even when the space formed between the plurality of wirings L1 is smaller than the width of the wiring L1, the dummy pattern DP can be spread in the small space. Therefore, since a very small space can be filled with the dummy pattern DP, the flatness of the uppermost wiring layer can be sufficiently ensured. In particular, as shown in FIG. 3, the size of the dummy pattern DP itself is small, but the interval at which the plurality of dummy patterns DP are arranged is as small as 0.6 μm, for example. That is, it can be seen that the interval between the dummy patterns DP is smaller than the length of the short side of the dummy pattern DP itself, so that the space can be embedded at high density.

  FIG. 4 is a diagram illustrating an arrangement example of dummy patterns DP different from those in FIG. As shown in FIG. 4, the lower layer (uppermost wiring layer) of the bump electrode BP1 is occupied by a plurality of wirings L1. That is, in the lower layer (uppermost wiring layer) of the bump electrode BP1, a space for arranging the dummy pattern DP is not secured, and the plurality of wirings L1 are arranged at high density. Therefore, in the configuration shown in FIG. 4, it is considered that the problem of a step does not occur in the lower layer (uppermost wiring layer) of the bump electrode BP1. However, as shown in FIG. 4, even if the wiring L1 is formed so as to fill the region immediately below the bump electrode BP1, the wiring L1 is formed in the peripheral region that does not overlap the bump electrode BP1 in plan view. Absent. That is, in the peripheral region of the bump electrode BP1, there are a region where the wiring L1 is formed in the uppermost wiring layer and a space region. For this reason, the level | step difference resulting from the height difference by the wiring L1 and space generate | occur | produces. It is important from the viewpoint of ensuring the flatness of the bump electrode BP1 to suppress the step in the region immediately below the bump electrode BP1. However, even if a step occurs in the peripheral region of the bump electrode BP1, the step affects the flatness of the bump electrode BP1, and therefore, it is necessary to suppress the step in the uppermost wiring layer also in the peripheral region of the bump electrode BP1. Therefore, also in the configuration shown in FIG. 4, the dummy pattern DP is also formed in the region adjacent to the wiring L1 (the peripheral region of the bump electrode BP1). As a result, even in the peripheral region of the bump electrode BP1, the step of the uppermost wiring layer can be relaxed, and the flatness of the bump electrode BP1 formed above the uppermost wiring layer can be reliably ensured. Considering the configuration shown in FIGS. 2 and 4, when there is a space and the wiring L1 in the region immediately below the bump electrode BP1, it is most effective to cover the dummy pattern DP so as to fill the space. It can be seen that it is useful to form the dummy pattern DP in the uppermost wiring layer not only in the region directly below the bump electrode BP1, but also in the peripheral region within a certain distance from the bump electrode BP1. The arrangement relationship between the bump electrode BP1 and the dummy pattern DP formed in the lower layer (uppermost wiring layer) of the bump electrode BP1 has been described, but the arrangement relationship between the bump electrode BP2 and the dummy pattern DP is the same. It has become.

  Next, the configuration of the dummy pattern DP will be described with reference to cross-sectional views. FIG. 5 is a cross-sectional view taken along line AA in FIG. In FIG. 5, only the structure above the multilayer wiring layer including the uppermost wiring layer is shown, and the structure below the uppermost wiring layer is omitted.

  As shown in FIG. 5, a wiring 42 is formed on a silicon oxide film 40 which is an interlayer insulating film. This wiring 42 is connected to a lower wiring by a plug 43. In FIG. 5, wiring and semiconductor elements below the plug 43 formed in the silicon oxide film 40 are not shown, but a multilayer wiring and a semiconductor element such as a MISFET are formed below the wiring 42. An interlayer insulating film is formed so as to cover the wiring 42. The interlayer insulating film includes a silicon oxide film 20 and a silicon oxide film 21 made of TEOS (Tetra Ethyl Ortho Silicate) formed on the silicon oxide film 20. An uppermost wiring layer is formed on the interlayer insulating film. The uppermost wiring layer includes a pad PD, a wiring L1, and a dummy pattern DP. The pad PD, the wiring L1, and the dummy pattern DP are formed by patterning the same conductor film, and each has the same thickness. That is, the height of the wiring L1 and the height of the dummy pattern DP are substantially the same. The pad PD is electrically connected to the wiring 42 by a plug 41 that penetrates the silicon oxide film 20 and the silicon oxide film 21. That is, the pad PD is electrically connected to the semiconductor element through the wiring 42 and the lower layer wiring. A silicon oxide film 22a is formed so as to cover the uppermost wiring layer, and a silicon oxide film 23 made of TEOS is formed on the silicon oxide film 22a. Further, a silicon nitride film 24 is formed on the silicon oxide film 23. These silicon oxide film 22a, silicon oxide film 23, and silicon nitride film 24 constitute a surface protective film (passivation film). The surface protective film is a film provided for protecting the semiconductor chip from mechanical stress and intrusion of impurities. For this reason, the surface protective film is required to have barrier properties against contamination impurities such as mechanical strength and mobile ions. For example, as shown in FIG. 5, a silicon oxide film 22a, a silicon oxide film 23, and a silicon nitride film 24 are formed. It consists of a laminated film.

  An opening 25 reaching the pad PD is formed in the surface protective film, and a plug SIL is formed by embedding a conductive material in the opening 25. A bump electrode BP1 electrically connected to the plug SIL is formed on the surface protective film. The bump electrode BP1 is composed of, for example, a UBM (Under Bump Metal) film 26 and a gold film 28.

  The bump electrode BP1 is formed larger than the pad PD, and is formed so as to extend on the surface protective film. For this reason, the bump electrode BP1 has an overlapping region X that overlaps the pad PD in plan and a non-overlapping region Y that does not overlap the pad PD in plan. In the lower layer (uppermost wiring layer) of the non-overlapping region Y, a wiring L1 is formed. Further, a dummy pattern DP is disposed between the wirings L1. Therefore, when only the wiring L1 is formed in the lower layer (uppermost wiring layer) of the non-overlapping region Y, a step (unevenness) due to the height difference between the wiring L1 and the space occurs, and the surface protection film Reflects the step and becomes uneven. As a result, the surface of the bump electrode BP1 formed on the surface protective film has an uneven shape. However, in this embodiment, since the dummy pattern DP having the same height as the wiring L1 is formed so as to fill the space existing between the wirings L1, the lower layer (the uppermost layer wiring) of the non-overlapping region Y is formed. Layer) can be relaxed. For this reason, the flatness of the surface protective film formed on the uppermost wiring layer is also improved, and the flatness of the bump electrode BP1 formed on the surface protective film is also improved.

  That is, one of the features of the present embodiment (first feature point) is that the wiring L1 and the dummy pattern DP are formed under the non-overlapping region Y of the bump electrode BP1 (the uppermost wiring layer). Since the pattern DP has the same height as the wiring L1 and is disposed in the space between the wirings L1, the step of the uppermost wiring layer is reduced. As a result, an effect of improving the flatness of the bump electrode BP1 is obtained. Therefore, in the present embodiment, the wiring L1 made up of the power supply wiring and the signal wiring can be arranged in the lower layer (uppermost wiring layer) of the non-overlapping region Y of the bump electrode BP1, and as a result, directly below the large bump electrode BP1. The area can be used effectively. Further, the deterioration of the flatness of the bump electrode BP1 caused by arranging the wiring L1 below the non-overlapping region Y is improved by filling the space between the wirings L1 with the dummy pattern DP. Yes. As described above, in the first embodiment, it is possible to promote downsizing of the semiconductor chip and improve the flatness of the bump electrode BP1, and further improve the connection reliability between the semiconductor chip and the mounting substrate. be able to.

  Furthermore, one of the features of the present embodiment (second feature point) is that a planarization process is performed on the surface protective film. As described above, by forming the dummy pattern DP together with the wiring L1 in the uppermost wiring layer, the unevenness generated in the uppermost wiring layer can be reduced. However, as shown in FIG. 5, some unevenness remains on the surface of the silicon oxide film 22a formed so as to cover the uppermost wiring layer. Therefore, in order to realize further planarization of the surface protective film, a silicon oxide film 23 made of TEOS is formed on the silicon oxide film 22a. Then, the surface of the silicon oxide film 23 is flattened by polishing, for example, by chemical mechanical polishing (CMP). Thereby, the surface of the silicon oxide film 23 constituting a part of the surface protective film can be planarized. That is, after the silicon oxide film 22a is formed on the uppermost wiring layer, the silicon oxide film 23 is formed on the silicon oxide film 22a and the surface thereof is flattened, thereby further improving the flatness of the surface protective film. can do. A silicon nitride film 24 is formed on the silicon oxide film 23. Since the silicon nitride film 24 is formed on the silicon oxide film 23 planarized by the CMP method, the planarized state is maintained. To do. In this way, the flatness of the surface protective film formed so as to cover the uppermost wiring layer can be reliably improved. As a result, the bump electrode BP1 is formed on the planarized surface protective film, so that the flatness of the bump electrode BP1 is ensured. Here, since the surface of the surface protective film is the silicon nitride film 24, the surface of the silicon nitride film 24 is polished by the CMP method instead of the silicon oxide film 23 formed under the silicon nitride film 24. Is also possible. However, it is unsuitable for the surface of the silicon nitride film 24 to be polished by a normal CMP method because of the nature of the silicon nitride film 24, and thus the silicon oxide film 23 formed under the silicon nitride film 24. The surface is flattened by the CMP method. In other words, since the silicon oxide film 23 is a film that can be easily polished by the CMP method, the surface protective film is planarized by planarizing the silicon oxide film 23.

  From the above, in the present embodiment, the first feature point by laying the dummy pattern DP on the uppermost wiring layer and the second feature point of planarizing the surface protective film covering the uppermost wiring layer by the CMP method are provided. By combining, the bump electrode BP1 formed on the surface protective film can be surely flattened. However, the combination of the first feature point and the second feature point is not essential, and the bump electrode BP1 can be planarized only by the configuration serving as the first feature point, and the configuration serving as the second feature point. The planarization of the bump electrode BP1 can be realized only by this.

  Next, FIG. 6 is a cross-sectional view taken along line BB in FIG. As shown in FIG. 6, it can be seen that the dummy patterns DP constituting the uppermost wiring layer are arranged side by side along the arrangement direction of the bump electrodes BP1. That is, the dummy pattern DP extends in the same direction as the wiring L1 (not shown in FIG. 6). However, the dummy pattern DP is not composed of a single line like the wiring L1, but a plurality of dummy patterns DP. Are arranged side by side. Each dummy pattern DP has a small rectangular shape, and the short side width and the long side width thereof are smaller than the width of the wiring L1. The dummy pattern DP having such a small rectangular shape is arranged so as to cover the space of the uppermost wiring layer.

  By making the dummy pattern DP into a small rectangular shape, the following advantages can be obtained. This advantage will be described. First, the first advantage is that it can be sufficiently embedded regardless of the size of the space formed in the uppermost wiring layer. In other words, a plurality of wirings L1 are formed in the uppermost wiring layer, but there are small spaces and large spaces between the wirings L1. Therefore, if the size of the dummy pattern DP is set to the size of the wiring width of the wiring L1, it becomes impossible to fill the dummy pattern DP in a space having a narrow wiring interval. On the other hand, if the short side width and the long side width of the dummy pattern DP are made smaller than the width of the wiring L1, the dummy pattern DP can be filled in a relatively narrow space. Further, by reducing the size of the dummy pattern DP, it is possible to cover the space having various shapes with the plurality of dummy patterns DP without changing the shape of the dummy pattern DP.

  Further, a second advantage of reducing the shape of the dummy pattern DP will be described. For example, as shown in FIG. 7, when the size of the dummy pattern DP is increased and the interval between the dummy patterns DP is increased, the uneven width of the surface of the silicon oxide film 22 formed so as to cover the dummy pattern DP. S1 increases. This is not desirable from the viewpoint that the dummy pattern DP formed in the uppermost wiring layer is provided for the purpose of suppressing the unevenness of the uppermost wiring. On the other hand, as shown in FIG. 8, when the size of the dummy pattern DP is reduced and the interval between the dummy patterns DP is reduced, the surface of the silicon oxide film 22a formed so as to cover the dummy pattern DP. The uneven width S2 is reduced. This is desirable from the viewpoint that the dummy pattern DP formed in the uppermost wiring layer is provided for the purpose of suppressing the unevenness of the uppermost wiring. From this, it can be understood that it is desirable to reduce the dummy pattern DP and to reduce the interval between the dummy patterns DP from the viewpoint of promoting the flattening of the bump electrode BP1.

  The arrangement relationship between the bump electrode BP1 for input signals formed on the semiconductor chip and the uppermost wiring layer has been described above. Next, the arrangement relationship between the bump electrode BP2 for output signal and the uppermost wiring layer is described. Will be described. The positional relationship between the bump electrode BP2 for output signals and the uppermost wiring layer is the same as the positional relationship between the bump electrode BP1 for input signals and the uppermost wiring layer.

  FIG. 9 is an enlarged view of the vicinity of the corner of the semiconductor chip CHP. As shown in FIG. 9, the horizontal direction on the paper surface indicates the long side direction of the semiconductor chip CHP, and the vertical direction on the paper surface indicates the short side direction of the semiconductor chip CHP. It can be seen that the bump electrodes BP2 for output signals are arranged side by side in the long side direction of the semiconductor chip CHP. In particular, the bump electrodes BP2 for output signals are arranged in two rows in a staggered manner. Thereby, many bump electrodes BP2 can be arranged with high density in the long side direction of the semiconductor chip CHP.

  The bump electrode BP2 has a rectangular shape having a long side and a short side, and a pad PD is disposed on the uppermost wiring layer under a part of the bump electrode BP2. The pad PD and the bump electrode BP2 are electrically connected by a plug SIL. In the present embodiment, the bump electrode BP2 has the largest size, and is connected to a pad PD smaller than the bump electrode BP2 by a plug SIL smaller than the pad PD. However, the length in the short side direction of the bump electrode BP2 is smaller than the length of the pad PD. This is because when the length of the bump electrode BP2 in the short side direction is longer than that of the pad PD, the short side of the bump electrode BP2 has an uneven shape reflecting the step of the uppermost wiring layer depending on the presence or absence of the pad PD. . That is, from the viewpoint of flattening the shape of the bump electrode BP2 in the short side direction, it is desirable that all the short sides of the bump electrode BP2 are arranged on the pad PD.

  In addition to the pad PD, a wiring L1 and a dummy pattern DP are formed below the long side of the bump electrode BP2. The length in the long side direction of the bump electrode BP2 is much larger than that of the pad PD, and a space is vacant in the uppermost wiring layer immediately below the bump electrode BP2. Therefore, the wiring L1 is also arranged under the output signal bump electrode BP2 in order to effectively use the space formed in the uppermost wiring layer. The wiring L1 is, for example, a power supply wiring or a signal wiring. The wiring L1 is disposed immediately below the bump electrode BP2, and extends along the long side of the semiconductor chip CHP in which the bump electrode BP2 is arranged.

  Thus, when the wiring L1 is formed immediately below the bump electrode BP2, a step due to the wiring L1 and the space is reflected in the surface protective film, and the bump electrode BP2 is formed on the unevenness of the surface protective film. As a result, the surface of the bump electrode BP2 is not flat but uneven. When the surface of the bump electrode BP2 has an uneven shape, a problem occurs when the semiconductor chip is mounted on the glass substrate. Therefore, it is necessary to flatten the surface of the bump electrode BP2.

  Therefore, in the present embodiment, the dummy pattern DP is formed in the uppermost wiring layer of the same layer as the wiring L1 just below the output signal bump electrode BP2 as well as the input signal bump electrode BP1. For example, in FIG. 9, the dummy pattern DP is arranged so as to cover an area adjacent to the wiring L1. In particular, the dummy pattern DP is arranged in a space between the plurality of wirings L1. As a result, the space immediately below the bump electrode BP2 can be filled with the dummy pattern DP. That is, the uppermost wiring layer immediately below the bump electrode BP2 is provided with a plurality of wirings L1 and a dummy pattern DP formed between these wirings L1. Therefore, the step between the wiring L1 and the space generated in the lower layer (uppermost wiring layer) of the bump electrode BP2 can be reduced. This is because the dummy pattern DP having the same height as the wiring L1 is formed in the space formed in the lower layer (uppermost wiring layer) of the bump electrode BP2, so that the bump electrode BP2 is formed by the wiring L1 and the dummy pattern DP. This is because the level difference in the lower layer (uppermost wiring layer) is relaxed.

  FIG. 10 is a diagram showing an arrangement example of dummy patterns DP different from those in FIG. As shown in FIG. 10, the lower layer (uppermost wiring layer) of the bump electrode BP2 is occupied by a plurality of wirings L1. That is, in the lower layer (uppermost wiring layer) of the bump electrode BP2, a space for arranging the dummy pattern DP is not secured, and the plurality of wirings L1 are arranged at high density. Therefore, in the configuration shown in FIG. 10, it is considered that the problem of the step does not occur in the lower layer (uppermost wiring layer) of the bump electrode BP2. However, as shown in FIG. 10, even if the wiring L1 is formed so as to fill the region immediately below the bump electrode BP2, the wiring L1 is formed in the peripheral region that does not overlap with the bump electrode BP2 in plan view. Absent. That is, in the peripheral region of the bump electrode BP2, there are a region where the wiring L1 is formed and a space region in the uppermost wiring layer. For this reason, the level | step difference resulting from the height difference by the wiring L1 and space generate | occur | produces. It is important from the viewpoint of ensuring the flatness of the bump electrode BP2 to suppress the step in the region immediately below the bump electrode BP2. However, even if a step occurs in the peripheral region of the bump electrode BP2, the step affects the flatness of the bump electrode BP2. Therefore, it is necessary to suppress the step in the uppermost wiring layer also in the peripheral region of the bump electrode BP2. Therefore, also in the configuration shown in FIG. 10, the dummy pattern DP is also formed in the region adjacent to the wiring L1 (the peripheral region of the bump electrode BP2). Thereby, also in the peripheral region of the bump electrode BP2, the step of the uppermost wiring layer can be relaxed, and the flatness of the bump electrode BP1 formed above the uppermost wiring layer can be reliably ensured.

  Next, FIG. 11 shows a cross-sectional view taken along line AA in FIG. As shown in FIG. 11, a wiring 42 is formed on a silicon oxide film 40 that is an interlayer insulating film. This wiring 42 is connected to a lower wiring by a plug 43. In FIG. 11, wiring and semiconductor elements below the plug 43 formed in the silicon oxide film 40 are not shown, but a multilayer wiring and a semiconductor element such as a MISFET are formed below the wiring 42. An interlayer insulating film is formed so as to cover the wiring 42. The interlayer insulating film includes a silicon oxide film 20 and a silicon oxide film 21 made of TEOS (Tetra Ethyl Ortho Silicate) formed on the silicon oxide film 20. An uppermost wiring layer is formed on the interlayer insulating film. The uppermost wiring layer includes a pad PD, a wiring L1, and a dummy pattern DP. The pad PD, the wiring L1, and the dummy pattern DP are formed by patterning the same conductor film, and each has the same thickness. That is, the height of the wiring L1 and the height of the dummy pattern DP are substantially the same. The pad PD is electrically connected to the wiring 42 by a plug 41 that penetrates the silicon oxide film 20 and the silicon oxide film 21. That is, the pad PD is electrically connected to the semiconductor element through the wiring 42 and the lower layer wiring. A silicon oxide film 22a is formed so as to cover the uppermost wiring layer, and a silicon oxide film 23 made of TEOS is formed on the silicon oxide film 22a. Further, a silicon nitride film 24 is formed on the silicon oxide film 23. These silicon oxide film 22a, silicon oxide film 23, and silicon nitride film 24 constitute a surface protective film (passivation film).

  An opening 25 reaching the pad PD is formed in the surface protective film, and a plug SIL is formed by embedding a conductive material in the opening 25. A bump electrode BP2 electrically connected to the plug SIL is formed on the surface protective film. The bump electrode BP2 is composed of, for example, a UBM (Under Bump Metal) film 26 and a gold film 28.

  The bump electrode BP2 is formed larger than the pad PD, and is formed to extend on the surface protective film. For this reason, the bump electrode BP2 has an overlapping area that overlaps the pad PD in a plane and a non-overlapping area that does not overlap the pad PD in a plane. A wiring L1 is formed in the lower layer (uppermost wiring layer) of the non-overlapping region. Further, a dummy pattern DP is disposed between the wirings L1. Therefore, when only the wiring L1 is formed in the lower layer (uppermost wiring layer) of the non-overlapping region, a step (unevenness) due to the height difference between the wiring L1 and the space occurs, and the surface protective film has this step. Reflects and becomes an uneven shape. As a result, the surface of the bump electrode BP2 formed on the surface protective film has an uneven shape. However, in this embodiment, since the dummy pattern DP having the same height as the wiring L1 is formed so as to fill the space existing between the wirings L1, the lower layer (the uppermost wiring layer) of the non-overlapping region is formed. ) Can be reduced. For this reason, the flatness of the surface protective film formed on the uppermost wiring layer is also improved, and the flatness of the bump electrode BP2 formed on the surface protective film is also improved.

  Further, the present embodiment is characterized in that a planarization process is also performed on the surface protective film formed under the output signal bump electrode BP2. For example, the surface of the silicon oxide film 23 constituting a part of the surface protective film is planarized by polishing, for example, by chemical mechanical polishing (CMP). Thereby, the surface of the silicon oxide film 23 can be planarized. That is, after the silicon oxide film 22a is formed on the uppermost wiring layer, the silicon oxide film 23 is formed on the silicon oxide film 22a and the surface thereof is flattened, thereby further improving the flatness of the surface protective film. can do. A silicon nitride film 24 is formed on the silicon oxide film 23. Since the silicon nitride film 24 is formed on the silicon oxide film 23 planarized by the CMP method, the planarized state is maintained. To do. In this way, the flatness of the surface protective film formed so as to cover the uppermost wiring layer can be reliably improved. As a result, the bump electrode BP2 is formed on the planarized surface protective film, so that the flatness of the bump electrode BP2 is ensured.

  In the present embodiment, even in the uppermost wiring layer under the bump electrode BP2 for output signals, the first feature point by spreading the dummy pattern DP and the surface protective film covering the uppermost wiring layer are flattened by the CMP method. It has the 2nd feature point to do.

  In the present embodiment, as a first feature point, the dummy pattern DP is formed in both the region directly below the input signal bump electrode BP1 and the region directly below the output signal bump electrode BP2. Thereby, since the space in the uppermost wiring layer can be filled with the dummy pattern, the flatness of the surface protective film covering the uppermost wiring layer can be improved, and as a result, formed on the surface protective film. The flatness of the bump electrodes BP1 and BP2 can be improved.

  Therefore, it can be said that it is desirable to form the dummy pattern DP over the entire region of the semiconductor chip from the viewpoint of eliminating the level difference caused by the height difference of the space between the wiring L1 and the wiring L1 formed in the uppermost wiring layer. In other words, the dummy pattern DP is formed so as to fill the space formed on the entire surface of the uppermost wiring layer, and the planarization of the surface protective film formed so as to cover the uppermost wiring layer and the surface protective film are performed. It can be said that it is desirable from the viewpoint of promoting flattening of the formed bump electrode BP1.

  However, in this embodiment, the dummy pattern DP is not formed over the entire uppermost wiring layer. For example, as shown in FIG. 1, the uppermost wiring layer of the semiconductor chip CHP includes a dummy pattern formation region DR in which a dummy pattern is formed and a dummy pattern non-formation region NDR in which no dummy pattern is formed. I understand. The dummy pattern formation region DR is formed in a region within a certain distance from the bump electrode BP1 and the bump electrode BP2. This is because, from the viewpoint of realizing flattening of the bump electrode BP1 and the bump electrode BP2, at least, if a dummy pattern is provided immediately below the bump electrode BP1 and the bump electrode BP2 and its peripheral region, the bump electrode BP1 and the bump electrode This is because the step of the uppermost wiring layer that directly affects the flatness of BP2 can be eliminated. That is, in order to realize the planarization of the bump electrode BP1 and the bump electrode BP2, it is not necessary to fill the entire space of the uppermost wiring layer with the dummy pattern. In other words, the dummy pattern non-formation region NDR in which no dummy pattern is formed is a range that does not affect the planarization of the bump electrode BP1 and the bump electrode BP2.

  As described above, the reason why the dummy pattern formation region DR for forming the dummy pattern is not provided in the entire semiconductor chip CHP is as follows. The first reason is that the convenience of defect analysis in the semiconductor chip CHP is taken into consideration. The semiconductor chip CHP which is an LCD driver is shipped as a product, but a defective product may also be shipped. The defective products are collected from customers and analyzed for defects. At this time, if a dummy pattern is formed in the entire space of the uppermost wiring layer, the dummy pattern is formed of a metal film, so that the inside is shielded. That is, semiconductor elements and multilayer wiring are formed inside the semiconductor chip CHP. When performing a failure analysis on these semiconductor elements and multilayer wiring, if a dummy pattern is provided in the uppermost wiring layer, the failure analysis of the semiconductor elements and multilayer wiring formed inside the semiconductor chip CHP is performed. Hinder. For this reason, no dummy pattern is formed on the entire surface of the uppermost wiring layer. Therefore, the dummy pattern is formed in a region within a certain distance from the bump electrode BP1 and the bump electrode BP2. Specifically, the dummy pattern formation region DR is formed only in a region within 70 μm from each of the bump electrode BP1 and the bump electrode BP2. The other area is a dummy pattern non-formation area NDR in which no dummy pattern is formed to improve the convenience of defect analysis. That is, in the present embodiment, a dummy pattern is provided only in a region that affects the flatness of the bump electrode BP1 and the bump electrode BP2 (part of the uppermost wiring layer), and the flatness of the bump electrode BP1 and the bump electrode BP2 Improvements are made, and dummy patterns are not formed in other areas, thereby improving the convenience of defect analysis.

  Furthermore, the second reason that the dummy pattern formation region DR is not provided in the entire semiconductor chip CHP will be described. FIG. 12 is a diagram illustrating a case where the occupation ratio of the wiring L1 and the dummy pattern DP formed in the uppermost wiring layer of the semiconductor chip CHP is 70% or less. That is, FIG. 12 is a diagram illustrating a case where the ratio of the dummy pattern DP formed in the uppermost wiring layer is relatively low. FIG. 13 is a diagram showing a process of forming a dummy pattern in a partial cross section cut along the line AA in FIG. As shown in FIG. 13, a conductor film constituting the wiring L1 and the dummy pattern DP is formed on the silicon oxide film 21 serving as an interlayer insulating film, and a patterned resist film RF is formed on the conductor film. Has been. The patterning of the resist film RF is performed so that the resist film RF remains in a region where the wiring L1 and the dummy pattern DP are formed. The wiring L1 and the dummy pattern DP are formed by etching the conductor film using the patterned resist film RF as a mask. At this time, when the occupation ratio of the dummy pattern DP is relatively low at 70% or less, the ratio of the conductor film removed by etching increases. This means that the etching area is increased. When the etching area is large, it is easy to detect the end of etching. Therefore, the end point of etching can be accurately detected, and the shapes of the wiring L1 and the dummy pattern DP can be easily processed normally.

  Next, a case where the occupation ratio of the wiring L1 and the dummy pattern DP formed in the uppermost wiring layer of the semiconductor chip CHP is 70% or more will be described. FIG. 14 is a diagram illustrating a case where the occupation ratio of the wiring L1 and the dummy pattern DP formed in the uppermost wiring layer of the semiconductor chip CHP is 70% or more. That is, FIG. 14 is a diagram showing a case where the ratio of the dummy pattern DP formed in the uppermost wiring layer is relatively high. FIG. 15 is a diagram showing a process of forming a dummy pattern in a partial cross section cut along the line BB in FIG.

  As shown in FIG. 15, a conductor film constituting the wiring L1 and the dummy pattern DP is formed on the silicon oxide film 21 serving as an interlayer insulating film, and a patterned resist film RF is formed on the conductor film. Has been. The patterning of the resist film RF is performed so that the resist film RF remains in a region where the wiring L1 and the dummy pattern DP are formed. The wiring L1 and the dummy pattern DP are formed by etching the conductor film using the patterned resist film RF as a mask. At this time, when the occupation ratio of the dummy pattern DP is relatively high, such as 70% or more, the ratio of the conductor film removed by etching is low. This means that the etching area is reduced. When the etching area is reduced, there is a problem that the end point of etching cannot be detected accurately. This is a phenomenon that occurs in a general etching apparatus. In a general etching apparatus, a difference occurs in the accuracy of detecting the end point of etching depending on the size of the etching area.

  If the etching end point cannot be detected well because the etching area becomes small, there arises a problem that the processing failure of the wiring L1 and the dummy pattern DP occurs due to the influence of the remaining etching or overetching. Therefore, a method of managing the etching time instead of judging the end point of etching from the actual etching state is also conceivable. However, even if the etching time is managed, it cannot be sufficiently avoided that the dimensions processed by the actual etching vary. For this reason, it is necessary to detect the end point of etching from the actual etching state, not the indirect method of managing the etching time, for detecting the end point of etching. Therefore, from the viewpoint of accurately detecting the end point of etching and improving the processing accuracy of the dummy pattern, the dummy pattern formation region DR shown in FIG. 1 is not provided in the entire semiconductor chip CHP, and the dummy pattern in the uppermost wiring layer is not provided. It is necessary to reduce the occupation ratio.

  Reason 2 will be further described in detail. FIG. 16 shows, for example, a process of etching the conductor film 22 formed on the silicon oxide film 21. When the conductor film 22 is etched, a wiring or a dummy pattern constituting the uppermost wiring layer is formed. Is shown. FIG. 16 shows a case where the occupation rate of the dummy pattern is 70% or less, and shows a case where the etching region of the conductor film 22 is relatively large. In the etching of the conductor film 22, a chlorine-based gas such as BCl3 or Cl2 is used as an etching gas. This chlorine gas and the aluminum film constituting the conductor film 22 are chemically reacted and etched. At this time, the aluminum film is gradually removed by vaporizing the reaction product. When the aluminum film is sufficiently present, the chemical reaction between the aluminum film and the etching gas proceeds sufficiently. For this reason, a reaction product is produced | generated in large quantities. By detecting light emission (plasma light emission) from the reaction product, the progress of etching of the aluminum film can be predicted. That is, since the aluminum film is sufficiently present in the initial stage of etching, the chemical reaction between the aluminum film and the etching gas sufficiently proceeds, and a large amount of reaction products are generated. For this reason, in the initial stage of etching, since a large amount of reaction product exists, the amount of light emitted from the reaction product also increases.

  Next, FIG. 17 is a diagram showing an etching end stage after the etching progresses from the state shown in FIG. As shown in FIG. 17, the patterning of the conductor film 22 is almost finished, and the etching of the aluminum film constituting the conductor film 22 is at the end stage. At this time, since the aluminum film hardly remains, the chemical reaction between the aluminum film and the etching gas is considerably reduced as compared with the state shown in FIG. For this reason, the production amount of the reaction product due to the chemical reaction between the aluminum film and the etching gas is reduced, and the amount of light emitted from the reaction product is also reduced. That is, there is a feature that the amount of light emitted from the reaction product is reduced at the end of etching. From this, the end point of etching can be detected by monitoring the amount of light emitted from the reaction product in the etching process. That is, if the amount of light emitted from the reaction product is equal to or less than a predetermined amount, it can be determined that the etching is in an end stage. At this time, as shown in FIG. 16 and FIG. 17, when the etching area is large, the difference between the light emission intensity at the initial stage of etching and the light emission intensity at the end stage of etching becomes large. Can be carried out with high accuracy.

  Next, FIG. 18 shows a case where the occupation ratio of the dummy pattern is 70% or more, and shows a case where the etching region of the conductor film 22 is relatively small. In this case, as shown in FIG. 18, since the etching region is small even in the initial stage of etching, the emission intensity is also reduced. That is, in the initial stage of etching, the conductor film 22 remains sufficiently, but the area of the etching region that is not covered with the resist film RF is very small, so that the chemical reaction between the aluminum film and the etching gas causes the occupation rate of the dummy pattern. Less than 70% or less. For this reason, there are few reaction products even in the initial stage of etching, and the intensity of light emitted from the reaction products becomes weak.

  Thereafter, the etching proceeds and the etching is finished. FIG. 19 is a diagram showing an etching end stage following FIG. As shown in FIG. 19, since the aluminum film constituting the conductor film 22 is almost completely removed, the chemical reaction between the aluminum film and the etching gas is reduced and the reaction products are also reduced. Therefore, the intensity of light emitted from the reaction product is also weakened. However, as shown in FIGS. 18 and 19, when the dummy pattern occupancy is 70% or more, the etching region is small even in the initial stage of etching. As a result, the light quantity (intensity) of light emitted from the reaction product is also weak. This means that when the occupation rate of the dummy pattern is 70% or more, there is no difference in the light emission intensity between the initial stage and the end stage of etching. Therefore, it becomes difficult to clearly determine the end point detection of etching. If the etching end point cannot be detected well, there will be a problem that defective processing of the wiring and the dummy pattern occurs due to the remaining etching or the influence of over-etching. For these reasons, it is desirable to avoid forming unnecessary dummy patterns in the uppermost wiring layer. That is, from the viewpoint of improving the etching accuracy of the dummy pattern by accurately detecting the end point of etching, the dummy pattern formation region DR shown in FIG. 1 is not provided in the entire semiconductor chip CHP, and the dummy pattern in the uppermost wiring layer is not provided. It is necessary to reduce the occupation ratio.

  The conductor film 22 has a structure in which an aluminum film and the upper and lower sides of the aluminum film are sandwiched between titanium / titanium nitride films. In the etching of the titanium / titanium nitride film, the etching is usually managed not by the light emission intensity of the reaction product but by the etching time. Therefore, when the end point detection of the aluminum film can be performed with high accuracy, the titanium / titanium nitride film can be sufficiently removed in the prescribed etching time, but if the end point detection of the aluminum film is unclear, the etching of the aluminum film Remaining and over-etching occur, and with the specified etching time, etching remaining and over-etching occur in the etching of the titanium / titanium nitride film. From this, it can be understood that it is important to accurately detect the end point in the etching of the aluminum film from the viewpoint of processing the conductor film 22 with high accuracy.

  For the above reasons, the formation area of the dummy pattern in the uppermost wiring layer is limited to a range necessary and sufficient for planarizing the bump electrode. In other words, it is avoided that a dummy pattern is formed in the uppermost wiring layer more than necessary to be disadvantaged.

  To briefly summarize the features of the present embodiment, a first feature point by laying a dummy pattern on the uppermost wiring layer, and a second feature point that planarizes the surface protection film covering the uppermost wiring layer by the CMP method, There is. Then, as a necessary and sufficient range for realizing the first feature point, a dummy pattern is provided only directly under the bump electrode and its peripheral region, so that the uppermost wiring layer that directly affects the flatness of the bump electrode is provided. The step is eliminated.

  Here, the technical idea (first feature point) in the present embodiment is to provide a dummy pattern in the uppermost wiring layer. Conventionally, in a normal semiconductor device, a dummy pattern is provided in an intermediate wiring layer in a multilayer wiring layer. This is because it is necessary to provide another wiring layer above the intermediate wiring layer constituting the multilayer wiring layer, and it is necessary to flatten the intermediate wiring layer. However, in the conventional technique, there is no technical idea of providing a dummy pattern on the uppermost wiring layer. That is, it is not necessary to further provide a wiring layer on the uppermost wiring layer, and therefore there is no idea of relaxing the step due to the wiring formed in the uppermost wiring layer. That is, the uppermost wiring layer did not need to be flattened with high accuracy.

  On the other hand, the semiconductor device in the present embodiment is premised on the LCD driver. The LCD driver is characterized in that the size of the bump electrode formed on the uppermost wiring layer via the surface protective film is increased. On the premise of this configuration, in order to effectively utilize the lower layer (uppermost wiring layer) of the bump electrode, a configuration is adopted in which wiring is arranged directly below the large bump electrode. Assuming this configuration, wiring and space are formed in the uppermost wiring layer immediately below the bump electrode, and a step due to the height difference between the wiring and space is generated. This step is reflected on the surface protective film formed so as to cover the uppermost wiring layer, and unevenness is generated on the surface of the surface protective film. As a result, since the size of the bump electrode formed on the surface protective film is large, the surface of the bump electrode has an uneven shape reflecting the uneven shape of the surface protective film. In the present embodiment, this is a problem, and a configuration (first feature point) is conceived in which a dummy pattern is provided on the uppermost wiring layer to flatten the surface of the bump electrode. That is, the technical idea of providing a dummy pattern in the intermediate layer, which is a conventional technique, is different in the premise and configuration, and even if it is suggested that the dummy pattern is simply formed in the intermediate layer, There is no suggestion of a motivation to easily come up with feature points.

  The second feature point (technical idea) in the present embodiment is that the surface protective film covering the uppermost wiring layer is planarized by the CMP method. The technique of polishing the surface of the intermediate layer of the multilayer wiring layer by the CMP method is generally used. In this intermediate layer, the interlayer insulating film is flattened to form another wiring layer on the upper layer. It is necessary. However, in the conventional technique, there is no idea of planarizing the surface protective film formed so as to cover the uppermost wiring layer. This is because it is not necessary to form a wiring layer on the surface protective film, and thus it is not necessary to flatten the surface protective film.

  On the other hand, the semiconductor device in the present embodiment is premised on the LCD driver. The LCD driver is characterized in that the size of the bump electrode formed on the uppermost wiring layer via the surface protective film is increased. On the premise of this configuration, in order to effectively utilize the lower layer (uppermost wiring layer) of the bump electrode, a configuration is adopted in which wiring is arranged directly below the large bump electrode. Assuming this configuration, wiring and space are formed in the uppermost wiring layer immediately below the bump electrode, and a step due to the height difference between the wiring and space is generated. This step is reflected on the surface protective film formed so as to cover the uppermost wiring layer, and unevenness is generated on the surface of the surface protective film. As a result, since the size of the bump electrode formed on the surface protective film is large, the surface of the bump electrode has an uneven shape reflecting the uneven shape of the surface protective film. In the present embodiment, this is a problem, and the surface of the surface protective film is planarized by polishing by the CMP method. In other words, it differs from the technical idea of polishing the interlayer insulating film, which is a conventional technique, and flattening the surface thereof by using a CMP method. Even if it is suggested, the idea that motivates to easily arrive at the feature point of the present embodiment is not suggested.

  The above configuration is a characteristic configuration of the present embodiment. That is, the characteristic configuration of the present embodiment resides in the uppermost wiring layer of the semiconductor chip and the surface protective film on the uppermost wiring layer. A wiring is formed below the uppermost wiring layer of the semiconductor chip, and a semiconductor element is formed on a semiconductor substrate formed below the wiring. The semiconductor chip in this embodiment is an LCD driver. This LCD driver converts the input signal, which is serial data, into parallel data and converts it into an output signal, or converts the voltage value inside the LCD driver so as to apply a predetermined voltage to the liquid crystal display element (pixel). It has functions such as a level shift circuit. The functions of these LCD drivers are realized by a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor) formed on a semiconductor chip. The CMISFET formed in the LCD driver includes a low voltage MISFET that operates at a relatively low operating voltage and a high voltage MISFET that operates at a relatively high operating voltage. Hereinafter, the configuration of the CMISFET and the first layer wiring will be described.

  FIG. 20 is a cross-sectional view showing the configuration of the CMISFET formed in the semiconductor chip in the present embodiment. As shown in FIG. 20, an element isolation region 2 is formed on the surface of a semiconductor substrate 1S made of silicon single crystal. The element isolation region 2 divides active regions (active regions) that form semiconductor elements from each other. Of the active regions divided by the element isolation region 2, a p-type well 3a is formed in the n-channel MISFET formation region, and an n-type well 3b is formed in the p-channel MISFET formation region.

  An n-channel MISFET is formed on the p-type well 3a, and a p-channel MISFET is formed on the n-type well 3b. First, the configuration of the n-channel MISFET will be described. The n-channel MISFET has a gate insulating film 4 on the p-type well 3 a, and a gate electrode 6 a is formed on the gate insulating film 4. The gate electrode 6 a is composed of a laminated film of a polysilicon film 5 and a cobalt silicide film 12 formed on the surface of the polysilicon film 5. The cobalt silicide film 12 is formed to reduce the resistance of the gate electrode 6a.

  Sidewalls 9 are formed on the sidewalls on both sides of the gate electrode 6a, and shallow low-concentration n-type impurity diffusion regions 7 are formed in the semiconductor substrate 1S immediately below the sidewalls 9. The shallow low-concentration n-type impurity diffusion region 7 is a semiconductor region in which an n-type impurity such as phosphorus or arsenic is introduced into the semiconductor substrate 1S, and is formed in alignment with the gate electrode 6a. A deep high-concentration n-type impurity diffusion region 10 is formed in the semiconductor substrate 1S outside the shallow low-concentration n-type impurity diffusion region 7. The deep high-concentration n-type impurity diffusion region 10 is also a semiconductor region in which an n-type impurity such as phosphorus or arsenic is introduced into the semiconductor substrate 1S, and is formed in alignment with the sidewall 9.

  The shallow low-concentration n-type impurity diffusion region 7 and the deep high-concentration n-type impurity diffusion region 10 form the source region and drain region of the n-channel MISFET. Thus, by forming each of the source region and the drain region from the shallow low-concentration n-type impurity diffusion region 7 and the deep high-concentration n-type impurity diffusion region 10, the source region and the drain region can have an LDD structure. The electric field concentration under the end of the gate electrode 6a can be suppressed. A cobalt silicide film 12 is formed on the surface of the deep high-concentration n-type impurity diffusion region 10. The cobalt silicide film 12 is formed for reducing the resistance of the source region and the drain region.

  Next, the configuration of the p-channel MISFET will be described. The p-channel type MISFET has a gate insulating film 4 on the n-type well 3 b, and a gate electrode 6 b is formed on the gate insulating film 4. The gate electrode 6 b is composed of a laminated film of a polysilicon film 5 and a cobalt silicide film 12 formed on the surface of the polysilicon film 5. The cobalt silicide film 12 is formed to reduce the resistance of the gate electrode 6b.

  Sidewalls 9 are formed on the sidewalls on both sides of the gate electrode 6b, and shallow low-concentration p-type impurity diffusion regions 8 are formed in the semiconductor substrate 1S immediately below the sidewalls 9. The shallow low-concentration p-type impurity diffusion region 8 is a semiconductor region in which a p-type impurity such as boron is introduced into the semiconductor substrate 1S, and is formed in alignment with the gate electrode 6b. A deep high-concentration p-type impurity diffusion region 11 is formed in the semiconductor substrate 1S outside the shallow low-concentration p-type impurity diffusion region 8. This deep high-concentration p-type impurity diffusion region 11 is also a semiconductor region in which a p-type impurity such as boron is introduced into the semiconductor substrate 1 </ b> S, and is formed in alignment with the sidewall 9.

  The shallow low-concentration p-type impurity diffusion region 8 and the deep high-concentration p-type impurity diffusion region 11 form the source region and drain region of the p-channel MISFET. Thus, by forming each of the source region and the drain region from the shallow low-concentration p-type impurity diffusion region 8 and the deep high-concentration p-type impurity diffusion region 11, the source region and the drain region can have an LDD structure. The electric field concentration under the end of the gate electrode 6b can be suppressed. A cobalt silicide film 12 is formed on the surface of the deep high-concentration p-type impurity diffusion region 11. The cobalt silicide film 12 is formed for reducing the resistance of the source region and the drain region.

  Next, a wiring structure connected to the CMIFET will be described. An interlayer insulating film 13 made of a silicon oxide film is formed on the CMISFET so as to cover the CMISFET. A contact hole 14 is formed in the interlayer insulating film 13 so as to penetrate the interlayer insulating film 13 and reach the cobalt silicide film 12 constituting the source region and the drain region. Inside the contact hole 14, a titanium / titanium nitride film 15 a that is a barrier conductor film is formed, and a tungsten film 15 b is formed so as to fill the contact hole 14. Thus, the conductive plug 16 is formed by embedding the titanium / titanium nitride film 15a and the tungsten film 15b in the contact hole 14. A wiring 18 is formed on the interlayer insulating film 13 and the wiring 18 and the plug 16 are electrically connected. The wiring 18 is formed of, for example, a laminated film of a titanium / titanium nitride film 17a, an aluminum film 17b, and a titanium / titanium nitride film 17c. An interlayer insulating film 19 is formed on the wiring 18.

  Further, a multilayer wiring layer is formed in the upper layer, and the above-described uppermost wiring layer is formed in the uppermost layer. The structure above the uppermost wiring layer has the structure shown in FIGS. 5 and 6 described above. Thus, the semiconductor device (LCD driver) in the present embodiment is configured.

  The CMISFET in this embodiment is configured as described above, and a simple operation will be described below. The operation will be described by taking an n-channel type MISFET as an example. First, the operation for turning on the n-channel MISFET will be described. When a predetermined voltage equal to or higher than the threshold voltage is applied to the gate electrode 6a, a channel which is an n-type semiconductor region is formed on the surface of the semiconductor substrate 1S (p-type well 3a) immediately below the gate electrode 6a. At this time, since the source region and the drain region are formed of n-type semiconductor regions, the source region and the drain region are electrically connected through the channel. Therefore, when a potential difference between the source region and the drain region is given, a current flows between the source region and the drain region. As a result, the n-channel MISFET is turned on.

  Next, an operation for turning off the n-channel MISFET will be described. When a predetermined voltage equal to or lower than the threshold voltage is applied to the gate electrode 6a, the channel formed on the surface of the semiconductor substrate 1S (p-type well 3a) immediately below the gate electrode 6a disappears. At this time, the source region and the drain region which are electrically connected through the channel are electrically insulated as the channel disappears. Therefore, no current flows between the source region and the drain region. As a result, the n-channel MISFET is turned off. By thus turning on / off the n-channel MISFET, the integrated circuit constituting the LCD driver performs a predetermined operation.

  Next, a method for manufacturing a semiconductor device (LCD driver) in the present embodiment will be described with reference to the drawings. FIG. 21 is a flowchart showing the CMISFET manufacturing process. First, the process of forming the CMISFET and the first layer wiring will be described with reference to FIGS.

  First, a semiconductor substrate 1S made of a silicon single crystal into which a p-type impurity such as boron (B) is introduced is prepared. At this time, the semiconductor substrate 1S is in a state of a substantially wafer-shaped semiconductor wafer. Then, an element isolation region 2 for isolating elements is formed in the CMISFET formation region of the semiconductor substrate 1S (S101). The element isolation region 2 is provided in order to prevent the elements from interfering with each other. This element isolation region can be formed by using, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region 2 is formed as follows. That is, the element isolation trench is formed in the semiconductor substrate 1S by using the photolithography technique and the etching technique. Then, a silicon oxide film is formed on the semiconductor substrate 1S so as to fill the element isolation trench, and then unnecessary silicon oxide formed on the semiconductor substrate 1S by chemical mechanical polishing (CMP). Remove the membrane. Thereby, the element isolation region 2 in which the silicon oxide film is buried only in the element isolation trench can be formed.

  Next, a well is formed by introducing impurities into the active region isolated in the element isolation region (S102). For example, the p-type well 3a is formed in the n-channel MISFET formation region of the active region, and the n-type well 3b is formed in the p-channel MISFET formation region. The p-type well 3a is formed by introducing a p-type impurity such as boron into a semiconductor substrate by ion implantation. Similarly, the n-type well 3b is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate by ion implantation.

  Subsequently, a semiconductor region for channel formation (not shown) is formed in the surface region of the p-type well and the surface region of the n-type well. This channel forming semiconductor region is formed to adjust the threshold voltage for forming the channel.

  Next, the gate insulating film 4 is formed on the semiconductor substrate 1S (S103). The gate insulating film 4 is formed of, for example, a silicon oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating film 4 is not limited to the silicon oxide film and can be variously changed. For example, the gate insulating film 4 may be a silicon oxynitride film (SiON). That is, a structure in which nitrogen is segregated at the interface between the gate insulating film 4 and the semiconductor substrate 1S may be employed. The silicon oxynitride film has a higher effect of suppressing generation of interface states in the film and reducing electron traps than the silicon oxide film. Therefore, the hot carrier resistance of the gate insulating film 4 can be improved, and the insulation resistance can be improved. In addition, the silicon oxynitride film is less likely to penetrate impurities than the silicon oxide film. For this reason, by using a silicon oxynitride film for the gate insulating film 4, it is possible to suppress fluctuations in threshold voltage caused by diffusion of impurities in the gate electrode toward the semiconductor substrate. For example, the silicon oxynitride film may be formed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO2, or NH3. Further, after forming the gate insulating film 4 made of a silicon oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in an atmosphere containing nitrogen, and nitrogen is segregated at the interface between the gate insulating film 4 and the semiconductor substrate 1S. The same effect can be obtained also by making it.

  The gate insulating film 4 may be formed of a high dielectric constant film having a dielectric constant higher than that of a silicon oxide film, for example. Conventionally, a silicon oxide film has been used as the gate insulating film 4 from the viewpoint of high insulation resistance and excellent electrical and physical stability at the silicon-silicon oxide interface. However, with the miniaturization of elements, the thickness of the gate insulating film 4 is required to be extremely thin. When such a thin silicon oxide film is used as the gate insulating film 4, a so-called tunnel current is generated in which electrons flowing through the channel of the MISFET tunnel through the barrier formed by the silicon oxide film and flow to the gate electrode.

  Therefore, by using a material having a dielectric constant higher than that of the silicon oxide film, a high dielectric film capable of increasing the physical film thickness even with the same capacitance has been used. According to the high dielectric film, since the physical film thickness can be increased even if the capacitance is the same, the leakage current can be reduced.

  For example, a hafnium oxide film (HfO 2 film), which is one of hafnium oxides, is used as the high dielectric film. Instead of the hafnium oxide film, a hafnium aluminate film, an HfON film (hafnium oxynitride film) is used. Other hafnium-based insulating films such as HfSiO film (hafnium silicate film), HfSiON film (hafnium silicon oxynitride film), and HfAlO film can also be used. Further, a hafnium-based insulating film in which an oxide such as tantalum oxide, niobium oxide, titanium oxide, zirconium oxide, lanthanum oxide, or yttrium oxide is introduced into these hafnium-based insulating films can also be used. Since the hafnium-based insulating film has a dielectric constant higher than that of the silicon oxide film or the silicon oxynitride film, like the hafnium oxide film, the same effect as that obtained when the hafnium oxide film is used can be obtained.

  Subsequently, a polysilicon film 5 is formed on the gate insulating film 4. The polysilicon film 5 can be formed using, for example, a CVD method. Then, n-type impurities such as phosphorus and arsenic are introduced into the polysilicon film 5 formed in the n-channel type MISFET formation region by using a photolithography technique and an ion implantation method. Similarly, p-type impurities such as boron are introduced into the polysilicon film 5 formed in the p-channel MISFET formation region.

  Next, the polysilicon film 5 is processed by etching using the patterned resist film as a mask to form a gate electrode 6a in the n-channel MISFET formation region and a gate electrode 6b in the p-channel MISFET formation region ( S104).

  Here, an n-type impurity is introduced into the polysilicon film 5 at the gate electrode in the n-channel MISFET formation region. For this reason, the work function value of the gate electrode 6a can be set to a value in the vicinity of the conduction band of silicon (4.15 eV), so that the threshold voltage of the n-channel MISFET can be reduced. On the other hand, a p-type impurity is introduced into the polysilicon film 5 in the gate electrode 6b in the p-channel MISFET formation region. Therefore, the work function value of the gate electrode 6b can be set to a value in the vicinity of the valence band of silicon (5.15 eV), so that the threshold voltage of the p-channel MISFET can be reduced. Thus, in the first embodiment, the threshold voltage can be reduced in both the n-channel MISFET and the p-channel MISFET (dual gate structure).

  Subsequently, a shallow low-concentration n-type impurity diffusion region 7 aligned with the gate electrode 6a of the n-channel MISFET is formed by using a photolithography technique and an ion implantation method. The shallow low-concentration n-type impurity diffusion region 7 is a semiconductor region. Similarly, a shallow low-concentration p-type impurity diffusion region 8 is formed in the p-channel type MISFET formation region. The shallow low-concentration p-type impurity diffusion region 8 is formed in alignment with the gate electrode 6b of the p-channel MISFET. The shallow low-concentration p-type impurity diffusion region 8 can be formed by using a photolithography technique and an ion implantation method (S105).

  Next, a silicon oxide film is formed on the semiconductor substrate 1S. The silicon oxide film can be formed using, for example, a CVD method. Then, the silicon oxide film is anisotropically etched to form side walls 9 on the side walls of the gate electrodes 6a and 6b (S106). Although the sidewall 9 is formed from a single layer film of a silicon oxide film, the present invention is not limited to this. For example, a sidewall formed of a laminated film of a silicon nitride film and a silicon oxide film may be formed.

  Subsequently, a deep high-concentration n-type impurity diffusion region 10 aligned with the sidewall 9 is formed in the n-channel MISFET formation region by using a photolithography technique and an ion implantation method (S107). The deep high-concentration n-type impurity diffusion region 10 is a semiconductor region. The deep high-concentration n-type impurity diffusion region 10 and the shallow low-concentration n-type impurity diffusion region 7 form a source region. Similarly, a drain region is formed by the deep high-concentration n-type impurity diffusion region 10 and the shallow low-concentration n-type impurity diffusion region 7. By forming the source region and the drain region with the shallow n-type impurity diffusion region and the deep n-type impurity diffusion region in this way, the source region and the drain region can have an LDD (Lightly Doped Drain) structure.

  Similarly, a deep high-concentration p-type impurity diffusion region 11 aligned with the sidewall 9 is formed in the p-channel MISFET formation region. The deep high-concentration p-type impurity diffusion region 11 and the shallow low-concentration p-type impurity diffusion region 8 form a source region and a drain region. Therefore, the source region and the drain region also have an LDD structure in the p-channel type MISFET.

  In this way, after the deep high-concentration n-type impurity diffusion region 10 and the deep high-concentration p-type impurity diffusion region 11 are formed, a heat treatment at about 1000 ° C. is performed. Thereby, the introduced impurities are activated.

  Thereafter, a cobalt film is formed on the semiconductor substrate. At this time, a cobalt film is formed so as to be in direct contact with the gate electrodes 6a and 6b. Similarly, the cobalt film is also in direct contact with the deep high-concentration n-type impurity diffusion region 10 and the deep high-concentration p-type impurity diffusion region 11.

  The cobalt film can be formed using, for example, a sputtering method. Then, after the cobalt film is formed, heat treatment is performed to react the polysilicon film 5 constituting the gate electrodes 6a and 6b with the cobalt film, thereby forming the cobalt silicide film 12 (S108). As a result, the gate electrodes 6 a and 6 b have a laminated structure of the polysilicon film 5 and the cobalt silicide film 12. The cobalt silicide film 12 is formed for reducing the resistance of the gate electrode. Similarly, by the heat treatment described above, the cobalt silicide film 12 is formed by the reaction between the silicon and the cobalt film on the surfaces of the deep high-concentration n-type impurity diffusion region 10 and the deep high-concentration p-type impurity diffusion region 11. Therefore, the resistance can be reduced also in the deep high-concentration n-type impurity diffusion region 10 and the deep high-concentration p-type impurity diffusion region 11.

  Then, the unreacted cobalt film is removed from the semiconductor substrate 1S. In the first embodiment, the cobalt silicide film 12 is formed. However, for example, a nickel silicide film or a titanium silicide film may be formed instead of the cobalt silicide film 12.

  Next, a silicon oxide film to be the interlayer insulating film 13 is formed on the main surface of the semiconductor substrate 1S (S109). This silicon oxide film can be formed using, for example, a CVD method using TEOS (tetraethyl orthosilicate) as a raw material. Thereafter, the surface of the silicon oxide film is planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

  Subsequently, contact holes 14 are formed in the silicon oxide film by using a photolithography technique and an etching technique. Then, a titanium / titanium nitride film 15 a is formed on the silicon oxide film including the bottom surface and inner wall of the contact hole 14. The titanium / titanium nitride film 15a is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by using, for example, a sputtering method. The titanium / titanium nitride film 15a has a so-called barrier property that prevents, for example, tungsten, which is a material of a film to be embedded in a later step, from diffusing into silicon.

  Subsequently, a tungsten film 15b is formed on the entire main surface of the semiconductor substrate 1S so as to fill the contact hole. The tungsten film 15b can be formed using, for example, a CVD method. Then, the plug 16 can be formed by removing the unnecessary titanium / titanium nitride film 15a and tungsten film 15b formed on the silicon oxide film, for example, by CMP (S110).

  Next, a titanium / titanium nitride film 17a, an aluminum film 17b containing copper, and a titanium / titanium nitride film 17c are sequentially formed on the silicon oxide film and the plug 16. These films can be formed by using, for example, a sputtering method. Subsequently, these films are patterned by using a photolithography technique and an etching technique to form the wiring 18 (S111). Further, a wiring is formed on the upper layer of the wiring to form a multilayer wiring. In this way, the CMISFET and the multilayer wiring can be formed on the semiconductor substrate 1S.

  Subsequently, steps after the step of forming the uppermost wiring layer constituting the multilayer wiring layer will be described with reference to the drawings. As shown in FIG. 22, first, an interlayer insulating film is formed. The interlayer insulating film is composed of a laminated film of the silicon oxide film 20 and the silicon oxide film 21. The silicon oxide film 20 can be formed using, for example, a plasma CVD (Chemical Vapor Deposition) method. The silicon oxide film 21 is formed using TEOS as a material.

  Next, a conductor film 22 is formed on the silicon oxide film 21. The conductor film 22 is formed of, for example, an aluminum film, and can be formed by using, for example, a sputtering method. The conductor film 22 is formed of an aluminum film, but actually has a structure in which the upper and lower sides of the aluminum film are sandwiched between titanium / titanium nitride films. Then, as shown in FIG. 23, the conductor film 22 is processed by using a photolithography technique and an etching technique. By processing the conductor film 22, an uppermost wiring layer is formed on the silicon oxide film 21. The uppermost wiring layer is formed of, for example, a pad PD, a wiring L1, and a dummy pattern DP. The dummy pattern DP is formed in the space between the wirings L1, and the step caused by the height difference between the wiring L1 and the space can be relaxed by the dummy pattern DP formed in the same layer as the wiring L1.

  Subsequently, as shown in FIG. 24, a silicon oxide film 22a covering the uppermost wiring layer is formed. The silicon oxide film 22a can be formed by, for example, a plasma CVD method. Since the dummy pattern DP is formed in the uppermost wiring layer so as to fill the space between the wirings L1, an uneven shape reflecting the shape of the uppermost wiring layer is formed on the surface of the silicon oxide film 22a. Can be suppressed. That is, since the space between the wirings L1 is filled with the dummy pattern DP, the unevenness formed on the surface of the silicon oxide film 22a is relaxed in the dummy pattern DP formation region.

  Thereafter, as shown in FIG. 25, a silicon oxide film 23 is formed on the silicon oxide film 22a. The silicon oxide film 23 can be formed by, for example, a CVD method using TEOS as a material. Next, as shown in FIG. 26, the surface of the silicon oxide film 23 is planarized. In order to planarize the surface of the silicon oxide film 23, for example, a chemical mechanical polishing method (CMP method) can be used. The CMP method is a method in which a polishing liquid (slurry) containing silica particles is flowed over a semiconductor substrate, and the surface of the semiconductor substrate is pressed against a polishing pad for polishing. Both the chemical mechanism of oxidizing the surface of the material layer to be polished with the slurry and the mechanical mechanism of mechanically scraping the oxide layer are utilized.

  Here, the surface unevenness of the silicon oxide film 22a formed under the silicon oxide film 23 is relaxed by the dummy pattern DP. For this reason, the unevenness | corrugation of the silicon oxide film 23 formed on the silicon oxide film 22a is eased. Accordingly, the polishing for polishing the surface of the silicon oxide film 23 (polishing by CMP) is relatively easy because the unevenness formed on the surface of the silicon oxide film 23 is relaxed. it can. That is, by forming the dummy pattern DP in the uppermost wiring layer, it is possible to facilitate the flattening of the silicon oxide film 23 performed thereafter.

  Next, as shown in FIG. 27, a silicon nitride film 24 is formed on the silicon oxide film 23. The silicon nitride film 24 can be formed by, for example, a plasma CVD method. In this manner, a surface protective film made of the silicon oxide film 22a, the silicon oxide film 23, and the silicon nitride film 24 can be formed on the uppermost wiring layer.

  Subsequently, as shown in FIG. 28, an opening 25 is formed in the surface protective film by using a photolithography technique and an etching technique. The opening 25 is formed on the pad PD and exposes the surface of the pad PD. The size of the opening 25 is formed to be smaller than the size of the pad PD.

  Next, as shown in FIG. 29, an UBM (Under Bump Metal) film 26 is formed on the surface protective film including the inside of the opening 25. The UBM film 26 can be formed by using, for example, a sputtering method, and is formed by a single layer film or a laminated film such as a titanium film, a nickel film, a palladium film, a titanium / tungsten alloy film, a titanium nitride film, or a gold film. ing. Here, the UBM film 26 has a function of improving the adhesiveness between the bump electrode and the pad PD or the surface protective film, and the metal element of the gold film formed in the subsequent process moves to the wiring L1 or the like. On the contrary, it is a film having a barrier function for suppressing or preventing the metal element such as the wiring L1 from moving to the gold film side.

  Subsequently, as shown in FIG. 30, after a resist film 27 is applied on the UBM film 26, the resist film 27 is subjected to exposure / development and patterned. The patterning is performed so that the resist film 27 does not remain in the bump electrode formation region. Then, as shown in FIG. 31, a gold film 28 is formed using a plating method. At this time, the gold film 28 is formed on the surface protective film (silicon nitride film 24) and is also embedded in the opening 25. A plug SIL is formed by embedding the gold film 28 in the opening 25.

  Thereafter, as shown in FIG. 32, the patterned resist film 27 and the UBM film 26 covered with the resist film 27 are removed, thereby forming the bump electrode BP1 including the gold film 28 and the UBM film 26. The bump electrode BP1 is formed larger than the pad PD, and the wiring L1 is disposed in the uppermost wiring layer immediately below the bump electrode BP1. Thus, by forming the wiring L1 directly under the bump electrode BP1, the region immediately under the bump electrode BP1 can be used effectively, and the semiconductor device can be downsized. Further, by arranging the dummy pattern DP in addition to the power supply wiring and the signal wiring L1 in the region immediately below the bump electrode BP1, the flatness of the surface protective film formed on the uppermost wiring layer is improved. Can do. That is, if only the power supply wiring and the signal wiring (wiring L1) are formed in the uppermost layer of the multilayer wiring layer, the uppermost layer cannot be densely filled with wiring, so that the unevenness due to the power supply wiring and the signal wiring (wiring L1) is remarkable However, the flatness of the uppermost wiring layer can be improved by spreading the dummy pattern DP in addition to the power supply wiring and the signal wiring. Further, since the surface of the surface protective film is flattened by the CMP method, the flatness of the surface protective film formed on the uppermost wiring layer is ensured, and the flatness of the bump electrode formed on the surface of the surface protective film is also ensured. It can be improved. Thereafter, the semiconductor substrate can be obtained by dicing the semiconductor substrate.

  Next, the semiconductor chip formed as described above is mounted on the mounting substrate. FIG. 33 shows a case where the semiconductor chip CHP is mounted on the glass substrate 30 (COG: Chip On Glass). As shown in FIG. 33, a glass substrate 31 is mounted on the glass substrate 30, whereby a display portion of the LCD is formed. A semiconductor chip CHP, which is an LCD driver, is mounted on the glass substrate 30 in the vicinity of the display unit of the LCD. Bump electrodes BP1 and BP2 are formed on the semiconductor chip CHP, and the bump electrodes BP1 and BP2 and terminals formed on the glass substrate 30 are connected via an anisotropic conductive film ACF. Yes. Further, the glass substrate 30 and a flexible printed circuit (Flexible Printed Circuit) 32 are also connected by an anisotropic conductive film ACF. In the semiconductor chip CHP mounted on the glass substrate 30 as described above, the output bump electrode BP2 is electrically connected to the display unit of the LCD, and the input bump electrode BP1 is connected to the flexible printed circuit board 32. .

  FIG. 34 is an enlarged view of a portion where the semiconductor chip CHP is mounted on the glass substrate 30. In FIG. 34, a terminal 30a is formed on the glass substrate 30, and bump electrodes BP1 and BP2 formed on the semiconductor chip CHP are electrically connected to the terminal 30a. At this time, the bump electrodes BP1 and BP2 and the terminal 30a are not in direct contact, but are connected via the anisotropic conductive film ACF. The anisotropic conductive film ACF is a film formed by mixing a thermosetting resin with fine metal particles 33 having conductivity and molding it into a film shape. The metal particles 33 are formed of spheres having a diameter of 3 μm to 5 μm, in which a nickel layer and a gold plating layer are mainly formed from the inside, and an insulating layer is stacked on the outermost side.

  When the semiconductor chip CHP is mounted on the glass substrate 30, the anisotropic conductive film ACF is sandwiched between the terminals 30a of the glass substrate 30 and the bump electrodes BP1 and BP2 of the semiconductor chip CHP. When the semiconductor chip CHP is pressurized while applying heat with a heater or the like, pressure is applied only to the portions corresponding to the bump electrodes BP1 and BP2. Then, the metal particles 33 dispersed in the anisotropic conductive film ACF are overlapped while contacting, and the metal particles 33 are pressed against each other. As a result, a conductive path is formed in the anisotropic conductive film ACF via the metal particles 33. Since the metal particles 33 in the portion of the anisotropic conductive film ACF where no pressure is applied hold the insulating layer formed on the surface of the metal particles 33, between the bump electrodes BP1 arranged side by side and sideways. The insulation between the arranged bump electrodes BP2 is maintained. For this reason, there is an advantage that the semiconductor chip CHP can be mounted on the glass substrate 30 without causing a short circuit even if the interval between the bump electrodes BP1 or the bump electrodes BP2 is narrow.

  In the first embodiment, in the semiconductor chip, a dummy pattern is spread over the uppermost wiring layer, and a surface protective film covering the uppermost wiring layer is planarized by CMP. For this reason, the flatness of the bump electrode formed on the surface protective film is improved. Therefore, the contact between the bump electrode and the metal particles in the anisotropic conductive film can be satisfactorily performed over the entire bump electrode. Therefore, the connection reliability between the bump electrode of the semiconductor chip and the terminal (wiring) of the mounting substrate can be improved.

  FIG. 35 is a diagram showing an overall configuration of an LCD (liquid crystal display device 35). As shown in FIG. 35, an LCD display unit 34 is formed on a glass substrate, and an image is displayed on the display unit 34. A semiconductor chip CHP, which is an LCD driver, is mounted on a glass substrate in the vicinity of the display unit 34. A flexible printed circuit board 32 is mounted in the vicinity of the semiconductor chip CHP, and a semiconductor chip CHP as a driver is mounted between the flexible printed circuit board 32 and the display unit 34 of the LCD. In this way, the semiconductor chip CHP can be mounted on the glass substrate. As described above, the semiconductor chip CHP as the LCD driver can be mounted on the liquid crystal display device 35.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

1S semiconductor substrate 2 element isolation region 3a p-type well 3b n-type well 4 gate insulating film 5 polysilicon film 6a gate electrode 6b gate electrode 7 low-concentration n-type impurity diffusion region 8 low-concentration p-type impurity diffusion region 9 sidewall 10 high N-type impurity diffusion region 11 High-concentration p-type impurity diffusion region 12 Cobalt silicide film 13 Interlayer insulating film 14 Contact hole 15a Titanium / titanium nitride film 15b Tungsten film 16 Plug 17a Titanium / titanium nitride film 17b Aluminum film 17c Titanium / titanium nitride Film 18 Wiring 19 Interlayer insulating film 20 Silicon oxide film 21 Silicon oxide film 22 Conductor film 22a Silicon oxide film 23 Silicon oxide film 24 Silicon nitride film 25 Opening 26 UBM film 27 Resist film 28 Gold film 30 Glass substrate 30a Terminal 3 Glass substrate 32 Flexible substrate 33 Metal particle 34 Display unit 35 Liquid crystal display device 100 Interlayer insulating film 101 Surface protective film 102 Conductive particle 103 Glass substrate 103a Wiring ACF Anisotropic conductive film BP Bump electrode BP1 Bump electrode BP2 Bump electrode CHP Semiconductor chip DP Dummy pattern DR Dummy pattern forming area L1 wiring L2 wiring NDR Dummy pattern non-forming area PD pad R area RF resist film S1 uneven width S2 uneven width SIL plug X overlapping area Y non-overlapping area

Claims (10)

A rectangular semiconductor substrate;
A semiconductor element formed on the semiconductor substrate;
A multilayer wiring layer formed on the semiconductor element;
A first pad and a second pad formed in the same layer as the uppermost wiring of the multilayer wiring layer;
A plurality of dummy patterns formed in the same layer as the uppermost layer wiring of the multilayer wiring layer and disposed in a region different in plan from the first pad and the second pad;
The first pad is formed on the first pad, the second pad, and the plurality of dummy patterns, and has a first opening and a second opening, and the first opening is formed on a surface of the first pad. And a first insulating film in which the second opening is disposed on the surface of the second pad;
A first bump electrode formed on the first insulating film and electrically connected to the first pad via the first opening, and electrically connected to the second pad via the second opening A second bump electrode connected to
With
The first bump electrode and the second bump electrode are disposed adjacently along one long side of the semiconductor substrate,
The plurality of dummy patterns are disposed in regions different from the first bump electrode and the second bump electrode in a plane,
In plan view, the plurality of dummy patterns are disposed between the first bump electrode and the second bump electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of dummy patterns are disposed between the first pad and the second pad. The semiconductor device according to claim 1,
The semiconductor device, wherein the plurality of dummy patterns are arranged at different positions in a plane between the first pad and the second pad. The semiconductor device according to claim 1,
The first pad and the second pad are disposed along the one long side,
Each of the first bump electrode and the second bump electrode extends in a direction orthogonal to one long side of the semiconductor substrate. The semiconductor device according to claim 1,
The first bump electrode and the second bump electrode have a rectangular shape,
A semiconductor device, wherein each short side of each of the first bump electrode and the second bump electrode is disposed along one long side of the semiconductor substrate. The semiconductor device according to claim 1,
The thickness of the plurality of dummy patterns is the same as that of the first pad and the second pad. The semiconductor device according to claim 1,
The first insulating film includes a silicon oxide film formed so as to cover the first pad, the second pad, and the plurality of dummy patterns, and a silicon nitride film formed on the silicon oxide film. Semiconductor device. The semiconductor device according to claim 1,
The uppermost layer wiring of the multilayer wiring layer includes a first wiring that extends in a plane so as to intersect with the long sides of the first bump electrode and the second bump electrode. The semiconductor device according to claim 8,
The plurality of dummy patterns have a rectangular shape,
A semiconductor device, wherein a short side of each of the plurality of dummy patterns is smaller than a width of the first wiring. The semiconductor device according to claim 9.
A semiconductor device, wherein a long side of each of the plurality of dummy patterns is smaller than a width of the first wiring.

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