JP5916515B2 - Capacitance measurement system, capacitance measurement method, capacitor cell degradation state estimation system, and degradation state estimation method - Google Patents

Description

  The present invention relates to a capacitance measuring system and a capacitance measuring method for measuring the capacitance of a capacitor cell when equalizing the cell voltage of the capacitor cell in a power storage device including a plurality of capacitor cells. In addition, the present invention relates to a degradation state estimation system and degradation state estimation method for a capacitor cell that estimates a degradation state of the capacitor cell from the measured capacitance of the capacitor cell.

  It is known that the characteristics of a capacitor cell such as an electric double layer capacitor or a lithium ion capacitor change due to deterioration over time, the capacitance of the capacitor cell gradually decreases, and the internal resistance gradually increases.

For this reason, a power storage device including a plurality of capacitor cells has a reduced power storage capacity as the capacitor cells age.
Such a deterioration state of the capacitor cell is determined by detecting the charging current or the discharging current during charging / discharging of the power storage device, and measuring the static voltage of each capacitor cell measured based on the change over time of the charging current or discharging current and the cell voltage. It is common to estimate from the electric capacity.

  As described above, when the method of estimating the capacitance of the capacitor cell using the charging current or the discharging current is used, the deterioration state of the capacitor cell cannot be estimated unless the power storage device is in a charging / discharging state. In order to estimate the deterioration state of the capacitor cell, a measuring device for measuring the charge / discharge current is required.

  For this reason, for example, in Patent Document 1, as shown in FIG. 4, the voltage detection means 104 for detecting the cell voltage of the capacitor cell 102 connected in parallel to the capacitor cell 102 and the capacitor cell 102 are connected in parallel. There has been proposed a capacitor life determination device 100 provided with an inspection circuit 106 connected to the capacitor.

In the inspection circuit 106, a discharge switch 108 and a short-circuit switch 110 to which a discharge resistor r is connected in parallel are connected in series.
In this life determination apparatus 100, when the capacitor cell 102 is fully charged, the discharge switch 108 is turned on and the short-circuit switch 110 is turned off, thereby forming a closed circuit of the capacitor cell 102 and the discharge resistor r. Then, the discharge of the capacitor cell 102 is started.

  Then, by measuring the constant resistance discharge time from the fully charged state to the set voltage, based on the initial constant resistance discharge time when the capacitor is not deteriorated and the time constant resistance discharge time when the capacitor is deteriorated The determination of the deterioration state of the electric double layer capacitor is disclosed.

JP 2008-27946 A

  By the way, the power storage device including such a capacitor cell has a problem that the voltage range that can be used by the power storage device becomes narrow when the voltage between the cells varies.

For this reason, the power storage device including the capacitor cell is provided with an equalization control circuit (balance correction circuit) for correcting the voltage balance between the cells.
FIG. 5 is a circuit configuration diagram of the power storage device 200 including the equalization control circuit 202.

As shown in FIG. 5, in the equalization control circuit 202, charge consuming resistors R _{S1 to} R _Sn and FETs (Field Effect Transistors) are connected to a plurality of capacitor cells C _{S1 to} C _Sn connected in series. Switches S _{S1 to} S _Sn composed of field effect transistors are connected in parallel.

Then, the microcomputer 204, with on the basis of the voltage signal from the voltmeter V _s1 ~V _sn measuring the open circuit voltage of the capacitor cells C _S1 -C _Sn, calculates a target voltage value of each capacitor cell C _S1 -C _Sn The switches S _{S1 to} S _Sn are controlled in order to adjust the voltages of the capacitor cells C _{S1 to} C _Sn .

In the equalization control circuit 202 configured as described above, the switches S _{S1 to} S _Sn are turned on by the microcomputer 204 until the voltage values of the capacitor cells C _{S1 to} C _Sn reach the target voltage values, and the capacitor cell S Control is performed so that the charges of _{S1 to} S _Sn are consumed by the resistors R _{S1 to} R _Sn .

  Thus, by equalizing the cell voltage by the equalization control circuit, the voltage range that can be used by the power storage device can always be maximized. For this reason, the equalization control circuit plays an important role in a power storage device including a plurality of capacitor cells.

  In the present invention, a capacitance measurement system that measures the capacitance of a capacitor cell using an equalization control circuit during cell voltage equalization control without providing a dedicated circuit for measuring capacitance, and An object of the present invention is to provide a capacitance measuring method.

  A further object of the present invention is to provide a degradation state estimation system and degradation state estimation method for a capacitor cell that estimates the degradation state of the capacitor cell from the measured capacitance of the capacitor cell.

The present invention was invented to achieve the above-described object, and the capacitance measurement system of the present invention measures the capacitance of a capacitor cell in a power storage device including a plurality of capacitor cells. A capacitance measuring system that
An equalization control resistor and an equalization control switch connected in parallel to each of the plurality of capacitor cells;
A cell voltage detection circuit for detecting a cell voltage of each of the plurality of capacitor cells;
An equalization cell selection circuit for controlling the equalization control switch;
An arithmetic processing unit for controlling the equalization cell selection circuit,
The arithmetic processing unit is
Based on the cell voltage of the plurality of capacitor cells measured by the cell voltage detection circuit, to calculate the equalization control time,
The equalization control switch connected in parallel to the capacitor cell is turned on so that a current flows from the capacitor cell to the equalization control resistor so as to consume the charge of the capacitor cell. Controlling the equalization cell selection circuit,
The cell voltage detection circuit detects a measurement start voltage that is a cell voltage of the capacitor cell at the time when the equalization control switch is turned on,
After the equalization control time has elapsed, the equalization cell selection circuit is controlled to turn off the equalization control switch connected in parallel to the capacitor cell,
The cell voltage detection circuit detects a measurement end voltage that is a cell voltage of the capacitor cell when the equalization control switch is turned off.
The capacitance of the capacitor cell is calculated based on the equalization control time, the measurement start voltage, and the measurement end voltage.

Further, the capacitance measuring method of the capacitor cell of the present invention is a capacitance measuring method for measuring the capacitance of the capacitor cell in a power storage device including a plurality of capacitor cells,
Measuring cell voltages of the plurality of capacitor cells;
Calculating an equalization control time based on the measured cell voltages of the plurality of capacitor cells;
The equalization control of the plurality of capacitor cells is performed based on the equalization control time, the measurement start voltage that is the voltage of the capacitor cell at the start of the equalization control, and the capacitor cell at the end of the equalization control Measuring a measurement end voltage which is a voltage of
Calculating a capacitance of the capacitor cell based on the equalization control time, the measurement start voltage, and the measurement end voltage.

  With this configuration, for example, the capacitance of the capacitor cell can be measured using an equalization control circuit provided in the power storage device, so that no dedicated circuit is provided, and the capacitor cell Capacitance of the capacitor cell can be measured while performing equalization control.

Moreover, the capacitance measuring system of the present invention is configured such that the arithmetic processing unit calculates the capacitance of the capacitor cell based on the following formula 4.

The capacitance measuring method of the present invention is characterized in that the effective capacitance of the capacitor cell is calculated based on the following formula 4.

The capacitance measuring system of the present invention is characterized in that the capacitor cell is a lithium ion capacitor.
The capacitance measuring method of the present invention is characterized in that the capacitor cell is a lithium ion capacitor.

Moreover, the deterioration state estimation system of the present invention includes any one of the capacitance measurement systems described above,
The arithmetic processing unit is
Calculating the capacitance of the capacitor cell which is calculated based on the voltage measurement time, the capacity ratio of the rated capacity of the capacitor cell,
The deterioration state of the capacitor cell is estimated based on the capacity ratio.

The degradation state estimation method of the present invention includes a step of measuring the capacitance of the capacitor cell by any one of the capacitance measurement methods described above.
Calculating a capacitance ratio between the capacitance of the capacitor cell and the rated capacity of the capacitor cell;
And a step of estimating a deterioration state of the capacitor cell based on the capacity ratio.

  According to the present invention, since the equalization control circuit provided in the power storage device is used to measure the capacitance of the capacitor cell and to estimate the deterioration state of the capacitor cell, the deterioration state is estimated. There is no need to provide a dedicated circuit for this.

  Furthermore, since the capacitance is measured during the equalization control of the capacitor cell and the deterioration state of the capacitor cell is estimated, the measurement is performed only for the measurement of the capacitance of the capacitor cell and the estimation of the deterioration state. The power of the power storage device is not consumed.

FIG. 1 is a circuit configuration diagram of a power storage device including the degradation state estimation system of the present invention. FIG. 2 is a flowchart showing a flow of measuring the effective capacitance of the capacitor cells C _{1 to} C _n using the capacitance measuring circuit 11 in the power storage device 10 of FIG. FIG. 3 is a graph of an example of equalization control time calculation data indicating the relationship between the cell voltage and the capacitance stored in advance in the calculation processing device 16. FIG. 4 is a circuit configuration diagram of a conventional capacitor life determination apparatus. FIG. 5 is a circuit configuration diagram showing an example of an equalization control circuit used for equalization control of cell voltages of a plurality of capacitors.

  Hereinafter, embodiments (examples) of the present invention will be described in more detail based on the drawings. In addition, although embodiment of a present Example is shown below, this invention is not limited to this embodiment. The embodiment used in the present invention can be suitably used for capacitor cells such as lithium ion capacitors and electric double layer capacitors.

FIG. 1 is a circuit configuration diagram of a power storage device including the degradation state estimation system of the present invention.
The power storage device 10 of this embodiment includes capacitor cells C _{1 to} C _n and an equalization control circuit 12.

The equalization control circuit 12 is for equalization control composed of equalization control resistors R _{1 to} R _n and FETs (Field Effect Transistors) connected in parallel to the capacitor cells C _{1 to} C _n , respectively. Equalization control switch S connected in parallel to switches S _{1 to} S _n , a cell voltage detection circuit for detecting cell voltages of capacitor cells C _{1 to} C _n , and a capacitor cell for performing equalization control and equalization IC14 comprising equalizing cell selection circuit for controlling the ₁ to S _n, the arithmetic processing unit 16 for controlling the equalizing IC14, operating the processing unit 16 from the capacitor cells C ₁ -C _n And a power supply circuit 18 for supplying electric power for the purpose.

In the present embodiment, FETs are used as the equalization control switches S _{1 to} S _n , but the present invention is not limited to this, and equalization such as high-frequency switches such as diode switches and MEMS (Micro Electro Mechanical Systems) switches is used. A switch capable of controlling on / off based on the output of the cell selection circuit (equalization IC 14 in this embodiment) can be used.

  In this embodiment, an equalization IC 14 (for example, LTC6802 manufactured by Linear Technology Co., Ltd.) including a cell voltage detection circuit and an equalization cell selection circuit is used. However, the cell voltage detection circuit and the equalization cell selection circuit are respectively used. You may comprise independently.

  The arithmetic processing unit 16 is constituted by a CPU (Central Processing Unit), a RAM (Random Access Memory), a ROM (Read Only Memory) in which an arithmetic processing program is stored, and the like. It is configured.

  Further, the arithmetic processing device 16 and the equalization IC 14 transmit, for example, a control command from the arithmetic processing device 16 to the equalization IC 14, or transmit a cell voltage value, a current value, or the like from the equalization IC 14 to the arithmetic processing device 16. For example, the communication means 20 for two-way communication is provided.

On the other hand, the power storage unit 22 of the power storage device 10 is configured by connecting _n capacitor cells C _{1 to} C _n made of lithium ion capacitors in series.
Both ends of the power storage unit 22 are connected to the power supply circuit 18, and are configured to operate the arithmetic processing device 16 using the power of the power storage unit 22. That is, the power storage device 10 including the capacitance measurement circuit 11 of the present embodiment can measure the capacitances of the capacitor cells C _{1 to} C _n using the power of the power storage device 10 itself.

In this embodiment, in order to measure the capacitances of the capacitor cells C _{1 to} C _n using the power of the power storage device 10 itself, a power supply circuit that operates the arithmetic processing device 16 using the power of the power storage unit 22. 18, the power for operating the arithmetic processing device 16 without the power supply circuit 18 when the arithmetic processing device 16 is configured to operate using electric power from the outside of the power storage device 10. Can be directly supplied to the arithmetic processing unit 16 from the outside.

The operation flow of the equalization control circuit 12 when measuring the capacitance of the capacitor cell of this embodiment will be described below with reference to the flowchart shown in FIG.
FIG. 2 is a flowchart showing a flow of measuring the capacitance of the capacitor cells C _{1 to} C _n using the equalization control circuit 12 in the power storage device 10 of FIG.

When a command is sent from the arithmetic processing unit 16 to the equalization IC 14 to measure the capacitances of the capacitor cells C _{1 to} C _n (S10), first, the cell voltage detection circuit (equalization IC 14) is used. Then, the cell voltages of the capacitor cells C _{1 to} C _n are sequentially measured (S20).

It is determined whether or not the cell voltage has been measured for all the capacitor cells C _{1 to} C _n (S25). If there is a capacitor cell whose cell voltage has not been measured, the cell voltage of the next capacitor cell is measured. The The measured cell voltage value is stored in the RAM of the arithmetic processing unit 16 in association with the capacitor cells C _{1 to} C _n .

Next, from the cell voltage values of the capacitor cells C _{1 to} C _n stored in the RAM of the arithmetic processing unit 16, it is determined by the arithmetic processing unit 16 whether equalization control of the capacitor cells C _{1 to} C _n is necessary. (S30).

Whether or not the equalization control of the capacitor cells C _{1 to} C _n is necessary depends on, for example, the case where the difference between the highest cell voltage value and the lowest cell voltage value among the capacitor cells is larger than a predetermined value. When the cell voltage value of the cell is larger than a predetermined upper limit voltage value, it can be determined that equalization control is necessary.

If it is determined that the equalization control is unnecessary, the process returns to S20 and the cell voltages of the capacitor cells C _{1 to} C _n are measured again.
On the other hand, when it is determined that equalization control is necessary, the equalization control time t _m of the capacitor cells C _{1 to} C _n is calculated (S40).

The calculation method of the equalization control time t _m is not particularly limited. For example, the cell voltage values of the capacitor cells C _{1 to} C _n and the equalization target voltage value stored in the RAM of the arithmetic processing unit 16 are used. Based on the cell voltage drop amount calculated by the arithmetic processing unit 16 as a difference from V _T, and the equalization control time calculation data indicating the relationship between the cell voltage and the capacitance stored in the arithmetic processing unit 16 in advance. Can be calculated.

Note that the equalization target voltage value V _T may be a predetermined voltage value, for example, or may be an average of the cell voltage values of the capacitor cells C _{1 to} C _n or input by the user every time equalization control is performed. It can also be configured as follows.

Further, the equalization control time calculation data is, for example, data indicating the relationship between the cell voltage and the capacitance of the capacitor cell as shown in FIG. 3, and by using the equalization control time calculation data, The equalization control time t _m can be calculated as follows.

  For example, when the cell voltage of the capacitor cell is lowered from 3.8 V to 3.7 V, first, the capacitance of the capacitor cell at each voltage is read from the equalization control time calculation data. In this embodiment, the capacitance at 3.8V is 1040F, and the capacitance at 3.7V is 1000F.

At this time, the discharge charge amount Q necessary for lowering the voltage is 102C as shown in Equation 1.

Here, _if the resistance values of the equalization control resistors R _{1 to} R _n are 5.0Ω, the average current value I of the current flowing through the resistors for adjustment is 0.75 A as shown in Equation 2.

From the discharge charge amount Q and the average current value I, the equalization control time t _m necessary for lowering the voltage is calculated as 136 seconds as shown in Equation 3.

The equalization control time t _m calculated in this way is stored in the RAM of the arithmetic processing unit 16 in association with the capacitor cells C _{1 to} C _n .
Next, the equalization control and the equalization control connected in parallel to the capacitor cell C _m for measuring the capacitance (m is a cell number and a value between 1 and n (n ≧ 2)). the use switch S _m is sequentially input state (S50), a current flows to the equalization control resistor R _m from the capacitor cells C _m, to consume the charge of the capacitor cells C _m.

In this state, the measurement start voltage Vds of the capacitor cells C _m measured by the cell voltage detection circuit (equalization IC 14) (S60), in association with the capacitor cells C ₁ -C _n is stored in the RAM of the arithmetic processing unit 16.

Then, actuating the timer for measuring the equalization control time t _m (S70).
For example, a timer or a counter provided in the arithmetic processing unit 16 or the equalization IC 14 can be used as the timer. When the counter is used, the timer is based on the difference between the counter at the end of measurement and the counter at the start of measurement. Thus, the measurement time can be calculated.

During the equalization control of the adjustment target cell C _Tm , the timer is always measured (S80), and it is determined whether the equalization control time t _m has been reached (S85).
Timer, when it reaches the equalization control time t _m is the connected equalizing control switch S _m in parallel to the capacitor cells C _m a switching state (S90), the measuring end of the capacitor cells C _m measure the voltage Vde by the cell voltage detection circuit (equalization IC 14) (S100), in association with the capacitor cells C ₁ -C _n is stored in the RAM of the arithmetic processing unit 16.

It is determined whether equalization control has been performed for all capacitor cells C _m (S110). If there is a capacitor cell for which equalization control has not been performed, the process returns to S50 to repeatedly equalize the capacitor cells. Control is performed.

When equalization control is completed for all the capacitor cells C _{1 to} C _n , in S120, the measurement start voltage Vds, the measurement end voltage Vde, and the equalization control time t stored in the RAM of the arithmetic processing unit 16 are obtained. Based on _m , the capacitances of the capacitor cells C _{1 to} C _n are calculated.

The capacitances of the capacitor cells C _{1 to} C _n can be calculated by, for example, the arithmetic processing unit 16 as in the following Expression 4.

Further, when calculating the capacitance of the capacitor cell more accurately, the consumption current of the arithmetic processing unit 16 and a correction value _Cv as will be described later can be taken into consideration, as shown in the following Expression 5.

Capacitance of the thus calculated capacitor cells C ₁ -C _n is stored in RAM of the arithmetic processing unit 16 in association with the capacitor cells C ₁ -C _n, the capacitance of the capacitor cells C ₁ -C _n The calculation is completed (S130).

The correction value _Cv is a value added to more accurately measure the capacitance of the capacitor cell, and is, for example, the same test capacitor cell as the capacitor cells C _{1 to} C _n used in the power storage device 10. By using C _t and measuring the measurement start voltage Vds and the measurement end voltage Vde at a plurality of equalization control times t _m based on the above S10 to S130, the capacitance obtained from the following equation 6 and the test the difference between the rated capacity of use capacitor cells C _t can be corrected value C _v a.

The correction value C _v can be as a database associated with the voltage value, stored in the RAM of the arithmetic processing unit 16.

Then, the arithmetic processing unit 16 calculates the capacitance ratio between the capacitances of the capacitor cells C _{1 to} C _n stored in the RAM and the rated capacities of the capacitor cells C _{1 to} C _n , and the capacitance ratio is predetermined. If it is smaller than the deterioration ratio, it is determined that the capacitor cell has deteriorated.

The preferred embodiment of the present invention has been described above, but the present invention is not limited to this. For example, in the above embodiment, the cell voltages and voltage measurement times of the capacitor cells C _{1 to} C _n are individually set. The cell voltages of all the capacitor cells C _{1 to} C _n are simultaneously detected by the cell voltage detection circuit, and the cell voltages and voltage measurement times of the capacitor cells C _{1 to} C _n are simultaneously measured. You may make it measure.

Also, a temperature measuring means for measuring the temperature of the capacitor cells C _{1 to} C _n is provided, and when the temperature of the capacitor cell is higher than a predetermined temperature, it is determined that there is an abnormality and the equalization control of the capacitor cell is stopped. You may make it perform abnormality detection, such as making it do.

Further, when thus providing a temperature measuring means, changing the temperature at the time of measurement, by keeping obtain a correction value C _v as described above, to use a correction value C _v corresponding to the measured temperature Various modifications can be made without departing from the object of the present invention.

10 Power Storage Device 12 Equalization Control Circuit 14 Equalization IC
16 arithmetic processing unit 18 power supply circuit 20 communication means 22 power storage unit C ₁ -C _n capacitor cell R ₁ -R _n equalization control resistor S ₁ -S _n equalization control switch 100 life determination device 102 capacitor cell 104 voltage detection Means 106 Inspection circuit 108 Discharge switch 110 Short-circuit switch r Discharge resistor 200 Power storage device 202 Equalization control circuit 204 Microcomputer 206 Voltage measurement circuit C _{S1 to} C _Sn capacitor cells R _{S1 to} R _Sn resistors S _{S1 to} S _Sn switches

Claims (8)

In a power storage device including a plurality of capacitor cells, a capacitance measuring system that measures the capacitance of the capacitor cells,
An equalization control resistor and an equalization control switch connected in parallel to each of the plurality of capacitor cells;
A cell voltage detection circuit for detecting a cell voltage of each of the plurality of capacitor cells;
An equalization cell selection circuit for controlling the equalization control switch;
An arithmetic processing unit for controlling the equalization cell selection circuit,
The arithmetic processing unit is
Based on the cell voltage of the plurality of capacitor cells measured by the cell voltage detection circuit, to calculate the equalization control time,
The equalization control switch connected in parallel to the capacitor cell is turned on so that a current flows from the capacitor cell to the equalization control resistor so as to consume the charge of the capacitor cell. Controlling the equalization cell selection circuit,
The cell voltage detection circuit detects a measurement start voltage that is a cell voltage of the capacitor cell at the time when the equalization control switch is turned on,
After the equalization control time has elapsed, the equalization cell selection circuit is controlled to turn off the equalization control switch connected in parallel to the capacitor cell,
The cell voltage detection circuit detects a measurement end voltage that is a cell voltage of the capacitor cell when the equalization control switch is turned off.
A capacitance measurement system configured to calculate a capacitance of the capacitor cell based on the equalization control time, the measurement start voltage, and the measurement end voltage. 2. The capacitance measurement system according to claim 1, wherein the arithmetic processing unit is configured to calculate a capacitance of the capacitor cell based on the following Equation 4.

  The capacitance measuring system according to claim 1, wherein the capacitor cell is a lithium ion capacitor. A capacitance measuring system according to any one of claims 1 to 3,
The arithmetic processing unit is
Calculating the capacitance of the capacitor cell which is calculated based on the voltage measurement time, the capacity ratio of the rated capacity of the capacitor cell,
A deterioration state estimation system for a capacitor cell, wherein the deterioration state of the capacitor cell is estimated based on the capacity ratio. In a power storage device including a plurality of capacitor cells, a capacitance measuring method for measuring capacitance of the capacitor cells,
Measuring cell voltages of the plurality of capacitor cells;
Calculating an equalization control time based on the measured cell voltages of the plurality of capacitor cells;
The equalization control of the plurality of capacitor cells is performed based on the equalization control time, the measurement start voltage that is the voltage of the capacitor cell at the start of the equalization control, and the capacitor cell at the end of the equalization control Measuring a measurement end voltage which is a voltage of
Calculating a capacitance of the capacitor cell based on the equalization control time, the measurement start voltage, and the measurement end voltage. The capacitance measurement method according to claim 5, wherein an effective capacitance of the capacitor cell is calculated based on the following formula 4.

  The capacitance measuring method according to claim 5, wherein the capacitor cell is a lithium ion capacitor. The step of measuring the capacitance of the capacitor cell by the capacitance measuring method according to claim 5,
Calculating a capacitance ratio between the capacitance of the capacitor cell and the rated capacity of the capacitor cell;
Estimating the deterioration state of the capacitor cell based on the capacity ratio, and a method for estimating the deterioration state of the capacitor cell.

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