JP5911210B2 - Image display device - Google Patents

Description

  The present invention relates to an image display device.

  In the case where a high-definition image of 1980 × 540 pixels in each field is displayed on a VGA panel having a 16: 9 angle of view, conventionally, the following is performed. That is, each field is reduced to a 640 × 480 VGA image, and converted to a 59.94 Hz interlaced video signal for the NTSC range, and converted to a 50 Hz non-interlaced video signal for the PAL range.

  In the liquid crystal display device, an inversion driving method is employed in which the polarity of the driving voltage is inverted for each frame in the liquid crystal panel (see Patent Document 1). This is because, when a DC voltage is applied to the liquid crystal for a long time, polarization occurs in the liquid crystal, causing display defects such as image sticking and deterioration of the liquid crystal. The display defects are prevented by polarity inversion.

Japanese Patent No. 2577796

  When a high-definition image is displayed on a VGA size liquid crystal display device, the following problems may occur. Consider a high-definition image in which white and black appear alternately for each field as shown in FIG. When this high-definition field signal with 540 scanning lines is converted into a non-interlaced VGA video signal with 480 scanning lines, it is converted into an image in which white and black are inverted for each frame, as shown in FIG. 4B. The As described above, the frame frequency is 59.94 Hz in the NTSC zone and 50 Hz in the PAL zone.

  In this case, although the video signal is inverted in polarity for each frame in the image portion, each frame is inverted in white and black, so that a DC bias is always applied to the liquid crystal drive voltage as shown in FIG. It will be. FIG. 5A shows an example of a frame inversion drive signal when no DC bias is generated, and FIG. 5B shows an example of a frame inversion drive signal when a DC bias is generated. When such a still image is displayed for a long time, a DC voltage is always applied to a specific part of the liquid crystal display device, the characteristics of the liquid crystal change, and an afterimage phenomenon or the like is caused.

  It is an object of the present invention to provide an image display device that solves such inconveniences.

The image display device according to the present invention can selectively output a first image signal based on a first frequency and a second image signal based on a second frequency different from the first frequency, and the first image signal And an image display device for displaying an image output from an imaging means capable of selectively outputting each of the second image signals in either an interlace format or a non-interlace format, wherein the polarity is inverted for each frame. Display means for displaying an image by driving a liquid crystal element by voltage, and first clock generation means for generating a first clock used for outputting the first image signal based on the first frequency from the imaging means When a second clock generating means for generating a second clock used to output the second image signal based on the second frequency from said image pickup means The first image signal output from the imaging means according to the first clock selected by the selection means, a memory, and the selection means for selecting the output of the first clock generation means and the second clock generation means. Writing means for writing to the memory according to the first clock, and writing the second image signal output from the imaging means according to the second clock selected by the selection means to the memory according to the second clock; When the first image signal in the non-interlace format is stored in the memory, the first image signal in the non-interlace format is read from the memory according to the first clock, and the first image signal in the interlace format is read into the memory. Is stored from the memory according to the second clock. Read out the first image signal in the source format, and when the second image signal in the interlaced format is stored in the memory, read out the second image signal in the interlaced format from the memory according to the first clock, When the non-interlace format second image signal is stored in the memory, the non-interlace format second image signal is read from the memory according to the second clock, and is read by the read unit. And reducing means for reducing the image signal and outputting the reduced image signal to the display means as an image signal of each frame displayed by the display means.

According to the present invention, it is possible to suppress burn- in of a liquid crystal element that is driven by a drive voltage whose polarity is inverted every frame .

It is a schematic block diagram of one Example of this invention. It is a schematic diagram which shows the relationship between the write address and read address of a field memory. It is explanatory drawing of conversion from a non-interlace high definition video signal to a non-interlace VGA video signal. It is explanatory drawing of conversion from an interlace high-definition video signal to a non-interlace VGA video signal. It is an example of the drive signal of the liquid crystal panel of a frame inversion drive system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a schematic block diagram of a configuration in which an embodiment of an image display device according to the present invention is applied to an imaging device having a liquid crystal panel. The imaging apparatus shown in FIG. 1 displays a captured image and a reproduced image on a liquid crystal panel.

  Reference numeral 101 denotes a lens, 102 an image sensor, 103 a CDS / AD, 104 a color separation unit, 105 a white balance setting unit, 106 an AGC unit, and 107 a knee / gamma correction unit. Reference numeral 108 denotes a timing generation unit, 109 denotes an OSD superposition unit, 110 and 111 denote switches, 112 denotes a DA converter, 113 denotes an analog output terminal, 114 denotes an HDMI processing unit, and 115 denotes an HDMI terminal. 118 is a compression / decompression unit, 119 is a recording flash memory, 120 is a crystal oscillator, 121 and 122 are PLLs, and 123 is a timing generation unit. Reference numeral 124 denotes a field memory, 125 denotes a timing generation unit, 126 denotes a reduction unit, 127 denotes a sharp zebra processing unit, 128 denotes a matrix, 129 denotes a gamma / bright / contrast processing unit, and 130 denotes a liquid crystal panel. Reference numeral 131 denotes a system control unit, and 132 and 133 denote switches that can be switched between recording and reproduction. Reference numeral 150 denotes a camera system block. 117 is a block to which a 27 MHz clock is supplied.

  The system control unit 131 includes a CPU and a memory or a microprocessor. The system control unit 131 reads an imaging device control program recorded in a nonvolatile memory (not shown), develops it in the memory, and controls each block according to the program.

  A process at the time of imaging according to the present embodiment will be described. An optical image of the subject is formed on the image sensor 102 by the lens 101. The image sensor 102 converts the formed optical image into an electrical signal, and supplies the conversion result to the CDS / AD 103. The CDS / AD 103 converts the image signal from the image sensor 102 into a multi-value digital signal while removing low-frequency noise, and supplies the multi-value digital signal to the color separation unit 104. At this time, the timing generation unit 108 generates and supplies a timing signal for causing the image sensor 102 and the CDS / AD 103 to cooperate. The timing generation unit 108 generates different timing signals in the interlace shooting mode and the non-interlace (progressive) shooting mode in accordance with an instruction from the system control unit 131. For example, in the interlace shooting mode, a timing signal for obtaining an image of 1920 × 1080i (59.94 Hz) is generated. In the non-interlaced shooting mode, a timing signal for obtaining an image of 1920 × 1080p (50 Hz) or 1280 × 720p (50 Hz) is generated.

  The color separation unit 104 separates the image signal from the CDS / AD 103 into the three primary colors of RGB based on the arrangement of the color filters pasted on each pixel of the image sensor 102 and supplies it to the white balance setting unit 105. The white balance setting unit 105 detects portions close to white and gray from the RGB signal from the color separation unit 104 and adjusts the color balance so that these portions become achromatic colors.

  The AGC unit 106 adjusts the gain of the image signal from the white balance setting unit 105 so that the luminance of the image becomes a desired value, and supplies the result to the knee / gamma correction unit 107. The light amount may be adjusted by driving the lens aperture motor in place of or in combination with the AGC unit 106.

  The knee / gamma correction unit 107 performs knee correction on the image signal from the AGC unit 106 to compress the image signal of the high-brightness portion and gamma correction to perform correction in accordance with the monitor characteristics, and outputs the result to the switches 110 and 111. Supply.

  A portion from the image sensor 102 to the knee / gamma correction unit 107 functions as an image input unit that inputs an image signal.

  The switches 110 and 111 are switched by the system control unit 131 during recording and during reproduction. During recording, the switches 110 and 111 are connected to the R side. At this time, the captured image is compressed by the compression / decompression unit 118 using a moving image compression method such as MPEG2 or AVCHD (H.264) and stored in the recording flash memory 119.

  During reproduction, the switches 110 and 111 are connected to the P side. At this time, the moving image (compressed data) stored in the recording flash memory 119 is decompressed by the compression / decompression unit 118 and supplied to the OSD superimposing unit 109. The OSD superimposing unit 109 superimposes various information from the system control unit 131 on the playback video signal from the compression / decompression unit 118. The information to be superimposed is, for example, a time code, a battery remaining amount, a remaining recording amount, a recording mark or center mark, a horizontal mark, an outer frame, and the like. The output image signal of the OSD superimposing unit 109 is supplied to the DA converter 112, the HDMI processing unit 114, and the field memory 124. The DA converter 112 converts the image signal from the OSD superimposing unit 109 into an analog signal and outputs the analog signal to the analog output terminal 113. The HDMI processing unit 114 converts the image signal from the OSD superimposing unit 109 into a signal format conforming to the HDMI standard, and outputs the signal format to the HDMI terminal 115.

The crystal oscillator 120 is an oscillator that generates the entire master clock. Here, the frequency of the master clock is 27.000 MHz. The output of the crystal oscillator 120 is supplied to the PLL 121, the PLL 122, and the 27 MHz system block 117. The PLL 121 multiplies the frequency of the 27.000 MHz clock generated by the crystal oscillator 120 by 500/91 to generate a 148.35 MHz clock. The generated 148.35MHz clock, the terminal N of switch 13 3, applied to the terminal Y of switch 13 2. The system control unit 131 switches the switch 133 to the N side in the NTSC range where the field frequency is 59.94 Hz. The output of the switch 133 is supplied to the timing generator 123 and the field memory 124 and used as a clock for the camera system block 150. The timing generation unit 123 generates an address for writing the image signal output from the OSD superimposing unit 109 in the field memory 124 in raster order for each field.

  FIG. 2 shows an example of scanning lines on the screen. A solid line shows a state in which images are sequentially written in the field memory 124 according to a raster. A point indicates a write address at a certain time.

  The PLL 122 multiplies the frequency of the 27.000 MHz clock generated by the crystal oscillator 120 by 11/2 to generate a 148.5 MHz clock. The generated 148.5 MHz clock is applied to the terminal P of the switch 133 and the terminal X of the switch 132. The system control unit 131 switches the switch 132 to the X side in the interlace shooting mode and to the Y side in the non-interlace shooting mode. The output signal of the switch 132 is applied as a clock to the field memory 124, the timing generation unit 125, and the reduction unit 126, respectively.

  The timing generator 125 uses the clock from the switch 132 to generate read addresses to be given to the field memory 124 in raster order. In FIG. 2, broken lines indicate addresses that are sequentially read from the field memory 124. Point B indicates a read address at a certain time.

In FIG. 2, the write address A is calculated based on the 148.35 MHz clock. The read address B is calculated according to the 148.5 MHz clock in the interlaced shooting mode, and is calculated according to the same 148.35 MHz clock as the writing in the non-interlaced shooting mode. Here, the 148.35 MHz clock and the 148.5 MHz clock are multiplication results of the number of horizontal pixels, the number of vertical lines, and the frame frequency of the image. That is,
148.35 (MHz) = 2200 × 1125 × 59.94
148.50 (MHz) = 2200 × 1125 × 60.00
It is.

  In particular, in the interlace shooting mode, the write address A is calculated based on a clock of 148.35 Hz (field frequency 59.94 Hz). On the other hand, the read address B is calculated based on a 148.5 MHz clock (field frequency 60.00 Hz). Therefore, the movement of the read address B is faster than the write address A. Then, as time elapses, the address B gradually approaches the address A, overlaps and overtakes is repeated about every 16.7 seconds. This is a period of time where address A and address B overlap. This period corresponds to every 1000 fields of a 59.94 Hz image and corresponds to every 1001 fields of a 60 Hz image. In this respect, the field memory 124 and its peripheral circuits function as conversion means for converting the frequency of the video signal.

  Since the writing speed (59.94 Hz) is slower than the reading speed (60.00 Hz), when catching up, the same frame is displayed again. Then, one frame in VGA is repeatedly displayed once every 16.7 seconds. With such a configuration, the relationship between the fields before and after the original image and the driving of the liquid crystal panel 130 is switched, and the DC component of the driving signal of the liquid crystal panel 130 is inverted every 16.7 seconds. As a result, even when the liquid crystal panel 130 is driven by a method of inverting the polarity of the voltage applied to the liquid crystal element for each frame, the occurrence of burn-in of the liquid crystal panel 130 can be suppressed.

  The burn-in problem does not occur in the non-interlaced shooting mode. Therefore, the switch 132 is switched to the Y side so that the read clock of the field memory 124 is the same clock as the write clock.

  The image signal read from the field memory 124 is supplied to the reduction unit 126. The reduction unit 126 has, for example, a field signal of 1920 × 540 pixels in the interlaced shooting mode, and a frame signal of 1920 × 1080 pixels in the non-interlaced shooting mode. In the interlace shooting mode, the reduction unit 126 reduces the image signal from the field memory 124 to 1/3 horizontally and 8/9 vertically. On the other hand, in the non-interlace shooting mode, the reduction unit 126 reduces the image signal from the field memory 124 to 1/3 horizontally and 4/9 vertically. By such a reduction process, the reduction unit 126 generates a VGA size image signal, specifically, a VGA size non-interlaced video signal, and outputs the generated image signal to the sharp / zebra processing unit 127.

  FIG. 3 shows how the image is vertically reduced to 4/9 in the non-interlace shooting mode. 3A shows an original high-definition image signal (non-interlaced video signal), and FIG. 3B shows a non-interlaced video signal of VGA size after reduction. The sharp / zebra processing unit 127 adds the sharpness or zebra display that diagonally displays the highlight portion to the image, and outputs the result to the matrix 128. The matrix 128 matrix-converts the image signal from the sharp / zebra processing unit 127 from a 4: 2: 2 YC signal format to a 4: 4: 4 RGB signal format, and converts the conversion result into a gamma / bright / contrast processing unit 129. To supply. The gamma / bright / contrast processing unit 129 performs gamma processing / bright processing / contrast processing according to the liquid crystal panel 130 on the RGB image signal from the matrix 128, and outputs the processing result to the liquid crystal panel 130.

  In the liquid crystal panel 130, a built-in drive circuit generates a drive signal whose voltage polarity is inverted for each frame from the input image signal, and drives the liquid crystal element. That is, drive voltages having opposite polarities are alternately applied to the liquid crystal panel 130.

  In this embodiment, even if the liquid crystal panel 130 is driven by the frame inversion driving method, the direct current component of the driving voltage is increased by driving the liquid crystal panel 130 with a 59.94 Hz image signal at a different frequency of 60 Hz. Inverts every 16.7 seconds. As a result, image sticking of the liquid crystal panel 130 can be suppressed.

  In this embodiment, when the output frequency of the PLL 122 is 1, the PLL 121 generates a frequency of 1 / 1.001. In the NTSC area including Japan and the United States, the field frequency of the broadcast high-definition video signal is 59.94 Hz. Therefore, the clock generated by the PLL 121 is used as a writing clock to the camera system block 150 and the field memory 124, and the clock generated by the PLL 122 is used as a reading clock of the field memory 124 when it is necessary to prevent the burn-in of the liquid crystal panel.

  On the other hand, since the field frequency is 50.00 Hz in the PAL zone, the switch 133 is switched to the P side. A clock generated by the PLL 122 is used as a clock for writing to the camera system block 150 and the field memory 124, and the switch 132 is switched to the Y side during interlaced shooting. In the case of the PAL area, since the writing frequency to the field memory 124 is higher than the reading frequency, one frame in the VGA is skipped once every 16.7 seconds, and the image appears to advance for a moment. However, at that time, the relationship between the field before and after the original image and the drive signal of the liquid crystal panel 130 is switched, and the direct current component of the drive signal of the liquid crystal panel 130 is inverted, so that the occurrence of burn-in is suppressed. In the non-interlace shooting mode, no burn-in problem occurs, so the switch 132 is switched to the X side, and the read clock of the field memory 124 is set to the same clock as the write clock.

  In the above embodiment, the burn-in of the liquid crystal panel 130 is suppressed by changing the writing frequency and the reading frequency of the field memory 124 at a frequency ratio of 1000: 1001 at the time of interlaced photographing. However, when the OSD superimposing unit 109 superimposes a thin white image such as an outer frame, the writing frequency and the reading frequency of the field memory 124 may be changed at a frequency ratio of 1000: 1001. This is because there are not so many distinct horizontal stripes separated for each scanning line in the natural image, but the OSD superimposing unit 109 superimposes a graphic image that makes the black and white clear in parallel with the scanning line, This is because image sticking easily occurs.

Claims (4)

A first image signal based on a first frequency and a second image signal based on a second frequency different from the first frequency can be selectively output, and each of the first image signal and the second image signal is output. An image display device that displays an image output from an imaging means that can selectively output in either an interlace format or a non-interlace format,
Display means for displaying an image by driving a liquid crystal element with a driving voltage whose polarity is inverted every frame;
First clock generating means for generating a first clock used for outputting the first image signal based on the first frequency from the imaging means ;
Second clock generation means for generating a second clock used for outputting the second image signal based on the second frequency from the imaging means ;
Selecting means for selecting outputs of the first clock generating means and the second clock generating means;
Memory,
The first image signal output from the image pickup means according to the first clock selected by the selection means is written to the memory according to the first clock, and the image pickup means according to the second clock selected by the selection means. Writing means for writing the second image signal output from the memory into the memory according to the second clock;
When the first image signal in the non-interlace format is stored in the memory, the first image signal in the non-interlace format is read from the memory according to the first clock, and the first image signal in the interlace format is read into the memory. When the image signal is stored, the interlaced first image signal is read from the memory according to the second clock, and when the interlaced second image signal is stored in the memory, the first clock When the second image signal in the interlace format is read from the memory according to the second clock signal and the second image signal in the non-interlace format is stored in the memory, the second image signal in the non-interlace format is read from the memory according to the second clock. Reading means for reading two image signals;
Reduction means for reducing the image signal read by the reading means, and outputting the reduced image signal to the display means as an image signal of each frame displayed by the display means. An image display device. The image display device according to claim 1, wherein a frequency of the first clock is lower than a frequency of the second clock . When the first image signal is an interlaced image signal, an address for writing the first image signal into the memory by the writing unit is calculated based on the first clock, and the first unit from the memory by the reading unit. The image display device according to claim 1, wherein an address from which an image signal is read is calculated based on the second clock . Wherein the ratio between said second clock frequency frequency of the first clock, 1000: 1001 or 1001: image display apparatus according to claim 1, characterized in that 1000.

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