JP5906807B2 - Arithmetic processing device and stall monitoring method - Google Patents

Description

  The present invention relates to an arithmetic processing unit and a stall monitoring method, and more particularly to an arithmetic processing unit and a stall monitoring method that perform stall monitoring by setting priorities between processing processes.

  Generally, in a device that executes arithmetic processing, a stall state may occur in which operation is not possible due to some problem such as a program defect. The stall state is a state in which the arithmetic processing device cannot be processed. For this reason, the arithmetic processing unit needs to detect the stall state and promptly recover it.

  Therefore, as a method of monitoring the stall state, there is a method using a watch dog timer. Specifically, using a watchdog timer, the stall monitoring process is started at regular intervals, and if a response signal is output from the stall monitoring process, it is determined that no stall condition has occurred, and the stall monitoring process If no response signal is output, it is determined that a stall condition has occurred.

  A time chart of a stall monitoring process using a general watchdog timer will be described with reference to FIG. Stall monitoring using a general watchdog timer is designed so that a process for performing stall monitoring is always started at regular intervals. In this figure, for example, even when the process 2 having a medium execution priority is activated, the stall monitoring process having a high execution priority is activated at a predetermined time. Similarly, even when the process 1 having the medium execution priority is activated, the stall monitoring process having the high execution priority is activated at a predetermined time. Furthermore, even when a stall state occurs in the process 2, the stall monitoring process is activated at a predetermined time because the execution priority of the stall monitoring process is higher than the execution priority of the process 2.

  When the stall monitoring as shown in FIG. 6 is performed, the stall monitoring process cannot be started in the stall state where the OS task cannot be switched, so that the stall state can be detected. However, even if a certain process falls into an infinite loop due to a logic failure or the like, the stall monitoring process is activated when the OS task can be switched, so the monitoring process cannot detect the stall state of that process. .

  A method for detecting a stall state in such a state that task switching of the OS can be performed will be described with reference to FIG. The stall monitoring process in this figure is set by lowering the execution priority to the same or lower than other processes. Thereby, when a stall state occurs in the normal processing process, the stall monitoring process is not started, and the problem as shown in FIG. 6 is solved.

JP 2010-160597 A

  However, in the above-described method for detecting a stall state, the priority of the stall monitoring process is lowered to the same level as or lower than that of other processes. Therefore, if another process is activated when a stall monitoring process activation request is executed, the stall monitoring process is not activated. Therefore, when many other processing processes that are operating normally continue to be executed, a state in which the stall monitoring process cannot respond continues. For this reason, there is no response from the stall monitoring process even though other processing processes are operating normally, so that it may be erroneously determined that a stall condition has occurred.

  Japanese Patent Application Laid-Open No. 2004-151561 discloses that priority level correction processing is performed on a queue with a low priority level for a queue with a low priority level. However, in FIG. 7, when the priority of the stall monitoring process is increased and the priority of the stall monitoring process is increased over other processing processes, the problem shown in FIG. 6 may occur again.

  An object of the present invention is to provide an arithmetic processing unit and a stall monitoring method that improve the accuracy of detecting a stall state in stall monitoring using a monitoring process.

  The arithmetic processing device according to the first aspect of the present invention includes: a control unit that executes an arithmetic processing process; and a monitoring process that has a lower priority for activation than the arithmetic processing process and performs stall monitoring of the arithmetic processing process; A cache confirmation unit that monitors a change in state of a data cache accessed from the arithmetic processing process, a monitoring process activation control unit that controls activation of the monitoring process based on a monitoring result of the cache confirmation unit, and the monitoring And a failure determination unit that determines whether or not a stall state has occurred in the arithmetic processing process based on a process startup result.

  A stall monitoring method according to a second aspect of the present invention monitors a state change of a data cache accessed from a control unit that executes an arithmetic processing process, and controls the control unit based on a monitoring result of the state change in the data cache. Is controlled to determine whether or not a stall state has occurred in the arithmetic processing process based on the start result of the monitoring process.

  According to the present invention, it is possible to provide an arithmetic processing unit and a stall monitoring method that improve the accuracy of detecting a stall state in stall monitoring using a monitoring process.

1 is a configuration diagram of an arithmetic processing apparatus according to a first embodiment; 1 is a configuration diagram of an arithmetic processing apparatus according to a first embodiment; FIG. 3 is a diagram illustrating a processing operation of the arithmetic processing device in a normal state according to the first embodiment. It is a figure which shows the processing operation of the arithmetic processing unit when the stall state concerning Embodiment 1 generate | occur | produces. 5 is a flowchart showing a stall state determination process according to the first exemplary embodiment; It is a time chart of a stall monitoring process using a general watchdog timer. It is a figure of the time chart of the stall monitoring process using a general watchdog timer.

(Embodiment 1)
Embodiments of the present invention will be described below with reference to the drawings. A configuration example of the arithmetic processing apparatus according to the first embodiment of the present invention will be described with reference to FIG. The arithmetic processing unit may be a CPU, for example. The arithmetic processing device 10 includes a processor core 11, a processor core 12, and a data cache 13. The arithmetic processing unit is connected to the memory 14. The processor core 12 includes a cache confirmation unit 20, a monitoring process activation control unit 21, and a failure determination unit 22.

  The processor core 11 executes arithmetic processing in the arithmetic processing device 10. The processor core 11 may be referred to as a control unit in the arithmetic processing device 10. The processor core 11 executes an arithmetic processing process and a monitoring process for performing stall monitoring. The monitoring process is set to have a lower execution priority than the arithmetic processing process.

  The processor core 12 exclusively executes control processing by the cache confirmation unit 20, the monitoring process activation control unit 21, and the failure determination unit 22. The cache confirmation unit 20 monitors the state change of the data cache 13. For example, when an arithmetic processing process is executed in the processor core 11, the processor core 11 accesses the memory 14, and data output from the memory 14 is stored in the data cache 13, the state of the data cache 13 changes. Further, when the arithmetic processing process is not executed in the processor core 11, there is no access to the data cache 13 and the memory 14 from the processor core 11, so the state of the data cache 13 does not change.

  The data cache 13 is arranged inside the arithmetic processing unit 10 for the purpose of improving the data access speed to the data stored in the memory 14. The data cache 13 is accessed from both the processor core 11 and the processor core 12. The memory 14 stores a program executed in the processor core 11 and the processor core 12 and data used in executing the program.

  The monitoring process activation control unit 21 controls the activation of the monitoring process in the processor core 11 based on the monitoring result of the data cache 13 by the cache confirmation unit 20. For example, the monitoring process activation control unit 21 does not activate the monitoring process in the processor core 11 when the cache confirmation unit 20 detects that the state of the data cache 13 has changed. The monitoring process activation control unit 21 activates the monitoring process in the processor core 11 when the cache confirmation unit 20 does not detect that the state of the data cache 13 has changed.

  The failure determination unit 22 causes a stall state to occur in the arithmetic processing process of the processor core 11 based on the start result of the monitoring process when the monitoring process start control unit 21 executes control for starting the monitoring process in the processor core 11. It is determined whether or not. For example, when the monitoring process activation control unit 21 executes control for starting the monitoring process in the processor core 11, the failure determination unit 22 fails in the arithmetic processing process of the processor core 11 when the activation of the monitoring process is not confirmed. Is determined to have occurred. Alternatively, when the monitoring process activation control unit 21 executes the control to activate the monitoring process in the processor core 11, the failure determination unit 22 determines that the arithmetic processing process of the processor core 11 is performed when the activation of the monitoring process is confirmed. Judge that it is operating normally.

  As described above, by using the arithmetic processing unit 10 in FIG. 1, the processor core 12 can control the monitoring process activation process of the processor core 12. Furthermore, when the state of the data cache 13 in which the stall occurrence state is considered not changed, the processor core 12 monitors the start state of the monitoring process in the processor core 11, thereby generating the stall state in the processor core 11. It can be detected accurately.

  Next, operations of the processor core 11 and the processor core 12 according to the first exemplary embodiment of the present invention will be described with reference to FIG. The processor core 12 has the same configuration as in FIG. The processor core 11 includes a process activation control unit 30 and a process activation response unit 31.

  The process activation control unit 30 activates the arithmetic processing process and the monitoring process executed by the processor core 11 according to the respective priorities. When the monitoring process is activated, the process activation response unit 31 notifies the failure determination unit 22 of the processor core 12 that the monitoring process has been activated.

  The cache confirmation unit 20 confirms the state of the data cache 13 and determines whether or not a change has occurred in the data included in the data cache 13. When the cache checking unit 20 determines that the data held in the data cache 13 has not changed, the cache checking unit 20 notifies the monitoring process activation control unit 21 to that effect.

  When the monitoring process activation control unit 21 is notified from the cache confirmation unit 20 that the data in the data cache 13 has not changed, the monitoring process activation control unit 21 performs a monitoring process on the process activation control unit 30 of the processor core 11. A signal related to the monitoring process activation instruction is notified so as to be activated. In addition, the monitoring process activation control unit 21 notifies the failure determination unit 22 that the process activation control unit 30 has been notified of the signal related to the monitoring process activation instruction.

  The process activation control unit 30 executes the monitoring process when a monitoring process activation instruction is notified from the monitoring process activation control unit 21 of the processor core 12. Here, the monitoring process is set with a lower execution priority or the same execution priority than the other arithmetic processing processes. Therefore, when an arithmetic processing process is being executed in the processor core 11, the process activation control unit 30 cannot execute a monitoring process. The process activation control unit 30 can execute a monitoring process when the arithmetic processing process is not executed.

  When the process activation control unit 30 executes a monitoring process, the process activation response unit 31 notifies the failure determination unit 22 of activation of the monitoring process.

  The failure determination unit 22 is a processor when the monitoring process activation control unit 21 notifies the process activation control unit 30 of a signal related to the monitoring process activation instruction and the process activation response unit 31 does not notify the activation of the monitoring process. It is determined that a stall condition has occurred in the core 11. In addition, the failure determination unit 22 is notified of the start of the monitoring process from the process activation response unit 31 while the monitoring process activation control unit 21 notifies the process activation control unit 30 of a signal related to the monitoring process activation instruction. In this case, it is determined that the processor core 11 is operating normally.

  The monitoring process activation control unit 21 instructs the processor core 11 to activate the monitoring process when there is no change in the data cache 13. When there is no change in the data cache 13, the processor core 11 transitions to a steady state, a state where the arithmetic processing processor is not operating and a stall state occurs in the processor core 11, and the arithmetic processing process of the processor core 11 Is in a state where it cannot be processed.

  The processor core 11 can start the monitoring process in a state where the processor core 11 is transitioning to a steady state. Therefore, when the failure determination unit 22 receives the monitoring process activation notification from the process activation response unit 31, the failure determination unit 22 can determine that the processor core 11 is operating normally. On the other hand, when the stall state has occurred, the processor core 11 is in a state where the arithmetic processing process is activated, and the monitoring process cannot be activated. Therefore, the failure determination unit 22 can determine that the stall state has occurred in the processor core 11 when it has not received the monitoring process activation notification from the process activation response unit 31.

  If the failure determination unit 22 cannot receive the monitoring process activation notification within a certain time after the monitoring process activation control unit 21 is notified of the signal related to the monitoring process activation instruction to the process activation control unit 30, the processor It may be determined that a stall condition has occurred in the core 11.

  Next, the processing operation of the arithmetic processing unit in a normal state will be described using FIG. The processor core 11 executes a normal processing process and a monitoring process. When both processes are not executed, the processor core 11 transitions to a steady state in which data input wait or process execution wait is performed. The monitoring process has a lower execution priority than the normal processing process. When the processor core 12 executes the processing process and does not execute the processing process, the processor core 12 transitions to a steady state in which it waits for data input or waits for execution of the process.

  In the processor core 11, processing processes P1 to P3 are repeatedly executed. The processing processes P1 to P3 access the data cache 13 during the process execution to acquire necessary data or execute a program. When necessary data or the like does not exist in the data cache 13 when accessing the data cache 13 from the processor core 11, the processor core 11 accesses the memory 14, acquires the necessary data, and acquires the acquired data in the data cache. 13 is stored. In this way, the state of the data cache 13, that is, the stored data changes. This figure shows a state in which the state of the data cache 13 changes every time the processing processes P1 to P3 are executed.

  When the processor core 11 completes the execution of the processing processes P1 to P3, the processor core 11 transitions to a steady state. When the processor core 11 transitions to the steady state, the access to the data cache 13 and the memory 14 from the processor core 11 is not executed, so the state of the data cache 13 does not change.

  The processor core 12 executes a processing process for confirming the data cache state at regular intervals using the cache confirmation unit 20. When the processor core 12 detects that the state of the data cache 13 has changed, the processor core 12 transitions to a steady state and executes a processing process for checking the cache state at a predetermined timing. When detecting that the state of the data cache 13 has not changed, the processor core 12 monitors the processor core 11 using the monitoring process activation control unit 21 in order to activate the monitoring process of the processor core 11. Execute the process related to process startup control.

  The cache confirmation unit 20 may detect that the state of the data cache 13 has changed when there is a difference in the cache contents as compared to the cache contents at the previous confirmation of the data cache 13.

  The monitoring process activation control unit 21 may perform control so that the monitoring process of the processor core 11 is activated when the cache confirmation unit 20 detects that the state of the data cache 13 has not changed a plurality of times. . As a result, when the processing process of the processor core 11 is executed, the processing process is completed using only the data stored in the data cache 13, so that the processor core 11 does not access the memory 14. There is. In such a case, the state of the data cache 13 does not change. Therefore, the monitoring process activation control unit 21 controls the activation of the monitoring process in the processor core 11 based on the number of times that the state of the data cache 13 has not changed, so that the processing process is activated in the processor core 11. In addition, it is possible to avoid instructing the processor core 11 to start the monitoring process.

  When monitoring process activation control is executed by the processor core 11 in a steady state, the processor core 12 activates a monitoring process using the process activation control unit 30. Further, when the processor core 12 starts the monitoring process, the processor core 12 notifies the processor core 12 of the start response of the monitoring process using the process start response unit 31.

  When the processor core 12 receives the start response of the monitoring process from the processor core 11, the processor core 12 determines that the stall state has not occurred in the processor core 11.

  Next, a processing operation of the arithmetic processing device when a stall state occurs will be described with reference to FIG. This figure shows that a stall condition has occurred during the execution of the second processing process P3 in the processor core 11. When the stall state occurs in the processor core 11, the processor core 11 does not access the data cache 13 and the memory 14. For this reason, the state of the data cache 13 does not change.

  When detecting that the state of the data cache 13 has not changed, the processor core 12 monitors the processor core 11 using the monitoring process activation control unit 21 in order to activate the monitoring process of the processor core 11. Execute the process related to process startup control.

  Here, the processor core 11 is stalled while the process P3 is activated. Therefore, even when the monitoring process is activated from the processor core 12, the monitoring process having an execution priority lower than that of the normal processing process is not activated. Therefore, the process activation response unit 31 does not notify the processor core 12 of a process activation response. The failure determination unit 22 of the processor core 12 determines that a stall state has occurred in the processor core 11 when a process activation response is not received within a predetermined time after the processing process related to the monitoring process activation control is executed.

  Next, the flow of stall state determination processing will be described with reference to FIG. First, the cache check unit 20 of the processor core 12 checks the state of the data cache 13 (S11). Next, when the cache confirmation unit 20 does not detect a change in the state of the data cache 13 (S12), the monitoring process activation control unit 21 activates the monitoring process in the processor core 11 (S13).

  Next, the failure determination unit 22 of the processor core 12 determines whether or not a monitoring process activation response has been received within a predetermined specified time after the control related to the activation of the monitoring process is performed on the processor core 11. (S14). When the failure determination unit 22 receives the monitoring process activation response within the specified time, the failure determination unit 22 determines that the stall state has not occurred in the processor core 11 (S15).

  In step S14, when the failure determination unit 22 determines that the monitoring process activation response has not been received within the specified time, the failure determination unit 22 determines that the stall state has occurred in the processor core 11 (S16). If the cache checking unit 20 detects a change in the state of the data cache 13 in step S12, the processes after step S15 are executed.

  As described above, by using the arithmetic processing apparatus according to the first embodiment of the present invention, it is possible to reliably detect a stall state occurring in one processor core. In the watchdog timer type stall monitoring that is generally performed, even if a stall process occurs because a certain process falls into an infinite loop due to a logic failure, etc. The stall condition could not be detected. However, such a problem can be solved by using the arithmetic processing unit according to the present invention.

  In the arithmetic processing unit of the present invention, the execution priority of the stall monitoring process is set lower than that of the normal processing process. Further, the stall monitoring process is controlled using other processor cores. Therefore, by using the arithmetic processing unit of the present invention, the processing of the processor core that executes the stall monitoring process is not delayed, and further, the processing load is not increased.

(Other embodiments)
In the first embodiment described above, the configuration using the data cache 13 shared by the processor core 11 and the processor core 12 has been described, but the same applies to the configuration in which a data cache is allocated to each of the processor core 11 and the processor core 12. The present invention can be applied.

  In this case, the processor core 12 may detect that the state of the data cache assigned to the processor core 11 has changed by detecting that the memory 14 is accessed from the processor core 11. For example, the processor core 11 may operate so as to notify the processor core 12 that the memory 14 is accessed when accessing the memory 14. Thereby, the processor core 12 can detect access to the memory 14 in the processor core 11.

  Although the configuration in which two processor cores are arranged in the CPU has been described, in the configuration in which a data cache is allocated to each processor core, the number of processor cores is not limited to two. The CPU may be configured to include three or more processor cores.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 Arithmetic processor 11 Processor core 12 Processor core 13 Data cache 14 Memory 20 Cache confirmation part 21 Monitoring process starting control part 22 Fault determination part 30 Process starting control part 31 Process starting response part

Claims (8)

A control unit that executes an arithmetic processing process, and a monitoring process that has a lower priority on activation than the arithmetic processing process and performs stall monitoring of the arithmetic processing process;
A cache confirmation unit that monitors a change in the state of the data cache accessed from the arithmetic processing process;
A monitoring process activation control unit that controls activation of the monitoring process based on a monitoring result of the cache confirmation unit;
A failure determination unit that determines whether or not a stall condition has occurred in the arithmetic processing process, based on a startup result of the monitoring process;
A monitoring process start notification unit for notifying the start state of the monitoring process,
The monitoring process activation notification unit
When the monitoring process activation control unit is notified of the monitoring process activation control unit in a steady state in which the control process and the monitoring process are not executed by the control unit, the monitoring process is activated, and the activation instruction A response is notified to the failure determination unit, and when the monitoring process activation control unit is notified that the control unit is executing the arithmetic processing process, the monitoring process is activated. The arithmetic processing unit does not notify the failure determination unit of a response to the activation instruction . The monitoring process activation control unit
If the cache check unit determines that the data cache has changed, the monitoring process is not started. If it is determined that the data cache has not changed, the monitoring process is started. The arithmetic processing device according to claim 1, wherein: The failure determination unit
If the start of the monitoring process can be confirmed, it is determined that the stall process has not occurred. If the start of the monitoring process cannot be confirmed, the stall process has occurred. The arithmetic processing device according to claim 1, wherein the arithmetic processing device determines that the operation is being performed. The cache confirmation unit
Periodically check the status change of the data cache,
The monitoring process activation control unit
If it exceeds the number of times that the front Kide over data cache in the cache checking unit is determined not to be changed is predetermined, carries out activation of the monitoring process, any of claims 1 to 3 1 The arithmetic processing unit according to item. The cache checking unit, the monitoring process activation control unit and the fault determination unit is provided in a first control unit that is different from the control unit, the arithmetic processing apparatus according to any one of claims 1 to 4. Monitor the status change of the data cache accessed from the control unit that executes the arithmetic processing process,
Control the start of the monitoring process in the control unit based on the monitoring result of the state change in the data cache,
When the control unit is instructed to start the monitoring process in a steady state in which the arithmetic processing process and the monitoring process are not executed, the control unit is started, a response to the start instruction is notified, and the control When the monitoring process activation instruction is notified when the unit is executing the arithmetic processing process, the monitoring process is not activated, the response to the activation instruction is not notified,
A stall monitoring method for determining whether or not a stall state has occurred in the arithmetic processing process based on a start result of the monitoring process. When it is determined that the state of the data cache has changed, the monitoring process is not started, and when it is determined that the data cache has not changed, the monitoring process is started. The stall monitoring method according to claim 6 . If the start of the monitoring process can be confirmed, it is determined that the stall process has not occurred. If the start of the monitoring process cannot be confirmed, the stall process has occurred. to have a determined stall monitoring method according to claim 6 or 7.

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