JP5904405B2 - Nonvolatile logic integrated circuit - Google Patents

Description

  The present invention relates to a nonvolatile logic integrated circuit, and more particularly to a spintronic logic integrated circuit.

  Today's information communication technology has been developed separately for semiconductor device technology using electron charge and magnetic device technology using electron spin. In recent years, the maturity of each technology has increased, and the limits of the information processing performance of semiconductor devices and the information storage capability of magnetic devices are being hit. In order to solve this limitation, attention has been paid to a spintronics technology that attempts to overcome this limitation by a synergistic effect using both the degree of freedom of charge of electrons and the degree of freedom of spin.

  A typical example of the spintronic element is a magnetoresistive element (MTJ element). In a typical MTJ (Magnetic Tunnel Junction) element, a fixed magnetic layer whose magnetization is fixed in one direction and a free magnetic layer whose magnetization direction changes in two directions are used, and a tunnel barrier layer is interposed between these magnetic layers. It is formed. 1-bit information (0/1) is assigned to the magnetization of the free magnetic layer, and when the magnetizations of the two magnetic layers are parallel to each other (in the same direction), the tunnel current passing through the tunnel barrier layer increases ( In the case of a low resistance state) and antiparallel (in the opposite direction), information can be extracted by utilizing the property that the tunnel current decreases (high resistance state). One-bit information is rewritten by inverting the magnetization direction of the free magnetic layer by applying a magnetic field of a certain level or higher to the MTJ element or by passing a spin-polarized current.

  In this field of spintronics, MTJ elements are applied to semiconductor devices, and magnetic random access memory (MRAM) that can realize unprecedented performance with high capacity, high speed, and non-volatility, which can replace DRAM, is practical. Is in the process of becoming MRAM is an attempt to make a conventional semiconductor memory non-volatile. However, an attempt to simultaneously realize an arithmetic function and a non-volatile memory function by incorporating an MTJ element in a conventional logic circuit is also active.

  For example, Non-Patent Document 1 discloses a spintronics elemental logic circuit (hereinafter referred to as a spintronics logic gate) that performs a logical operation on bit information of an MTJ element and bit information input by voltage. FIG. 12 shows a basic configuration diagram of a spintronic logic gate. This circuit includes a pass transistor logic circuit section, precharge transistors (M2, M3), amplifier circuits (M0, M1, M4, M5), MTJ elements (RX, R / X), and an output buffer. Here, two MTJ elements are assigned 1-bit information to complementary resistance states. For example, when X = 0, RX is in a low resistance state (RL) and R / X is in a high resistance state (RH). Conversely, when X = 1, RX is in a high resistance state (RH) and R / X is in a low resistance state (RL). The pass transistor logic circuit can take various forms according to a truth table that is logically operated with input information and information of the MTJ element. For example, FIG. 13A shows an example of a pass transistor logic circuit that functions as an adder circuit, and its truth table is as shown in FIG.

  Next, the basic operation of the spintronic logic gate will be described. When the clock signal (CLK) is at the L level, the precharge operation in which the transistors M0, M2, and M3 are turned on and M1 is turned off. That is, both the terminals y and / y are precharged to Vdd, the MTJ element and the capacitor CL are electrically disconnected, and the charge of CL is discharged. When CLK is at the H level, the transistors M0, M2, and M3 are turned off and M1 is turned on to perform a logic operation. Specifically, the charges charged in the parasitic capacitances at the terminals y and / y are charged into the capacitor CL via the pass transistor circuit and the MTJ element. At this time, in the current path formed by the pass transistor and the MTJ element, since the time constants in the RX current path and the R / X current path are different, a small potential difference is generated between the terminals y and / y. This potential difference is amplified by the positive feedback of the transistors M4 and M5, and is amplified to the logic amplitude by the output buffer at the subsequent stage. As described above, the spintronics logic circuit consumes less power than the CMOS logic circuit because the number of transistors and the formation of a short circuit that causes a through current can be greatly reduced.

  Such various spintronic logic gates are connected in a complicated manner, so that a large-scale and complicated operation can be realized with a small area and power saving as compared with a conventional CMOS circuit. Furthermore, since the logic information inside the logic circuit is non-volatile, the calculation result before power off is not lost. Therefore, high performance and low power consumption can be achieved by reducing the amount of information transferred on the data bus, and the leakage current during non-operation, which has been increasing in recent years by frequently disconnecting the power supply, can be reduced to zero. It is also expected as a technology that enables low power design, which was difficult.

“Fabrication of a Nonvolatile Full Adder Based on Logic-in-Memory Architecture Using Magnetic Junction Junctions”, Applied Physics Exp.

  The operation method of the spintronic logic gate described above needs to perform a precharge operation before performing a logical operation. This operation restriction is a feature that is not found in the conventional CMOS logic circuit, and it is not easy to design a circuit by the same method as the conventional one. For example, as shown in FIG. 14, the time for which the operation result is correctly output is only during the period when CLK is at the H level, and during the precharge period when the output is fixed at the H level, It cannot be used for calculation. Further, if the input signal to the pass transistor circuit changes during the logical operation period, the current path may change and the output signal (logical operation result) may change. That is, as shown in FIG. 14, it is desirable that the input signal remains fixed during the logical operation period when CLK is at the H level. Since the circuit designer needs to consider this operation restriction, the circuit design has to be enormous.

  In addition, due to these operation restrictions, there is a disadvantage that the number of stages is only one in the spintronics logic gate capable of performing logical operation per clock cycle. For this reason, an operation that can be performed in one clock cycle in a CMOS logic circuit requires a plurality of clock cycles in a spintronics logic circuit, which causes a problem that an effective operation speed is reduced. For example, when considering the design of an 8-bit adder, a carry from a lower bit is propagated every clock cycle in a pipeline operation, so that at least 8 cycles are required to obtain an addition result.

  An object of the present invention is to provide a non-volatile logic integrated circuit that performs an arithmetic operation with control signals having different waveform parameters in a non-volatile logic integrated circuit including an element circuit to which a latch circuit is added.

  Another object of the present invention is to provide a non-volatile logic integrated circuit that performs arithmetic operations with control signals having different waveform parameters in a non-volatile logic integrated circuit including element circuits in order to solve at least one of the above-described problems. There is to do.

  In order to solve the above-described problem, one embodiment of the present invention includes a resistance change element, and a resistance value of the resistance change element is added to the plurality of element circuits used for a logical operation, and the plurality of element circuits, And a latch circuit that latches and temporarily holds the operation result of the element circuit, and each element circuit provides a non-volatile logic integrated circuit in which an operation is performed by a control signal having a different waveform parameter.

  Another aspect of the present invention is a non-volatile logic integrated circuit including a resistance change element, and including a plurality of element circuits in which the resistance value of the resistance change element is used for a logical operation. A second element circuit connected to a subsequent stage of the first element circuit and operating according to a second control signal, and the second element circuit operating according to the first control signal. The control signal has a duty ratio smaller than that of the first control signal, and provides a nonvolatile logic integrated circuit in which each element circuit starts an arithmetic operation at a different timing.

  According to the present invention described above, the operation restrictions peculiar to the spintronic logic gate can be satisfied by shifting the waveform parameters such as the phase of the clock and the duty ratio for controlling each spintronic logic gate in accordance with the order of the logical operations. In addition, it is possible to shorten the calculation processing time of the spintronic logic circuit.

FIG. 3 shows a spintronic logic gate with a latch circuit according to each embodiment of the present invention. FIG. 2 is a diagram showing an operation timing chart of the spintronic logic gate of FIG. 1. It is a figure which shows the basic composition of the non-volatile logic circuit by 1st Example of this invention. FIG. 4 is a diagram showing an operation timing chart in the nonvolatile logic circuit of FIG. 3. It is a figure which shows the basic composition of the non-volatile logic circuit in which the output signal of the spintronics logic gate by the 2nd Example of this invention was fed back. It is a figure which shows the modification of the basic composition of the non-volatile logic circuit to which the output signal of the spintronics logic gate by the 2nd Example of this invention was fed back. FIG. 7 is a timing chart showing logical operation propagation of feedback paths a to d in FIGS. 5 and 6. It is the schematic which shows the structure of the non-volatile logic circuit by 3rd Example of this invention. It is a figure which shows the operation | movement timing chart in the Example of FIG. It is the schematic which shows the structure of the non-volatile logic circuit by 4th Example of this invention. It is a figure which shows the operation | movement timing chart in the Example of FIG. It is a figure which shows the basic circuit structure of the conventional spintronics logic gate. FIG. 13 is an example of a pass transistor logic part of the spintronic logic gate of FIG. 12, (a) shows an XOR circuit, and (b) shows a truth table. It is a figure which shows the operation | movement timing chart of the spintronics logic gate of FIG.

  Hereinafter, each embodiment of the present invention will be described in detail.

(First embodiment)
First, a first embodiment of the present invention will be described.

  FIG. 1 shows a circuit (element circuit) in which a buffer provided at a subsequent stage of a spintronic logic gate circuit is replaced with a latch circuit. This latch circuit is an H-thru latch circuit having a function of outputting the operation result of the spintronics logic circuit to the terminal Q when the clock is at the H level and holding it as it is when the clock is at the L level. An operation timing chart of this circuit is shown in FIG. By adding a latch circuit in the subsequent stage, it is possible to prevent the output signal from being fixed during the precharge period, which is one of the above-described operation restrictions. Therefore, the circuit design is facilitated by defining the circuit including the latch circuit as one spintronic logic gate.

  However, simply adding a latch circuit cannot solve the problem that the input signal must continue to be determined during the logical operation period, which is another operation constraint. For example, consider a case where two spintronic logic gates are cascaded and the first-stage gate output is used as the next-stage gate input. Since the calculation result of the first stage gate is output with a certain delay from the rising edge of CLK, it changes to the next stage gate during the calculation operation. If the signal input to the gate of the next stage is not determined before the rising edge of the same CLK cycle, the logical operation cannot be performed correctly.

  FIG. 3 is a basic configuration diagram of an embodiment of the present invention that solves two operational restrictions of a spintronic logic gate. In this non-volatile logic integrated circuit, the spintronic logic gate with a latch is divided into an even number stage and an odd number stage, and the inputted CLK signals are inverted. For example, the phase of the odd-numbered latched spintronic logic gates (SP1, SP3) is 180 degrees behind the clock signal (CLK) input to the even-numbered latched spintronic logic gates (SP0, SP2) (inverted). Clock signal (/ CLK) is input. Here, a combinational circuit composed of CMOS gates is inserted between the spintronic logic gates in each stage, and it is possible to design a functional block that realizes a more complicated function.

  Next, the operation of the circuit illustrated in FIG. 3 will be described in detail with reference to FIG. The even-numbered spintronic logic gates SP0 and SP2 with a latch become a precharge period when the CLK signal is at the L level and an operation period when the CLK signal is at the H level. The calculation result output to the terminals Q0 and Q2 is output with a certain delay time from the rising edge of CLK, and the calculation result is held for one period until the next rising edge. On the other hand, the odd-numbered latched spintronics logic gates SP1 and SP3 have a precharge period when the / CLK signal is L level (CLK is H level) and an operation period when the / CLK signal is H level (CLK is L level). The calculation result output to the terminals Q1 and Q3 is output with a certain delay time from the rising edge of / CLK (falling edge of CLK), and the calculation result is held for one period until the next rising edge. In FIG. 3, the operation result y0 of the spintronics logic gate SP0 (even number stage) is output to the terminal Q0 and input to the next stage spintronics logic gate SP1 (odd number stage) via the combinational circuit. The input signal of the spintronics logic gate SP1 should not change while / CLK is at H level (while CLK is at L level), but the output signal y0 of the spintronics logic gate SP0 is that CLK of the same cycle is at L level. The interval is maintained and does not change. Accordingly, the odd-numbered spintronic logic gate SP1 can correctly perform a logical operation. Similarly, the operation result y1 of the spintronics logic gate SP1 (odd number stage) is output to the terminal Q1, and is input to the next stage spintronics logic gate SP2 (even number stage) via the combinational circuit. The input signal of the spintronics logic gate SP2 should not change while CLK is at H level (/ CLK is at L level), but the output signal y1 of the spintronics logic gate SP1 is that CLK of the next cycle is at H level. It is held during the period and will not change. Therefore, even the spintronics logic gate SP2 that is an even number can correctly perform a logical operation. The same applies to the logical operation from the spintronics logic gate SP2 to SP3, and the description thereof will be omitted. In this way, between the even-numbered and odd-numbered spintronics logic gates, a two-phase clock in which the clock signals for controlling them are mutually inverted can be used, and the interleaved operation avoids the operational restrictions peculiar to the spintronics logic gate. Furthermore, the number of clock cycles (latency) required for the logical operation is also halved. As shown in Fig. 3, if a certain logical operation is obtained through a four-stage spintronic logic gate, the interleave operation is performed while the interleave operation by the two-phase clock is not required. In this case, the calculation time can be limited to 2 cycles (FIG. 4).

(Second embodiment)
Subsequently, a second embodiment of the present invention will be described. FIG. 5 shows a basic configuration diagram of a nonvolatile logic circuit in which an output signal of a spintronics logic gate according to a second embodiment of the present invention is fed back.

  A spintronic logic gate with a latch can be viewed as a flip-flop with a logic operation function. That is, the output of the spintronic logic gate can be fed back to the preceding stage. In FIG. 5, the output Q2 of the spintronics logic gate SP2 is input to the combinational circuit CL1 before the spintronics logic gate SP1 (feedback path a). Further, the output Q3 of the spintronics logic gate SP3 is input to the combinational circuit CL0 in the previous stage of the spintronics logic gate SP0 (feedback path b). Referring to the operation timing chart of FIG. 7, the timing at which each output signal changes between the even-numbered and odd-numbered spintronic logic gates is shifted by a half period. That is, since the logical operation periods do not overlap each other, it is possible to form a feedback path (a, b) from the even number stage to the odd number stage or from the odd number stage to the even number stage. On the other hand, when feedback is performed from even-numbered stages to even-numbered stages or odd-numbered stages to odd-numbered spintronic logic gates, a latch circuit is inserted in the feedback path as shown in FIG. 6 to provide feedback information until the logical operation period of the next clock cycle. Need to hold. For example, a latch circuit for inserting CLK at the L level and holding it at the H level is inserted into the feedback path c in which the output Q2 of the spintronics logic gate SP2 is input to the combinational circuit CL0 at the preceding stage of the spintronics logic gate SP0. For the feedback path d in which the output Q3 of the spintronics logic gate SP3 is input to the combinational circuit CL1 in the preceding stage of the spintronics logic gate SP1, a latch circuit is inserted that holds CLK at H level and through at L level. As shown in the operation timing chart in the feedback paths c and d in FIG. 7, the input signal does not change at the timing of the logical operation of the feedback destination gate by delaying the feedback source signal by the insertion of the latch circuit by a half cycle. ing.

(Third embodiment)
Next, a third embodiment of the present invention will be described. FIG. 8 shows an example in which the time required for the logical operation of the spintronic logic circuit is further reduced by using the four-phase clock signals (CLK0 to CLK3) whose phases are shifted by 90 degrees, 180 degrees, and 270 degrees. FIG. 8 shows an example in which the four spintronic logic gates with latches shown in FIG. 1 are included (SP0 to SP3), and logic operations propagate as y0, y1, y2, and y3. FIG. 9 shows an operation timing chart in the circuit configuration of FIG. The logic gate SP0 has its precharge operation and logic operation controlled by the CLK0 signal. Here, CLK0 is a master clock signal and is defined as having no phase difference. The logic gate SP1 has its precharge operation and logic operation controlled by the CLK1 signal. Here, the phase of CLK1 is delayed by 90 degrees compared to CLK0. The logic gate SP2 has its precharge operation and logic operation controlled by the CLK2 signal. Here, the phase of CLK2 is delayed by 180 degrees compared to CLK0. The precharge operation and logical operation of the logic gate SP3 are controlled by the CLK3 signal. Here, the phase of CLK3 is delayed by 270 degrees compared to CLK0.

  The logical operation result y0 of the logic gate SP0 is input to the logic gate SP1 via the combinational circuit CL1 immediately after the rising edge of CLK0. As shown in FIG. 9, at this time, CLK1 is at L level and the logic gate SP1 is in a precharged state. That is, an input signal that depends on the logical operation result y0 of SP0 is determined by the rising edge of CLK1. Further, since the logic value of the input signal depending on y0 is continuously determined while CLK1 is at the H level, the logic gate SP1 can correctly perform the logic operation. The logical operation result y1 of the logic gate SP1 is output immediately after the rising edge of CLK1, and is input to the logic gate SP2 via the combinational circuit CL2. Similarly to the above, the input signal depending on the logical operation result y1 of SP1 is determined by the rising edge of CLK2, and since it keeps holding until CLK2 finishes the logical operation, the logical gate SP2 can correctly perform the logical operation. It is. The same applies to the case where the logical operation propagates from the logic gates SP2 to SP3 and from the SP3 to SP0 (not shown). In this way, each spintronic logic gate operates in a different phase, and logic operations can be processed in a pipeline manner.

  In this way, a certain series of logic operation time can be shortened by operating using a multiphase clock signal for each spintronic logic gate. In the embodiment of FIG. 8, when a multiphase clock is not used, four cycles are required for the logical operation from y0 to y3. The calculation result can be obtained with.

  In the embodiment described above, the operation restriction problem is solved by operating the spintronics logic gate with a latch circuit shown in FIG. 1 with a multiphase clock, and the logic operation time is shortened. However, the latch circuit becomes a circuit area overhead. FIG. 10 shows another embodiment that avoids the problem of operation restrictions while using the spintronics logic gate of FIG. 12 without a latch circuit.

(Fourth embodiment)
Furthermore, a fourth embodiment of the present invention will be described. FIG. 10 is a schematic diagram showing a configuration of a non-volatile logic circuit according to a fourth example of the present invention.

  In FIG. 10, three stages of spintronic logic gates are cascaded between delay flip-flops (DFF) through a combinational circuit. Here, the input signal of the DFF is latched by the clock signal (CLK), the spintronics logic gates (SPi) of each stage are operated by the multiphase control signal (ENi), and ENi is precharged at the L level and at the H level. Performs logical operation. Here, the control signal input to the spintronic logic gate SP0 is EN0, the control signal input to SP1 is EN1, and the control signal input to SP2 is EN2. Here, as shown in FIG. 11, EN0 to EN2 are waveforms having different duty ratios that simultaneously fall in synchronization with the rising edge of CLK and rise sequentially from EN1 with different delay times.

  The operation of this embodiment will be described with reference to FIGS. When CLK rises, EN0 to 2 change to the L level, and all spintronic logic gates perform a precharge operation. At this time, the spintronic logic gate at each stage outputs an L level (logical value is “0”). With a certain arbitrary delay time, EN0 becomes H level, and the logic gate SP0 performs a logic operation. The input signal (A0) of the logic gate SP0 needs to be determined before the rising edge of the control signal EN0, but the delay time of the DFF, the delay time of the combinational circuit CL0, and the setup time of the logic gate SP0 If EN0 rises with a delay time longer than the sum of the two, a correct logical operation can be performed. The control signal EN0 is at the H level until the next rising edge of CLK, during which the logical operation result (y0) of SP0 output to the terminal Y0 is held (FIG. 11). The calculation result y0 propagates to the spin logic gate SP1 through the combinational circuit CL1. At this time, EN1 is still at the L level, that is, SP1 is in the precharge operation state. When the input signal A1 of SP1 is determined, EN1 becomes H level and SP1 enters a logic operation. The control signal EN1 is at the H level until the next rising edge of CLK, and the logical operation result (y1) of SP1 output to the terminal Y1 is held during this period. The calculation result y1 further propagates to the spin logic gate SP2 through the combinational circuit CL2. At this time, EN2 is still at the L level, that is, SP2 is in the precharge operation state. When the input signal A2 of SP2 is determined, EN2 becomes H level and SP2 enters a logic operation. The control signal EN2 is at the H level until the next rising edge of CLK, and the logical operation result (y2) of SP2 output to the terminal Y2 is held during that period. The calculation result y2 is input to the next stage DFF via the combinational circuit CL3. Since the output signal of the spintronic logic gate at each stage does not change until the next rising edge of CLK, it is possible to correctly latch the logical operation results from the terminals Q0 to D1.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the technical scope of the present invention. For example, in the first embodiment, a spintronics logic gate having a four-stage configuration is illustrated, but the spintronic logic gate is not limited to this configuration and can be configured by five or more stages. In the fourth embodiment, a spintronics logic gate having a three-stage configuration is illustrated. However, the present invention is not limited to this, and a four-stage configuration or the like may be used, and the duty ratio of the control signal is variable according to the configuration. Thus, a desired calculation operation can be performed.

Claims (3)

  A non-volatile logic integrated circuit including a resistance change element and a plurality of element circuits in which the resistance value of the resistance change element is used for a logic operation, wherein the plurality of element circuits perform an arithmetic operation according to a first control signal A first element circuit; and a second element circuit connected to a subsequent stage of the first element circuit and operating in accordance with a second control signal, wherein the second control signal is the first control circuit A non-volatile logic integrated circuit having a duty ratio smaller than a signal and each element circuit starting an arithmetic operation at a different timing. 2. The nonvolatile logic integrated circuit according to claim 1 , wherein a delay flip-flop is connected to an input of a preceding stage of the first element circuit and an output of a succeeding stage of the second element circuit, and each element circuit has a rising edge. A non-volatile logic integrated circuit characterized in that an arithmetic operation is started by a control signal having a phase that is sequentially delayed. 3. The nonvolatile logic integrated circuit according to claim 1, wherein the variable resistance element is a magnetoresistive element.

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