JP5903814B2 - Semiconductor circuit performance estimation apparatus, method and program thereof - Google Patents

Description

  The present invention relates to a semiconductor circuit performance estimation apparatus, method and program thereof, and more particularly, to a semiconductor circuit performance estimation apparatus, method and program thereof for estimating the performance of a semiconductor circuit in semiconductor circuit architecture design.

  In recent years, the importance of designing semiconductor circuits that implement complex algorithms has increased. In processing algorithms such as image processing and recognition processing, the amount of data to be handled has increased, and the demand for real-time processing has increased. Processing with a general-purpose processor alone cannot meet the requirements, and a semiconductor circuit that implements these algorithms must be designed as a dedicated circuit.

  The design of a semiconductor circuit that implements a complex algorithm is generally performed as follows.

  First, an algorithm suitable for realization as a semiconductor circuit is designed. The design of an algorithm is generally performed by a designer creating source code of a program that realizes the algorithm, compiling the source code, and executing the program on a processor to confirm the operation of the algorithm. When designing an algorithm, an architecture (pipeline architecture or the like) for implementation as a semiconductor circuit is not considered. Also consider what kind of memory (in-module memory, off-module memory, on-chip memory, off-chip memory, occupied memory, shared memory, etc.) the type of storage area (array, etc.) used in the algorithm Not. For the algorithm design, a programming language such as C ++, C #, JAVA (registered trademark) or a programming language such as SystemC, SpecC, or the like, which is extended for circuit design is used.

  Next, the operation level for realizing the algorithm is designed. The behavior level design is generally performed by the designer creating a behavior description. In the operation level design, an architecture to be realized as a semiconductor circuit is determined. It is also determined what kind of memory the storage area is allocated to.

  Next, hardware level design is performed. The hardware level design is generally performed by the behavioral synthesis device creating an RTL (Register Transfer Level) description. In the hardware level design, necessary control processing (such as pipeline control) is implemented according to the architecture determined in the operation level design. In addition, necessary interface circuits (Static Random Access Memory (SRAM) interface, Dynamic Random Access Memory (DRAM) interface, bus interface, etc.) are implemented according to the type of memory determined in the operation level design. Is done.

  When a complicated algorithm is realized as a semiconductor circuit, the memory access cost determines the processing performance. However, when designing an algorithm, it is not possible to easily estimate the processing performance because it does not consider what kind of memory the storage area is allocated to. Therefore, the processing performance is known only after algorithm design, operation level design, and hardware design are finished (after the storage area is actually allocated to the memory and the necessary interface circuit is mounted). For example, if it is found that the processing performance has not reached the target performance after the hardware design is completed, it is necessary to restart the design from the algorithm design, which is a great rework.

  If the performance when implemented on a semiconductor circuit can be easily estimated at the time of algorithm design, it can be judged early whether the algorithm is good or bad, so that the design period can be shortened without causing rework. .

  Several methods for estimating the performance of a semiconductor circuit at an early stage have been disclosed. Patent Document 1 and Patent Document 2 disclose a method for estimating performance at high speed by preparing two models: a model for performing detailed operations and a simple model for estimating performance. However, a new model must be created to estimate the performance, and it is difficult to say that a simple estimate has been realized.

  Japanese Patent Application Laid-Open No. H11-228561 discloses a technique for estimating performance by measuring the number of memory accesses. However, this is a method for evaluating the performance of a program mainly operating on a processor. When the algorithm is implemented as a dedicated semiconductor circuit, the performance varies greatly depending on the type of memory to which the storage area is allocated due to the difference in access cost due to the memory, unlike the case where the algorithm is operated on the processor. Therefore, it is indispensable for simple estimation to consider the memory type to which the storage area is allocated. However, Patent Document 3 does not consider which type of memory the storage area is allocated to.

  Patent Documents 4 and 5 disclose a method for determining a suitable memory allocation from the number of accesses to a storage area. However, a method for realizing simple estimation is not disclosed.

  Patent Document 6 discloses a method of automatically synthesizing a suitable circuit by analyzing a memory access pattern (access order to memory elements) to a storage area. However, a method for realizing simple estimation is not disclosed.

  Patent Document 7 discloses a technique for calculating processing times of programs operating on a plurality of program execution devices by analyzing access competition to a memory from a plurality of semiconductor circuits. However, there is no disclosure of a method for simply estimating the performance of a semiconductor circuit that implements a complex algorithm described in a programming language.

  As described above, even with existing technology, it is not possible to easily estimate the performance of a semiconductor circuit that implements a complex algorithm described in a programming language.

JP 2003-256494 A US Publication No. 2008 / 0263486A1 JP-A-3-235138 JP 2005-173648 A JP 2011-22863 A JP 2007-323206 A JP 2010-286892 A

  The first problem is that there is no method for judging whether an algorithm is good or bad when designing a semiconductor circuit that implements a complex algorithm.

  The reason is that there is no simple method for estimating the performance of a logic circuit that implements a complex algorithm described in a programming language.

  An object of the present invention is to provide a semiconductor circuit performance estimation apparatus, a method thereof, and a program thereof that can easily estimate the performance of a semiconductor circuit that realizes a predetermined algorithm.

According to a first aspect of the present invention, there is provided a semiconductor circuit performance estimating apparatus for estimating the performance of a semiconductor circuit, wherein each storage area included in a source code which is design data of the semiconductor circuit is stored in the storage area. Means for storing memory type information of the allocated memory, means for storing access cost information for each type of memory, means for generating a performance evaluation model for calculating the number of accesses to each of the storage areas, and Means for calculating the memory type access count for each memory type from the memory area access count measured by operating the performance evaluation model and the memory type information, and access from the access cost information and the memory type access count An estimated performance generating means for calculating a total cost and generating an estimated performance of the semiconductor circuit based on the total; The performance evaluation model is generated by adding the access count unit to the source code, or is generated by combining a library incorporating the access count unit with the source code, or It is generated by combining the source code with a simulator incorporating a means for counting the number of accesses, and the estimated performance generating means generates the estimated performance for each type when there are a plurality of types of access costs. A semiconductor circuit performance estimation device is provided.

According to a second aspect of the present invention, there is provided a semiconductor circuit performance estimation method for estimating the performance of a semiconductor circuit, wherein the number of accesses to each storage area included in a source code which is design data of the semiconductor is calculated. From the step of generating a performance evaluation model, the number of accesses by storage area measured by operating the performance evaluation model, and the memory type information of the memory allocated to the storage area stored in advance, for each type of the memory The step of calculating the memory type access count, the access cost information for each memory type stored in advance, and the memory type access count are calculated, and the access cost is calculated based on the total. Generating an estimated performance, and the performance evaluation model is included in the source code. A simulator and source code generated by adding access count means, or a library incorporating the access count means and combined with the source code, or a simulator incorporating the access count means and the source code The estimated performance generation step provides a semiconductor circuit performance estimation method for generating the estimated performance for each type when there are a plurality of types of access costs .

According to a third aspect of the present invention, there is provided a semiconductor circuit performance estimation program for causing a computer to function as a semiconductor circuit performance estimation apparatus for estimating the performance of a semiconductor circuit, wherein the computer is used as design data for the semiconductor. A means for generating a performance evaluation model for calculating the number of accesses to each storage area included in a certain source code , an access count for each storage area measured by operating the performance evaluation model, and assigned to the storage area stored in advance Means for calculating the memory type access count for each memory type from the memory type information of the memory to be stored, the access cost information for each memory type stored in advance, and the total access cost from the memory type access count And calculate the estimated performance of the semiconductor circuit based on the total. The performance evaluation model is generated by adding the access count unit to the source code, or a library incorporating the access count unit is generated as the source code. Generated in combination, or generated by combining the simulator incorporating the access counting means and the source code, and the estimated performance generating means, when there are a plurality of types of access costs, the estimated performance for each type A semiconductor circuit performance estimation program characterized by generating performance is provided.

  According to the present invention, it is possible to easily estimate the performance of a semiconductor circuit that realizes a predetermined algorithm.

It is a block diagram which shows the structure of the semiconductor circuit performance estimation apparatus by embodiment of this invention. It is a flowchart which shows the semiconductor circuit performance estimation method performed by the semiconductor circuit performance estimation apparatus shown in FIG. 3 is a program list (1/2) showing an example of analysis target source code stored in an analysis target source code storage unit shown in FIG. 1. 3 is a program list (2/2) showing an example of analysis target source code stored in an analysis target source code storage unit shown in FIG. 1. FIG. 2 is a diagram illustrating an example of memory allocation information representing a correspondence relationship between a variable described in an analysis target source code and a type of an allocation destination memory of the variable, stored in a memory allocation information storage unit illustrated in FIG. 1. . It is a figure which shows an example of the access cost correspondence table showing the access cost for every kind of memory memorize | stored in the access cost correspondence table memory | storage part shown in FIG. 1 is a program list (1/2) of performance evaluation models generated by the performance evaluation model generation unit illustrated in FIG. 1 based on the analysis target source codes illustrated in FIGS. 1 is a program list (2/2) of performance evaluation models generated by the performance evaluation model generation unit illustrated in FIG. 1 based on the analysis target source codes illustrated in FIGS. FIG. 3 is a diagram illustrating an access count correspondence table generated by the access count analysis unit illustrated in FIG. 1 based on the performance evaluation model illustrated in FIGS. FIG. 8 is a diagram showing the number of accesses for each type of memory generated by the estimated performance calculator shown in FIG. 1 based on the memory allocation information shown in FIG. 4 and the access count correspondence table shown in FIG. FIG. 9 is a diagram illustrating estimated performance generated by the estimated performance calculation unit illustrated in FIG. 1 based on the access cost correspondence table illustrated in FIG. 5 and the number of accesses for each type of memory illustrated in FIG. 8. It is a program list (1/2) which shows another example of the analysis object source code memorize | stored in the analysis object source code memory | storage part shown in FIG. It is a program list (2/2) which shows another example of the analysis object source code memorize | stored in the analysis object source code memory | storage part shown in FIG. Access count correspondence table generated by the access count analysis unit shown in FIG. 1 based on the performance evaluation model generated by the performance evaluation model generation unit shown in FIG. 1 based on the analysis source code shown in FIGS. FIG. FIG. 13 is a diagram illustrating estimated performance generated by the estimated performance calculation unit illustrated in FIG. 1 based on the memory allocation information illustrated in FIG. 4, the access cost correspondence table illustrated in FIG. 5, and the access count correspondence table illustrated in FIG. 11. The figure which shows another example of the memory allocation information showing the correspondence of the variable described in the analysis object source code, and the kind of memory to which the variable is allocated, stored in the memory allocation information storage unit shown in FIG. It is. It is a figure which shows the estimated performance which the estimated performance calculation part shown in FIG. 1 produced | generated based on the memory allocation information shown in FIG. 13, the access cost correspondence table shown in FIG. 5, and the access frequency correspondence table shown in FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

  Referring to FIG. 1, the semiconductor circuit performance estimation apparatus of this embodiment includes a performance evaluation model generation unit 101, an access count analysis unit 102, and an estimated performance calculation unit 103. The performance evaluation model generation unit 101 is an analysis target. A performance evaluation model capable of calculating the number of accesses to each storage area included in the source code is generated, and the access number analysis unit 102 executes the performance evaluation model to determine the number of accesses for each storage area being executed. The estimated performance calculation unit 103 calculates the total access cost from the number of accesses for each storage area, information on the allocation destination memory type for each storage area, and access cost information for each memory type, and generates estimated performance. It works like this. By adopting such a configuration, the object of the present invention can be achieved.

  Referring to FIG. 1, an embodiment of the present invention includes a computer (central processing unit; processor; data processing unit) 100 that operates under program control, and a storage device 200.

  The computer 100 includes a performance evaluation model generation unit 101, an access count analysis unit 102, and an estimated performance calculation unit 103.

  The storage device 200 includes an analysis target source code storage unit 111, a performance evaluation model storage unit 112, a storage area-specific access count correspondence table storage unit 113, a memory allocation information storage unit 114, and a memory type access count correspondence table storage. Unit 115, access cost correspondence table storage unit 116, and performance estimation result storage unit 117.

  Next, the overall operation of the present embodiment will be described in detail with reference to the flowcharts of FIGS.

  Prior to the operation, the analysis target source code storage unit 111 stores in advance a source code to be analyzed, which is design data of the semiconductor circuit. The source code to be analyzed is described in a software programming language such as C language, C ++ language, Java (registered trademark) language, for example. A software program language such as SystemC or SpecC may be described in a language that is extended for semiconductor circuit design.

  The memory allocation information storage unit 114 stores in advance information on the type of memory to which the storage area is allocated for each storage area (array, etc.) included in the source code to be analyzed. A semiconductor device reflecting this can be manufactured based on the source code, the memory allocation information, and the like.

  The memory type is, for example, a memory mounted inside a chip. Alternatively, it is a memory mounted outside the chip. Alternatively, it is a memory occupied by a semiconductor circuit that realizes a source code to be analyzed. Alternatively, it is a memory shared with other semiconductor circuits. Alternatively, it is a memory directly connected to a semiconductor circuit that realizes a source code to be analyzed. Alternatively, it is a memory connected via a bus.

  The access cost correspondence table storage unit 116 stores in advance access cost information for each type of memory.

  The access cost is, for example, the time required for access (access time). Alternatively, it is the number of clock cycles required for access (number of access clock cycles). Alternatively, it is power consumed by access (access power consumption). Alternatively, it is the amount of heat generated by access (access generated heat amount). Alternatively, it is the area of the memory to be accessed (access target memory area). Alternatively, it is the ratio of the time to occupy the access target memory (access target memory occupation time ratio). Or the combination (for example, weighted average) of two or more of these may be sufficient.

  First, the performance evaluation model generation unit 101 reads a source code from the analysis source code storage unit 111 (step A1 in FIG. 2).

  Next, the performance evaluation model generation unit 101 detects a storage area included in the source code (step A2 in FIG. 2).

  The storage area is, for example, an array declared in the source code. Alternatively, for example, a memory area secured by the malloc function in the source code. Or, for example, a memory area secured by the new function.

  Next, the performance evaluation model generation unit 101 adds, to the source code, a means for counting the number of accesses (reading and writing) for each of the storage areas, and generates this as a performance evaluation model (step A3 in FIG. 2). ).

  The means for counting the number of accesses is, for example, a method in which a counter is prepared for each storage area and an operation for incrementing the counter for each access is added to the source code. Alternatively, a function incorporating a means for counting the number of accesses is prepared, and reading and writing of the memory are replaced with the function.

  The performance evaluation model is obtained by modifying the source code to be analyzed, for example. Alternatively, a library incorporating means for counting the number of accesses can be obtained in combination with the source code to be analyzed. Alternatively, it can be obtained by combining a simulator incorporating means for counting the number of accesses and a source code to be analyzed.

  Next, the performance evaluation model generation unit 101 stores the performance evaluation model in the performance evaluation model storage unit 112.

  Next, the access count analysis unit 102 reads the performance evaluation model from the performance evaluation model storage unit 112.

  Next, the access count analysis unit 102 operates the performance evaluation model, measures the number of accesses for each storage area included in the source code, and creates an access count correspondence table for each storage area (step in FIG. 2). A4).

  The access count correspondence table for each storage area is obtained, for example, by converting the performance evaluation model into a code that can be executed on the processor by a compiler and operating it on the processor. Alternatively, the performance evaluation model is obtained by converting the performance evaluation model into a code that can be executed on the processor together with a library in which means for counting the number of accesses is incorporated, and operating the processor on the processor. Alternatively, it is obtained by executing the performance evaluation model on a simulator incorporating means for counting the number of accesses.

  Next, the access count analysis unit 102 stores the access count correspondence table for each storage area in the access count correspondence table storage unit 113 for each storage area.

  Next, the estimated performance calculation unit 103 reads the storage area access count correspondence table from the storage area access count correspondence table storage section 113.

  Next, the estimated performance calculation unit 103 reads the memory allocation information from the memory allocation information storage unit 114 (step A5 in FIG. 2).

  Next, the estimated performance calculation unit 103 accesses the information on the number of accesses for each storage area described in the access count correspondence table for each storage area and the type of the allocation destination memory for each storage area described in the memory allocation information. The number of accesses for each memory type is calculated from the above information and stored in the memory type access count correspondence table storage unit 115 as a memory type access count correspondence table (step A6 in FIG. 2).

  Next, the estimated performance calculation unit 103 reads the access cost correspondence table from the access cost correspondence table storage unit 116 (step A7 in FIG. 2).

  Next, the estimated performance calculation unit 103 uses the access count information for each memory type described in the memory type access count correspondence table and the access cost information for each memory type described in the access cost correspondence table. Then, the total access cost is calculated and the estimated performance is generated (step A8 in FIG. 2).

  Finally, the estimated performance calculation unit 103 stores the estimated performance in the estimated performance storage unit 117.

  For multiple types of access costs, the estimated performance is calculated for each type of access cost, and the value obtained by combining these (for example, the value obtained by taking the weighted average) is the final. The estimated performance may be good.

  Next, the effect of this embodiment will be described.

  In the present embodiment, the performance evaluation model generation unit 101 generates a performance evaluation model that can calculate the number of accesses to each storage area included in the source code to be analyzed, and the access number analysis unit 102 performs the performance evaluation. The model is executed to calculate the number of accesses for each storage area being executed, and the estimated performance calculation unit 103 determines the number of accesses for each storage area, the information on the allocation destination memory type for each storage area, and the access cost for each memory type. Provides a semiconductor circuit performance estimation device that can easily estimate the performance of a logic circuit that implements a complex algorithm because the estimated performance is generated by calculating the total access cost from the information of be able to.

  Next, the operation of the best mode for carrying out the present invention will be described using specific examples.

  Referring to FIGS. 3A and 3B, the source code to be analyzed is illustrated. Although the source code is described using “System C language”, parts not related to the description of the present invention are partially omitted.

  The source code of FIGS. 3-1 and 3-2 generally operates as follows. It has two input terminals in0 and in4 and one output terminal out3. 128 pieces of data are read from the input terminals in0 and in4, and the data are once stored in the array. Thereafter, an operation is performed based on the data stored in the array, and the result is stored in the array. Further, 128 pieces of data stored in the array are written to the output terminal out3.

  Input / output terminals are declared in the first to fifth lines of the source code in FIG. Specifically, unsigned 8-bit wide input terminals in0 and in4 and an output terminal out3 are declared.

  Operations are defined from the 6th line to the 31st line of the source code in FIG. In the 7th to 11th lines, an unsigned 8-bit array ary0 to ary4 is declared. From the 15th line to the 18th line, 128 pieces of data are read from the input terminals in0 and in4, respectively, and written to the arrays ary0 and ary4.

  Calculation is performed from the 20th line to the 24th line of the source code in FIG. Specifically, in the 20th line, it is designated that the 21st to 23rd lines are repeated until the value of the loop counter i changes from 0 to 123. In the 21st row, it is specified that the i-th, i + 1-th, and i + 2-th elements of the array ary0 are read, the sum is calculated, and written as the i-th element of the array ary1. Similarly, in the 22nd line, it is specified that the i + 3th and i + 4th elements of the array ary0 are read, the sum thereof is calculated, and written as the ith element of the array ary2. In line 23, the i-th and i + 1-th elements of the array ary4 are read, the values are used to read the values from the arrays ary1 and ary2, and the sum is calculated and written as the i-th element of the array ary3. Is specified.

  In the 26th to 28th lines of the source code in FIG. 3B, it is specified that 128 values of the array ary3 are written to the output terminal out3.

  The source codes in FIGS. 3A and 3B are stored in advance in the analysis target source code storage unit 111.

  Referring to FIG. 4, memory allocation information is illustrated. In the memory allocation information of FIG. 4, three types of memory, that is, a first external memory, a first internal memory, and a second internal memory are used, and five storage areas (in the source code of FIG. 3 ( For the array) ary0 to ary4, the type of memory to which each is assigned is specified. For example, it is specified that the array ary0 is assigned to the first external memory, the array ary1 is assigned to the first internal memory, and the like.

  The memory allocation information in FIG. 4 is stored in advance in the memory allocation information storage unit 114.

  Referring to FIG. 5, an access cost correspondence table is illustrated. The access cost correspondence table of FIG. 5 shows the time (number of clock cycles) required for accessing the first external memory, the first internal memory, and the second internal memory.

  The access cost correspondence table in FIG. 5 is stored in advance in the access cost correspondence table storage unit 116.

  First, the performance evaluation model generation unit 101 reads the source codes of FIGS. 3A and 3B from the analysis target source code storage unit 111 (step A1 in FIG. 2), and is an array that is a storage area included in the source code ary0 to ary4 are detected (step A2 in FIG. 2).

  Next, the performance evaluation model generation unit 101 adds, to the source code, a means for counting the number of accesses (reading and writing) for each of the storage areas, and generates this as a performance evaluation model (step A3 in FIG. 2). ).

  With reference to FIGS. 6A and 6B, a performance evaluation model is illustrated. In the performance evaluation models of FIGS. 6A and 6B, five counters cnt [0] to cnt [4 for five arrays ary0 to ary4 with respect to the source code of FIGS. ] Is prepared, and the part that operates to increment the counter each time the array is accessed is different.

  In the twelfth line of the performance evaluation model of FIG. 6B, five counters cnt [0] to cnt [4] are declared and initialized with a value of zero.

  In the 17th and 18th lines, cnt [0] and cnt [4] are incremented each time the arrays ary0 and ary4 are accessed. Similarly, in the 22nd to 24th lines and the 28th line, the value of the corresponding counter is increased every time the array is accessed.

  Next, the performance evaluation model generation unit 101 stores the performance evaluation model in FIG. 6 in the performance evaluation model storage unit 112.

  Next, the access count analysis unit 102 reads the performance evaluation model of FIG. 6 from the performance evaluation model storage unit 112.

  Next, the access count analysis unit 102 operates the performance evaluation model of FIG. 6, measures the number of accesses for each storage area included in the source code, and creates a storage area-specific access count correspondence table (FIG. 2). Step A4).

  Referring to FIG. 7, an access frequency correspondence table by storage area is illustrated. In the access count correspondence table by storage area in FIG. 7, the number of accesses for each array (counters cnt [0] to cnt [0] obtained by executing the 15th to 30th rows of the performance evaluation model in FIG. 6 once. 4)) is shown.

  Next, the access count analysis unit 102 stores the access count correspondence table for each storage area in FIG. 7 in the access count correspondence table storage unit 113 for each storage area.

  Next, the estimated performance calculation unit 103 reads the access count correspondence table in FIG. 7 from the access count correspondence table storage unit 113 by storage area, and reads the memory allocation information in FIG. 4 from the memory allocation information storage unit 114.

  Next, from the information on the number of accesses for each storage area described in the access count correspondence table for each storage area in FIG. 7 and the information on the memory type of the allocation destination for each storage area described in the memory allocation information in FIG. The number of accesses for each memory type is calculated.

  Referring to FIG. 8, the number of accesses for each memory type is illustrated. FIG. 8 illustrates the number of accesses to each of the first external memory, the first internal memory, and the second internal memory. For example, since the numbers of accesses of the arrays ary0 and ary3 allocated to the first external memory are 743 times and 251 times, respectively, the total number of accesses to the first external memory is the sum of 994 times.

  Next, the estimated performance calculation unit 103 reads the access cost correspondence table in FIG. 5 from the access cost correspondence table storage unit 116, and information on the number of accesses for each memory type in FIG. 8 and information on the access correspondence table in FIG. From the above, the total access cost is calculated and the estimated performance is generated.

  Referring to FIG. 9, the access cost for each memory type is illustrated. FIG. 9 illustrates the access costs of the first external memory, the first internal memory, and the second internal memory. For example, since the access cost per time of the first external memory is 10 and the access count is 994 times, the access cost of the first external memory is calculated as 9940. The access costs of the first internal memory and the second internal memory are also calculated in the same manner, and the estimated performance that is the sum of these is calculated as 10,806. That is, the product sum of the number of accesses for each access destination memory type and the access cost for each access for each access destination memory type is calculated as the estimated performance.

  Finally, the estimated performance calculation unit 103 stores the estimated performance in the estimated performance storage unit 117.

  Next, consider that the source code of FIGS. 3-1 and 3-2 is changed as shown in FIGS. The source code illustrated in FIGS. 10A and 10B is functionally the same as the source code of FIGS. 3-1 and 3-2, but reduces reading from the same element of the array ary0. It is different that it has been changed.

  An array sr for temporarily storing data to be reused is declared in the 12th line of the source code in FIG. From the 20th line to the 22nd line, the elements from the 0th element to the 3rd element of the array ary are read and written to the array sr.

  In the 25th line, a new value is read from the array ary0 and written to the fourth element of the array sr. In the 26th and 27th lines, instead of reading the value from the array ary0, the value is read from the array sr, the sum is calculated in the same way as the source code of FIG. 3, and the result is stored in the arrays ary1 and ary2.

  The values of the array sr are shifted from the 29th line to the 31st line to prepare for the next calculation.

  The performance evaluation model generation unit 101 generates a performance evaluation model from the source codes of FIGS. 10-1 and 10-2. The access count analysis unit 102 executes the performance evaluation model and measures the number of accesses for each array. Create an access count correspondence table.

  Referring to FIG. 11, an access count correspondence table for the source code of FIG. 10 is illustrated. Compared to the access count correspondence table illustrated in FIG. 7, it can be seen that the access count of the array ary0 is reduced.

  The estimated performance calculation unit 103 reads the access count correspondence table of FIG. 11, the memory allocation of FIG. 4 and the access cost of FIG. 5, calculates the access count for each memory type, and further calculates the access cost for each memory type. calculate.

  Referring to FIG. 12, the source code of FIG. 11, the memory allocation of FIG. 4, and the access cost for each memory type and the sum total obtained from the access cost of FIG. 5 are illustrated. Compared to the access cost illustrated in FIG. 9, it can be seen that the access cost of the first external memory is reduced, and as a result, the total access cost is also reduced.

  As described above, it is easy to estimate that the semiconductor circuit that realizes the source code of FIGS. 10A and 10B is lower in cost than the semiconductor circuit that realizes the source code of FIGS. Can do.

  Next, consider that the memory allocation in FIG. 4 is changed as shown in FIG. The memory allocation in FIG. 13 differs from the memory allocation in FIG. 4 in that the array ary0 is allocated to the first internal memory.

  The estimated performance 103 reads the access count correspondence table of FIG. 11, the memory allocation of FIG. 13 and the access cost of FIG. 5, calculates the access count for each memory type, and further calculates the access cost for each memory type. .

  Referring to FIG. 14, there are illustrated an access cost for each memory type and a total sum obtained from the source code in FIG. 11, the memory allocation in FIG. 13, and the access cost in FIG. 5. Compared to the access cost illustrated in FIG. 12, although the access cost of the first internal memory is increased, the access cost of the first external memory is reduced, and as a result, the total access cost is also reduced. You can see that

  Thus, the semiconductor circuit that realizes the source code of FIG. 10 using the memory allocation of FIG. 13 is lower in cost than the semiconductor circuit that realizes the source code of FIG. 10 using the memory allocation of FIG. It can be easily estimated.

  According to the present embodiment, when the algorithm is changed, the performance of the logic circuit that realizes the source code corresponding to the algorithm can be easily estimated, and this can be used as a judgment material for examining the algorithm. Further, according to the present embodiment, when the allocation to the memory is changed, the performance of the logic circuit that realizes the source code can be easily estimated, and this can be used as a material for determining the architecture study.

  The semiconductor circuit performance estimation device described above can be realized by hardware, software, or a combination thereof. The semiconductor circuit performance estimation method performed by the semiconductor circuit performance estimation apparatus described above can also be realized by hardware, software, or a combination thereof. Here, “realized by software” means realized by a computer reading and executing a program.

  The program may be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD- R, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (random access memory)). The program may also be supplied to the computer by various types of transitory computer readable media. Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A semiconductor circuit performance estimation device for estimating the performance of a semiconductor circuit,
Based on the source code that is the semiconductor design data, obtain the number of accesses for each memory type of the access destination, and estimate based on the number of accesses for each memory type of the access destination and the access cost for each memory type of the access destination A semiconductor circuit performance estimation apparatus characterized by calculating performance.

(Appendix 2)
A semiconductor circuit performance estimation device according to appendix 1,
The access count for each memory type of the access destination is obtained based on the access count for each storage area and the memory type for each storage area.

(Appendix 3)
A semiconductor circuit performance estimation device according to appendix 2,
2. A semiconductor circuit performance estimation apparatus, wherein the number of accesses for each access destination storage area is obtained by executing a performance evaluation model generated based on the source code.

(Appendix 4)
A semiconductor circuit performance estimation device according to attachment 3, wherein
The performance evaluation model includes a description for counting the number of accesses for each storage area when the performance evaluation model is executed.

(Appendix 5)
The semiconductor circuit performance estimation device according to any one of appendices 1 to 4,
The product-sum of the access count for each access destination memory type and the access cost for each access destination memory type calculated based on the access count for each access destination memory type and the access cost for each access destination memory type Is calculated as the estimated performance.

(Appendix 6)
The semiconductor circuit performance estimation device according to any one of appendices 1 to 5,
The access cost is an access time, an access clock cycle number, an access power consumption, an access heat generation amount, an access target memory area or an access target memory occupation time ratio, or a combination thereof.

(Appendix 7)
The semiconductor circuit performance estimation device according to any one of appendices 1 to 5,
A semiconductor circuit performance estimation apparatus characterized in that, for a plurality of types of access costs, an estimated performance is calculated for each access cost type, and a value obtained by combining these is used as a final estimated performance.

(Appendix 8)
A semiconductor circuit performance estimation method for estimating the performance of a semiconductor circuit,
Based on the source code that is the semiconductor design data, obtain the number of accesses for each memory type of the access destination, and estimate based on the number of accesses for each memory type of the access destination and the access cost for each memory type of the access destination A semiconductor circuit performance estimation method characterized by calculating performance.

(Appendix 9)
A semiconductor circuit performance estimation method according to appendix 8,
The access count for each memory type of the access destination is obtained based on the access count for each storage area and the memory type for each storage area.

(Appendix 10)
A semiconductor circuit performance estimation method according to attachment 9, wherein
A method for estimating a semiconductor circuit performance, wherein the number of accesses for each storage area of the access destination is obtained by executing a performance evaluation model generated based on the source code.

(Appendix 11)
A semiconductor circuit performance estimation method according to appendix 10,
The performance evaluation model includes a description for counting the number of accesses for each storage area when the performance evaluation model is executed.

(Appendix 12)
A semiconductor circuit performance estimation method according to any one of appendices 8 to 11,
The product-sum of the access count for each access destination memory type and the access cost for each access destination memory type calculated based on the access count for each access destination memory type and the access cost for each access destination memory type Is calculated as the estimated performance, a semiconductor circuit performance estimation method.

(Appendix 13)
A semiconductor circuit performance estimation method according to any one of appendices 8 to 12,
The access cost is an access time, an access clock cycle number, an access power consumption, an access heat generation amount, an access target memory area or an access target memory occupation time ratio, or a combination thereof.

(Appendix 14)
A semiconductor circuit performance estimation method according to any one of appendices 8 to 12,
A semiconductor circuit performance estimation method characterized in that, for a plurality of types of access costs, an estimated performance is calculated for each type of access cost, and a value obtained by combining these is used as a final estimated performance.

(Appendix 15)
A semiconductor circuit performance estimation program for causing a computer to function as a semiconductor circuit performance estimation device for estimating the performance of a semiconductor circuit,
The semiconductor circuit performance estimation device is:
Based on the source code that is the semiconductor design data, obtain the number of accesses for each memory type of the access destination, and estimate based on the number of accesses for each memory type of the access destination and the access cost for each memory type of the access destination A semiconductor circuit performance estimation program for calculating performance.

(Appendix 16)
A semiconductor circuit performance estimation program according to appendix 15,
The semiconductor circuit performance estimation apparatus obtains the access count for each access destination memory type based on the access count for each storage area and the memory type for each storage area.

(Appendix 17)
A semiconductor circuit performance estimation program according to appendix 16,
The semiconductor circuit performance estimation apparatus obtains the number of accesses for each access destination storage area by executing a performance evaluation model generated based on the source code.

(Appendix 18)
A semiconductor circuit performance estimation program according to appendix 17,
The performance evaluation model includes a description for counting the number of accesses for each storage area when the performance evaluation model is executed.

(Appendix 19)
A semiconductor circuit performance estimation program according to any one of appendices 15 to 18,
The semiconductor circuit performance estimation apparatus includes: an access count for each access destination memory type calculated based on an access count for each access destination memory type and an access cost for each access destination memory type; and the access destination memory A semiconductor circuit performance estimation program characterized by calculating a product sum of access costs by type as the estimated performance.

(Appendix 20)
A semiconductor circuit performance estimation program according to any one of appendices 15 to 19,
The access cost is an access time, an access clock cycle number, an access power consumption, an access heat generation amount, an access target memory area or an access target memory occupation time ratio, or a combination thereof.

(Appendix 21)
A semiconductor circuit performance estimation program according to any one of appendices 15 to 19,
The semiconductor circuit performance estimation device is characterized in that, for a plurality of types of access cost, an estimated performance is calculated for each type of access cost, and a value obtained by combining these is set as a final estimated performance. Semiconductor circuit performance estimation program.

  The present invention can be used to easily estimate the performance of a logic circuit that implements a complex algorithm.

DESCRIPTION OF SYMBOLS 100 Computer 101 Performance evaluation model production | generation part 102 Access frequency analysis part 103 Estimated performance calculation part 111 Analysis object source code memory | storage part 112 Performance evaluation model memory | storage part 113 Access count correspondence table memory | storage part according to storage area 114 Memory allocation information memory | storage part 115 Memory type Separate access count correspondence table storage unit 116 Access cost correspondence table storage unit 117 Estimated performance storage unit 200 storage device

Claims (6)

A semiconductor circuit performance estimation device for estimating the performance of a semiconductor circuit,
Means for storing memory type information of a memory allocated to the storage area for each storage area included in the source code which is design data of the semiconductor circuit ;
Means for storing access cost information for each type of memory;
Means for generating a performance evaluation model for calculating the number of accesses to each of the storage areas;
Means for calculating the memory type access count for each type of the memory from the memory area access count and the memory type information measured by operating the performance evaluation model;
An estimated performance generating means for calculating a total access cost from the access cost information and the memory type access count, and generating an estimated performance of the semiconductor circuit based on the total;
With
The performance evaluation model is generated by adding the access count unit to the source code, or is generated by combining the source code with a library incorporating the access count unit, or the access count It is generated by combining the simulator incorporating the counting means and the source code,
The estimated performance generating means generates the estimated performance for each type when there are a plurality of types of the access cost . The semiconductor circuit performance estimation device according to claim 1,
When the source code is changed, the estimated performance generating means calculates the total access cost after the change of the source code so as to be comparable with the total access cost before the change of the source code. Semiconductor circuit performance estimation device. The semiconductor circuit performance estimation device according to claim 1,
When the memory allocation to the storage area is changed, the estimated performance generating means calculates the total access cost after the memory allocation change so as to be comparable with the total access cost before the memory allocation change. A semiconductor circuit performance estimating apparatus. A semiconductor circuit performance estimation device according to any one of claims 1 to 3 ,
The access cost is an access time, an access clock cycle number, an access power consumption, an access heat generation amount, an access target memory area or an access target memory occupation time ratio, or a combination thereof. A semiconductor circuit performance estimation method for estimating the performance of a semiconductor circuit,
Generating a performance evaluation model for calculating the number of accesses to each storage area included in the source code which is the semiconductor design data ;
Calculating the memory type access count for each memory type from the memory area access count measured by operating the performance evaluation model and the memory type information of the memory allocated to the storage area stored in advance. ,
Calculating a total access cost from the access cost information for each memory type stored in advance and the memory type access count, and generating an estimated performance of the semiconductor circuit based on the total;
With
The performance evaluation model is generated by adding the access count unit to the source code, or is generated by combining the source code with a library incorporating the access count unit, or the access count It is generated by combining the simulator incorporating the counting means and the source code,
In the estimated performance generation step, when there are a plurality of types of the access cost, the estimated performance is generated for each type . A semiconductor circuit performance estimation program for causing a computer to function as a semiconductor circuit performance estimation device for estimating the performance of a semiconductor circuit,
The computer,
Means for generating a performance evaluation model for calculating the number of accesses to each storage area included in the source code which is the design data of the semiconductor ;
Means for calculating the memory type access count for each type of the memory from the memory area access count measured by operating the performance evaluation model and the memory type information stored in advance in the memory allocated to the storage area;
An estimated performance generating means for calculating the total access cost from the information of the access cost for each memory type stored in advance and the memory type access count, and generating the estimated performance of the semiconductor circuit based on the total;
Act as
The performance evaluation model is generated by adding the access count unit to the source code, or is generated by combining the source code with a library incorporating the access count unit, or the access count It is generated by combining the simulator incorporating the counting means and the source code,
The estimated performance generation means generates the estimated performance for each type when there are a plurality of types of access costs .

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