JP5881586B2 - Defective pixel detection device and defective pixel detection method - Google Patents

Description

  Embodiments described herein relate generally to a defective pixel detection device and a defective pixel detection method for a solid-state imaging device.

  The imaging device includes a solid-state imaging device (for example, a CCD (Charge Coupled Device) image sensor or a CMOS (Complementary Metal Oxide Semiconductor) image sensor), and obtains an image by performing photoelectric conversion using the solid-state imaging device. Usually, a solid-state imaging device includes a defective pixel having a scratch. If the image contains scratches, the obtained image deteriorates. For this reason, conventionally, a defective pixel is detected by detecting a defective pixel (defective pixel).

  By the way, at present, in order to obtain a higher-definition image, the number of pixels of the solid-state imaging device is increasing. As a result, the time required for detecting the defective pixel has increased, and a defective pixel detection apparatus and a defective pixel detection method capable of reducing the time required for detecting the defective pixel are demanded.

JP 2008-60621 A JP 2008-148129 A JP 2008-306565 A

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a defective pixel detection apparatus and a defective pixel detection method capable of reducing the time required for detecting a defective pixel.

  The defective pixel detection apparatus according to the embodiment includes a detector that detects a color signal that exceeds a predetermined threshold from a color signal output from a solid-state imaging device, and an address of a pixel corresponding to the color signal detected by the detector. Of the first and second memories stored in units of screens and the color signals constituting the first screen output from the solid-state imaging device, the address of the pixel corresponding to the color signal detected by the detector is set to the first address. The pixel corresponding to the color signal detected by the detector among the address stored in the first memory and the color signal constituting the second screen output from the solid-state imaging device. And a control circuit for storing the addresses in the second memory in accordance with the coincidence / non-coincidence of the addresses.

The block diagram of the defective pixel detection apparatus which concerns on embodiment. FIG. 3 is a simplified circuit diagram illustrating an example of a circuit constituting the defective pixel detection device according to the embodiment. 5 is a timing chart showing the operation of the defective pixel detection device according to the embodiment. The timing chart which shows operation | movement of the defective pixel detection apparatus which concerns on a comparative example.

Hereinafter, embodiments will be described in detail with reference to the drawings.
(Embodiment)

  FIG. 1 is a configuration diagram of a defective pixel detection apparatus 100 according to the embodiment. The defective pixel detection apparatus 100 includes a detector 101, an AND / OR selection circuit (hereinafter, control circuit) 102, a memory 103, a memory 104, and an output circuit 105. The defective pixel detection device 100 is configured by a single FPGA (field-programmable gate array).

  The detector 101 detects a color signal that exceeds a predetermined threshold from R, G, and B signals (color signals) output from the solid-state imaging device 10. Specifically, the detector 101 compares the value (voltage V) of the R, G, B signal (hereinafter, color signal) of each pixel of the solid-state imaging device 10 with a threshold (reference voltage Vr), and exceeds the threshold. Output things. The solid-state imaging device 10 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, and the number of pixels is 2M (mega).

  The memories 103 and 104 are, for example, RAMs (Random Access Memory), and store pixel addresses corresponding to the color signals detected (output) by the detector 101 in units of screens (frames). The memory 103 (first memory) stores an odd number (odd number) screen address. The memory 104 (second memory) stores an even number screen address.

  The control circuit 102 stores the addresses of pixels corresponding to the color signals detected by the detector 101 among the color signals constituting the screen (frame) output from the solid-state imaging device 10 in the memories 103 and 104. Specifically, the control circuit 102 performs the following operations (1) to (4).

(1) The address of the pixel corresponding to the color signal detected by the detector 101 among the color signals constituting the first screen (frame) output from the solid-state imaging device 10 is stored in the memory 103.
(2) An address stored in the memory 103 and an address of a pixel corresponding to the color signal detected by the detector 101 among the color signals constituting the second screen output from the solid-state imaging device 10 And stored in the memory 104 in accordance with the address match / mismatch.
(3) An address stored in the memory 104 and an address of a pixel corresponding to the color signal detected by the detector 101 among the color signals constituting the third screen output from the solid-state imaging device 10 And stored in the memory 103 in accordance with the address match / mismatch.
(4) For the third and subsequent screens output from the solid-state imaging device 10, the operations (2) and (3) are repeated a predetermined number of times for the color signals constituting each screen.

  When the operation of the control circuit 102 is completed, the output circuit 105 once reads and stores the address of the pixel stored in the memory 103 or 104, and then an external microcomputer (not shown) (hereinafter referred to as a microcomputer) not shown. To output.

  FIG. 2 is a simplified circuit diagram illustrating an example of a circuit constituting the defective pixel detection apparatus 100. The detector 101 shown in FIG. 1 includes three comparators COMP that compare R, G, and B signals with a threshold value Vr, and one OR circuit. The output from the detector 101 is input to a subsequent flip-flop (FF).

  The AND / OR selection circuit 102 in FIG. 1 includes one AND circuit, one OR circuit, and a plurality of switches SW for switching input / output of signals between the AND circuit side and the OR circuit side.

  The memories 103 and 104 in FIG. 1 are RAM (Random Access Memory) provided on the FPGA, and preferably have a large capacity so that the addresses of defective pixels of the solid-state imaging device 10 can be stored at a time. For example, when the number of pixels (pixels) of the solid-state imaging device 10 is 2M (mega), the memories 103 and 104 are preferably capable of storing 120,000 addresses. Each of the memories 103 and 104 is input with an address counter so that the address of the pixel corresponding to the color signal detected by the detector 101 can be known.

  The output circuit 105 in FIG. 1 includes three RAMs (RAM1 to RAM3) for temporarily storing the addresses of pixels detected by first to third detection described later with reference to FIG. A switch SW for switching the storage destination, three counters (counter 1 to counter 3) for counting the number of pixels detected by the first to third detections, and the like. The address of the defective pixel once stored in RAM1 to RAM3 of the output circuit 105 is output to an external microcomputer (not shown) for correcting the defective pixel.

  FIG. 3 is a timing chart showing the operation of the defective pixel detection apparatus 100. Hereinafter, the operation of the defective pixel detection apparatus 100 will be described in more detail with reference to FIG. Scratches (defects) of the solid-state imaging device 10 include those having randomness and those having no randomness (so-called fixed scratches). Moreover, since the value is low, there is a scratch that is hidden by noise.

  In this defective pixel detection apparatus 100, in order to detect a defective pixel more reliably, a defective pixel having a defect is detected by combining the following first to third detection methods. In the first and second detections, scratches and flashing scratches that are independent of the exposure time / temperature are mainly detected, and in the third detection, scratches that are mainly dependent on the exposure time / temperature are detected. .

(First detection)
In the first detection, in order to detect a flaw buried in noise, the threshold value used in the detector 101 is set low (hereinafter, the threshold value used in the first detection is referred to as the first threshold value). However, noise is also detected by setting the threshold value low. For this reason, even normal pixels are detected.

  Thus, in this embodiment, the logical product (AND) of the address stored in the memory 103 or 104 and the address of the pixel corresponding to the color signal newly detected by the detector 101 is obtained. This avoids the problem of detecting up to a pixel.

  Next, the first detection will be described with reference to FIG. FIG. 3A is a timing chart showing the operation of the defective pixel detection apparatus 100 when taking a logical product (AND).

  In the 1st step, the defective pixel detection apparatus 100 detects, with the detector 101, a color signal that exceeds the threshold among the color signals that form the first screen (frame) output from the solid-state imaging device 10. Next, the pixel address corresponding to the color signal detected by the detector 101 is stored in the memory 103.

  In the 2nd step, the defective pixel detection device 100 is a color signal constituting the second screen output from the solid-state imaging device 10, and among the pixels corresponding to the color signal detected by the detector 101, the address is the memory 103. Only those that match the address stored in the memory 104 are stored in the memory 104.

  In the 3rd step, the defective pixel detection apparatus 100 is a color signal constituting the third screen output from the solid-state imaging device 10, and among the pixels corresponding to the color signal detected by the detector 101, the address is the memory 104. Only those that match the address stored in the memory 103 are stored in the memory 103.

  Thereafter, the defective pixel detection apparatus 100 repeats the operation (AND processing) of the 2nd step and the 3rd step for the color signal output from the solid-state imaging device 10 a predetermined number of times (for example, AND processing is performed three times). Thereafter, the defective pixel detection apparatus 100 temporarily saves the address of the pixel stored in the memory 103 or 104 in the RAM 1 (see FIG. 2) in the output circuit 105 and then outputs it to an external microcomputer.

(Second detection)
In the second detection, a threshold used in the detector 101 is set to be high in order to detect a scratch that suddenly occurs on an arbitrary screen (frame) (hereinafter, the threshold used in the second detection is set to the second threshold). Threshold). That is, the second threshold value is higher than the first threshold value. In this second detection, in order to detect a sudden flaw, the logical sum of the address stored in the memory 103 or 104 and the address of the pixel corresponding to the color signal newly detected by the detector 101 is obtained. Take (OR).

  Next, the second detection will be described with reference to FIG. FIG. 3B is a timing chart showing the operation of the defective pixel detection apparatus 100 when taking a logical sum (OR).

  In the 1st step, the defective pixel detection apparatus 100 detects, with the detector 101, a color signal that exceeds the threshold among the color signals that form the first screen (frame) output from the solid-state imaging device 10. Next, the pixel address corresponding to the color signal detected by the detector 101 is stored in the memory 103.

  In the 2nd step, the defective pixel detection apparatus 100 stores the color signal constituting the second screen output from the solid-state imaging device 10 and the pixel address corresponding to the color signal detected by the detector 101 in the memory 103. The stored address is stored in the memory 104.

  In the 3rd step, the defective pixel detection device 100 stores the color signal constituting the third screen output from the solid-state imaging device 10 and the pixel address corresponding to the color signal detected by the detector 101 in the memory 104. The stored address is stored in the memory 103.

  Thereafter, the defective pixel detection apparatus 100 repeats the operation (OR process) of the 2nd step and the 3rd step for the color signal output from the solid-state imaging device 10 a predetermined number of times (for example, OR process is performed 3 times). Thereafter, the defective pixel detection apparatus 100 temporarily saves the address of the pixel stored in the memory 103 or 104 in the RAM 2 (see FIG. 2) in the output circuit 105 and then outputs it to an external microcomputer.

(Third detection)
In the third detection, a defective pixel whose color signal value exceeds a predetermined threshold during long exposure is detected. In the third detection, in the 1st step, the defective pixel detection device 100 detects a color signal that exceeds the threshold among the color signals that form the first screen (frame) output from the solid-state imaging device 10. Detect with.

  Next, the defective pixel detection apparatus 100 temporarily stores the pixel address stored in the memory 103 in the RAM 3 (see FIG. 2) in the output circuit 105, and then outputs it to an external microcomputer.

(Comparative example)
FIG. 4 is a timing chart showing the operation of the defective pixel detection apparatus according to the comparative example. FIG. 4A is a timing chart showing an operation when taking a logical product (AND), and FIG. 4B is a timing chart showing an operation when taking a logical sum (OR).

  As can be seen from FIG. 4, in the defective pixel detection device according to the comparative example, since the memory capacity corresponding to the memories 103 and 104 of the defect detection device 100 according to the embodiment is small, one screen is divided into a plurality of areas. However, the first to third detections described with reference to FIG. 3 are performed for each of the divided areas (for example, 60 divisions).

  For this reason, compared with the defective pixel detection apparatus 100 according to the embodiment having the memories 103 and 104 that can collectively store the addresses of defective pixels for one screen, the number of times the stored addresses are output to an external microcomputer is extremely high. You can see that it is increasing.

  As described above, since the defective pixel detection apparatus 100 includes the memories 103 and 104 that can collectively store the addresses of defective pixels for one screen, the number of times the stored defective pixel addresses are output to an external microcomputer. Can be reduced. For this reason, the time required for detecting a defective pixel can be significantly shortened. For example, the defective pixel detection apparatus 100 according to the present embodiment can be shortened to about 3 seconds for detection of a defective pixel that is required for about 12 seconds in the conventional defective pixel detection apparatus. Further, since the time for detecting defective pixels can be shortened, it is possible to detect defective pixels on the user side, which is conventionally performed on the supplier side. In addition, it is possible to easily deal with a late (after shipment) scratch.

(Other embodiments)
As mentioned above, although several embodiment of this invention was described, the said embodiment is shown as an example and is not intending limiting the range of invention. The above embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the defective pixel detection device 100 has been described by taking a color CMOS (3CMOS) image sensor that outputs R, G, and B signals as an example. However, the CMOS image sensor is not limited to color. Further, defective pixels of a CCD (Charge Coupled Device) image sensor can be detected instead of CMOS.

  DESCRIPTION OF SYMBOLS 100 ... Defect pixel detection apparatus, 101 ... Detector, 102 ... AND / OR selection circuit (control circuit), 103, 104 ... Memory, 105 ... Output circuit.

Claims (14)

A detector for detecting a color signal exceeding a predetermined threshold from the color signal output from the solid-state imaging device;
First and second memories in which pixel addresses corresponding to color signals detected by the detector are stored in units of screens;
Among the color signals constituting the first screen output from the solid-state imaging device, the address of the pixel corresponding to the color signal detected by the detector is stored in the first memory,
An address stored in the first memory and an address of a pixel corresponding to the color signal detected by the detector among the color signals constituting the second screen output from the solid-state imaging device. A control circuit for storing in the second memory according to the coincidence / non-coincidence of the address;
A defective pixel detection apparatus comprising: The control circuit includes:
Of the address stored in the first memory and the color signal constituting the second screen output from the solid-state imaging device, the pixel address corresponding to the color signal detected by the detector, The defective pixel detection device according to claim 1, wherein an address of a pixel having a matching address is stored in the second memory. The control circuit includes:
The address stored in the first memory and the address of the pixel corresponding to the color signal detected by the detector in the color signal constituting the second screen output from the solid-state imaging device The defective pixel detection apparatus according to claim 1, wherein the defective pixel detection apparatus is stored in a second memory. The control circuit includes:
An address stored in the second memory and an address of a pixel corresponding to the color signal detected by the detector among the color signals constituting the third screen output from the solid-state imaging device. The defective pixel detection device according to claim 1, wherein the defective pixel detection device stores the address in the first memory in accordance with a match / mismatch of the addresses. The control circuit includes:
Of the address stored in the second memory and the color signal constituting the third screen output from the solid-state imaging device, the pixel address corresponding to the color signal detected by the detector, The defective pixel detection device according to claim 4, wherein an address of a pixel having a matching address is stored in the first memory. The control circuit includes:
The address stored in the second memory and the color signal constituting the third screen output from the solid-state image sensor, and the address of the pixel corresponding to the color signal detected by the detector The defective pixel detection apparatus according to claim 4, wherein the defective pixel detection apparatus is stored in a first memory. The control circuit includes:
Concerning the color signals constituting the third and subsequent screens output from the solid-state image sensor, the address stored in the first or second memory and the screen output from the solid-state image sensor are configured. The operation of repeatedly storing an address of a pixel corresponding to the color signal detected by the detector in the second or first memory according to the coincidence / mismatch of the address among the color signals to be performed is performed. 5. The defective pixel detection device according to 4. A detector for detecting a color signal exceeding a predetermined threshold from color signals output from the solid-state imaging device, first and second memories for storing addresses of pixels corresponding to the color signal, and the first A defective pixel detection method by a defective pixel detection device comprising: a control circuit for storing the address in a second memory;
A first step in which the detector detects a color signal exceeding a predetermined threshold value from a color signal constituting a first screen output from the solid-state imaging device;
A second step in which the control circuit stores an address of a pixel corresponding to the color signal detected in the first step in a first memory;
A third step in which the detector detects a color signal exceeding a predetermined threshold value from the color signal constituting the second screen output from the solid-state imaging device;
The control circuit uses the address stored in the first memory and the address of the pixel corresponding to the color signal detected by the detector in the third step according to the match / mismatch of the address. And a fourth step of storing in the second memory,
A defective pixel detection method comprising: In the fourth step, the control circuit includes:
Of the address stored in the first memory and the address of the pixel corresponding to the color signal detected by the detector in the third step, the address of the pixel that matches the address is the second memory. The defective pixel detection method according to claim 8 , wherein the defective pixel detection method is stored. In the fourth step, the control circuit includes:
The address stored in the first memory, according to claim 8 which stores the address of the pixel in the second memory corresponding to the third color signal detected by said detector in step Defective pixel detection method. A fifth step in which the detector detects a color signal exceeding a predetermined threshold value from the color signal constituting the third screen output from the solid-state imaging device;
The control circuit uses the address stored in the second memory and the address of the pixel corresponding to the color signal detected by the detector in the fifth step according to the coincidence / mismatch of the address. A sixth step of storing in the first memory;
The defective pixel detection method according to claim 8 , comprising: The control circuit comprises:
Of the address stored in the second memory and the address of the pixel corresponding to the color signal detected by the detector in the fifth step, the address of the pixel that matches the address is the first memory. The defective pixel detection method according to claim 11 , wherein the defective pixel detection method is stored. The control circuit comprises:
And address stored in said second memory, according to claim 11 which stores the address of the pixel in the first memory corresponding to the fifth color signal detected by said detector in step Defective pixel detection method. The detector and the control circuit are:
The defective pixel detection method according to claim 11 , wherein the third to sixth steps are repeated for a color signal constituting a screen output from the solid-state imaging device.

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