JP5879235B2 - Method, apparatus and program for parallel verification of semi-structured messages - Google Patents

Description

  The present invention provides a computing device having a large number of cores for establishing / disabling constraints on mutual relations between tags and / or contents in semi-structured messages described in a format such as XML or JSON (java script object notation). The present invention relates to a method, an apparatus, and a program for using and verifying in parallel.

  Fixed-length telegrams have been used for electronic transactions between companies, linkages between systems, and the like, but nowadays semi-structured telegrams written in a format such as XML or JSON have become widespread. Semi-structured messages can be described with meanings and structures by tags, so they are more readable and extensible than fixed-length messages. On the other hand, semi-structured messages are large in size and complex in structure. For this reason, verification of semi-structured messages against restrictions is a heavy burden on the computer.

  For example, XML Schema (Non-patent Document 1) is used to describe the verification contents for an XML message. In XML Schema, it is possible to describe restrictions (variable types and regular expressions) on tag names and contents used in XML messages.

  Against this background, analysis of tag structures of semi-structured messages and verification of constraints are performed in parallel using a number of core processors (arithmetic units) (hereinafter simply referred to as “cores”) of CPUs and GPUs. Attempts have been made. For example, in Non-Patent Document 3, identification of tags and contents specified by a plurality of XPaths is processed in parallel by assigning each XPath to each core. Non-Patent Document 4 creates an index for searching or searching for tags in parallel by assigning only one tag name to each core. Further, Non-Patent Document 5 describes a parallel processing method for regular expression matching necessary for verification of the format of content in a semi-structured electronic message.

H. S. Thompson, D. Beech, M. Maloney, and N. Mendelsohn, “XML Schema Part 1: Structures Second Edition”, W3C Recommendation 28 October 2004 ISO 20022, Payments Initiation-Maintenance 2012, Message Definition Report, Edition June 2012 R. Moussalli, R. Halstead, M. Salloum, W. Najjar, and V. J. Tsotras, “Efficient XML Path Filtering Using GPUs”, In Proceeding of ADMS, 2011 Norihiro Muto, Masaharu Hamada, Shohei Yokoyama, Naoki Fukuda, Hiroshi Ishikawa: XML Index Generation and Search Method Suitable for Parallel Processing of GPU and CPU, 4th Forum on Data Engineering and Information Management, 2012 L. David and S. Sagi, “30x faster regular expression on a GPU”, Nvidia GPU Technology Conference, 2012 J. I. Munro and V. Raman, “Succinct Representation of Balanced Parentheses and Static Trees”, SIAM Journal on Computing, 31 (3): 762-776, 2001

  However, in certain industries, there are cases in which restrictions that cannot be described in XML Schema are defined for XML messages. For example, in ISO20022 that defines a financial settlement message, various restrictions are defined according to the settlement method (see Non-Patent Document 2).

  FIG. 1 shows an example of a CusutomerCreditTransferInitiation XML message for a remittance instruction defined in ISO20022. However, in order to simplify the description, a part of the message is omitted in FIG. In the example of FIG. 1, ABC Corporation instructs DEF Electronics to remit 10 million yen and GHI Semiconductors to remit 500,000 euros.

  For this CustomerCreditTransferInitiation message, ISO20022 defines the following rules (constraints).

R4 PaymentTypeInformationRule
If PaymentTypeInformation is present, then CreditTransferTransactionInformation / PaymentTypeInformation is not allowed.
On Condition
/ PaymentTypeInformation is present
Following Must be True
/ CreditTransferTransactionInformation [*] / PaymentTypeInformation Must be absent

  This R4 PyamentTypeInformationRule is an example of a specified rule (constraint). If <CstmrCdtTrfInitn> <Pmtiinf> (<PmtInf> is a tag name corresponding to PaymentTypeInformation) exists in the XML message of FIG. 1, <CstmrCdtTrfInitn > <CdtTrfTxInf> <PmtInf> (<CdtTrfTxInf> is a tag name corresponding to CreditTransferTransactionInformation) should not exist. Such constraints on the interrelationship between tags cannot be described by XML Schema.

In order to efficiently verify such constraints on the interrelationship between tags and / or contents using a large number of cores, there are the following technical problems.
(1) Constraint Description Method In the first place, there is a problem of how to describe a constraint related to a mutual relationship between tags and / or contents that cannot be described in XML Schema.
(2) About fast identification of tag structure With the method described in Non-Patent Literature 3, the number of tag names described in the schema is limited with the number of designated XPaths, and with the method described in Non-Patent Literature 4. Until then, processing can be parallelized. Currently commercially available GPUs have thousands of cores, but the prior art can only achieve tens to hundreds of parallelism, and does not sufficiently bring out the performance of the GPU.
(3) High-speed search for tags used for constraint verification In the conventional method, when the relative position between two tags (Parent / Children, Anchors, etc.) is specified, the two tags are efficiently used. Cannot be acquired.

  As described above, the conventional semi-structured electronic message verification technology using a large number of cores has a technical problem that it is not possible to efficiently verify the establishment / non-establishment of restrictions on the mutual relationship between tags and / or contents.

  Therefore, the present inventor provides a mechanism for executing verification processing of constraints on the mutual relation between tags and / or contents in a semi-structured message in parallel using as many cores as possible.

  Specifically, before receiving the semi-structured electronic message to be verified, the first arithmetic device (for example, CPU) excellent in sequence processing acquires the tag name from the schema of the semi-structured electronic message (i) A program for generating a tag name finite automaton for column matching, and (ii) executing a semi-structured message verification in parallel using a second arithmetic unit (for example, GPU) excellent in parallel processing Is generated based on the verification file describing the constraints.

  Next, when the semi-structured electronic message is received, the first arithmetic unit generates a tree structure of the tag structure together with an array for specifying the tag position in the semi-structured electronic message as preprocessing.

  After that, each core processor constituting the second arithmetic unit described above identifies a tag name based on a finite automaton through parallel execution of a program created in advance, and creates a tree structure of the tag structure created in advance. Provided is a mechanism for acquiring a tag and / or content that is a target of verification of constraints on mutual relations between tags and / or content and verifying a semi-structured electronic message based on the acquired tag and / or content.

  Here, the verification file includes a Let clause that specifies a tag and / or content to be verified, an Ever clause that specifies whether all tags and / or content to be verified satisfy a constraint, a tag that satisfies the constraint, and / or Alternatively, it is desirable that the content is described in a Some clause that specifies whether content exists or a Satify clause that specifies constraints to be satisfied.

According to the present invention, for example, at least one of the following effects can be realized.
(1) By providing a verification file that describes restrictions on the interrelationship between tags and / or contents that cannot be described in XML Schema, as a result, correlated restrictions can be described.
(2) In the pre-processing by the first arithmetic device, by specifying the tag position of the semi-structured message in advance, each core constituting the second arithmetic device can match the character string of the tag name from the tag position. It can be performed. For this reason, processing can be parallelized by the number of tags. As a result, it is possible to analyze a semi-structured electronic message faster than the conventional method.
(3) In the pre-processing by the first arithmetic unit, an array for identifying the tag position of the semi-structured message and a tree structure of the tag structure are generated and compressed using a simple data structure, so that the tag structure of the semi-structured message is Information can be stored in the local memory of a number of cores comprising the second arithmetic unit. Thereby, the 2nd arithmetic unit can acquire a tag and / or content required in order to verify the restriction | limiting of a semi-structure message | telegram at high speed.

  As described above, according to the present invention, it is possible to efficiently verify the constraints related to the interrelationship between the tags and / or the contents by using many cores. Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

The figure which shows a semi-structure electronic message example. The figure which shows the system configuration | structure of a semi-structure message verification system. The figure which shows the structural example of a semi-structure message verification computer. The figure which shows the example of a verification file. An example of data secured in the RAM in the GPU. The flowchart which shows the whole outline | summary of semi-structure message verification. The flowchart of the initialization process of semi-structure message verification. The figure explaining the data structure production | generation process of the finite automaton of a tag name. The flowchart of the pre-process of semi-structure message verification. The figure explaining the production | generation process of the tag structure of a semi-structure message. The flowchart of a semi-structure message verification process.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the contents of the apparatus configuration and processing operation described later are examples for explaining the invention. The present invention provides an arbitrary combination of device configurations and processing operations described later, a combination of adding a known technology to the device configuration and processing operations described later, and replacing a part of the device configuration and processing operations described later with known technologies. Combinations to include are also included.

(1) Configuration of Semi-Structured Message Verification System FIG. 2 shows a configuration example of a semi-structured message verification system in which the semi-structured message verification computer 120 is installed. The semi-structured message verification system shown in FIG. 2 includes (1) a client computer 100 that generates a semi-structured message 140 such as a settlement, (2) an Internet 110 that transfers the generated semi-structured message 140, and (3) a number of cores. A semi-structured message verification computer 120 that verifies the received semi-structured message 140 using the CPU or GPU, and (4) a semi-structured message management computer 130 that receives the verification result of the semi-structured message 140; Consists of. The semi-structured telegram 140 in this embodiment is assumed to be an XML telegram (FIG. 1) of CusutomerCreditTransferInitiation of a remittance instruction prescribed by ISO20022.

  FIG. 3 shows a configuration example of the semi-structured electronic statement verification computer 120. The semi-structured electronic statement verification computer 120 includes a computer main body 300, an input device 330, a display device 331, and a communication device 332. Note that the communication device 332 communicates directly with the semi-structured message management computer 130 and communicates with the client computer 100 via the Internet 110.

  The computer main body 300 combines a CPU 301, a ROM 302, a CPU_RAM 310, a hard disk drive 320, a GPU 340 having a number of core processors (PU 341), a CPU bus 308 for realizing data transfer between these devices, and these devices and the CPU bus 308. Interfaces 303 to 307 are configured.

  Here, the CPU 301 is an arithmetic device that has both high operating frequency and high core processing capability and is excellent in sequence processing. On the other hand, the GPU 340 has a large number of cores although the operating frequency and the processing capacity of the core are lower than those of the CPU 301, and is an arithmetic unit excellent in parallel processing.

  In the CPU_RAM 310, at least an execution area for the semi-structured electronic statement verification program 311 executed by the CPU 301 and a work area 312 for storing data temporarily generated at the time of calculation are secured.

  In the storage area of the hard disk drive 320, at least a program storage unit 321 and a data storage unit 322 are secured. Among these, the program storage unit 321 stores a semi-structured message verification program 311 executed by the CPU 301 and a parallel semi-structured message verification program 351 executed by the GPU 340. The data storage unit 322 temporarily stores a schema such as XML Schema of the semi-structured message to be verified, a verification file describing restrictions on the mutual relationship between tags and / or contents, and the semi-structured message 140 received from the client computer 100. Stored. The schema and the verification file are given from an external computer (not shown), for example.

  FIG. 4 shows an example of a verification file describing the above-described PaymentTypeInformationRule. The verification file includes a Let clause 401 that specifies a tag and / or content to be verified by XPath and the like, and whether all of the tags and / or contents specified in the Let clause 401 satisfy the condition (Every). It comprises an Every / Some clause 402 that specifies whether something exists (Some), and a Satify clause 403 that specifies a condition to be satisfied.

  In this example of the verification file, the PmtInf tag and the CdtTrfTxInf / PmtInf tag specified by the Let clause 401 are acquired, and if the PmtInf tag exists, it is verified whether the condition that no CdTrfIxInf / PmtInf tag exists is satisfied. Is meant to do.

  The GPU 340 realizes data transfer between these devices by tens to thousands of arithmetic units PU 341 for executing data operations, GPU_GLOBAL_RAM 350 accessible from all PUs 341, GPU_LOCAL_RAM 360 accessible only from nearby PUs 341. It consists of a GPU bus 342. Here, the data transfer rate between the PU 341 and the GPU_LOCAL_RAM 360 is much higher than the data transfer rate between the PU 341 and the GPU_GLOBAL_RAM 350. However, the size of the GPU_LOCAL_RAM 360 is about several tens of KB, which is very small compared to the size (several GB) of the GPU_GLOBAL_RAM 350.

  In the GPU_GLOBAL_RAM 350, a parallel semi-structured electronic message verification program 351 that causes the PU 341 to perform arithmetic processing and a work area 352 that stores data temporarily generated during the arithmetic operation are secured. The GPU_LOCAL_RAM 360 has a work area 361 for storing data temporarily generated when the PU 341 is operated.

  FIG. 5 shows an example of a data area created at least in the work area of the GPU_GLOBAL_RAM 350 and the GPU_LOCAL_RAM 360. In the work area 352 of the GPU_GLOBAL_RAM 350, a character array 501 corresponding to each node of the finite automaton of the tag name and a tag ID array 502 corresponding to the finite automaton of the tag name are used to specify the tag name of the semi-structured message by character string matching. , Semi-structured message 503 in which unnecessary characters are deleted while maintaining structure of semi-structured message 140, tag position array 504 in semi-structured message, tag ID array 505 in semi-structured message, and individual verification results are held An array 506 of verification results is obtained.

  In the work area 361 of the GPU_LOCAL_RAM 360, the structure of the finite automaton and the semistructured telegram 140 for tag name character string matching uses a concise data structure, and the BP representation 511 of the finite automaton of the tag name and the tags in the semistructured telegram Holds a BP representation 512 of the structure. Here, the simple data structure is used in order to hold a large amount of structure with a small memory capacity of the GPU_LOCAL_RAM 360. In this embodiment, BP representation (see Non-Patent Document 6) is used as a concise data structure, but other concise data structures may be used.

(2) Semi-Structured Message Verification Operation FIG. 6 shows an outline of a semi-structured message verification process executed in the entire semi-structured message verification system.

(Step 600)
The semi-structured message verification computer 120 executes the semi-structured message verification program 311 when the power is turned on.

(Step 601)
The semi-structured electronic statement verification computer 120 uses the CPU 301 to acquire the semi-structured electronic message schema and verification file stored in the data storage unit 322 of the hard disk drive 320 and store them in the work area 312 of the CPU_RAM 310.

  Here, the CPU 301 generates a finite automaton for matching the character string of the tag name from the schema, and also generates a parallel semi-structured electronic message verification program for causing the GPU 340 to execute verification processing in parallel from the verification file. The generated finite automaton is transferred to the GPU_GLOBAL_RAM work area 352 and the GPU_LOCAL_RAM work area 361 of the GPU 340. Further, the generated parallel semi-structured message verification program is transferred to the parallel semi-structured message verification program 351 of the GPU_GLOBAL_RAM 350. Details of the processing contents of this program will be described later.

(Step 602)
When the semi-structured electronic text verification computer 120 receives the semi-structured electronic text 140 transmitted from the client computer 100 via the communication device 332, the semi-structured electronic text verification computer 120 stores it in the work area 312 of the CPU_RAM 310.

(Step 603)
The semi-structured message verification computer 120 executes pre-processing necessary for verification such as deletion of unnecessary characters and generation of a tag structure for the semi-structured message 140 received via the communication device 332. At this time, the semi-structured electronic text verification computer 120 transfers the semi-structured electronic text and the tag structure data from which unnecessary characters generated in the preprocessing are deleted to the GPU_GLOBAL_RAM work area 352 and the GPU_LOCAL_RAM work area 361 in the GPU 340. Details of these preprocessing will also be described later.

(Step 604)
The semi-structured electronic statement verification computer 120 executes the parallel semi-structured electronic message verification program 351 by using a large number of PUs 341 of the GPU 340, and verifies the contents described in the verification file with respect to the semi-structured electronic message. Details of this parallel verification processing will be described later.

(Step 605)
The semi-structured electronic statement verification computer 120 notifies the verification result obtained in step 604 to the semi-structured electronic statement management computer 130 via the communication device 332.

(3) Details of Initialization Process Details of the initialization process 601 in FIG. 6 will be described with reference to FIG.

(Step 701)
The semi-structured message verification computer 120 acquires the schema of the semi-structured message 140 from the data storage unit 322 of the hard disk drive 320, and creates a finite automaton for matching the tag name with the character string via the CPU 301.

  FIG. 8 is a diagram illustrating a procedure for generating a finite automaton having a data structure suitable for processing in the GPU 340 from the schema. First, the CPU 301 extracts a tag name 801 from the schema. Here, three tag names “AB, BC, ACD” are obtained. Next, the CPU 301 creates a finite automaton 802 from these three tag names. The leaf End of the finite automaton 802 means that a character other than the alphabet comes.

  A tree structure of the finite automaton 802 for matching the character string of the tag name is represented by 803 in BP expression. In the BP expression 803, a bit string in which “(” is replaced with bit 0 and “)” is replaced with bit 1 is referred to as “a BP expression 511 of a finite automaton of a tag name”. At this time, the character array of each node of the finite automaton 802 created according to the order of the nodes corresponding to the bit string of the BP representation 511 of the finite automaton of the tag name is referred to as “character array 501 corresponding to the finite automaton of the tag name”. . Further, according to the order of the nodes corresponding to the bit string of the BP representation 511 of the finite automaton of the tag name, the tag ID is stored at the position of the (End) node in the “tag ID array 502 corresponding to the finite automaton of the tag name”. Is generated.

  Thus, by representing the structure of the finite automaton 802 of the tag name in BP expression, it becomes possible to store the semi-structured message in the work area 361 of the GPU_LOCAL_RAM 360 having a small memory capacity, and each PU 341 can store the tag name at high speed. String matching can be performed.

(Step 702)
The semi-structured electronic statement verification computer 120 acquires a verification file stored in the data storage unit 322 of the hard disk drive 320, and performs parallel semi-structured electronic statement verification program for verifying in parallel with a large number of PUs 341 of the GPU 340 via the CPU 301. Create The contents of the parallel semi-structured message verification program will be described later.

(Step 703)
The semi-structured electronic statement verification computer 120 stores the finite automaton data of the tag name created in step 701 through the CPU 301 in the work area of the GPU_GLOBAL_RAM 350 and the GPU_LOCAL_RAM 360 according to FIG. In addition, the semi-structured electronic message verification computer 120 stores the parallel semi-structured electronic message verification program 351 created in step 702 in the data area of the GPU_GLOBAL_RAM 350 through the CPU 301.

(4) Details of Semi-Structured Message Verification Pre-Processing Process Details of the semi-structured message verification pre-processing process 603 of FIG. 6 will be described with reference to FIG.

(Step 901)
The semi-structured electronic text verification computer 120 uses the CPU 301 to delete unnecessary characters such as tabs, spaces, and line feeds from the received semi-structured electronic text 140 stored in the work area 312 of the CPU_RAM. This is because, in order to avoid erroneous matching when performing character string matching of tag names in the processing described later, and in step 903 described later, the semi-structured telegram 140 in the work area 312 of the CPU_RAM is changed to the work area 352 of the GPU_GLOBAL_RAM. This is because the transfer amount is reduced and the memory size used in the work area 352 of the GPU_GLOBAL_RAM is reduced.

  FIG. 10 shows an example in which unnecessary characters are deleted. Tabs, spaces, and line feed characters are deleted from the received semistructured message 140, and a semistructured message 503 from which unnecessary characters are deleted is generated.

(Step 902)
The semi-structured electronic text verification computer 120 uses the CPU 301 to generate a tag structure from the semi-structured electronic text 503 from which unnecessary characters created in step 901 are deleted.

  FIG. 10 shows a specific example of generating a tag structure. The semi-structured message verification computer 120 replaces “<” with bit 0, “</” and “/>” with bit 1 in the semi-structured message 503 from which unnecessary characters are deleted, and ignores other characters. (BP expression 512 of the tag structure in the semi-structured message) is generated. The semi-structured electronic statement verification computer 120 also generates an array of tag name positions corresponding to “<”, “</”, and “/>” (an array of tag positions 504 in the semi-structured electronic message) at the same time. However, “<”, “</”, and “/>” are simply replaced with bits, and the tag name itself is not specified.

  In this way, by identifying the tag structure and position via the CPU 301, which is good at sequential processing as preprocessing, parallel verification can be efficiently performed via a large number of PUs 341 in later processing. . By specifying the position of the tag name, it is possible to avoid that each PU 341 starts character string matching from a position unrelated to the tag name. By specifying a tag structure that is difficult to construct in parallel processing, it is possible to easily find a parent node and a child node necessary for verification. In particular, by using a simple data structure for the tag structure and storing it in an area with a small memory capacity of the GPU_LOCAL_RAM 360, it is possible to search for a parent node and a child node at high speed.

(Step 903)
The semi-structured electronic text verification computer 120 transfers the semi-structured electronic text 503 from which unnecessary characters generated in Step 901 are deleted to the work area 352 of the GPU_GLOBAL_RAM. Furthermore, the semi-structured electronic statement verification computer 120 uses the tag structure BP representation 512 in the semi-structured electronic message generated in step 902 as the GPU_LOCAL_RAM work area 361, and the tag position array 504 in the semi-structured electronic message as the GPU_GLLOB_RAM work area. Stored in 352.

(5) Details of Semi-Structured Message Verification Process Details of the semi-structured message verification process 604 in FIG. 6 will be described with reference to FIG. First, the semi-structured electronic statement verification computer 120 causes each PU 341 to execute the parallel semi-structured electronic statement verification program 351 of the GPU_GLOBAL_RAM 350. Hereinafter, the processing of each PU 341 will be described.

(Step 1101)
The semi-structured electronic statement verification computer 120 acquires a thread ID in which each PU 341 is uniquely assigned to itself in order.

(Step 1102)
In the semi-structured electronic statement verification computer 120, each PU 341 acquires the tag position corresponding to the thread ID acquired in Step 1101 from the tag position array 504 in the semi-structured electronic message stored in the work area 352 of the GPU_GLOBAL_RAM.

(Step 1103)
The semi-structured electronic statement verification computer 120 causes each PU 341 to perform tag character string matching. Each PU 341 uses the tag position acquired in step 1102 as a starting point, performs a tag name character string matching with reference to the BP representation 511 of the finite automaton of the tag name and the character array 501 corresponding to the finite automaton of the tag name, and tag Specify a name. Further, based on the tag name specified by the finite automaton, the semi-structured electronic statement verification computer 120 obtains a tag ID from the tag ID array 502 corresponding to the finite automaton of the tag name. Also, the semi-structured electronic message verification computer 120 refers to the BP expression 512 of the tag structure in the semi-structured electronic message, and when the bit corresponding to the thread ID number is 0, the code of the acquired tag ID is set to “+”. If the bit is 1, the sign of the tag ID is set to “-”, and this signed tag ID is stored at the position corresponding to the thread ID number in the tag ID array 505 in the semi-structured message.

(Step 1104)
The semi-structured electronic message verification computer 120 synchronizes each PU 341.

(Step 1105)
The semi-structured message verification computer 120 uses the PU 341 to obtain the sum of the array of tag IDs 505 in the semi-structured message. If the sum is 0, it can be seen that the start tag and the end tag correspond to each other.

(Step 1106)
The semi-structured message verification computer 120 acquires the tag and / or content specified by the Let clause 401 of the verification file from the semi-structured message 503 from which unnecessary characters are deleted by each PU 341.

  Here, the case of the verification file illustrated in FIG. 4 is considered. Each PU 341 acquires the value of its own thread ID number from the tag ID array 505 in the semi-structured message. When the acquired value matches the tag ID of PmtInf, each PU 341 acquires the tag ID of the parent node using the BP expression 512 of the tag structure in the semi-structured electronic message. If the tag ID of the parent node matches the tag ID of “document”, each PU 341 exists at the position of the number corresponding to the thread ID in the array of the variable $ a secured in the work area 352 of GPU_GLOBAL_RAM. Set bit 1 to mean If the tag ID of the parent node matches the tag ID of “CdtTrfTxInf”, each PU 341 exists at the position of the number corresponding to the thread ID of PU 341 in the array of the variable $ b secured in the work area 352 of GPU_GLOBAL_RAM. Bit 1 is set to mean this.

(Step 1107)
The semi-structured electronic message verification computer 120 synchronizes each PU 341.

(Step 1108)
The semi-structured electronic text verification computer 120 evaluates the Satify phrase 403 of the verification file using each PU 341 obtained in step 1106. The semi-structured electronic statement verification computer 120 stores bit 1 when the evaluation result is True and bit 0 when the evaluation result is False at the position of the thread ID number in the verification result array 506.

(Step 1109)
The semi-structured electronic message verification computer 120 synchronizes each PU 341.

(Step 1110)
The semi-structured electronic message verification computer 120 uses the PU 341 to tabulate the verification result array 506, and then summarizes the verification results and transfers the results to the work area 312 of the CPU_RAM. In the verification file's Every / Some clause 402, when “Every” is specified, the verification result array 506 is all bits 1 (True), and when “Some” is specified, it is stored in the verification result array 506. If bit 1 (True) is present, the semi-structured telegram 140 satisfies the constraint specified in the verification file.

(6) Effects of the embodiment
(i) According to the present embodiment, the Let clause 401 for designating a tag and / or content to be verified, and the Ever clause / constraint for designating whether all tags and / or content to be verified satisfy the constraints. It is possible to provide a verification file that can describe a Some clause 402 that specifies whether a tag and / or content to be satisfied and a Satify clause 403 that specifies a constraint to be satisfied are described. As a result, it is possible to describe constraints on the interrelationship between tags and / or content.
(ii) In the semi-structured electronic statement verification computer 120 according to the present embodiment, by specifying the tag position of the semi-structured electronic message in advance in the preprocessing by the CPU 301, each PU 341 constituting the GPU 340 Name string matching can be performed. For this reason, processing can be parallelized by the number of tags. As a result, it is possible to analyze a semi-structured electronic message faster than the conventional method.
(iii) In the semi-structured message verification computer 120 according to the present embodiment, the pre-processing by the CPU 301 specifies the tag structure of the semi-structured message in advance, and further compresses the tag structure using the simple data structure, thereby configuring the GPU 340 By storing them in the local memory of a large number of PUs 341, it is possible to acquire tags and / or contents for verifying constraints related to the correlation at high speed.

  As described above, according to the semi-structured electronic statement verification computer 120 according to the present embodiment, it is possible to efficiently verify the restrictions on the interrelationship between the tags and / or the contents by using a large number of PUs 341.

  In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Moreover, it is also possible to add, delete, or replace a part of the embodiment with another configuration. For example, the semi-structured message verification computer 120 and the semi-structured message management computer 130 may be formed on the same computer.

  Moreover, you may implement | achieve some or all of each structure, a function, a process part, a process means, etc. which were mentioned above as an integrated circuit or other hardware, for example. Each of the above-described configurations, functions, and the like may be realized by the processor interpreting and executing a program that realizes each function. That is, it may be realized as software. Information such as programs, tables, and files for realizing each function can be stored in a memory, a hard disk, a storage device such as an SSD (Solid State Drive), or a storage medium such as an IC card, an SD card, or a DVD.

  Control lines and information lines indicate what is considered necessary for the description, and do not represent all control lines and information lines necessary for the product. In practice, it can be considered that almost all components are connected to each other.

DESCRIPTION OF SYMBOLS 100 ... Client computer 110 ... Internet 120 ... Semi-structure message verification computer 130 ... Semi-structure message management computer 301 ... CPU
340 ... GPU
350 ... GPU_GLOBAL_RAM
360 ... GPU_LOCAL_RAM

Claims (5)

A first processing unit that executes sequence processing , obtains a tag name from the schema of the semi-structured message, and generates a tag name finite automaton for character string matching;
A program for causing a second arithmetic device that executes parallel processing to execute verification processing of a semi-structured message in parallel, the first arithmetic device describes restrictions on the interrelationship between tags and / or contents A second process generated based on the verification file;
The first processing unit that has received the semi-structured message generates, as pre-processing, a third process for generating an array for specifying the tag position in the semi-structured message and an array for specifying the tag structure of the semi-structured message;
Each core processor constituting the second arithmetic unit specifies a tag name based on the finite automaton through parallel execution of the program, and uses tags and / or content between the tags using an array that specifies the tag structure. A fourth process of acquiring a tag and / or content subject to verification of constraints relating to interrelationships from a semi-structured message, and verifying the semi-structured message based on the acquired tag and / or content;
A parallel verification method for semi-structured electronic statements, wherein the first arithmetic unit includes a fifth process for outputting the verification result. In the parallel verification method of the semi-structure message according to claim 1,
The core processor compresses the array that specifies the finite automaton generated in the first process and the tag structure generated in the third process using a concise data representation, and the core processor A parallel verification method for semi-structured messages, which is stored in a local memory adjacent to the. In the parallel verification method of the semi-structure message according to claim 1,
The verification file includes a Let clause that specifies a tag and / or content to be verified, and an Every / Some clause that specifies whether all of the target tags and / or content satisfy a condition or satisfy a condition. And a Satify clause that specifies a condition to be satisfied. In the first arithmetic unit that executes the sequence processing that constitutes the computer,
A first process for obtaining a tag name from the schema of the semi-structured message and generating a finite automaton of the tag name for character string matching;
A program for causing a second computing device that executes parallel processing to execute verification processing of a semi-structured message in parallel in a computer, in a verification file that describes restrictions on the mutual relationship between tags and / or contents A second process to be generated based on:
When a semi-structured message is received, as pre-processing, an array for specifying the tag position in the semi-structured message and a third process for generating an array for specifying the tag structure of the semi-structured message are executed,
For each core processor constituting the second arithmetic unit,
Processing for specifying a tag name based on the finite automaton through parallel execution of the program, a tag and / or a target of verification of constraints on a mutual relationship between tags and / or contents using an array for specifying the tag structure Alternatively, a process for acquiring content from the semi-structured message, a fourth process for verifying the semi-structured message based on the acquired tag and / or content,
In the first arithmetic unit,
A program for executing a fifth process for outputting the result of the verification. A first processing unit that executes sequence processing , obtains a tag name from the schema of the semi-structured electronic message, and generates a tag name finite automaton for character string matching;
A program for causing a second arithmetic device that executes parallel processing to execute verification processing of a semi-structured message in parallel, the first arithmetic device describes restrictions on the interrelationship between tags and / or contents A second processing unit that generates based on the verification file;
The first processing unit that has received the semi-structured message generates, as preprocessing, a third processing unit that generates an array for specifying the tag position in the semi-structured message and an array for specifying the tag structure of the semi-structured message;
Each core processor constituting the second arithmetic unit specifies a tag name based on the finite automaton through parallel execution of the program, and uses tags and / or content between the tags using an array that specifies the tag structure. A fourth processing unit that acquires a tag and / or content subject to verification of a constraint on a mutual relationship from a semi-structured message, and verifies the semi-structured message based on the acquired tag and / or content;
The parallel verification device for a semi-structured electronic statement, wherein the first arithmetic device includes a fifth processing unit that outputs the verification result.

Images