JP5869968B2 - Decoding device - Google Patents

Description

  The present disclosure relates to a decoding apparatus suitable for error correction of a signal generated in a communication transmission line.

  In information communication, it is required to increase the data transfer rate. For this reason, a decoding process corresponding to high-speed transmission is required.

  As a conventional example for performing decoding processing corresponding to high-speed transmission, for example, Patent Document 1 discloses a method (partial parallel decoding method) in which decoding processing is partially parallelized.

JP 2007-110265 A

  The present inventors have studied a decoding device that performs a decoding process corresponding to high-speed transmission. However, even if the conventional parallel processing method is used, it has been difficult to obtain a decoding processing result sufficiently corresponding to high-speed transmission.

  Therefore, in order to solve the above-described problem, the present disclosure provides a decoding device that can further improve the processing capability of decoding processing corresponding to high-speed transmission.

  The present disclosure uses a storage unit that stores a plurality of likelihoods obtained by demodulating a received packet and a partial check matrix obtained by dividing a check matrix used for decoding, and a decoding core that performs decoding processing in parallel for each likelihood. A decoding device having a plurality of decoding units, wherein the partial parity check matrix is a matrix whose number of rows is equal to or greater than the number of columns.

  According to the present disclosure, a decoding device capable of high-speed decoding processing can be realized.

The block diagram which shows the structure of the decoding apparatus which concerns on 1st Embodiment. Timing chart showing timing of decoding processing in the first embodiment The figure which shows the example of the test matrix divided | segmented into the processing unit of partial parallel decoding Timing chart showing the timing of column processing and row processing in partial parallel decoding Schematic showing the whole process of decoding by partial parallel decoding Timing chart showing the case of doubling the number of parallel operations for column processing in partial parallel decoding The block diagram which shows the structure of the decoding apparatus which concerns on 2nd Embodiment. Timing chart showing timing of decoding processing in the second embodiment The block diagram which shows the structure of the decoding apparatus which concerns on 3rd Embodiment. Timing chart showing timing of decoding processing in the third embodiment The block diagram which shows the structure of the decoding apparatus which concerns on 4th Embodiment. The figure which shows an example of the relationship between propagation path environment and MCS according to user orientation The sequence diagram which shows the handshake procedure at the time of the communication initialization in 4th Embodiment

<Background to this disclosure>
In information communication, advancement of communication functions such as an increase in data transfer speed has been promoted. For example, in the wireless communication field represented by a wireless local area network (LAN) and mobile communication, demand for high-speed wireless communication has been increasing in recent years. For example, “IEEE802.11ad” is being standardized as a high-speed wireless communication standard. In order to cope with an increase in communication speed, high-speed decoding processing is required also in error correction decoding.

IEEE 802.11ad employs an LDPC code (Low Density Parity Check Code) as a code for correcting a signal error in a radio propagation path as a transmission path. The LDPC code has an advantage that it is relatively easy to mount a high-speed decoding device as compared with the turbo code.

  Here, one method for further improving the communication speed is to increase the number of modulation levels of transmission data.

For example, the modulation method is changed from BPSK (Binary Phase Shift Keying, multi-value number = 1) to QP.
When changed to SK (Quadrature Phase Shift Keying, multi-value number = 2), the LDPC decoding apparatus is required to have a processing capacity that is double as the modulation multi-value number increases.

  However, the partially parallel decoding method of Patent Document 1 has a problem that it is difficult to double the processing throughput under the same clock speed. The reason is as follows.

  This is because in the decoding process of the LDPC code by the partial parallel decoding method, the column processing is started after the row processing of the processing target row is completed.

In addition, the amount of calculation required for row processing (minimum value search) per iteration, which is one of decoding units, is constant. Furthermore, the amount of computation that can be serially processed per cycle of decoding processing is limited.

  Here, even if the partial parallel number (the number of arithmetic units) is increased to increase the processing capacity per cycle, the row processing calculation amount is constant and the number of operations that can be serially processed is limited. The number of processing cycles required for row processing per iteration does not decrease. The same applies to the case where row processing is started after completion of column processing.

  Therefore, even if the number of partial parallels is increased, the processing time for one iteration becomes a bottleneck and high-speed processing becomes difficult. On the other hand, when the clock speed of the decoding circuit is increased in order to shorten the processing time, another problem that power consumption increases occurs.

<Outline of this disclosure>
The first disclosure uses a storage unit that stores a plurality of likelihoods obtained by demodulating received packets, and a partial check matrix obtained by dividing a check matrix used for decoding, respectively, and performs decoding processing in parallel for each likelihood. And the partial check matrix includes a decoding device having a number of rows equal to or greater than the number of columns.

As a result, the decoding processing is distributed in a plurality of decoding cores, and the first decoding core and the second decoding core can be processed in parallel. Therefore, the entire decoding processing speed can be improved, and the transmission data can be modulated in many ways. It can respond to changes in the number of values. The processing time can be shortened without increasing the clock speed of the decoding core, and the power consumption can be reduced. In addition, processing time can be shortened by performing distributed processing for each decoding core corresponding to the partial parallel decoding method.

  The second disclosure is the decoding device according to the first disclosure, wherein the MCS information acquisition unit acquires MCS information of the received packet, and the clock output unit selectively outputs a clock for operating the decoding core. And the clock output unit is a decoding core that supplies a clock in the high-speed communication in a predetermined low-speed communication in which a communication method for transmitting the received packet is slower than a predetermined high-speed communication based on the MCS information. A decoding device for supplying the clock to a number of decoding cores less than the number;

  Thereby, in the case of low-speed communication, the number of operating decoding cores can be reduced and power consumption can be reduced by supplying clocks to a smaller number of decoding cores than in the case of high-speed communication.

  Further, the third disclosure is the decoding device according to the first disclosure, wherein the MCS information acquisition unit that acquires MCS information of the received packet, and the number of modulation schemes included in the MCS information, A clock output unit that outputs either a first clock used for normal operation of the decoding core or a second clock that is slower than the first clock; and a multilevel number of modulation schemes included in the MCS information. Accordingly, when the clock output unit outputs the first clock, the first power source of the normal operation voltage supplied to the decoding unit is output, and the clock output unit outputs the second clock. A decoding device comprising: a power supply unit that outputs a second power supply having a voltage lower than the normal operating voltage.

  Thus, when the communication method is a communication method that can be processed at a processing speed lower than the maximum processing speed of the decoding core, the power consumption can be reduced by lowering the clock frequency for operating the decoding unit. Further, power consumption can be reduced by lowering the power supply voltage.

  The fourth disclosure is the decoding device according to the third disclosure, wherein the power supply unit notifies the communication partner of information relating to an allowable communication speed of the own device at the time of communication initialization with the communication partner, and the modulation multi-value number A decoding device that outputs a low-voltage power supply of the second power supply in advance when the communication partner is notified that low-speed communication with a small amount of communication is permitted.

  Thereby, it is possible to reduce power consumption by notifying a communication partner that low-speed communication is permitted and operating the decoding core using a low-voltage power source in advance.

  The fifth disclosure is the decoding device according to the fourth disclosure, further including a setting unit that inputs user-oriented information regarding communication speed or power consumption, wherein the clock output unit is based on the user-oriented information. , Selecting a clock to be output, and the power supply unit includes a decoding device that selects a voltage to be output based on the user-oriented information. Here, for example, priority is given to low-speed communication in the case of power saving, and priority is given to high-speed communication in the case of best effort (high-speed communication).

  For example, if the user is more interested in low power consumption operation than high-speed communication, the allowable MCS is limited to low-speed communication (for example, BPSK). On the other hand, when the user intends to perform high-speed communication, the allowable MCS is permitted up to high-speed communication (for example, QPSK).

  Thereby, according to the user orientation, in the case of power saving orientation, low-speed communication is prioritized and power consumption can be reduced.

Further, a sixth disclosure is the decoding device according to the fourth disclosure or the fifth disclosure, and includes a propagation path environment estimation unit that estimates a propagation path environment for transmitting the decoding target data, and the decoding unit includes the communication A decoding device configured to set the allowable communication speed using a propagation path environment estimated value at initialization;

  Thereby, according to the propagation path environment estimated value at the time of communication start, an allowable communication speed can be set, and when low-speed communication is permitted, power consumption can be reduced.

  The seventh disclosure is the decoding device according to any one of the first disclosure to the third disclosure, and includes a propagation path environment estimation unit that estimates a propagation path environment for transmitting the decoding target data, and the control unit Based on the estimation result of the propagation path environment, when the propagation path environment estimated value is equal to or greater than a predetermined value, the number of iterations in the decoding process of the decoding core is less than when the propagation path environment estimated value is less than the predetermined value. A decoding device.

  For example, the decoding unit has a plurality of decoding modes of MCS (for example, BPSK, QPSK) having a maximum number of iterations of 2r and MCS (for example, 16QAM) having a maximum number of iterations of r or less, and the control unit has If there is a threshold table of propagation path environment estimation values that can be communicated using the decoding mode, and the propagation path environment estimation value obtained from the propagation path environment estimation unit exceeds the threshold value of the threshold table, communication is performed to the communication partner. Notify possible MCS.

  As a result, if the channel environment estimated value is greater than or equal to a predetermined value, the number of iterations in the decoding process of the decoding core is reduced, thereby ensuring error correction capability when the channel environment is good and further reducing the processing time. And high-speed decoding can be realized.

<Embodiment>
Hereinafter, an embodiment of a decoding device according to the present disclosure will be described. Each of the following embodiments will be described using the decoding device according to the present disclosure, but may be expressed as a decoding method that defines the operation of the decoding device. In the following embodiments, the same components are denoted by the same reference numerals, and the description thereof will be omitted because it is redundant.

(First embodiment)
FIG. 1 is a block diagram showing the configuration of the decoding apparatus according to the first embodiment. The first embodiment is a configuration example for realizing high-speed decoding processing.

  The decoding device according to the present embodiment includes a decoding unit 10, a likelihood storage unit 21, a selection unit 22, and a control unit 51.

  The decoding unit 10 includes a plurality of decoding cores 11-1 to 11-N. In the illustrated example, an example having N decoding cores 11-1 to 11-N is shown, but the number of decoding cores is arbitrary. Hereinafter, the decoding cores 11-1 to 11-N (N is an integer of 1 or more) may be represented as the decoding core 11. The configuration and operation of the decoding core 11 will be described later.

  The likelihood storage unit 21 as an example of a storage unit is configured to include, for example, a memory, and stores the likelihood obtained by demodulating a received packet as an example of decoding target data. For example, the receiver of the wireless communication apparatus stores the likelihood of the result of demodulating the received signal. The decoding target data is not limited to the likelihood, and encoded data may be used as appropriate.

  The decoding core 11 of the decoding unit 10 processes input likelihood data and decodes decoded bits corresponding to one codeword per unit time. Here, the code word is an LDPC code word encoded by the encoding device, and one code word corresponds to one word obtained by LDPC encoding information bits. The decoding core 11 outputs a hard decision bit (decoded bit) as a decoding result.

  FIG. 2 is a timing chart showing the timing of decoding processing in the first embodiment. In the decoding core 11, as the likelihood input from the likelihood storage unit 21, likelihood # 1, likelihood # 2, likelihood # 3, likelihood # 4, to #m (m is 1 or more) Integers) are sequentially input in time series. The likelihood #m is a likelihood corresponding to the code word #m.

  The first decoding core 11-1 (decoding core # 1) decodes the first likelihood (likelihood # 1) and outputs a first decoding bit (decoding bit # 1). The second decoding core 11-2 (decoding core # 2) decodes the second likelihood (likelihood # 2) and outputs a second decoding bit (decoding bit # 2). The first decoding core 11-1 completes the decoding process for the likelihood # 1 before starting the decoding process for the likelihood # 3. After the decoding process is completed, the first decoding core 11-1 starts the decoding process with the likelihood # 3.

  Hereinafter, similarly, the plurality of decoding cores 11-1 and 11-2 alternately decode input likelihoods. In the illustrated example, two decoding cores 11-1 and 11-2 (decoding cores # 1 and # 2) are operated to perform decoding alternately, but the same procedure is performed using three or more decoding cores. Decoding may be performed in parallel by shifting the decoding timing in order.

  The control unit 51 controls the decoding process of the decoding unit 10. The control unit 51 controls the decoding timing of each decoding core for the plurality of decoding cores 11-1 to 11-N of the decoding unit 10 so that the decoding process is performed at the decoding timing according to predetermined decoding scheduling. Control. In the example of FIG. 2, the control unit 51 causes the decoding unit 10 to decode the two decoding cores 11-1 and 11-2 (decoding cores # 1 and # 2) at the above-described decoding timing. Control.

  The control unit 51 determines the decoding timing using the “received codeword valid signal”. The received codeword valid signal is provided as a signal indicating the position of likelihood in the packet converted from the packet synchronization timing, for example.

  Based on the decoding timing of each likelihood, the control unit 51 performs likelihood reading control of likelihood to be decoded with respect to the likelihood storage unit 21. For example, the control unit 51 performs control to read the likelihood # 1 from the likelihood storage unit 12 to the decoding core 11-1 (decoding core # 1) when decoding the likelihood # 1.

  The selection unit 22 selects and outputs hard decision bits (decoding bits) output from the plurality of decoding cores 11-1 to 11 -N of the decoding unit 10 based on the control of the control unit 51, so that the selection unit 22 outputs the correct decision order. The decryption result of is output. The control unit 51 controls the selection operation in the selection unit 22 according to decoding scheduling. In the example of FIG. 2, the selection unit 22 performs decoding (likelihood # 1), decoding (likelihood # 2), decoding (likelihood # 3), decoding (likelihood # 4), ..., decoding (likelihood #m). ) (M is an integer equal to or greater than 1), and the decoded bits obtained in order are selected and output. The output decoded bits shown in FIG. 2 correspond to the decoded bits selected and output by the selection unit 22.

  Next, the configuration and operation of the decoding core 11 will be described in detail. The decoding core 11 includes a column processing unit 111, a row processing unit 112, a prior value storage unit 113, an external value storage unit 114, and a hard decision unit 115.

  The column processing unit 111 performs a column processing operation. The prior value storage unit 113 stores the prior value obtained by the column processing of the column processing unit 111. The row processing unit 112 performs a row processing operation. The external value storage unit 114 stores an external value obtained by the row processing of the row processing unit 112. The hard decision unit 115 generates and outputs hard decision bits using the soft decision values obtained by the decoding processing of the column processing unit 111 and the row processing unit 112.

  Decoding processing of the partial parallel decoding method will be described. FIG. 3 is a diagram illustrating an example of a partial check matrix divided into processing units of partial parallel decoding, a likelihood divided corresponding to the partial check matrix, and a divided codeword used for dividing the likelihood. . In the present embodiment, a check matrix divided into processing units for partial parallel decoding is used in order to perform decoding processing of target data.

First, the check matrix H uses the same matrix in the encoding device and the decoding device. In addition, a decoded bit is obtained by decoding a code word, which is a data bit sequence encoded by the encoding device, by the decoding device. Here, when the check matrix is H, the codeword is C, and the likelihood is S,
H * C = 0 (1)
This relationship holds in the encoding apparatus.

  In the present embodiment, the decoding device uses a partial matrix obtained by dividing the parity check matrix H into processing units for partial parallel decoding, such as Hsub 1, Hsub 2, Hsub 3,..., Hsub N−1, Hsub N. Here, the parity check matrix H is divided so that the number of rows of the partial matrix obtained by dividing the parity check matrix is equal to or greater than the number of columns.

  Here, when the codeword multiplied by the submatrix obtained by dividing the check matrix H is divided into Csub1, Csub2, Csub3,..., CsubN-1, CsubN so as to satisfy the expression (1). The following formula (2) is established.

[Hsub 1, Hsub 2, ..., Hsub N]
* [Csub 1 ^T , Csub 2 ^T ,..., Csub N ^T ] ^T = 0
[Hsub 1 * Csub 1+ to + Hsub N * Csub N] = 0 (2)
(T represents transposition)

  That is, the codeword vector is determined so that Hsub M (M is an integer) is multiplied by Csub M.

Next, the likelihood S used in the decoding apparatus is divided using a vector having the same length as each divided codeword Csub M. FIG. 3 shows a matrix that represents the likelihood S divided by using Ssub 1, Ssub 2, Ssub 3,..., Ssub N-1, Ssub N.
The likelihood is divided by the above method.

  In the decoding core 11 of this embodiment, column processing and row processing are performed in the order of Hsub 1, 2, 3,.

  In this embodiment, the parity check matrix is divided so that the number of rows of the partial matrix obtained by dividing the parity check matrix is equal to or greater than the number of columns.

The reason for dividing as described above is as follows.
(I) The storage capacity of the prior value storage unit can be reduced.
(Ii) The number of comparators used during row processing in partial parallel decoding can be reduced.
(Iii) The storage capacity of the external value storage unit can be reduced.

Among the reasons described above, factors of (ii) comparator reduction and (iii) external value storage capacity reduction will be described below. In the present embodiment, a description will be given using a Min-Sum decoding algorithm as a decoding method. Note that the decoding method is not limited to this, and other decoding methods such as Sum-Product decoding may be used. Details of the decoding algorithm are described in, for example, Reference 1 (Masawa Wadayama, “Low Density Parity Check Code and its Decoding Method”, Trikeps Publishing, June 5, 2002, (P92-P99)). .

  By the processing of the column processing unit 111 and the row processing unit 112, the external value αmn and the prior value βmn are obtained by the following equations (3) and (4).

The column processing and row processing for calculating the term min | βmn | in equation (3) are Hsub 1 and Hsub.
2,..., Hsub N are executed sequentially for each partial parallel unit. Let β_min be the current minimum value. β_min is stored in the external value storage unit 114.

The minimum value searched by the row processing of Hsub 1 is compared with β_min, and the smaller one becomes a new β_min.
β_min = min (β_min, β_Hsub x) (5)
Here, β_Hsub x is a β value obtained by the row processing of Hsub x.

  In the present embodiment, as described above, since the comparison operation can be performed in a distributed manner, the number of comparators can be reduced by making the number of rows of the partial matrix obtained by dividing the check matrix equal to or greater than the number of columns. Further, since β_min only needs to store the updated value, the capacity of the external value storage unit 114 can be reduced.

  Among the reasons described above, the factor of (i) reduction of the prior value storage capacity will be described. In this embodiment, since the prior value obtained from the column processing calculation result can be reflected and used in the row processing without saving, all the column processing intermediate calculation results are saved as in the conventional partial parallel decoding method. There is no need to keep it.

  That is, the required prior value storage capacity is from the completion of the column processing corresponding to the submatrix Hsub x until the row processing is performed, and may be a pipeline register. Therefore, the prior value storage unit 113 can be configured as a pipeline register, and the capacity of the prior value storage unit 113 can be reduced. Details will be described with reference to FIG.

  FIG. 4 is a diagram showing the timing of column processing and row processing in partial parallel decoding, and represents decoding scheduling at the time of decoding processing. Here, decoding scheduling represents the order in which row processing and column processing are performed in the partially parallel decoding method.

  In the partial parallel decoding, the row processing is performed after the column processing of the column including the row to be processed is completed. Therefore, after the column processing Hsub 1, the processing is performed in the order of the row processing Hsub 1. That is, after the column processing of Hsub 1 is performed, the row processing of Hsub 1 is performed, and further, the column processing of Hsub 2 is performed.

  Thereafter, column processing and row processing are executed in the same manner up to Hsub N. Row processing and column processing are sequentially pipelined from Hsub 1 to Hsub N, and one iteration is completed when the row processing Hsub N is completed.

  Therefore, the time required for processing from the start of the column processing Hsub 1 to the end of the row processing Hsub N is one iteration processing delay. After one iteration, the next iteration can be started.

  As described above, after the column processing corresponding to Hsub x is completed, row processing using the column processing result is performed. Therefore, the prior value storage unit 113 stores a pipeline register having a capacity corresponding to the submatrix Hsub x. Can be configured.

  In FIG. 4, at the time corresponding to the column processing Hsub 1, the row processing is not performed and is blank.

  FIG. 5 is a schematic diagram showing the entire process of decoding processing by partial parallel decoding. In the column processing unit 111 and the row processing unit 112, after one iteration of the decoding process is repeated a predetermined number of times, a hard decision is performed in the hard decision unit 115, and the decoding is completed. “1 likelihood decoding” at this time corresponds to “decoding (likelihood #x)” in FIG.

  FIG. 6 is a diagram illustrating an example of doubling the number of parallel operations for column processing in partial parallel decoding, and explaining that the iteration processing delay does not decrease even if the number of parallel operations for column processing is doubled. To do.

  First, Hsub 1 and Hsub 2 can be simultaneously processed in parallel by doubling the number of parallel operations in column processing. On the other hand, in the row processing of Hsub 1 and Hsub 2, the minimum value search (calculation of β_min) is serial processing (serial processing), and therefore, it is not configured in parallel processing like column processing.

The operation for collectively performing the row processing of Hsub 1 and Hsub 2 is as follows:
β_min = min (β_min, β_Hsub 1, Hsub 2) (6), but as an actual calculation,
β_min1 = min (β_min, β_Hsub 1)
β_min = min (β_min1, β_Hsub 2) (7)
It is. That is, in order to obtain β_min, β_min1 must first be obtained, and serial processing is required.

  For this reason, it is difficult to reduce the processing delay, and one iteration processing delay requires a processing time of Hsub × (N + 1) that does not change the processing time as compared with FIG. Therefore, it can be seen that it is difficult to shorten the decoding processing time by simply increasing the number of parallel operations in column processing.

  As described above, in the present embodiment, the decoding unit has a multi-core configuration having a plurality of decoding cores, and the decoding process is distributed for each decoding core. For this reason, in the conventional decoding method in which the parity check matrix is not divided into sub-matrices, the row processing and the column processing cannot be pipelined, so that the processing time of Hsub1 × N × 2 processing delay is high speed. Decoding processing can be realized.

Further, by using the above configuration, the processing time per iteration can be shortened without increasing the clock speed of the decoding circuit, and an increase in power consumption accompanying the increase in speed can be suppressed. Also,
Even if the partial parallel decoding method is used, by using the above configuration, it is possible to reduce the storage capacity of the prior value storage unit and the external value storage unit, and it is possible to suppress the increase in size and complexity of the device configuration accompanying the increase in speed.

(Second Embodiment)
FIG. 7 is a block diagram showing the configuration of the decoding apparatus according to the second embodiment. The second embodiment is a configuration example that realizes high-speed decoding processing and low power consumption.

  The decoding device according to the second embodiment includes a decoding unit 10, a likelihood storage unit 21, a selection unit 22, a clock generation unit 23, a clock gate unit 24, a header analysis unit 25, and a control unit 52.

  For example, the packet communication system based on IEEE 802.11ad supports a plurality of combinations of modulation schemes and coding rates. The plurality of combinations are called MCS (Modulation and Coding Scheme) information and are described in a header in packet communication.

  For example, a decoding apparatus that can support a plurality of communication methods and operates at the maximum capacity during QPSK communication of 2 bits / symbol has a redundant decoding core for 1 bit during BPSK communication of 1 bit / symbol. There is a decoding core that goes into an idle state.

  Here, since the idle decoding core also consumes power, there is a problem that unnecessary power consumption occurs. In the second embodiment, unnecessary power consumption is reduced to enable low power consumption operation.

  The header analysis unit 25 as an example of the MCS information acquisition unit analyzes a header in packet communication. The header includes MCS information. The header analysis unit 25 acquires MCS information based on the analysis result of the header of the received packet, and notifies the control unit 52 of the acquired MCS information.

  The clock generation unit 23 includes, for example, an oscillator, and generates a clock for operating the circuit of the decoding device including the decoding unit 10. The control unit 52 controls the clock supply from the clock gate unit 24 to the decoding unit 10 according to the MCS information. The clock gate unit 24 as an example of the clock output unit can selectively output a clock. Based on the control of the control unit 52, the clock gate unit 24 gates the clock generated by the clock generation unit 23, and supplies or stops the clock to each of the decoding cores 11-1 to 11-N.

  FIG. 8 is a timing chart showing the timing of the decoding process in the second embodiment. In the second embodiment, it is assumed that communication is performed by switching between QPSK communication and BPSK communication, corresponding to a plurality of communication methods. FIG. 8A shows the operation during QPSK communication, and FIG. 8B shows the operation during BPSK communication. In this example, QPSK communication corresponds to predetermined high-speed communication, and BPSK communication corresponds to predetermined low-speed communication.

  During QPSK communication, the clock gate unit 24 supplies clocks to the two decoding cores to operate each decoding core. That is, the clock gate unit 24 supplies the clock # 1 to the first decoding core 11-1 (decoding core # 1) and supplies the clock # 2 to the second decoding core 11-2 (decoding core # 2). To do. As a result, as in the first embodiment shown in FIG. 2, the decoding processing is performed in a distributed manner by the two decoding cores 11-1 and 11-2, and the likelihoods # 1, # 2, # 3, # 4, ~, #M is decoded.

At the time of BPSK communication, the clock gate unit 24 operates by supplying a clock to a smaller number, in this example, one decoding core than at the time of QPSK communication. That is, the clock gate unit 24
Supplies the clock # 1 to the first decoding core 11-1 (decoding core # 1) and stops the clock supply to the second decoding core 11-2 (decoding core # 2). Accordingly, in FIG. 8B, the decoding process is performed by one decoding core 11-1, and the likelihoods # 1, # 2,..., #M are decoded.

  In BPSK communication, the transmission rate of each codeword is half (transmission time is twice) and the input rate of input likelihood is halved compared to QPSK communication, so that the decoding core has half the processing capacity (2 Double the processing time). For this reason, the control unit 52 operates half of the decoding cores 11-1 to 11-N in the decoding unit 10 and pauses half of the decoding cores in the idle state, thereby reducing unnecessary power consumption. Reduce.

  As described above, in this embodiment, based on the MCS information obtained from the header analysis result, the clock of the decoding core in the idle state is gated, and the operation of the decoding core in the idle state is stopped. Thereby, unnecessary power consumption in the decoding core in the idle state can be reduced, and power consumption can be reduced. Therefore, in a configuration that realizes high-speed decoding processing, for example, power consumption can be reduced and power consumption can be reduced according to various situations during operation typified by a communication method and a transmission rate.

(Third embodiment)
FIG. 9 is a block diagram illustrating a configuration of a decoding device according to the third embodiment. The third embodiment is a configuration example that realizes high throughput when the propagation path environment is good even when the maximum number of iterations of the decoding apparatus is equal to or less than a predetermined value.

  The decoding apparatus according to the third embodiment includes a decoding unit 10, a likelihood storage unit 21, a selection unit 22, a clock generation unit 23, a clock gate unit 24, a header analysis unit 25, a radio unit 26, a demodulation unit 27, and a propagation path environment. The configuration includes an estimation unit 28 and a control unit 53.

  The radio unit 26 includes a high frequency circuit including an amplifier and a frequency converter, and performs radio signal processing including amplification and frequency conversion of a radio signal received by an antenna. The demodulator 27 is configured by an electronic circuit having a signal processing circuit, for example, performs demodulation processing on the received signal output from the radio unit 26, and outputs a likelihood related to the received signal.

The propagation path environment estimation unit 28 is based on the received signal demodulated by the demodulation unit 27, for example, the propagation path environment of the radio signal, such as SNR (Signal to Noise Ratio), CNR (Carrier to Noise Ratio).
) And the quality of a received signal typified by RSSI (Received Signal Strength Indicator).

  When the control unit 53 determines that the propagation path environment is good based on the estimation result of the propagation path environment by the propagation path environment estimation unit 28, the control unit 53 decreases the number of iterations in the decoding process of the decoding core 11.

  For example, a first decoding mode corresponding to MCS (for example, BPSK, QPSK) having a maximum number of iterations of 2r, and a second decoding mode corresponding to MCS (for example, 16QAM) having a maximum number of iterations of r or less. Suppose you have

  In the first decoding mode, the propagation path environment estimated value is less than a predetermined value, and low-speed communication is often selected as the communication method.

In the second decoding mode, the propagation path environment estimated value is not less than a predetermined value, and high-speed communication is often selected as the communication method. When the propagation path environment is good, the decoding process with a small number of iterations is performed using the second decoding mode.

  The control unit 53 feeds back to the communication partner that high-speed communication is possible.

  FIG. 10 is a timing chart showing the timing of the decoding process in the third embodiment. In the third embodiment, it is assumed that 16QAM communication is performed when the propagation path environment is good. In 16QAM communication, the transmission rate (input likelihood input rate) of each codeword is twice that of QPSK (transmission time is half of QPSK).

  At the time of high-speed communication, since the input rate of the input likelihood is high, it can be considered to use a decoding core with a higher clock frequency or increase the number of decoding cores.

  On the other hand, in the present embodiment, even when the maximum number of iterations of the decoding device is less than or equal to a predetermined value, in a good propagation path environment, high-speed communication is performed by feedback to the communication partner, and the number of iterations in decoding The decoding time per likelihood is shortened by using the second decoding mode in which is reduced. Note that, except for a good propagation path environment, the first decoding mode that is the decoding method in the first embodiment or the second embodiment is used.

  If the number of iterations is reduced, the error correction capability deteriorates. However, since the propagation path environment is good, the number of errors included in the received signal is statistically small. Since the error occurrence rate is low, errors can be corrected even with a small number of iterations.

  According to the present embodiment, the decoding device changes from the first decoding mode to the second decoding mode when the propagation path environment is good even when the maximum number of iterations is not more than a predetermined value during high-speed communication. High throughput can be realized by switching.

(Fourth embodiment)
FIG. 11 is a block diagram illustrating a configuration of a decoding device according to the fourth embodiment. The fourth embodiment is another configuration example for realizing low power consumption of the decoding device.

  The decoding device according to the fourth embodiment includes a decoding unit 10, a likelihood storage unit 21, a selection unit 22, a clock generation unit 23, a clock gate unit 24, a header analysis unit 25, a radio unit 26, a demodulation unit 27, and a propagation path environment. The configuration includes an estimation unit 28, a clock frequency division unit 29, a power supply 31, a low voltage power supply 32, a setting unit 33, and a control unit 54.

  The clock divider 29 is configured to have, for example, a frequency divider, divides the clock for circuit operation generated by the clock generator 23, and outputs a low-speed clock. The clock gate unit 24 switches the output of the clock based on the control of the control unit 54, and sends the clock from the clock generation unit 23 or the low-speed clock from the clock frequency division unit 29 to each decoding core 11-1 to 11-N. Supply. In this example, the clock from the clock generator 23 corresponds to the first clock, and the low-speed clock from the clock divider 29 corresponds to the second clock. The clock dividing unit 29 and the clock gate unit 24 realize the function of the clock output unit.

  In this example, the power source 31 corresponds to a first power source that outputs power of a normal operating voltage. The low voltage power supply 32 corresponds to a second power supply that outputs power having a voltage lower than the normal operating voltage. The power supply 31 and the low voltage power supply 32 are each realized by a power supply circuit that outputs predetermined power.

  The setting unit 33 receives a setting input by the user and sets the user's intention. User-oriented setting information is sent to the control unit 54. As the user orientation, for example, best effort (high-speed communication) orientation or power saving orientation is set.

  The control unit 54 supplies the low-speed clock from the clock dividing unit 29 to the decoding unit 10 at the time of low-speed communication (at the time of low throughput) according to the user's preference, and reduces the clock speed. Power is supplied to the decoding unit 10 to lower the power supply voltage.

  For example, the decoding unit 10 of the present embodiment has a capability of performing decoding processing corresponding to the communication speed of QPSK. If the modulation method of the received packet is BPSK, the decoding unit 10 can perform the decoding process even if the clock speed is low after using a decoding method corresponding to the communication speed of QPSK.

  For example, the normal clock frequency is K, and the number of clock cycles for 1-likelihood decoding when decoding processing corresponding to the communication speed of QPSK is performed is L. At this time, the time required for decoding with one likelihood is Tq = L / K. Here, it is assumed that the clock speed is halved to K / 2. At this time, the time required for decoding one codeword is Tb = L / (K / 2) = 2L / K = 2Tq, which is twice as long.

  On the other hand, the time required for 1 likelihood decoding in the decoding process corresponding to the communication speed of BPSK is Tb = 2Tq. This is because QPSK has a transmission rate of 1 bit / symbol while QPSK has a transmission rate of 2 bits / symbol.

  Therefore, the decoding unit 10 corresponding to QPSK can decode a packet using BPSK even if the clock speed is halved.

  It is assumed that the modulation multilevel number that can be processed by the decoding unit 10 is N, the multilevel number of the modulation scheme used in the received packet is M, and the clock frequency division number is R.

The decoding unit 10
N / R ≧ M (8)
If the above is satisfied, the clock speed can be lowered.

  Therefore, the control unit 54 reduces the clock speed based on the MCS information acquired from the header analysis result of the header analysis unit 25 when the received packet is BPSK modulated, that is, during BPSK communication. The clock gate 24 supplies the low-speed clock from the clock divider 29 to the decoding core 11 under the control of the controller 54.

  When the clock speed is low, it is possible to drive the circuit even if the power supply voltage is lowered (Reference 2: “Low Energy LSI by Extremely Low Voltage Operation”, IEICE Journal Vol.93, No. 11, pp943-p47, November 2010). Therefore, the control unit 54 supplies low-voltage power to the decoding core 11 using the low-voltage power supply 32 during BPSK communication.

  In the fourth embodiment, when the communication method allows processing at a processing speed lower than the maximum processing speed of the decoding core 11, the clock supplied to the decoding core 11 is a low-speed clock and the power supply is a low-voltage power supply. The voltage value supplied from the low-voltage power supply 32 is lower than the normal operating voltage from the power supply 31 and is equal to or higher than the lowest voltage that can drive the decoding core 11 with a low-speed clock.

  As described in Reference Document 2, the relationship between the power supply voltage and the clock frequency of the circuit can drive the circuit by lowering the operation clock even when the power supply voltage is lowered with respect to the normal operation voltage. Further, it is described that power consumption can be reduced by reducing the power supply voltage and the operation clock.

  Here, when the power supply voltage is lowered in the BPSK communication with respect to the clock frequency and the power supply voltage set in the QPSK communication, the clock frequency at which the decoding core 11 can operate is lowered due to the drop in the power supply voltage.

  However, in this embodiment, since the clock frequency required in BPSK communication is half of the clock frequency required in QPSK communication, the lower limit of the operation clock frequency decrease due to the power supply voltage decrease in the decoding core 11. The operation satisfying the desired number of iterations is possible up to half the original clock frequency. Further, power consumption can be reduced by lowering the clock frequency and lowering the power supply voltage.

  That is, in the present embodiment, when changing to the low voltage power supply 32, the clock dividing unit 29 is changed.

  The power consumption of the circuit is proportional to the square of the power supply voltage and proportional to the operation clock frequency. Therefore, power consumption can be reduced by performing low-voltage driving and low-speed clock operation.

  When the power supply voltage is lowered, the low voltage power supply may be driven after analyzing the MCS of the received packet. However, in order to drive the decoding apparatus using the low voltage power supply more stably, in this embodiment, The following control is performed.

  The control unit 54 feeds back information (for example, MCS, communication throughput) relating to the allowable communication speed allowed by the receiving side to the communication partner to the communication partner on the transmission side when handshaking with the communication partner at the start of communication. The communication partner's transmitting device communicates at the allowable communication speed of the receiving side (the receiving device having the decoding device of the present embodiment). Here, an allowable MCS is used as the allowable communication speed.

  FIG. 13 is a sequence diagram illustrating a handshake procedure at the time of communication initialization in the fourth embodiment. The receiving device STA 2 (Rx) and the communication partner transmitting device STA 1 (Tx) have the decoding device of this embodiment.

  First, the transmitting apparatus STA 1 transmits a link establishment request to the receiving apparatus STA 2 [1], and the receiving apparatus STA 2 receives the link establishment request and performs propagation path environment estimation [2]. Then, the receiving apparatus STA 2 approves the link establishment [3], refers to the MCS corresponding to the preset user orientation, and feeds back the allowable MCS information to the transmitting apparatus STA 1.

  The transmitting apparatus STA 1 receives the allowable MCS information and completes the link establishment confirmation [4]. Thereafter, the transmitting apparatus STA 1 starts communication by the allowable MCS and transmits transmission data to the receiving apparatus STA 2 [5]. Thereafter, communication is performed using the MCS set between the transmission apparatus STA 1 and the reception apparatus STA 2. If the reception device STA 2 can normally demodulate and decode the received data, the reception device STA 2 feeds back an ACK to the transmission device STA 1.

  Since the allowable communication speed information is notified to the communication partner at the time of communication initialization, the receiving device can be driven in advance by a low voltage power source.

Further, the allowable communication speed information represented by MCS allowed by the receiving side may be controlled according to the user's intention. For example, when the user intends to operate with low power consumption rather than high-speed communication, the control unit 54 limits the allowable MCS to, for example, BPSK. On the other hand, when the user intends to perform high-speed communication, the control unit 54 performs control such as “allowable MCS is up to QPSK”, for example.

  FIG. 12 is a diagram illustrating an example of a relationship between a propagation path environment and user-oriented MCS. The control unit 54 has, as user-oriented information, for example, a table in which a propagation path environment estimated value and an MCS based on user-oriented are associated. MCS values 1 to 3 are such that 1 is a low transmission rate communication (for example, BPSK), 2 is a medium transmission rate communication (for example, QPSK), and 3 is a high transmission rate communication (for example, 16 QAM).

  In the best effort orientation (communication speed orientation), transmission speed is given priority, and high-speed communication is performed when the propagation path environment is good. In the power saving direction, priority is given to power consumption, and low-speed or moderate communication is performed even if the propagation path environment is good.

  The control unit 54 compares the estimated channel environment estimated value Pest (for example, CNR, SNR, RSSI) with the thresholds (P1, P2 in the example of FIG. 12) described in the table, and compares the corresponding MCS with the communication on the transmission side. Give feedback to the other party. The communication device on the transmission side determines the MCS based on the feedback information, and transmits the transmission data generated according to the MCS.

  According to the present embodiment, when performing low-speed communication with respect to the processing capability of the decoding circuit, the power consumption can be reduced and the power consumption can be reduced by using a low-speed clock and a low-voltage power supply.

  While various embodiments have been described above with reference to the drawings, it goes without saying that the present disclosure is not limited to such examples. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present disclosure. Understood. In addition, each component in the above embodiment may be arbitrarily combined within a scope that does not depart from the spirit of the disclosure.

  In each of the above-described embodiments, the present disclosure has been described by taking as an example the case where the present disclosure is configured using hardware. However, the present disclosure can also be realized by software in cooperation with hardware.

  In addition, each functional block used in the description of each of the above embodiments is typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of each functional block. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

  Further, the method of circuit integration is not limited to LSI, and may be realized using a dedicated circuit or a general-purpose processor. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI, or a reconfigurable processor in which connection and setting of circuit cells in the LSI can be reconfigured may be used.

  Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using another technology. Biotechnology can be applied.

  The present disclosure has an effect of enabling high-speed decoding processing, and is useful as an implementation of high-speed, low-power-consumption decoding processing, for example, in an error correction decoding device that corrects an error in a signal generated in a communication transmission line. It is.

DESCRIPTION OF SYMBOLS 10 Decoding part 11, 11-1 to 11-N Decoding core 21 Likelihood storage part 22 Selection part 23 Clock generation part 24 Clock gate part 25 Header analysis part 26 Radio | wireless part 27 Demodulation part 28 Propagation path environment estimation part 29 Clock division | segmentation Unit 31 Power source 32 Low voltage power source 33 Setting unit 51, 52, 53, 54 Control unit 111 Column processing unit 112 Row processing unit 113 Prior value storage unit 114 External value storage unit 115 Hard decision unit

Claims (5)

A storage unit for storing a plurality of likelihoods obtained by demodulating the received packet;
A decoding unit having a plurality of decoding cores that perform decoding processing in parallel for each likelihood using a partial check matrix obtained by dividing a check matrix used for decoding,
An MCS information acquisition unit for acquiring MCS information of the received packet;
A clock output unit that selectively outputs a clock for operating the decoding core, and
The partial check matrix is a matrix whose number of rows is equal to or greater than the number of columns,
Based on the MCS information, the clock output unit is configured to transmit the received packet in a predetermined low-speed communication that is slower than a predetermined high-speed communication.
Supplying the clock to a smaller number of decoding cores than the number of decoding cores supplying the clock in the high-speed communication;
Decoding device. A storage unit for storing a plurality of likelihoods obtained by demodulating the received packet;
A decoding unit having a plurality of decoding cores that perform decoding processing in parallel for each likelihood using a partial check matrix obtained by dividing a check matrix used for decoding,
An MCS information acquisition unit for acquiring MCS information of the received packet;
A clock that outputs either the first clock used for the normal operation of the decoding core or the second clock slower than the first clock according to the multi-value number of the modulation method included in the MCS information An output section;
According to the multi-level number of modulation schemes included in the MCS information,
When the clock output unit outputs the first clock, the first power source of the normal operating voltage supplied to the decoding unit is output;
When the clock output unit outputs the second clock, a power supply unit that outputs a second power supply having a voltage lower than the normal operation voltage;
Bei to give a,
The partial check matrix is a matrix whose number of rows is equal to or greater than the number of columns.
Decoding device. The decoding device according to claim 2 ,
The power supply unit is
When notifying the communication partner of information regarding the allowable communication speed of the own device at the time of communication initialization with the communication partner, and notifying the communication partner that low-speed communication with a small number of modulation multivalues is allowed
Outputting a low-voltage power source of the second power source in advance;
Decoding device. The decoding device according to claim 3 , wherein
It further has a setting unit for inputting user-oriented information regarding communication speed or power consumption,
The clock output unit
Based on the user-oriented information, select a clock to output,
The power supply unit is
Selecting a voltage to be output based on the user-oriented information;
Decoding device. The decoding device according to claim 3 or 4 ,
A propagation path environment estimation unit for estimating a propagation path environment for transmitting the decoding target data;
The decoding unit
Setting the allowable communication speed using a propagation path environment estimated value at the time of the communication initialization,
Decoding device.

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