JP5867903B2 - Image processing apparatus, image processing method, and program - Google Patents

Description

  The present invention relates to an image processing apparatus, an image processing method, and a program.

  Conventionally, in an image processing apparatus having a photographing function such as a digital camera or a mobile phone, when generating an image, Bayer data (original image data) captured from an image sensor is converted into YUV data, shading correction, Image correction such as edge enhancement, noise reduction, distortion correction, and enlargement / reduction are performed.

  When each of the processes described above is performed, if an entire image is processed, each processing circuit becomes very large. Therefore, the image is divided into a predetermined number of lines in the horizontal direction (this divided unit). Is called a belt), and a technique for performing various image processing by adding image data (ring pixels) necessary for image processing to the divided original image data is known (see, for example, Patent Document 1).

JP 2006-211402 A

  By the way, in the conventional image processing apparatus, processing units that can be processed by a plurality of image processing modules are different, and when another processed image processing module uses the processed image, the entire processed image is once stored in the external memory. However, another module needs to read it. For image processing, it is necessary to read data larger than the original image size.

  For this reason, when data input / output more than twice the image size is performed to the external memory, the processing capacity of the entire system can be reduced due to insufficient data bus bandwidth when many modules perform processing simultaneously. There is a problem that the processing is slowed down.

  SUMMARY An advantage of some aspects of the invention is that it provides an image processing apparatus, an image processing method, and a program that can significantly reduce the amount of data transferred to an external memory.

  An image processing apparatus of the present invention is an image processing apparatus that divides image data and sequentially processes the divided image data, and includes a buffer memory and a plurality of image processing amounts that can be processed at a time. For each of the divided image data sequentially processed by the image processing module and the upstream image processing module, an amount of first partial image data that can be processed at one time by the downstream image processing module is converted into the downstream image processing. A second partial image data other than the first partial image data is transferred to the buffer memory, and the processing for the first partial image data is completed in the downstream image processing module; An image data transfer unit that transfers the second partial image data stored in the buffer memory to the downstream image processing module. An image processing apparatus according to claim.

  An image processing method according to the present invention is an image processing method for dividing image data and sequentially processing the divided image data, wherein a plurality of image processing modules having different amounts of image processing that can be processed at one time are provided. Out of the divided image data sequentially processed by the upstream image processing module, an amount of the first partial image data that can be processed at one time by the downstream image processing module is transferred to the downstream image processing module. A step of transferring second partial image data other than the first partial image data to a buffer memory, and after the processing on the first partial image data is completed in the downstream image processing module, Transferring the second partial image data stored in the buffer memory to the downstream image processing module. The image processing method according to symptoms.

  The program of the present invention divides image data, and the computer of the image processing apparatus that sequentially processes the divided image data, among a plurality of image processing modules each having a different amount of image processing that can be processed at one time, For each of the divided image data sequentially processed by the upstream image processing module, transferring the first partial image data in an amount that can be processed at one time by the downstream image processing module to the downstream image processing module And transferring the second partial image data other than the first partial image data to a buffer memory, and after the processing on the first partial image data is completed in the downstream image processing module, the buffer The second partial image data stored in the memory is transferred to the downstream image processing module. Is a program for causing.

  According to the present invention, the amount of data transferred to the external memory can be greatly reduced.

It is a block diagram which shows the schematic structure of the digital camera by embodiment of this invention. It is a block diagram which shows the structure of ASIC2 by this embodiment. In this embodiment, it is a conceptual diagram which shows the processing unit of original image data. In this embodiment, it is a conceptual diagram for demonstrating the data transfer by the image data transfer part 14. FIG. It is a flowchart for demonstrating operation | movement of the image data transfer part 14 by this embodiment. It is a flowchart for demonstrating operation | movement of the image data transfer part 14 by this embodiment. It is a conceptual diagram for demonstrating operation | movement (1st input belt) of the image data transfer part 14 by this embodiment. It is a conceptual diagram for demonstrating operation | movement (2nd input belt) of the image data transfer part 14 by this embodiment. It is a conceptual diagram for demonstrating operation | movement (3rd input belt) of the image data transfer part 14 by this embodiment. It is a conceptual diagram for demonstrating operation | movement (4th input belt) of the image data transfer part 14 by this embodiment. In this embodiment, it is a conceptual diagram which shows the order in which the process result of the image process part 13 is written in RAM3.

  In order to reduce the amount of intermediate data to be output to an external memory when a plurality of modules perform image processing continuously, the present invention grasps the processing unit of each module and stores data to be stored in the external memory. The data to be processed is discriminated, and only the data to be stored is stored in the external memory. Further, the data that can be directly transferred from the upstream module to the downstream module and the data read from the external memory are combined and transferred to the downstream module. Further, in order to reduce the data stored in the external memory, the processing order of the downstream modules is changed and processed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

A. Configuration of Embodiment FIG. 1 is a block diagram showing a schematic configuration of a digital camera according to an embodiment of the present invention. In the figure, the CPU 1 controls the operation (photographing, image processing, etc.) of each part of the digital camera described later by executing a predetermined program. The ASIC 2 performs YUV data conversion, image correction such as edge enhancement and shading correction, enlargement and reduction of the image, and noise removal and distortion correction of the distorted image as necessary with respect to Bayer data input from the CCD 4 described later. Do. Further, the ASIC 2 performs various image processing and the like on the image data input from the CCD 4 to be described later and displays the image data on the LCD 6.

  The RAM 3 stores various parameters related to the operation of the CPU 1 and the ASIC 2, captured image data, image data after image processing is performed on the image data, and temporarily stores intermediate results in the image processing. save. In particular, in this embodiment, a buffer area required for some image processing (noise removal, distortion correction) is secured in the RAM 3. The CCD 4 captures an image formed through an optical system such as a lens as an electrical signal, and supplies the imaged image data (hereinafter referred to as original image data or Bayer data) to the ASIC 2.

  The ROM 5 stores predetermined programs executed by the CPU 1 and the ASIC 2, operation parameters, and the like. In particular, in this embodiment, parameters used in various image processes are stored. The LCD 6 displays various menu screens, various setting items on the menu screen, operation parameters, a through image at the time of shooting, original image data that has been shot, and the like. The keyboard 7 includes buttons for setting and specifying various shooting parameters and operation modes, a shutter button, and the like. The power supply unit 8 includes various batteries (primary battery, secondary battery, etc.) and supplies power for operating the above-described units.

Next, FIG. 2 is a block diagram showing a configuration of the ASIC 2 according to the present embodiment. In the figure, ASIC 2 is DMAC (Dynamic Memory Access).
Controller) 9, memory control unit 10, CCD control unit 11, image processing units 12 and 13, image data transfer unit 14, LCD control unit 15, keyboard control unit 16, and image conversion unit 17.

  The DMAC 9 directly accesses the RAM 3 and the ROM 5 by using the memory control unit 10 without using the CPU 1 to control the storage and reading of the original image data or the transfer to various image processing units described later. The memory control unit 10 directly accesses the RAM 3 and the ROM 5 under the control of the DMAC 9 and exchanges data between the DMAC 9 and the RAM 3 and the ROM 5. The CCD control unit 11 drives and controls the CCD 4 and supplies the original image data captured by the CCD 4 to the DMAC 9.

  The image processing unit 12 performs image processing such as enlargement on the image data supplied from the DMC 9 and supplies the processed image data to the image data transfer unit 14. The image processing unit 13 further performs image processing such as enlargement on the image data supplied from the image data transfer unit 14. The image data transfer unit 15 transfers image data between the image processing units 12 and 13 and the RAM 3 via the DMAC 9 when transferring the image data supplied from the image processing unit 12 to the image processing unit 13. Control processing.

  The LCD control unit 15 controls display of the original image data supplied from the DMAC 9 and image data subjected to image processing on the LCD 6. The keyboard control unit 16 controls input (scanning) of the keyboard 7. The image conversion unit 17 converts the original image data into YUV data.

  FIG. 3 is a conceptual diagram showing a processing unit of original image data in the present embodiment. In this embodiment, as shown in FIG. 2, the original image data is read out in the form of a partially overlapping belt such as a first input belt 101, a second input belt 102, a third input belt 103,. Supply to the processing unit 12. The image data transfer unit 14 distributes the image data after the image processing output from the image processing unit 12 to the image processing unit 103 in the next stage or the RAM 3 that is an external memory, and the image data to the RAM 3 that is an external memory. The processing order of each processing unit of the image processing unit 13 is changed so that data transfer is minimized. As a result, the amount of image data exchanged with the RAM 3 as the external memory can be reduced, and the bus bandwidth of the entire system can be reduced.

  FIG. 4 is a conceptual diagram for explaining data transfer by the image data transfer unit 14 in the present embodiment. In the present embodiment, it is assumed that both the image processing units 12 and 13 can perform image enlargement up to 4 times, and the 16-line image data is multiplied by 4 by the image processing unit 12 and expanded to 64 lines. A case will be described in which image processing for doubling and enlarging to 128 lines by the unit 13 is performed. The number of ring pixels required for enlargement is two pixels, and two lines of ring pixels are required above and below the belt when inputting data to the image processing units 12 and 13. When there are insufficient ring pixels in the original image data, the image data transfer unit 14 adds two lines of ring pixels (copies the upper and lower lines). The number of output lines of the image processing units 12 and 13 is 16 lines. Since the number of input lines of the image processing unit 13 is twice, it becomes 12 lines of 2 × 2 lines of output 16 lines ÷ 2 + rings.

B. Operation of Embodiment Next, the operation of the above-described embodiment will be described.
5 and 6 are flowcharts for explaining the operation of the image data transfer unit 14 according to the present embodiment. In each figure, the processing unit is called a belt. Also, the number of pixels in the vertical direction is set as the Y coordinate, and is set to 0 to image size-1. The output image of the image processing unit 12 is 0 to 63 lines.

  First, the Y coordinate (InEndY = number of belt lines−1) of the end position of the input side belt is calculated (step S10), and the Y coordinate (OutEndY = number of belt lines + lower ring−1) of the end position of the output side belt is calculated. Calculate (step S12). Next, the number of lines to be output to the RAM 3 is calculated (step S14), input data is output to the image processing unit 13, and temporarily stored in an internal buffer. Only necessary line data is output to the RAM 3, and image processing is performed. The processing result of the unit 13 is output to the RAM 3 (step S16).

  Next, the Y coordinate of the end value of the input side belt is stored as InEndY_old = InEndY, and the Y coordinate of the end value of the input side belt (InEndY = InEndY + number of input belt lines) is calculated (updated) (step S18). Next, it is determined whether or not the output side is the final belt (step S20). If it is not the final belt, the Y coordinate of the end value of the output side belt is stored as OutEndY_old = OutEndY, and the end value of the output side belt is stored. Y coordinate (OutEndY = OutEndY + number of output belt lines) is calculated (updated) (step S22).

  Next, the number of transfer lines (OutEndY-InEndY_old) to the image processing unit 13 is calculated (step S24). Next, it is determined whether the Y coordinate InEndY of the end value of the input side belt is smaller than the Y coordinate OutEndY of the end value of the output side belt (step S26). When the Y coordinate InEndY of the end value of the input side belt is equal to or larger than the Y coordinate OutEndY of the output side belt (NO in step S26), the process returns to step S20 and the above-described processing is repeatedly executed.

  If the output side is the final belt (YES in step S20), or the Y coordinate InEndY of the end value of the input side belt is equal to or less than the Y coordinate OutEndY of the end value of the output side belt (YES in step S26), a plurality of outputs If there is a belt process, a belt having a large number of transfer lines to the image processing unit 13 is selected (step S28 in FIG. 6). Then, as the processing of the selected belt, the input data is output to the image processing unit 13, temporarily stored in the internal buffer, only the necessary line data is output to the RAM 3, and the processing result of the image processing unit 13 is output to the RAM 3. (Step S30).

  Next, as processing of the belt that has not been selected, data is fetched from the RAM 3, the fetched data is output to the image processing unit 13, and the processing result of the image processing unit 13 is output to the RAM 3 (step S32).

  Next, it is determined whether or not the input belt is the final belt (step S34). If it is not the final belt (NO in step S34), the process returns to step S18 and the above-described processing is repeatedly executed. On the other hand, if the input side is the final belt (YES in step S34), the process ends.

Next, the process described above will be described in more detail.
FIGS. 7 to 10A, 10B, and 10C are conceptual diagrams for explaining the operation of the image data transfer unit 14 according to the present embodiment. FIG. 11 is a conceptual diagram showing the order of writing the processing results of the image processing unit 13 to the RAM 3 in the present embodiment. In the following description, the numerical values in parentheses indicate the number of lines.

First, processing of the first input belt 101 will be described with reference to FIG.
When the operation starts, the image data transfer unit 14 first calculates the Y coordinate (InEndY = number of belt lines (16) -1 = 15) of the lower end of the first input belt 101 (step S10). The Y coordinate (OutEndY = number of belt lines (8) + lower ring (2) −1 = 9) of the lower end on the output side of 101 is calculated (step S12).

  Next, as shown in FIG. 7, the image data transfer unit 14 starts data input from the image processing unit 12, and copies 0 line data of 2 lines among 0 to 15 line input data. 0 to 9 lines of data (first output belt 201) are added to 12 lines of data and output to the image processing unit 13 to perform an enlargement operation (twice), and the processing result data (0 to 7) Line) is written into the RAM 3 as shown at the left end of FIG. 11 (step S16). On the other hand, among the data input from the image processing unit 12, the image processing unit 13 stores 6 to 15 lines of data required after the next belt in the RAM 3 via the DMAC 9 (also in step S16). This completes the processing of the first input belt 101.

Next, the process of the 2nd input belt 102 is demonstrated with reference to FIG. 8 (a), (b).
First, the image data transfer unit 14 stores the Y coordinate (InEndY_old = InEndY = 15) of the lower end of the first input belt 101 and the Y coordinate (InEndY = InEndY (15) + input) of the lower end of the second input belt 102. The number of belt lines (16) = 31) is calculated (step S18).

  Next, since the output side is not the final belt (NO in step S20), the image data transfer unit 14 calculates the Y coordinate (OutEndY_old = OutEndY = 9) of the lower end of the first output belt 201 and outputs the second output. The Y coordinate OutEndY of the lower end of the belt 202 is calculated (step S22). In this case, since the output side is not the final belt, the Y coordinate OutEndY = OutEndY (9) + the number of output belt lines (8) = 17 at the lower end of the second output belt 202.

  Next, when the number of lines that can be output as the second output belt 202 in the second input belt 102 is calculated, OutEndY (17) −InEndY_old (15) = 2 (step S24). Since InEndY (31) is larger than OutEndY (17) (NO in step S26), the Y coordinate of the lower end of the third output belt 203 is calculated, OutEndY_old = OutEndY = 17, OutEndY = OutEndY (17) + output belt line The number (8) = 25 (step S22).

  Next, when the number of lines that can be output as the third output belt 203 in the second input belt 102 is calculated, OutEndY (25) −InEndY_old (15) = 10 is obtained (step S24). Since InEndY (31) is still larger than OutEndY (25) (NO in step S26), the Y coordinate of the lower end of the fourth output belt is calculated, OutEndY_old = OutEndY = 25, OutEndY = OutEndY (25) + output belt line The number (8) = 33 (step S22).

  Next, when the number of lines that can be output as the fourth output belt in the second input belt 102 is calculated, OutEndY (33) −InEndY_old (15) = 18 (step S24), InEndY (31) <OutEndY ( 33) (YES in step S26), and since all lines cannot be output, the processing of the second output belt 202 and the third output belt 203 is performed. At this time, among the second input belts 102, the number of lines that can be output as the third output belt 203 is larger than that of the second output belt 202, so the third output belt 203 is processed first ( Step S28).

  Therefore, as shown in FIG. 8A, the image data transfer unit 14 reads the 14 to 15 line data stored in the RAM 3 in the previous process from the RAM 3 via the DMAC 9, and receives the second input. Of the data of the belt 102, the data is added to the data of 16 to 25 lines (the third output belt 203), and is output to the image processing unit 13 as the data for 12 lines to perform the enlargement operation (twice). The resulting data (lines 16-23) is written into the RAM 3 as shown in the center of FIG. 11 (step S30).

  On the other hand, as shown in FIG. 8A, the image data transfer unit 14 includes 16 to 17 lines and 22 to 31 lines necessary for the image processing unit 13 after the next belt among the data inputs from the image processing unit 12. Are stored in the RAM 3 via the DMAC 9 (also in step S30).

  Next, as shown in FIG. 8B, the image data transfer unit 14 sends the 6 to 17 line data (second output belt 202) stored in the RAM 3 in the previous process via the DMAC 9. Data is read from the RAM 3 and output to the image processing unit 13 to perform an enlargement operation (doubled), and data (8 to 15 lines) as a result of the processing is written into the RAM 3 as shown at the right end of FIG. 11 (step S32). . Thus, the processing of the second input belt 102 ends.

Next, the process of the 3rd input belt 103 is demonstrated with reference to Fig.9 (a), (b).
The third input belt 103 is the same as the second input belt 102 described above, and will be described briefly. As shown in FIG. 9A, the image data transfer unit 14 reads 30 to 31 line data from the RAM 3 via the DMAC 9, and among the data of the third input belt 103, 32 to 41 line data. (Sixth output belt 206) is output to the image processing unit 13 as data for 12 lines to perform an enlargement operation (twice), and the processing result data (32 to 39 lines) is written to the RAM 3. (Step S30).

  On the other hand, as shown in FIG. 9A, the image data transfer unit 14 includes 32 to 33 lines and 38 to 47 lines necessary for the image processing unit 13 after the next belt among the data inputs from the image processing unit 12. Are stored in the RAM 3 via the DMAC 9 (also in step S30).

  Next, as shown in FIG. 9B, the image data transfer unit 14 sends the 22-33 line data (the fifth output belt 205) stored in the RAM 3 in the previous process via the DMAC 9. The data is read from the RAM 3 and output to the image processing unit 13 to perform an enlargement operation (doubled), and the processing result data (line 24 to 31) is written to the RAM 3 (step S32). Above, the process of the 3rd input belt 103 is complete | finished.

  Finally, the processing of the fourth input belt (input final belt) 104 will be described with reference to FIGS. First, the image data transfer unit 14 stores the Y coordinate (InEndY_old = InEndY = 47) of the lower end of the third input belt 103 and the Y coordinate (InEndY = InEndY (47) + input of the lower end of the fourth input belt 104. The number of belt lines (16) = 63) is calculated (step S18).

  Next, the output side calculates the Y coordinate (OutEndY_old = OutEndY = 41) of the lower end of the sixth output belt 206 that has been processed, and calculates the Y coordinate of the lower end of the seventh output belt 207 that has not yet been processed. Calculate (step S22). Since the output side is not the final belt, the Y coordinate OutEndY = OutEndY (41) + the number of output belt lines (8) = 49 at the lower end of the seventh belt 207 on the output side.

  Next, when the number of lines that can be output as the seventh output belt 207 in the fourth input belt 104 is calculated, OutEndY (49) −InEndY_old (47) = 2 (step S24). Since InEndY (63) is larger than OutEndY (49), the Y coordinate of the lower end of the eighth output belt 208 is calculated, OutEndY_old = OutEndY = 49, OutEndY = OutEndY (49) + number of output belt lines (8) = 57 (Step S22).

  Next, when the number of lines that can be output as the eighth output belt 208 in the fourth input belt 104 is calculated, OutEndY (57) −InEndY_old (47) = 10 is obtained (step S24). Although InEndY (63) is still larger than OutEndY (57) (YES in step S26), the output side is the final belt (YES in step S20), so the processing of the seventh output belt 207 and the eighth output belt 208 is performed. I will do it. At this time, in the fourth input belt 104, the number of lines that can be output as the eighth output belt 208 is larger than that in the seventh output belt 207, so the eighth output belt 208 is processed first ( Step S28).

  Therefore, as shown in FIG. 10A, the image data transfer unit 14 reads the data of 46 to 47 lines stored in the RAM 3 in the previous process from the RAM 3 through the DMAC 9, and receives the fourth input. Of the data of the belt 104, it is added to the data of 48 to 57 lines (eighth output belt 208), and is output to the image processing unit 13 as data for 12 lines to perform the enlargement operation (twice). The resulting data (48 to 55 lines) is written into the RAM 3 (step S30).

  On the other hand, as shown in FIG. 10A, the image data transfer unit 14 includes 48 to 49 lines and 54 to 63 lines necessary for the image processing unit 13 after the next belt among the data inputs from the image processing unit 12. Are stored in the RAM 3 via the DMAC 9 (also in step S30).

  Next, as shown in FIG. 10B, the image data transfer unit 14 transfers the 38-49 line data (seventh output belt 207) stored in the RAM 3 in the previous process via the DMAC 9. The data is read from the RAM 3 and output to the image processing unit 13 to perform an enlargement operation (double), and the processing result data (line 40 to 47) is written to the RAM 3 via the DMAC 9 (step S32).

  Next, as shown in FIG. 10C, the image data transfer unit 14 reads data of 54 to 63 lines (the ninth output belt 209) from the RAM 3 via the DMAC 9, and outputs the data of 63 lines to 2 lines. Copies and appends the data, outputs the data to the image processing unit 13 as 12-line data, performs an enlargement operation, and writes the data (56 to 63 lines) of the processing result to the RAM 3 via the DMAC 9 (also in step S32) ). Thus, the process of the fourth input belt 104 ends.

  As described above, in the present embodiment, when image data is transferred by the image processing units 12 and 13 (a plurality of modules) during image data processing, output data of the image processing unit 12 (upstream image processing module) is used. Data that can be processed by the image processing unit 13 (downstream image processing module) without being expanded on the RAM 3 (buffer memory) is directly transferred to the image processing unit 13 (downstream image processing module) and can be processed. Since data other than special data is transferred to the RAM 3 (buffer memory), the bus bandwidth of the entire system can be reduced by reducing the amount of image data exchanged with the external memory (RAM 3). .

  In this embodiment, when ring pixels located before and after the image data are required for image processing, the image processing unit 13 (downstream) is set so that the image data transfer to the RAM 3 (buffer memory) is minimized. Since the processing order of each processing unit of the image processing module) is changed, the amount of image data transmitted to and received from the RAM 3 (buffer memory) can be reduced, and the bus bandwidth of the entire system can be reduced. it can.

  More specifically, the transmission / reception amount with the RAM 3 (buffer memory) is read / write for 98 lines. When all the image data is stored in the RAM 3 as in the prior art, overlapping reading for ring pixels is performed, so that reading / writing for 156 lines, which is at least twice the image size, is performed. That is, in this embodiment, the data transfer amount is about 63%, and the reduced amount can be used for accessing the external memory of other modules.

  As described above, according to the above-described embodiment, the data transfer amount to the external memory can be greatly reduced as compared with the related art, so that the bandwidth usage of the data bus can be reduced and the entire image processing system can be reduced. Can be speeded up.

  In the above-described embodiment, the description has been made on the assumption that the processing capability of the upstream image processing module (image processing unit 12) is larger than the processing capability of the downstream image processing module (image processing unit 13). However, the present invention is not limited to this, and comparison means for comparing the processing capabilities of the upstream image processing module (image processing unit 12) and the downstream image processing module (image processing unit 13) is provided, and the upstream image processing module (image processing unit 12). ) Is equal to the processing capability of the downstream image processing module (image processing unit 13) or smaller than the processing capability of the downstream image processing module (image processing unit 13). Since there is no need to transfer image data to the RAM 3 as an external memory, the image data processed by the upstream image processing module (image processing unit 12) is not changed. It may be caused to process and transfer to a downstream image processing modules (the image processing unit 13).

As mentioned above, although several embodiment of this invention was described, this invention is not limited to these, The invention described in the claim, and its equal range are included.
Below, the invention described in the claims of the present application is appended.

(Appendix 1)
The invention according to attachment 1 is an image processing apparatus that divides image data and sequentially processes the divided image data, and includes a buffer memory and a plurality of image processing amounts that can be processed at a time. For each of the divided image data sequentially processed by the image processing module and the upstream image processing module, an amount of first partial image data that can be processed at one time by the downstream image processing module is converted into the downstream image processing. A second partial image data other than the first partial image data is transferred to the buffer memory, and the processing for the first partial image data is completed in the downstream image processing module; An image data transfer unit that transfers the second partial image data stored in the buffer memory to the downstream image processing module. An image processing apparatus characterized.

(Appendix 2)
According to the second aspect of the present invention, when the plurality of image processing modules sequentially process the divided image data, the image data transfer unit includes ring pixels positioned before and after the divided image data. When performing image processing with a ring pixel that requires input of image data including, among the divided image data processed next by the upstream image processing module, the downstream image processing module at once. A part of the second partial image data stored in the buffer memory is transferred to the third partial image when the processable amount of the third partial image data is transferred to the downstream image processing module. It is transferred to the downstream image processing module together with the third partial image data to be used as ring pixels located before and after the data. The image processing apparatus according to note 1,.

(Appendix 3)
According to the third aspect of the present invention, the image data transfer unit may transfer the second partial image data stored in the buffer memory before transferring the second partial image data to the downstream image processing module. The image processing apparatus according to appendix 2, wherein the third partial image data is transferred to the downstream image processing module in order to process data first.

(Appendix 4)
According to the fourth aspect of the present invention, the image data transfer unit includes the divided image processed next by the upstream image processing module out of the second partial image data and the third partial image data. The image processing apparatus according to appendix 3, wherein one that can output more data is first transferred to the downstream image processing module.

(Appendix 5)
In the invention according to attachment 5, the image data transfer unit includes at least an image processing amount of the upstream image processing module, an image processing amount of the downstream image processing module, a size of the ring pixel, and the divided image 5. The image processing apparatus according to claim 2, wherein a transfer amount to the downstream image processing module and a transfer amount to the memory are determined based on a data processing position. It is.

(Appendix 6)
The invention according to appendix 6 is an image processing method for dividing image data and sequentially processing the divided image data, wherein a plurality of image processing modules having different image processing amounts that can be processed at a time are provided. Out of the divided image data sequentially processed by the upstream image processing module, an amount of the first partial image data that can be processed at one time by the downstream image processing module is transferred to the downstream image processing module. A step of transferring second partial image data other than the first partial image data to a buffer memory, and after the processing on the first partial image data is completed in the downstream image processing module, Transferring the second partial image data stored in the buffer memory to the downstream image processing module. The image processing method according to.

(Appendix 7)
The invention according to appendix 7 includes a plurality of image processing modules having different image processing amounts that can be processed at one time in a computer of an image processing apparatus that divides image data and sequentially processes the divided image data. Out of the divided image data sequentially processed by the upstream image processing module, an amount of the first partial image data that can be processed at one time by the downstream image processing module is transferred to the downstream image processing module. A step of transferring second partial image data other than the first partial image data to a buffer memory, and after the processing on the first partial image data is completed in the downstream image processing module, And transferring the second partial image data stored in the buffer memory to the downstream image processing module. It is a program characterized by making it carry out.

1 CPU
2 ASIC
3 RAM
4 CCD
5 ROM
6 LCD
7 Keyboard 8 Power supply 9 DMAC
DESCRIPTION OF SYMBOLS 10 Memory control part 11 CCD control part 12, 13 Image processing part 14 Image data transfer part 15 LCD control part 16 Keyboard control part

Claims (7)

An image processing apparatus that divides image data and sequentially processes the divided image data,
Buffer memory,
A plurality of image processing modules having different image processing amounts that can be processed at one time;
For each of the divided image data sequentially processed by the upstream image processing module, an amount of the first partial image data that can be processed at one time by the downstream image processing module is transferred to the downstream image processing module, Second partial image data other than the first partial image data is transferred to the buffer memory, and stored in the buffer memory after the processing on the first partial image data is completed in the downstream image processing module. An image processing apparatus comprising: an image data transfer unit configured to transfer the second partial image data that has been transferred to the downstream image processing module. The image data transfer unit
An image with ring pixels that requires the plurality of image processing modules to input image data including ring pixels positioned before and after the divided image data when sequentially processing the divided image data. When processing,
Of the divided image data processed next by the upstream image processing module, the third partial image data that can be processed at once by the downstream image processing module is transferred to the downstream image processing module. At this time, in order to use a part of the second partial image data stored in the buffer memory as a ring pixel positioned before and after the third partial image data, the third partial image data is used together with the third partial image data. The image processing apparatus according to claim 1, wherein the image processing device is transferred to a downstream image processing module. The image data transfer unit
Before transferring the second partial image data stored in the buffer memory to the downstream image processing module, the third partial image data is processed in advance so that the third partial image data is processed. The image processing apparatus according to claim 2, wherein the image processing module is transferred to the downstream image processing module. The image data transfer unit
Of the second partial image data and the third partial image data, the one that can output more of the divided image data processed next by the upstream image processing module is the first downstream image. The image processing apparatus according to claim 3, wherein the image processing apparatus is transferred to a processing module. The image data transfer unit
Based on at least the image processing amount of the upstream image processing module, the image processing amount of the downstream image processing module, the size of the ring pixel, and the processing position of the divided image data, to the downstream image processing module The image processing apparatus according to claim 2, further comprising: determining a transfer amount to the buffer and a transfer amount to the memory. An image processing method for dividing image data and sequentially processing the divided image data,
Of a plurality of image processing modules having different image processing amounts that can be processed at one time, the amount that can be processed at one time by the downstream image processing module for each of the divided image data sequentially processed by the upstream image processing module Transferring the first partial image data to the downstream image processing module;
Transferring second partial image data other than the first partial image data to a buffer memory;
Transferring the second partial image data stored in the buffer memory to the downstream image processing module after the processing on the first partial image data is completed in the downstream image processing module; An image processing method comprising: A computer of an image processing apparatus that divides image data and sequentially processes the divided image data.
Of a plurality of image processing modules having different image processing amounts that can be processed at one time, the amount that can be processed at one time by the downstream image processing module for each of the divided image data sequentially processed by the upstream image processing module Transferring the first partial image data to the downstream image processing module;
Transferring second partial image data other than the first partial image data to a buffer memory;
Transferring the second partial image data stored in the buffer memory to the downstream image processing module after the processing on the first partial image data is completed in the downstream image processing module; A program characterized by being executed.

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