JP5863069B2 - Semiconductor device and manufacturing method - Google Patents

Description

  The present invention relates to a semiconductor device which is a III-V CMOS transistor formed in a semiconductor layer provided on a support substrate via an insulating film, and a manufacturing method.

  CMOS transistors using high mobility materials are expected to be applied to high-speed operation circuits such as power-saving devices and high-speed CPUs. In particular, in both the n-MOSFET and the p-MOSFET, a structure using a III-V group compound semiconductor having higher mobility than Si is expected. Further, application of a III-V compound semiconductor CMOS transistor in which a III-V compound semiconductor channel layer is formed on an Si substrate via an insulating film is expected.

  FIG. 18 shows a structure of a group III-V compound semiconductor device having a plurality of channels, which has been conventionally proposed, in which channels suitable for n-MOSFETs and p-MOSFETs are integrated. A buried oxide layer (BOX) layer 1802 is stacked on a Si substrate 1801, and a III-Sb layer 1803 and a III-As layer 1804 are stacked thereon. Here, the III-Sb layer 1803 includes a gate stack formed by stacking a High-K gate insulating layer 1806-1 and a metal gate layer 1807-1, and a metal source / drain layer 1805-1. A MOSFET is formed. The III-As layer 1804 includes a gate stack formed by stacking a High-K gate insulating layer 1806-2 and a metal gate layer 1807-2, and a metal source / drain layer 1805-2, and an n-MOSFET. Is configured.

S. Takagi et al., Solid-State Electron. 51, 526 (2007).

  However, in the conventional method, the layers that become the channels of the n-MOSFET and the p-MOSFET are different in type, such as the III-Sb layer 1803 and the III-As layer 1804, and therefore it is necessary to form each layer separately. (See Non-Patent Document 1).

  The present invention has been made in view of such problems. The object of the present invention is to form a III-As layer and a III-Sb layer in the same channel, control the channel polarity by electric field control, and n- An object of the present invention is to provide a semiconductor device and a manufacturing method which are III-V CMOS transistors capable of switching between a MOSFET and a p-MOSFET.

In order to solve the above-described problems, the present invention provides a semiconductor device, which includes a Si substrate, a first insulating film stacked on the Si substrate, and a semiconductor layer stacked on the insulating film. A semiconductor layer including a III-Sb layer and a III-As layer stacked on the III-Sb layer, a metal source / drain electrode formed on an upper surface or a side surface of the III-As layer , or III comprising a metal source and drain electrodes formed so as to be joined to the the -As layer the III-Sb layer, the III-as layer is configured as a common channel layer n-MOSFET and p-MOSFET cage, wherein the Si comprises a back gate electrode formed on the back surface of the substrate, a first back gate voltage acts as the said n-a MOSFET T by applying to the back gate electrode, Characterized in that it operates as the p-MOSFET by applying a second back gate voltage to the back gate electrode.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a second insulating film stacked on the semiconductor layer, and a metal front gate electrode formed on the second insulating film, further comprising a operates as the n-MOSFET by applying a third gate voltage to the front gate electrode, operates as the p-MOSFET by applying a fourth gate voltage to the front gate electrode It is characterized by that. That, characterized in that to control the polarity of the channel of a transistor made of single element p-channel and n-channel.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the III-As layer is InAs, and the III-Sb layer is GaSb or InGaSb.

  According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the film thickness of the III-As layer is 0.6 nm to 2.5 nm, and the III-Sb The film thickness of the layer is 0.6 nm or more and 20 nm or less.

Invention according to claim 5, in the semiconductor device according to any one of claims 1 to 4, wherein the semiconductor layer further comprises a second III-As layer, before Symbol III-Sb layer is the second It is characterized by being laminated on the III-As layer.

The invention according to claim 6 is a method of manufacturing a semiconductor device, comprising: laminating a first insulating film on a Si substrate; laminating a III-Sb etch stopper layer on an InAs substrate; Laminating a group III-V semiconductor layer on the III-Sb etch stopper layer, laminating a second insulating film on the group III-V semiconductor layer, the first insulating film and the second layer insulating the steps of bonding a film, and etching the InAs substrate and the III-Sb etch stopper layer, and Luz step to form the metal source and drain electrode on the group III-V semiconductor layer, wherein forming a back gate electrode on the back surface of the Si substrate, it characterized by having.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, a step of laminating a third insulating film on the III-V group semiconductor layer, and a step of forming on the third insulating film a step of laminating a metal front gate electrode, further comprising a.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the sixth aspect, the step of laminating the group III-V semiconductor layer includes the step of: Laminating a layer, laminating a second III-Sb layer on the first III-As layer, and laminating a second III-As layer on the second III-Sb layer. And a step.

The invention according to claim 9 is the method of manufacturing a semiconductor device according to claim 8, wherein the step of etching the InAs substrate and the III-Sb etch stopper layer uses hydrochloric acid having a concentration of 36%, and the InAs Selectively etching the substrate from the III-Sb etch stopper layer, and using an ammonium sulfide solution with a concentration of 0.6-1.0% to remove the III-Sb etch stopper layer from the first III-As layer. And selectively etching.

  According to the present invention, the dominant carrier polarity induced in the channel layer is controlled by controlling the voltage using the back gate electrode and the front gate electrode in the III-V-OI single channel structure. Therefore, the polarity of the channel can be controlled, and the operation of the III-V CMOS transistor can be performed in a single element transistor. A manufacturing method can be provided.

1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. (A) is an energy band figure, (b), (c) is a figure explaining the outline | summary of operation | movement of the III-V CMOS transistor by the single channel which concerns on one Embodiment of this invention. (A), (b) is a conceptual diagram of the metal source / drain junction of the III-V CMOS transistor by the single channel which concerns on one Embodiment of this invention. (A) is a figure which shows the laminated structure of a semiconductor, (b) is a band figure, (c) is a figure which shows the calculation result of the InAs layer film thickness dependence of the effective band gap of an InAs layer. (A) is a figure which shows the laminated structure of a semiconductor, (b), (c) is a figure which shows the calculation result of the carrier concentration distribution at the time of the voltage application in a single channel layer. (A), (b) is a figure which shows the calculation result of the film thickness dependence of the InAs layer and GaSb layer of the relationship between a carrier concentration when a back gate voltage is 0 V and a front gate voltage, (c) It is a figure which shows the calculation result of the back gate voltage dependence of the relationship between a carrier concentration when the film thickness of an InAs layer and a GaSb layer is made constant, and a front gate voltage. (A)-(d) is a figure which shows the mode of the improvement of the GaSb MOS interface by introduction | transduction of an InAs layer. (A) is a figure explaining the preparation procedure of the III-V-OIonSi substrate used with the III-V CMOS transistor which concerns on one Embodiment of this invention, (b)-(f) is III-V It is a figure which shows the preparation results of -OI on Si substrate. (A)-(d) is a figure which shows the XPS measurement result before and behind each selective etching. It is a figure which shows the result of the cross-sectional TEM image and EDX mapping measurement of the semiconductor which laminated | stacked the InAs / GaSb / InAs layer via the insulating film on Si substrate. (A) is a figure which shows the structure of the InAs / GaSb III-V CMOS transistor of the back gate structure which concerns on one Embodiment of this invention, (b)-(e) is a figure which shows the back gate operation | movement. is there. (A) is a figure which shows the structure of the InAs / GaSb III-V CMOS transistor of the front gate structure which concerns on one Embodiment of this invention, (b)-(e) is a figure which shows the front gate operation | movement. is there. (A), (b) is a figure which shows the effective electron mobility and effective hole mobility of InAs n-MOSFET and GaSb p-MOSFET in a back gate operation | movement, respectively. (A)-(c) is a figure which shows the preparation results of an InGaSb-OI board | substrate and an InAs / InGaSb / InAs-OI board | substrate. (A)-(d) is a figure which shows the device characteristic of InGaSb-OI p-MOSFET of a back gate structure. (A)-(d) is a figure which shows the structure of an InAs / InGaSb III-V CMOS transistor of a back gate structure, and its back gate operation | movement. It is a figure which shows the effective electron mobility and effective hole mobility of InAs n-MOSFET and InGaSb p-MOSFET in back gate operation | movement (a), (b) respectively. It is a figure which shows the structure of the III-V group compound semiconductor device which has multiple channels with respect to the conventional n-MOSFET and p-MOSFET.

  Hereinafter, embodiments of the present invention will be described in detail.

In the present invention, in order to make it possible to produce a III-V CMOS transistor using a single channel in which an III-Sb layer and a III-As layer are stacked on an insulating film, a substrate bonding method, epitaxial growth, III-V-OI (group III semiconductor-group V semiconductor-on insulator = insulator = Al ₂ O ₃ , insulating film is HfO ₂ , La ₂ O ₃ , ZrO _2, etc. manufactured by selective etching A substrate having a composite structure including one of the above may be used. In the present invention, the III-V-OI substrate has the same thickness as the III-Sb layer and the III-As layer so that the III-V CMOS transistor using a single channel is identical. The device can be operated as an n-MOSFET and a p-MOSFET.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. The BOX layer 102 is laminated on the Si substrate 101, and the III-Sb layer 103 and the III-As layer 104 are laminated in this order. A High-K gate insulating layer 106 and a metal front gate layer 107 are stacked on the gate stack to form a gate stack. Further, a metal source / drain layer 105 is formed for the III-Sb layer 103 and the III-As layer 104. At this time, Ni may be used as the source / drain metal, and the source / drain junction reaching the InAs and GaSb channels may be formed by alloying by a self-aligned process in a gate-first process.

  The film thickness of the III-As layer 104 is 0.6 nm or more and 2.5 nm or less, and the film thickness of the III-Sb layer 103 is 0.6 nm or more and 20 nm or less. The upper limit of the film thickness is determined by the reason described later, but the lower limit of the film thickness is that the thickness at which the film thickness can be precisely controlled and a layered thin film can be produced is about bilayer (0.6 nm). It is decided by.

  FIG. 2 (a) shows an energy band diagram, and FIGS. 2 (b) and 2 (c) are diagrams for explaining the outline of the operation of a single channel III-V CMOS transistor according to an embodiment of the present invention. Show. The band gap (FIGS. 2B and 2C) of the InAs layer in the III-V CMOS transistor is larger than that in the bulk state (FIG. 2A) due to the quantum confinement effect. As described above, the III-V CMOS transistor of the present invention can operate the n-MOSFET and the p-MOSFET with a single channel by controlling the polarity of the channel with an appropriate voltage.

  3A and 3B are conceptual diagrams of metal sources / drains of a single channel III-V CMOS transistor according to an embodiment of the present invention. Fermi level pinning of InAs and GaSb can provide a low Schottky barrier for each channel of InAs and GaSb and the metal source / drain.

4A shows a stacked structure of semiconductor layers, FIG. 4B shows an energy band diagram, and FIG. 4C shows a calculation result of the InAs film thickness dependence of the effective band gap of the InAs layer. . 4B and 4C show a GaSb layer 401, an InAs layer 402, an Al ₂ O ₃ layer 403 (corresponding to the High-K gate insulating layer 106 in FIG. 1), a gate layer 404 (the metal front gate in FIG. 1). The effective band gap is calculated when the film thickness T _InAs of the InAs layer 402 is changed. It can be seen that by reducing the film thickness T _InAs of the InAs layer 402, the effective band gap is increased by the quantum effect. Thus, by designing the thickness of the InAs layer to an appropriate value, not only the InAs layer can be used as an n-MOSFET channel but also an insulating layer when the GaSb layer is used as a p-MOSFET channel. Is possible.

FIG. 5A shows the stacked structure of the semiconductor layers, and FIGS. 5B and 5C show the calculation results of the carrier concentration distribution during voltage application in the single channel layer. The single channel layers used for the calculation are a back gate layer 501, an Al ₂ O ₃ layer 502 (corresponding to the BOX layer 102 in FIG. 1), an InAs layer 503, a GaSb layer 504, an InAs layer 505, and an Al ₂ O ₃ layer 506. A front gate layer 507 is sequentially stacked (corresponding to the High-K gate insulating layer 106 in FIG. 1). The thickness of each layer was 5 nm for the Al ₂ O ₃ layers 502 and 506, 1.5 nm for the InAs layers 503 and 505, and 20 nm for the GaSb layer 504. FIG. 5B shows the hole concentration distribution when 0 V is applied to the back gate layer 501 and −1 V is applied to the front gate layer 507. FIG. 5C shows 0 V to the back gate layer 501. The electron concentration distribution when 1 V is applied to the front gate layer 507 is shown.

  By applying an appropriate voltage, it can be seen that electrons are accumulated in the InAs layer and holes are accumulated in the GaSb layer as shown in FIG. Here, since it is calculated by the work function, it differs from the actual external voltage. It is considered that the channel polarity and device operation can be controlled with an appropriate voltage by appropriately selecting the work function of the gate electrode.

  FIGS. 6A and 6B show the calculation results of the film thickness dependence of the InAs layer and the GaSb layer in the relationship between the carrier concentration and the front gate voltage when the back gate voltage is 0 V. FIG. 4 shows the calculation result of the back gate voltage dependency of the relationship between the carrier concentration and the front gate voltage when the thickness of the InAs layer and the GaSb layer is constant. By applying an appropriate voltage to the back gate, the carrier concentration is controlled so that each of the InAs layer and the GaSb layer operates as an n-MOSFET and a p-MOSFET with respect to the front gate in a single channel. The polarity of the channel can be controlled. Thus, by using a single channel having an InAs / GaSb-OI structure, a III-V CMOS transistor that can operate as an n-MOSFET or a p-MOSFET can be manufactured.

  7A to 7D show how the GaSb MOS interface is improved by introducing the InAs layer. By inserting an InAs layer having a thickness of 1.5 nm, it was confirmed that the interface state in the conduction electron band was improved from the vicinity of the GaSb mid gap. In the InAs / GaSb-OI structure, not only the front gate side but also the interface on the back gate side is important. Therefore, an InAs layer is also introduced into the BOX layer side to form an InAs / GaSb / InAs-OI structure.

FIG. 8A is a diagram for explaining a manufacturing procedure of a III-V-OI on Si substrate used in a III-V CMOS transistor according to an embodiment of the present invention. FIGS. 8B to 8F show the results of manufacturing a III-V-OI on Si substrate. First, a GaSb layer 807, an InAs layer 806, a GaSb layer 805, an InAs layer 804, and an Al ₂ O ₃ layer 803 are sequentially stacked on an InAs (100) substrate 808. Separately, an Al ₂ O ₃ layer 802 is laminated on the Si (100) substrate 801.

Next, the Al ₂ O ₃ layer 803 provided on the semiconductor layer including the InAs (100) substrate 808 is bonded to the Al ₂ O ₃ layer 802 provided on the Si (100) substrate 801, and the InAs (100) The substrate 808 and the GaSb layer 807 are selectively etched. Here, etching in a manufacturing process of the III-V-OI on Si substrate will be described. The selective etching is performed using hydrochloric acid and an ammonium sulfide solution. First, the InAs (100) substrate 808 is thinned with sulfuric acid / hydrogen peroxide, and the InAs (100) substrate 808 is selectively etched from the GaSb layer 807, which is a GaSb etch stopper layer, using hydrochloric acid having a concentration of 36%. This process is the same as for GaSb single layer. If the Ga composition is 1, since the GaSb layer 807 is hardly etched with hydrochloric acid, a high selectivity can be obtained for selective etching with the InAs (100) substrate 808. However, when In enters like InGaSb, the selectivity with hydrochloric acid drops, so care must be taken.

  When the etching stopper layer GaSb layer 807 is selectively etched from the InAs layer 806, an ammonium sulfide solution having a concentration of 0.6 to 1.0% is used. In the case of an alkaline solution, selective etching is possible because the Sb-based etching rate is faster than that of the As-based solution. However, for example, ammonia water with a concentration of 29% has a high As-based etching rate, and therefore, when the InAs layer is thin, it is difficult to use it for selective etching. Therefore, when the InAs layer 806 is as thin as about 1-2 nm, the InAs layer 806 is hardly etched, and an ammonium sulfide solution having a concentration of 0.6 to 1.0% capable of sulfur termination on the surface of the InAs layer 806 is used. There is a need to.

  9A to 9D show XPS (X-ray Photoelectron Spectroscopy) measurement results before and after each selective etching. This shows that selective etching of InAs and GaSb was performed by using hydrochloric acid and an ammonium sulfide solution.

In this way, by using the substrate bonding method and selective etching, the InAs / GaSb / InAs layer is integrated on the Si substrate through the insulating film (Al ₂ O ₃ ) with a 2-inch substrate size. Can do. In FIG. 1, the III-As layer 104 corresponds to the InAs layer 806, the III-Sb layer 103 corresponds to the GaSb layer 805, and the BOX layer 102 corresponds to the Al ₂ O ₃ layers 802 and 803. The size of the substrate may be larger or smaller than this.

  FIG. 10 shows a cross-sectional TEM image and EDX (Energy Dispersive X-ray Spectroscopy) mapping measurement result of a semiconductor in which an InAs / GaSb / InAs layer is stacked on an Si substrate via an insulating film. Show. FIG. 10 also shows that the InAs / GaSb / InAs layer integrated on the Si substrate maintains good crystallinity. This method for manufacturing a substrate for III-V CMOS transistor can be applied even when the thickness of the InAs layer is 1.5 nm, and shows the high selectivity of the selective etching used in the present invention.

(Embodiment 2)
FIG. 11A shows the structure of an InAs / GaSb III-V CMOS transistor having a back gate structure according to an embodiment of the present invention, and FIGS. 11B to 11E show the back gate operation. As shown in FIG. 11A, the transistor includes an Al back gate electrode 1001, an n ⁺ -Si (100) layer 1002, an Al ₂ O ₃ BOX layer 1003, an InAs layer 1004 that forms an InAs / GaSb-OI channel, and GaSb. A layered structure of a layer 1005, an InAs layer 1006, and a source / drain electrode in which a Ni layer 1007 and an Al layer 1008 are stacked. The InAs layers 1004 and 1006 have a thickness of 2.5 nm, and the GaSb layer 1005 has a thickness of 20 nm.

  Here, the front gate side can be regarded as a state in which a certain voltage is applied although there is no electrode. As a result, the InAs layer 1004 and the GaSb layer 1005 operate as an n-MOSFET and a p-MOSFET, respectively. Here, it was confirmed that when the thickness of the InAs layer 1004 is 5 nm or more, only the n-MOSFET operation is performed.

(Embodiment 3)
FIG. 12A shows the structure of a front gate InAs / GaSb III-V CMOS transistor according to an embodiment of the present invention, and FIGS. 12B to 12E show the front gate operation. As shown in FIG. 12A, the transistor includes an Al back gate electrode 1101, an n ⁺ -Si layer 1102, an Al ₂ O ₃ BOX layer 1103, an InAs layer 1104 forming an InAs / GaSb-OI channel, a GaSb layer 1105, The InAs layer 1106 is formed by a laminated structure, a source / drain electrode made of a Ni layer 1007, an Al ₂ O ₃ layer 1108, and a Ni front gate electrode 1109. The InAs layer 1106 has a thickness of 2.5 nm, and the GaSb layer 1105 has a thickness of 20 nm.

  Here, it was confirmed that by applying an appropriate voltage to the back gate, the InAs layer 1106 and the GaSb layer 1105 operate as an n-MOSFET and a p-MOSFET, respectively, in a single element. In the present embodiment, when −0.5 V is applied to the back gate, it operates as an n-MOSFET, and when −2 V is applied, it operates as a p-MOSFET.

FIGS. 13A and 13B show effective electron mobility and effective hole mobility of the InAs n-MOSFET and the GaSb p-MOSFET, respectively, in the back gate operation. When the thickness of the InAs layer is 2.5 nm, the InAs n-MOSFET exceeds the mobility of the SOI MOSFET having the same thickness. Further, when the thickness of the InAs layer was 5 nm, the effective electron mobility exceeded 1200 cm ² / Vs.

  On the other hand, the GaSb layer is not high in mobility as compared with Si because the GaSb single layer has a high interface state density at the GaSb MOS interface. However, mobility exceeding Si can be realized by introducing an InAs layer as a surface immobile layer and improving the GaSb MOS interface.

  From the above, III-V CMOS operation is possible in an III-V CMOS transistor composed of a single channel layer of InAs / GaSb, and mobility exceeding Si can be realized in each of an n-MOSFET and a p-MOSFET.

  In order to improve the mobility of the p-MOSFET in the III-V CMOS transistor, introduction of an InGaSb layer was examined. 14A to 14C show the results of manufacturing an InGaSb-OI substrate and an InAs / InGaSb / InAs-OI substrate. The result of the XRD measurement shows that the InGaSb-OI substrate and the InAs / InGaSb / InAs layer retain good crystallinity.

  In the second and third embodiments, the semiconductor layer in which the III-As layer, the III-Sb layer, and the III-As layer are stacked is used, but the III-Sb layer, the III-As layer, and the III-Sb layer are stacked. A semiconductor layer may be used.

(Embodiment 4)
15A to 15D show device characteristics of an InGaSb-OI p-MOSFET having a back gate structure. The InGaSb-OI p-MOSFET has a structure in which InAs / GaSb / InAs in FIG. 11A is replaced with InGaSb. FIG. 15 (a) -0.05 V to V _D, -0.5 changes to V _G of I _D when the V (-3~3 V), FIG. 15 (b) 3 to the V _G FIG. 15C shows the change in I _D when V _D is −0.05 V and −1 V when I _D is changed at −3 V with respect to V _D (0 to −0.5 V). changes to V _G (-3 to 3 V), FIG. 15 (d) show no changes to V _D (0~-1 V) of I _D when changing in. 3 to-3 V to V _G, respectively Yes. FIG. 15C also shows data when InGaSb is replaced with GaSb for comparison. This result, InGaSb-OI p-MOSFET can be seen to increase the current value I _D as compared to the GaSb-OI p-MOSFET.

(Embodiment 5)
FIGS. 16A to 16D show the structure of an InAs / InGaSb III-V CMOS transistor having a back gate structure and its back gate operation. The InAs / InGaSb III-V CMOS transistor having a back gate structure has a structure in which the InAs / GaSb / InAs GaSb in FIG. 11A is replaced with InGaSb. Here, the thickness of the InAs layer is 2.5 nm, and the thickness of the InGaSb layer is 20 nm. Here, the front gate side can be regarded as a state in which a certain voltage is applied although there is no electrode. As a result, it was confirmed that the InAs layer and the InGaSb layer operate as an n-MOSFET and a p-MOSFET, respectively. Here, when the thickness of the InAs layer is 5 nm or more, only the n-MOSFET operation is performed.

  17A and 17B show the effective electron mobility and effective hole mobility of the InAs n-MOSFET and InGaSb p-MOSFET, respectively, in the back gate operation. When the thickness of the InAs layer is 2.5 nm, the mobility of the SOI MOSFET having the same thickness is exceeded. On the other hand, the InGaSb layer realizes mobility exceeding Si even in an InGaSb single layer, and the mobility can be improved by introducing the InAs layer as a surface immobile layer and improving the InGaSb MOS interface. .

  Similarly, III-V CMOS operation is also possible in an III-V CMOS transistor composed of a single channel layer of InAs / InGaSb, and mobility exceeding Si can be realized in each of an n-MOSFET and a p-MOSFET.

101, 801, 1701, 1801 Si substrate 102, 1802 BOX layer 103, 1803 III-Sb layer 104, 1804 III-As layer 105, 1805 Metal source / drain layer 106, 1806 High-K gate insulating layer 107, 1807 Metal gate Layer 401, 504, 805, 807, 1005, 1105, 1705, 1707 GaSb layer 402, 503, 505, 804, 806, 1004, 1006, 1104, 1106, 1704, 1706 InAs layer 403, 502, 506, 802, 803 , 1108,1702,1703 Al ₂ O ₃ layer 404 gate layer 501 back gate layer 507 front gate layer 808,1708 InAs (100) substrate 1001,1101 Al substrate 1002,1102 n ⁺ -S (100) layers 1003,1103 Al ₂ O ₃ BOX layer 1007,1107,1109 Ni layer 1008 Al layer

Claims (9)

A Si substrate;
A first insulating film laminated on the Si substrate;
A semiconductor layer stacked on the insulating film, the semiconductor layer including a III-Sb layer and a III-As layer stacked on the III-Sb layer;
The III-As layer on the top surface or side to form made metal source and drain electrodes or the metal source and drain electrodes formed so as to be bonded to the III-As layer and the III-Sb layer,
With
The III-As layer is configured as a channel layer common to the n-MOSFET and the p-MOSFET,
The Si comprises a back gate electrode formed on the back surface of the substrate, said first back gate voltage acts as the said n-a MOSFET T by applying to the back gate electrode, the second to the back gate electrode wherein a operating as the p-MOSFET by applying a back gate voltage. A second insulating film stacked on the semiconductor layer;
The second insulating anda metal front gate electrode formed on the membrane operates in said n-a MOSFET T by applying a third gate voltage to the front gate electrode, the front gate electrode the semiconductor device according to claim 1, characterized in that to operate as the p-MOSFET by applying a fourth gate voltage.   The semiconductor device according to claim 1, wherein the III-As layer is InAs, and the III-Sb layer is GaSb or InGaSb.   The film thickness of the III-As layer is 0.6 nm or more and 2.5 nm or less, and the film thickness of the III-Sb layer is 0.6 nm or more and 20 nm or less. 4. The semiconductor device according to any one of 3.   5. The semiconductor device according to claim 1, wherein the semiconductor layer further includes a second III-As layer, and the III-Sb layer is stacked on the second III-As layer. The semiconductor device described. Laminating a first insulating film on a Si substrate;
Laminating a III-Sb etch stopper layer on an InAs substrate;
Laminating a III-V semiconductor layer on the III-Sb etch stopper layer;
Laminating a second insulating film on the III-V semiconductor layer;
Bonding the first insulating film and the second insulating film;
Etching the InAs substrate and the III-Sb etch stopper layer;
And Luz step to form the metal source and drain electrode on the group III-V semiconductor layer,
Forming a back gate electrode on the back surface of the Si substrate;
A method for manufacturing a semiconductor device, comprising: Laminating a third insulating film on the III-V semiconductor layer;
Laminating a metal front gate electrode on the third insulating film;
The method of manufacturing a semiconductor device according to claim 6, further comprising: The step of stacking the III-V semiconductor layer includes
Laminating a first III-As layer on the III-Sb etch stopper layer;
Laminating a second III-Sb layer on the first III-As layer;
Laminating a second III-As layer on the second III-Sb layer;
The method of manufacturing a semiconductor device according to claim 6, comprising: Etching the InAs substrate and the III-Sb etch stopper layer selectively etching the InAs substrate from the III-Sb etch stopper layer using hydrochloric acid having a concentration of 36%;
Selectively etching the III-Sb etch stopper layer from the first III-As layer using an ammonium sulfide solution having a concentration of 0.6-1.0%;
The method of manufacturing a semiconductor device according to claim 8, comprising: