JP5861765B2 - Optical receiver and optical receiving method - Google Patents

Description

  The present invention relates to an optical receiver and an optical reception method.

  In recent years, with an increase in the amount of traffic in optical transmission, a technique capable of high-quality data communication is demanded even in high-speed transmission of about 100 Gbps, which is greatly affected by optical dispersion. One such technology is digital coherent technology. As an optical communication apparatus to which the digital coherent technology is applied, for example, there is an optical communication apparatus using a DP-QPSK (Dual Polarization-Quadrature Phase Shift Keying) modulation method that is being standardized by OIF (Optical Internetworking Forum). In this optical communication apparatus, an optical receiver receives a signal multiplexed in a polarization state orthogonal to the optical transmitter. The optical receiver has a local light source (for example, LD: Laser Diode) having substantially the same wavelength as the received signal light, and causes the output light to interfere with the received signal light so that two (X, Y) polarizations To an electrical signal of the IQ component (coherent detection). The converted signal is subjected to AD (Analog / Digital) conversion, is subjected to distortion correction and error correction, and is output to the outside as an information signal of 100 Gbps.

JP 2010-93656 A JP 2010-80665 A JP 2008-109562 A

  However, optical coherent transmission by the above-described optical communication device has the following problems. That is, prior to AD conversion, the receiver of the optical communication apparatus optimizes an input electric signal within a dynamic range of an ADC (Analog Digital Converter), thereby reducing an error rate associated with decoding. The receiver reduces the level of the input analog signal at the time of optimization. Along with this, the gain (gain) of the clock component extracted from the input signal in the subsequent digital signal processing circuit is reduced. The decrease in the gain of the clock component makes it difficult to establish synchronization, and causes a decoding error in combination with the secular change and the characteristic variation between lanes. An increase in error rate at the receiver hinders improvement in optical transmission quality. On the other hand, when the receiver increases the level of the analog signal in order to maintain the gain of the clock component, the signal amplitude exceeds the dynamic range of the ADC. As a result, the digital signal processing circuit cannot extract a data component from the digital signal after AD conversion.

  The disclosed technology has been made in view of the above, and an object thereof is to provide an optical receiver and an optical reception method capable of improving optical transmission quality.

  In order to solve the above-described problems and achieve the object, an optical receiver disclosed in the present application receives coherent light in one aspect. The optical receiver includes an amplitude adjustment circuit, a signal processing circuit, and a control circuit. The amplitude adjustment circuit adjusts the amplitude of the input signal and outputs it. The signal processing circuit inputs a digital signal generated using the analog signal output from the amplitude adjustment circuit, extracts a clock component from the digital signal, and establishes synchronization between the clock component and the data component. Then, the data component is extracted and processed from the digital signal. The control circuit sets the amplitude of the analog signal to a first amplitude before establishment of synchronization by the digital signal, and after the establishment of synchronization, the amplitude after the setting is smaller than the first amplitude. Change to the second amplitude.

  According to one aspect of the optical receiver disclosed in the present application, it is possible to improve the optical transmission quality.

FIG. 1 is a diagram illustrating the configuration of the optical receiver according to the embodiment. FIG. 2 is a flowchart for explaining the operation of the optical receiver according to the embodiment. FIG. 3 is a diagram illustrating the configuration of the CDR circuit according to the embodiment. FIG. 4 is a diagram for explaining the operation of the phase detector according to the embodiment. FIG. 5A is a diagram illustrating an example of waveforms of two signals input to the phase detector according to the embodiment. FIG. 5B is a diagram illustrating an example of a waveform of a signal output from the phase detector according to the embodiment. FIG. 6 is a diagram illustrating the configuration of the digital coherent receiving unit according to the embodiment. FIG. 7A is a diagram for explaining a synchronization establishment method when the input amplitude is small. FIG. 7B is a diagram for explaining a synchronization establishment method when the input amplitude is large. FIG. 8 is a diagram illustrating an example of the gain characteristic of the OA of the optical receiver according to the embodiment. FIG. 9 is a diagram illustrating a configuration of an optical receiver according to a modification.

  Hereinafter, embodiments of an optical receiver and an optical receiving method disclosed in the present application will be described in detail with reference to the drawings. The optical receiver and the optical receiving method disclosed in the present application are not limited by the following embodiments.

  FIG. 1 is a diagram illustrating a configuration of an optical receiver 100 according to an embodiment. The optical receiver 100, together with an optical transmitter (not shown), constitutes an optical communication apparatus using the DP-QPSK modulation method being standardized by OIF. In the optical transmitter, a 100 Gbps information signal to be transmitted is converted into four 28 Gbps signals in an error correction / encoding circuit and then input to the polarization multiplexed optical modulator. The optical transmitter has a wavelength variable light source using a narrow linewidth semiconductor laser as a transmission light source. The output light from the transmission light source is separated into two lights inside the polarization multiplexing optical modulator and then input to two QPSK modulators, each having a modulation speed of 28 Gsps (Giga symbol per second). It is converted into value phase modulated light. The signal output from each QPSK modulator is multiplexed and output by the polarization combiner into orthogonal polarization states (S polarization and P polarization). As a result, the transmission speed of the polarization multiplexed signal is 112 Gbps. As the QPSK modulator, a composite optical modulator that orthogonally synthesizes an input electric signal and outputs it can be used.

  On the other hand, as shown in FIG. 1, the optical receiver 100 includes a polarization separator 101, an X polarization receiver 102, a Y polarization receiver 103, an LD (Laser Diode) 104, a polarization separator 105, and a TIA ( Trans Impedance Amplifiers) 106a to 106d and AGC (Automatic Gain Controller) 107a to 107d. The optical receiver 100 also includes OA (Output Adjuster) 108a to 108d, capacitors 109a to 109d, offset adjusters 110a to 110d, high-speed ADCs 111a to 111d, a digital signal processing circuit 112, and a control circuit 113. Each of these components is connected so that signals and data can be input and output in one direction or in both directions.

  The optical receiver 100 includes an LD 104 as a local light source having the same wavelength as that of the received signal light, and performs coherent detection by causing the output light from the LD 104 to interfere with the received signal light and converting it into an electrical signal. Coherent detection has strong polarization dependence. For this reason, one polarization receiver can receive only an optical signal having the same polarization state as that of the local light. Therefore, the optical receiver 100 is provided with two polarization separators 101 and 105 at a portion where a reception signal is input, and separates the reception signal into two orthogonal polarization components (X component and Y component). By adopting such a configuration, two receivers 102 and 103 are required to receive one optical signal, but the optical receiver 100 performs polarization multiplexing of signal light and doubles the amount of information transmission. As a result, it is possible to compensate for a decrease in transmission speed accompanying polarization component separation.

  The polarization separator 101 separates the optical signal P1 input at 112 Gbps into two orthogonal polarization components. The X polarization receiver 102 includes an optical 90-degree hybrid 102a and two balanced photodiodes 102b and 102c. The optical 90-degree hybrid 102a receives signal light and local light (LD light). The optical 90-degree hybrid 102a has a set of output lights P7 and P8 obtained by causing these lights to interfere with each other in the same phase (I) and in the opposite phase (Q), and orthogonal (90 degrees, X) and inverse orthogonal (-90). A total of four lights with a set of output lights P9 and P10 interfered with each other at Y degree) are output. The latter-stage balanced photodiodes 102b and 102c receive the two sets of the output lights P7 to P10 differentially. Accordingly, the balanced photodiodes 102b and 102c can cancel unnecessary DC components from the signal light and the local light, and can efficiently extract only the beat component of each light. The balanced photodiodes 102b and 102c convert the received optical signals P7 to P10 separated into a total of four components, that is, the IQ component of the X polarization and the IQ component of the Y polarization into electric signals E1 and E2 (current).

  Similarly, the Y polarization receiver 103 has an optical 90-degree hybrid 103a and two balanced photodiodes 103b and 103c. The configuration and operation of the Y polarization receiver 103 are the same as the configuration and operation of the X polarization receiver 102 except that the polarization component to be received is the Y component. Therefore, the same reference numerals are used for common components, and detailed description thereof is omitted.

  The TIAs 106a to 106d receive electric signals E1 to E4 output from the balanced photodiodes 102b, 102c, 103b, and 103c, respectively. That is, the TIAs 106a and 106b receive the in-phase interference component (I) of the received optical signals P7 and P8 and the quadrature interference component (Q) of the local light signals P9 and P10 from the two balanced photodiodes 102b and 102c, respectively. To do. Similarly, the TIAs 106c and 106d transmit the in-phase interference component (I) of the received optical signals P11 and P12 and the quadrature interference component (Q) of the local light signals P13 and P14 from the two balanced photodiodes 103b and 103c, respectively. input. The TIAs 106a to 106d amplify the input electric signals E1 to E4 by impedance conversion and output the electric signals as electric signals E5 to E8.

  The AGCs 107a to 107d control the electric signals E5 to E8 input from the TIAs 106a to 106d to a preset amplitude value. The OAs 108a to 108d adjust the amplitudes of the input signals E9 to E12 from the AGCs 107a to 107d and output them. The OAs 108a to 108d have four lanes caused by imperfections in the characteristics of the analog portion (such as the X polarization receiver 102, the Y polarization receiver 103, the TIAs 106a to 106d, the AGCs 107a to 107d, and the high speed ADCs 111a to 111d). Signal quality degradation due to variations between them is individually suppressed and normalized.

  The capacitors 109a to 109d are passive elements that store and discharge the electric signals E13 to E16 input from the OAs 108a to 108d, respectively, by electrostatic capacity. Based on an instruction from the control circuit 113, the offset adjusters 110a to 110d give a bias to the high-speed signals E17 to E20 that are DC (Direct Current) cut so as to be within the input range of the high-speed ADCs 111a to 111d.

  When the high-speed ADCs 111a to 111d input a total of four electrical signals E21 to E24 of the IQ component of the X polarization and the IQ component of the Y polarization, each signal D1 is AD-converted at high speed, and the signal D1 converted into a digital signal To D4 are output to the subsequent digital signal processing circuit 112. The high-speed ADCs 111a to 111d take in the analog signals E21 to E24 at a sampling frequency that is at least twice that of the received signal, convert the analog signals E21 to E24 into digital signals D1 to D4, and output them to the digital signal processing circuit 112.

  When the digital signal processing circuit 112 receives the digital signals D1 to D4 output from the high-speed ADCs 111a to 111d, the digital signal processing circuit 112 performs various processes on the digital signals D1 to D4 and performs error correction based on instructions from the control circuit 113. After that, it is output to the outside as a 100 Gbps information signal D5. The digital signal processing circuit 112 performs processing such as light source frequency offset compensation, carrier phase estimation, chromatic dispersion compensation, and polarization mode dispersion compensation, for example.

  The control circuit 113 constantly monitors the OAs 108a to 108d for amplitude adjustment and the digital signals D1 to D4 after AD conversion for each lane of a high-speed signal of 28 Gbps or more, and applies feedback control to the OAs 108a to 108d. That is, the control circuit 113 monitors the data after AD conversion by firm processing, and feeds back the feedback to the OAs 108a to 108d so as to optimize the amplitudes of the input signals E21 to E24 within the dynamic range specific to each of the high speed ADCs 111a to 111d. Take control. As a result, the data component can be extracted in the digital signal processing circuit 112.

  Next, the operation will be described. FIG. 2 is a flowchart for explaining the operation of the optical receiver 100 according to the embodiment. When the control circuit 113 of the optical receiver 100 detects the input of the optical reception signal to the polarization beam splitter 101 with the cancellation of the optical power LOS (Loss Of Signal) (S1), the control circuit 113 sets the value of the signal amplitude in the OAs 108a to 108d. Adjust to a higher value (S2). That is, the control circuit 113 constantly monitors an RMS (Root Mean Square) value after AD conversion, and feedback-controls the value of the signal amplitude to a higher amplitude value set in advance. The higher amplitude value is an amplitude value by which the clock component necessary for the digital signal processing circuit 112 to establish line synchronization can be extracted from the input signals D1 to D4, and preferably 600 mVpp or more (for example, about 700 mVpp). ).

  In S3, the control circuit 113 determines whether line synchronization is established in the high-speed ADCs 111a to 111d based on the feedback control signal F1 (see FIG. 1) input from the high-speed ADCs 111a to 111d via the digital signal processing circuit 112. I do. When line synchronization is established as a result of the determination (S3; Yes), the control circuit 113 causes the decrease in the amplitude value set higher in S2 to the OAs 108a to 108d by the feedback control signal F2 (see FIG. 1). Instruct (S4). Thereby, when each value of the signal amplitude in OA108a-108d is settled in the input range of corresponding high-speed ADC 111a-111d (S5; Yes), the control circuit 113 judges that the optimization of the amplitude was completed. The signal communication state is maintained (S6).

  On the other hand, if there is an amplitude value that does not fall within the input range of the corresponding high-speed ADC 111a to 111d among the signal amplitude values in the OAs 108a to 108d in S5 (S5; No), the process returns to S4 again. The control circuit 113 further reduces the amplitude value. The amplitude value lowering process is repeatedly executed until the signal amplitude values in all the OAs 108a to 108d are within the input range (optimized), and ends when the optimization is completed.

  Note that the control circuit 113 may individually execute the amplitude value reduction process for only the lanes (for example, one) exceeding the input range, or for a plurality of lanes (for example, 2 to 4). May be executed uniformly. The amplitude value of the input range is an amplitude value by which the digital signal processing circuit 112 can extract a data component to be processed from the input signals D1 to D4, and preferably 200 to 600 mVpp (for example, about 300 to 500 mVpp). It is.

  If the line synchronization is not established even though the amplitude value is set higher in S3, the control circuit 113 sets the amplitude value once set in S2 until the line synchronization is established. Increase gradually. In other words, the control circuit 113 holds in advance an upper limit value (for example, 10 times) of the number of times of increasing the amplitude value as a count value, and gradually increases the amplitude value until the increase number (natural number N times) reaches the count value. (S7). As a result, when the line synchronization is established (S3; Yes), the control circuit 113 starts decreasing each value of the signal amplitude in the OAs 108a to 108d (S4). On the other hand, while the line synchronization is not established (S3; No), the control circuit 113 increases the amplitude value until the number of increase of the amplitude value reaches the upper limit count value (S7; Yes) (S7). ; No, S2).

  When the initial setting value is 600 mVpp with respect to the increase in amplitude value in S2, the control circuit 113 increases the amplitude value with a width of, for example, about 10 to 20 mVpp. Further, the increment per amplitude value need not be constant every time. For example, the control circuit 113 may increase the amplitude value by 20 mVpp for the first five times and increase the amplitude value by 10 mVpp for the subsequent five times. In addition, the upper limit value, which is a determination index for determining whether to increase the amplitude value for establishing synchronization, does not necessarily need to be set by the number of times (for example, 10 times), and may be set based on the amplitude value itself. Good. In this aspect, an upper limit value of, for example, 800 mVpp is set as the count value, and in S7, the current amplitude value is compared with the upper limit value.

  Next, a method for extracting a clock component will be described with reference to FIGS. In addition, the reason why the optical receiver 100 increases the amplitude of the signal input to the digital signal processing circuit 112 to facilitate the extraction of the clock component and improve the characteristics until the synchronization is established.

  FIG. 3 is a diagram illustrating a configuration of a CDR (Clock Data Recovery) circuit 200 according to the embodiment. As shown in FIG. 3, the CDR circuit 200 includes a buffer 201, a PLL (Phase Locked Loop) circuit 202, and a data decoding circuit (DECoder) 203. Furthermore, the PLL circuit 202 includes a phase detector (PD) 202a, an LPF (Low Pass Filter) 202b, and a VCO (Voltage Controlled Oscillator) 202c. Each of these components is connected so as to be able to input and output signals in one direction or in both directions.

  In high-speed optical transmission of about 100 Gbps, a clock component is included in a transmitted digital signal. The CDR circuit 200 has a function of receiving a signal on a transmission line in which a clock component is superimposed on a data component and separating a digital signal into a clock component and a data component, and the digital signal processing circuit of the optical receiver 100 112 is realized. In particular, in digital coherent communication, the CDR circuit 200 extracts a clock component from, for example, four serial signals encoded (FEC (Forward Error Correction) encoding, error correction, etc.) on the transmitter side. This clock component is used as a sampling clock in the high-speed ADCs 111a to 111d.

  The digital signal processing circuit 112 on the receiving side needs to decode both clock and data components. Therefore, as shown in FIG. 3, the clock component and the data component input to the PLL circuit 202 first pass through the buffer 201 and are branched into two paths. The digital signal D6 transmitted through one path is input to the PLL circuit 202 that extracts the clock component, and the digital signal D9 transmitted through the other path is input to the data decoding circuit 203 that generates the data component. Entered. The phase detector 202a receives two digital signals D6 and D7 and outputs a digital signal D8 corresponding to the phase difference between these signals. For example, the phase detector 202a generates a digital signal D8 such that the output voltage becomes 0 V when the phase difference between the two input signals D6 and D7 is 90 degrees, and outputs the digital signal D8 to the downstream LPF 202b.

  Next, taking the mixer type phase detector as an example, the operation of the phase detector 202a will be described. FIG. 4 is a diagram for explaining the operation of the phase detector 202a according to the embodiment. As shown in FIG. 4, a sine wave digital signal D6 is input to a mixer-type phase detector 202a via an RF (Radio Frequency) port. Similarly, a rectangular wave digital signal D7 is input to the mixer type phase detector 202a via a LO (Local Oscillator) port. The digital signals D6 and D7 having different waveforms are combined and then input to the LPF 202b as an output signal D8 of the mixer via an IF (Intermediate Frequency) port. The digital signal D8 becomes a positive DC voltage by the LPF 202b and is output as the digital signal D10.

FIG. 5A is a diagram illustrating an example of waveforms of two signals input to the phase detector 202a according to the embodiment. In FIG. 5A, time (unit: second) is defined on the x-axis, and input signal voltage (unit: V) is defined on the y-axis. As shown in FIG. 5A, the digital signal D6 described above draws a sine wave having an amplitude of 0.5 V and a wavelength of 10 ns, and the digital signal D7 described above is a rectangular wave having the same phase, amplitude, and wavelength as the digital signal D6. Draw. Therefore, when these digital signals D6 and D7 are combined by the phase detector 202a, a waveform as shown in FIG. 5B is generated. FIG. 5B is a diagram illustrating an example of a waveform of a signal output from the phase detector 202a according to the embodiment. As shown in Figure 5B, the digital signal D8 described above, when through the LPF202b, high-frequency component is removed, as a digital signal D10 having a positive DC voltage _{V op,} is output from LPF202b.

The output voltage V _op from the LPF 202b becomes a control voltage for the VCO 202c. Therefore, if the amplitude of the digital signal D6 (corresponding to the digital signals D1 to D4 shown in FIG. 1) is small, the voltage V _op, that is, the VCO 202c control voltage also becomes small, and as a result, the followable clock speed of the VCO 202c decreases. At the same time, as the amplitude of the digital signal D6 decreases, the value of T _r / T _f also decreases (gradual inclination), and is easily affected by noise and the like. As a result, jitter performance is degraded. That is, as the amplitude of the input signal to the digital signal processing circuit 112 decreases, it becomes difficult to establish synchronization between the clock component and the data component included in the digital signal. In addition, the transmission speed of the digital signal D6 is as high as about 28 Gbps. For this reason, the optical receiver 100 is required to have a device design corresponding to a wider frequency band. Therefore, the optical receiver 100 increases the amplitude value of the digital signal D6 and increases the value of T _r / T _f until synchronization is established. This suppresses the influence of noise and the like, and increases the speed at which the VCO 202c can follow. As a result, the clock component can be easily extracted.

  FIG. 6 is a diagram illustrating the configuration of the digital coherent receiving unit according to the embodiment. As shown in FIG. 6, the phase shifter 203c shifts the output clock signal from the VCO 202c, which is established in synchronization by the PLL circuit 202, to four phases (0 °, 90 °, 180 °, 270 °). The 4-phase sampler 203b shifts the data input from the buffer 203a to each clock phase shifted by the phase shifter 203c. The data shifted into four phases by the four-phase sampler 203b is AD-converted by the high-speed ADCs 203d-1, 203d-2, 203d-3, and 203d-4, respectively, and then converted into a digital signal as an FEC frame synchronization detection circuit 203f. Is output. The FEC frame synchronization detection circuit 203f detects the preamble pattern (F6 F6 F6 28 28 28) of the FEC frame from this digital signal.

  Since the FEC frame synchronization detection circuit 203f cannot detect an FEC frame from data having a phase close to the data change point, the digital signal processing circuit 203g in the subsequent stage uses the clock closest to the midpoint of the data change point. select. This operation by the digital signal processing circuit 203g is defined as “establishment of synchronization”. With this operation, the XI input signal X1, the XQ input signal X2, the YI input signal Y1, and the YQ input signal Y2 respectively input to the data decoding circuits (DEC) 203, 204, 205, and 206 are converted into the clock component and the data component. After the synchronization is established, it is output to the outside as an XI output signal X3, an XQ output signal X4, a YI output signal Y3, and a YQ output signal Y4.

  FIG. 7A is a diagram for explaining a synchronization establishment method when the input amplitude is small. On the other hand, FIG. 7B is a diagram for explaining a synchronization establishment method when the input amplitude is large. 7A and 7B, the phase of the input signal is defined in the x-axis direction (time direction), and the voltage of the input signal is defined in the y-axis direction. As shown in FIG. 7A, when the input amplitude is small, the digital signal processing circuit 203g uses 0 ° and 270 ° (dashed lines in FIG. 7A), which are phases close to the data change points Z1 and Z2, as the phase of the data change point. to decide. Then, the digital signal processing circuit 203g samples any phase of 90 ° or 180 ° (solid line in FIG. 7A) positioned between them as a clock used for establishing synchronization. For this reason, depending on the wavelength and frequency of the input signal, the optimal phase is not determined, and the clock at the optimal point for establishing synchronization may not always be selected.

  On the other hand, as shown in FIG. 7B, when the input amplitude is large, the phase closest to the midpoint Z5 of the data change points Z3 and Z4 is easily specified as a phase of 180 ° (solid line in FIG. 7B). The For this reason, the digital signal processing circuit 203g can accurately select the clock phase that is the optimum point for establishing synchronization from the four phases. That is, the sampling process for establishing synchronization is realized simply and quickly. For the reasons described above, the greater the input amplitude, the easier it is for the optical receiver 100 to extract the clock component from the digital signal, and the establishment of synchronization becomes easier.

  As described above, the optical receiver 100 receives coherent light. The optical receiver 100 receives coherent light. The optical receiver 100 includes OAs 108a to 108d, a digital signal processing circuit 112, and a control circuit 113. The OAs 108a to 108d adjust the amplitude of the input signal and output it. The digital signal processing circuit 112 inputs a digital signal generated using the analog signals output from the OAs 108a to 108d, extracts a clock component from the digital signal, and establishes synchronization between the clock component and the data component. After that, the data component is extracted and processed from the digital signal. The control circuit 113 sets the amplitude of the analog signal to a first amplitude (for example, a large amplitude of about 700 mVpp) before establishment of synchronization by the digital signal, and after establishment of the synchronization, the control circuit 113 sets the amplitude after the setting. Is changed to a second amplitude smaller than the first amplitude (for example, a small amplitude of about 400 mVpp).

  In the optical receiver 100, the first amplitude is equal to or larger than an amplitude value at which the digital signal processing circuit 112 can establish synchronization between the clock component and the data component using the digital signal. . The second amplitude is an amplitude within the range in which the digital signal processing circuit 112 can extract the data component from the digital signal (optimized amplitude). Further, after the synchronization is established, the control circuit 113 changes the second amplitude to an amplitude within a range that is linear in the gain characteristic of the amplitude of the output signal with respect to the control voltage applied to the OAs 108a to 108d. It may be limited.

  That is, the optical receiver 100 sets the amplitude to a high value until the synchronization is established with respect to the electrical signal received coherently, and decreases the amplitude according to the input range of the high-speed ADCs 111a to 111d after the synchronization is established. Further, the optical receiver 100 always optimizes the amplitude of the electric signal by performing feedback control of the signal amplitude of each lane after the synchronization is established. More specifically, the optical receiver 100 increases the gain of the input signal until the synchronization is established, and improves the stability of the synchronization establishment. On the other hand, after the synchronization is established, the optical receiver 100 converts the AD converted digital value. By constantly monitoring, feedback control is performed to optimize the gain of the analog input signal within the input dynamic range. At that time, the optical receiver 100 can control the gain adjustment after the synchronization is established so as not to use a non-linear range in which waveform distortion is likely to occur, thereby reducing errors in data decoding and improving signal transmission quality. And

  In the embodiment, the optical receiver 100 configures the OAs 108a to 108d separately from the AGCs 107a to 107d. As a result, the optical receiver 100 is input with the signal variation between the capacitors 109a to 109d and the offset adjusters 110a to 110d being suppressed as compared with the case where the AGC 107a to 107d includes the OA function. It is possible to flexibly and easily cope with fluctuations in optical signals.

More specifically, in optical coherent transmission, the optimum signal amplitude value at the time of clock extraction is different from the optimum signal amplitude value at the time of data communication. In other words, in the case of conventional NRZ (Non Return to Zero) intensity modulation, the optical receiver can easily extract the clock component by increasing the input signal amplitude and abruptly swinging T _r / T _f. The line quality in the network is also improved. On the other hand, in the optical coherent transmission, the optical receiver 100 sets the output amplitude value of the optical reception FE (Front End) module to be low so that the signal amplitude falls within the input range of the high-speed ADCs 111a to 111d. In this case, in the digital signal processing circuit 112 provided in the subsequent stage of the high-speed ADCs 111a to 111d, the gain of the clock component extracted from the input signal is reduced. As a result, the data component and the clock component are not synchronized, or a long time is required until the synchronization is established.

  Therefore, the optical receiver 100 according to the present embodiment uses the amplitudes of the input signals to the high-speed ADCs 111a to 111d until the line synchronization is established between the data and the clock by the OAs 108a to 108d and the control circuit 113. Set to a higher value. Then, after establishment of line synchronization, the optical receiver 100 optimizes the amplitude within the ADC dynamic range. As an effect before the establishment of line synchronization, even if the input signals (sine waves) to the high-speed ADCs 111a to 111d are saturated, the optical receiver 100 increases the input amplitude when establishing line synchronization of an internal PLL (Phase Locked Loop). Thus, it is possible to increase the gain when extracting the clock component from the input signal. This increases the probability of line synchronization. Furthermore, as an effect after line synchronization is established, the optical receiver 100 can easily extract data components.

  Regarding amplitude control after synchronization is established, the optical receiver 100 can take various feedback control modes.

  For example, some existing optical reception FE modules used in optical coherent transmission include an AGC circuit. However, these optical reception FE modules usually have a large dependence on optical input power. Some output amplitudes are not constant. In particular, in the analog portion from the balanced photodiodes 102b, 102c, 103b, and 103c to the high-speed ADCs 111a to 111d, the input amplitude to the high-speed ADCs 111a to 111d due to various factors such as fluctuations in optical input power, temperature changes, and aging degradation. May deviate from the optimum range. Along with this, there may be a problem that the optical transmission quality deteriorates.

  In order to deal with such a problem, the control circuit 113 of the optical receiver 100 can adopt a feedback control method based on the monitoring result of the RMS value after AD conversion when controlling the amplitude after synchronization is established. Alternatively, the control circuit 113 can adopt a feedback control method based on the number of errors in the input signal F1 from the digital signal processing circuit 112. That is, the optical receiver 100 constantly monitors the RMS value or the number of errors in the digital signal processing circuit 112 by the control circuit 113 in the signal communication state after the synchronization is established, so that the output signal E13 from the OAs 108a to 108d. Always optimize the amplitude of ~ E16 within the ADC dynamic range. This reduces the error rate and improves the signal quality. That is, after the line synchronization of the internal clock is established, the optical receiver 100 realizes higher transparency by optimizing the input amplitude within the dynamic range of the ADC input and preventing signal deterioration due to waveform distortion. In addition, the optical receiver 100 uses the control circuit 113 to monitor variations in output data characteristics caused by fluctuations in optical input power, temperature changes, aging degradation, and the like, and feedbacks to the OAs 108a to 108d based on the monitoring results. Apply control. Thereby, the optimal input amplitude is always maintained. As a result, deterioration of the optical signal quality is prevented in advance.

  Also, in optical coherent transmission by the optical receiver 100, a total of four electrical signals corresponding to two polarization IQ components are connected to four different lanes connecting the polarization receivers 102 and 103 and the digital signal processing circuit 112. It is divided and transmitted. For this reason, there is a concern that the characteristics between the lanes of the analog portion vary, and this variation is derived from the amplitude variation. Variations in amplitude between lanes cause deterioration in transmission quality. Therefore, the optical receiver 100 is provided with OAs 108a to 108d for all the lanes. Thereby, the control circuit 113 can perform individual feedback control for each of the four lanes when controlling the amplitude after the synchronization is established. Therefore, the control circuit 113 can reduce or eliminate variations in characteristics and amplitude that occur between lanes. As a result, the error rate is reduced and the signal quality is improved. That is, the optical receiver 100 individually adjusts the input amplitudes of the four lanes, thereby eliminating variations that occur in the analog portion between the lanes, and performing chromatic dispersion compensation and polarization modes executed by the digital signal processing circuit 112 in the subsequent stage. It is possible to improve transparency in dispersion compensation.

  Furthermore, in optical coherent transmission, it is important to maintain good linearity in the analog portion from the photodiode to the ADC. FIG. 8 is a diagram illustrating an example of gain characteristics of the OAs 108a to 108d of the optical receiver 100 according to the embodiment. In FIG. 8, the voltage applied to each OA 108 a to 108 d is defined as the OA control voltage (unit: V) on the x axis, and the amplitude of the electric signal output from each OA 108 a to 108 d is on the y axis. The value is defined as OA output amplitude (unit: mVpp). As shown in FIG. 8, the value of the OA output amplitude increases as the OA control voltage increases, but the increase width (slope) varies depending on the value of the OA control voltage, and in the course of the increase, the linear range and the non-linear range. And mixed.

Particularly, the high-speed operational amplifier for amplitude adjustment has a predetermined output level range, and a non-linear portion in a low control voltage range (eg, 0 to 1.0 V) and a high range (eg, 1.8 V or more). Have In FIG. 8, the non-linear range R1 exists in a low range where the OA control voltage is V ₁ or less, while the non-linear range R3 also exists in a high range where the OA control voltage is V ₂ or more. A linear range R2 (about 200 to 700 mVpp) of the output amplitude exists when the OA control voltage is between V _{1 and} V ₂ (about 1.0 to 1.8 V). Accordingly, in the high-speed ADCs 111a to 111d of the optical receiver 100, if the output amplitude value is set to a high value (for example, 700 mVpp or more) for establishing synchronization, the input signal may be clipped (saturated). On the other hand, when the output amplitude value is set to a low value (for example, 200 mVpp or less) at the time of optimization, there arises a problem that quantization noise increases and signal quality deteriorates. That is, if the amplitude is increased too much, the waveform is distorted, and if it is lowered too much, it is easily affected by noise and the frequency band does not extend.

  Therefore, in order to deal with the above problem, the optical receiver 100 considers the gain of analog components such as the OAs 108a to 108d when controlling the amplitude after synchronization is established, and has a good range of OA characteristics (for example, about 200 to It is also possible to adopt a feedback control system that limits the output amplitude value to 700 mVpp (more preferably about 300 to 500 mVpp). In other words, the control circuit 113 enables the linear range R2 shown in FIG. 8 and the high range of the high-speed ADCs 111a to 111d (the most significant bit (MSB: Most Significant Bit) side) in the signal communication state after the synchronization is established. Feedback control to be used for As a result, the optical receiver 100 can limit the output amplitude value so as not to use the non-linear range of the analog component. As a result, waveform distortion is suppressed and the error rate is reduced. As a result, the optical signal quality is improved.

  In the optical receiver 100, the above-described feedback control is executed by a firm process. For this reason, the control load of the firmware increases, and problems such as degradation of existing functions are assumed depending on the amount of firm processing in the entire receiver. Therefore, the control circuit 113 of the optical receiver 100 monitors the predetermined time (for example, 1 to 100 μs) without performing real-time control when controlling the amplitude after establishment of synchronization in consideration of the stability of the output characteristics of light. Later, it is possible to adopt a method of performing feedback control collectively based on the monitoring result. As a result, the amount of firm processing by the control circuit 113 is reduced. As a result, the processing load on the optical receiver 100 is reduced.

(Modification)
The embodiment described above can also take a modified form as described below. That is, in the above-described embodiment, the optical receiver 100 uses the OAs 108a to 108d as independent components separate from the AGCs 107a to 107d. However, the functions of the OAs 108a to 108d may be included in the AGCs 107a to 107d. . FIG. 9 is a diagram illustrating a configuration of an optical receiver 100 according to a modification. As shown in FIG. 9, the configuration of the optical receiver 100 according to the modified example is the same as the configuration of the optical receiver 100 shown in FIG. 1 except that the OA 108a to 108d are not provided. Therefore, the same reference numerals are used for common components, and detailed description thereof is omitted. The AGCs 107a to 107d control the electrical signals E5 to E8 input from the TIAs 106a to 106d to preset amplitude values, adjust the amplitudes of the electrical signals E5 to E8, and send the adjusted electrical signals E9 to E12. And output to the capacitors 109a to 109d in the subsequent stage. The amplitudes of the electrical signals E5 to E8 are adjusted by feedback control based on the feedback control signal F2.

  In the above embodiment, the above-described feedback control is implemented by providing the optical receiver 100 with the OAs 108a to 108d for amplitude adjustment in each of the four lanes. The area also increases. Therefore, in the above modification, the optical receiver 100 performs the same amplitude adjustment as the OA 108a to 108d by the AGC 107a to 107d instead of the OA 108a to 108d in the feedback control described above. As a result, the circuit scale is reduced and the mounting area is also reduced. As a result, the optical receiver 100 can be downsized. In addition, power consumption can be reduced.

  In the above description, feedback control using different methods has been described individually. However, one optical receiver 100 may have a plurality of feedback control functions described above. Also, the number of methods to be combined is not limited to two, and any form such as a combination of three or more can be employed. Furthermore, it is of course possible to apply the various feedback control methods described above to the optical receiver 100 according to the modification. For example, the optical receiver 100 may individually apply the feedback control function based on the RMS value after AD conversion to four parallel lanes. The optical receiver 100 may combine feedback control based on the number of errors and batch feedback control after monitoring for a predetermined time. Furthermore, the optical receiver 100 according to the modified example may perform feedback control of a method of limiting the amplitude value of the output signal within a linear range.

DESCRIPTION OF SYMBOLS 100 Optical receiver 101 Polarization separator 102 X polarization receiver 102a Optical 90 degree hybrid device 102b, 102c Balanced photodiode 103 Y Polarization receiver 103a Optical 90 degree hybrid device 103b, 103c Balanced photodiode 104 LD
105 Polarization separator 106a-106d TIA
107a-107d AGC
108a-108d OA
109a-109d capacitor 110a-110d offset adjuster 111a-111d high speed ADC
112 Digital signal processing circuit 113 Control circuit 200 CDR circuit 201 Buffer 202 PLL circuit 202a Phase detector (mixer)
202b LPF
202c VCO
202d selector 203, 204, 205, 206 data decoding circuit (DEC)
203a buffer 203b 4 phase sampler 203c phase shifter 203d-1, 203d-2, 203d-3, 203d-4 high speed ADC
203e ADC sampling clock selection circuit 203f FEC frame synchronization detection circuit 203g Digital signal processing circuit D1-D4, D6-D10 Electrical signal (digital signal)
D5 Information signal (digital signal)
E1-E28 Electrical signal (analog signal)
F1, F2 feedback control signal P1~P14 optical signals R1, R3 OA output amplitude of the non-linear range R2 OA control voltage V _IH which ends the start OA control voltage V ₂ linear range of the linear range V ₁ linear range of the OA output amplitude, Input voltage to V _IL digital signal processing circuit V _op Output voltage from LPF X1 XI input signal X2 XQ input signal X3 XI output signal X4 XQ output signal Y1 YI input signal Y2 YQ input signal Y3 YI output signal Y4 YQ output signal Z1 ~ Z4 Data change point Z5 Midpoint of data change point

Claims (5)

An amplitude adjustment circuit configured to adjust the amplitude of the input signal,
A digital signal generated using the analog signal output from the amplitude adjustment circuit is input, a clock component is extracted from the digital signal , and the clock component of the digital signal and the data component of the digital signal are synchronized. A signal processing circuit for extracting and processing the data component from the digital signal after being established;
Before the synchronization by the digital signal is established, the amplitude of the analog signal is set to a first amplitude, and after the establishment of the synchronization, the amplitude after the setting is set to a second amplitude smaller than the first amplitude. An optical receiver comprising: a control circuit to be changed.   The first amplitude is an amplitude equal to or larger than an amplitude value at which the signal processing circuit can establish synchronization between the clock component and the data component using the digital signal. The optical receiver according to 1.   The optical receiver according to claim 1, wherein the second amplitude is an amplitude within a range in which the signal processing circuit can extract the data component from the digital signal.   The control circuit limits the second amplitude to an amplitude within a range having linearity in a gain characteristic of an output amplitude with respect to a control voltage applied to the amplitude adjustment circuit after the synchronization is established. The optical receiver according to claim 1. The optical receiver
Adjust and output the amplitude of the input signal,
After inputting a digital signal generated using the output analog signal, extracting a clock component from the digital signal, and establishing synchronization between the clock component of the digital signal and the data component of the digital signal , Extracting and processing the data component from the digital signal;
Before the synchronization by the digital signal is established, the amplitude of the analog signal is set to a first amplitude, and after the establishment of the synchronization, the amplitude after the setting is set to a second amplitude smaller than the first amplitude. An optical receiving method characterized by changing.

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