JP5855165B2 - Frame data processing method and frame data processing apparatus - Google Patents

Description

  The present invention relates to a frame data processing method and a frame data processing apparatus for performing CRC (Cyclic Redundancy Check) operation on transmission / reception frame data.

  In a system for storing a transmission / reception frame in a memory or the like, it is necessary to have a function of detecting the occurrence of a soft error such as data rewrite in the memory in order to improve reliability. The CRC calculation is generally used as a checksum for detecting a data error during data transfer or storage (see, for example, Patent Document 1).

  FIG. 1 shows a timing chart when CRC calculation is performed on data of an input frame. 11 is a system clock, 12 is a signal indicating an effective area of input frame data, 13 is input frame data, 14 is an input frame length, and 15 is a CRC calculation time.

The input frame length 14 has data for n cycle clocks. Since the CRC calculation sequentially calculates the input frame data and obtains the result, the calculation time depends on the input frame length 14. Here, the time (CRC calculation result time) at which the final CRC calculation result is obtained is shown in Equation 1.
(Equation 1)
T x n + T _CRC (1)
In Equation 1, T represents one cycle time, and T _CRC represents a CRC calculation time 15 of data 1 to n. Depending on the system, there is a case where the rewritten data is confirmed after the input of the input frame is completed, and the confirmed data is rewritten to the input frame. For example, there is a system that stores a packet signal in a memory.

  Next, an example in which frame data needs to be rewritten when frame data is stored in a memory will be described. 2 and 3 are timing charts of the acquisition timing of the frame length information 19 and the read control (read enable 17) signal.

  FIG. 2 shows a case where the frame data is read when there is no rewriting of the frame data, and shows a time chart when the frame has no frame data length and the frame length is known at the end of the frame. 11 is a system clock, 16 is a read request signal, 17 is a read enable signal, 18 is read data, and 19 is frame length information. In this case, since the read enable signal 17 is turned off (cannot be read) from the time when the frame length is known, the read enable signal 17 is in an underflow state (a state in which more than the write data is read) in which an extra read enable signal 17 is output. In such a state, reading invalid data may cause erroneous operations such as erroneous recognition and transmission of erroneous data.

  FIG. 3 shows a time chart when the frame data is read when the frame data is rewritten, and when the frame length information 19 is present at the head of the frame. In this case, since the length of the frame is known at the beginning of the frame at the time of reading, the read enable signal 17 can be turned off with a length corresponding to the clock corresponding to the frame length. Therefore, when the frame data is stored in the memory, the output period of the read enable signal 17 can be controlled according to the length of the frame when the frame is read from the memory by rewriting the frame length information 19 at the head of the frame. The problem as shown in FIG. 2 can be solved.

FIG. 4 shows a timing chart of CRC calculation when data is rewritten with respect to an input frame. 11 is a system clock, 12 is a signal indicating an effective area of input frame data, 13 is input frame data, 21 is input frame data after rewriting, 14 is an input frame length, 15 is a CRC calculation time, and 19 is frame length information. Len is shown. After the data of the input frame data 13 is read, Len indicating the frame length information 19 is determined, and the leading preamble of the input frame data 13 is rewritten to Len indicating the frame length information 19 and stored in the memory. In this case, a formula for calculating the time (CRC calculation result time) for obtaining the final CRC calculation result is shown in Formula 2.
(Equation 2)
T × 2n + T _CRC (2)
The CRC calculation result time for the rewritten input frame data 21 shown in Expression 2 requires twice the frame length and a CRC calculation time T _CRC .

JP 2002-135355 A

In the related art, when the transmission / reception input frame is rewritten and stored in the memory and the CRC calculation is performed on the input frame in the memory, there is a problem that it takes twice the frame length and the CRC calculation time T _CRC. It was.

  In order to solve the above-mentioned problems, the present invention separates an area in which input frame data is to be rewritten from an area that is not to be rewritten. Perform after input completion. Thereafter, the CRC calculation is performed again by combining the CRC calculation results of the area to be rewritten and the area not to be rewritten.

  In order to achieve the above object, in the present invention, in the input frame, a CRC calculation is performed by separating the area into a region to be rewritten or a region not to be rewritten.

Specifically, the frame data processing method according to the present invention includes frame data that separates data into a variable area in which data is rewritten and an invariant area in which data is not rewritten out of data in a frame having a predetermined area. A separation procedure;
A frame length information acquisition procedure for acquiring frame length information of the frame separated by the frame data separation procedure;
A first CRC calculation procedure for performing a CRC (Cyclic Redundancy Check) operation on the data of the invariant area separated by the frame data separation procedure;
A frame length information allocation procedure for allocating the frame length information acquired in the frame length information acquisition procedure to the data in the variable region;
A second CRC calculation procedure for performing CRC calculation on the data in the variable area to which the frame length information is assigned in the frame length information assignment procedure;
A third CRC calculation procedure for performing CRC calculation on the calculation result of the first CRC calculation procedure and the calculation result of the second CRC calculation procedure is performed.

In the frame data processing method according to the present invention,
The first CRC calculation procedure and the second CRC calculation procedure may be performed within the same clock.

Specifically, the frame data processing apparatus according to the present invention is a frame data that separates data into a variable area in which data is rewritten and an invariant area in which data is not rewritten out of data in a frame having a predetermined area. A separation circuit;
A frame length information acquisition circuit for acquiring frame length information of the frame;
A first CRC calculation circuit for performing CRC calculation on the data of the invariant area;
A frame length information allocation circuit for allocating the frame length information to the data in the variable region;
A second CRC calculation circuit that performs a CRC calculation on the variable area data to which the frame length information is allocated by the frame length information allocation circuit;
A third CRC calculation circuit that performs a CRC calculation on the calculation result of the first CRC calculation circuit and the calculation result of the second CRC calculation circuit;

  The above inventions can be combined as much as possible.

  According to the present invention, the area for rewriting the input frame data is separated from the area not to be rewritten, the CRC operation for the area not to be rewritten is performed on the input sequentially, and the CRC operation for the area to be rewritten is performed after the rewrite input is completed To do. After that, since the CRC calculation result of the area to be rewritten and the CRC calculation result of the area not to be rewritten is combined, the CRC calculation result time can be shortened to about ½ compared with the related art.

An example of the timing chart in the CRC calculation which concerns on related technology is shown. An example of a timing chart when there is no rewriting of the frame data which concerns on related technology is shown. An example of a timing chart when there is rewriting of frame data according to related technology is shown. An example of a timing chart of CRC calculation when there is rewriting of frame data according to related technology is shown. 1 shows an exemplary configuration of a frame data processing apparatus according to the present embodiment. An example of the timing chart in the CRC calculation which concerns on this embodiment is shown. An example of the flowchart in the CRC calculation which concerns on this embodiment is shown.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to embodiment shown below. These embodiments are merely examples, and the present invention can be implemented in various modifications and improvements based on the knowledge of those skilled in the art. In the present specification and drawings, the same reference numerals denote the same components.

(Embodiment 1)
FIG. 5 shows an example of the configuration of the frame data processing device 31 according to the present embodiment. The frame data processing device 31 according to the present embodiment includes a frame data separation circuit 32, a frame length information acquisition circuit 33, a first CRC calculation circuit 34, a frame length information allocation circuit 35, and a second CRC calculation circuit. 36 and a third CRC calculation / assignment circuit 37.

  In the frame data processing method according to the present embodiment, a frame data separation procedure, a frame length information acquisition procedure, a first CRC calculation procedure, a second CRC calculation procedure, and a third CRC calculation procedure are performed. . The order of the frame length information acquisition procedure and the first CRC calculation procedure is not limited to this. For example, the frame length information acquisition procedure may be performed after the first CRC calculation procedure. Further, the first CRC calculation procedure and the frame length information acquisition procedure may be performed simultaneously.

  In the frame data processing device 31 according to the present embodiment, the frame data separation circuit 32 applies to a variable area in which data is rewritten and a data area without rewriting data among data in a frame having a predetermined area. Separate data into immutable areas that are immutable. The frame length information acquisition circuit 33 acquires frame length information of the frame. The first CRC calculation circuit 34 performs CRC calculation on the data in the invariant area.

  In addition, the frame length information allocation circuit 35 in the frame data processing device 31 according to the present embodiment allocates frame length information to variable area data. The second CRC calculation circuit 36 performs CRC calculation on the variable area data to which the frame length information is allocated by the frame length information allocation circuit 35. The third CRC calculation / assignment circuit 37 performs a CRC calculation on the calculation result of the first CRC calculation circuit 34 and the calculation result of the second CRC calculation circuit 36.

  In the frame data processing method according to the present embodiment, a frame data separation procedure, a frame length information acquisition procedure, a first CRC calculation procedure, a second CRC calculation procedure, and a third CRC calculation procedure are performed. . An example of the frame data processing method according to the present embodiment is shown in FIG. In FIG. 6, 11 is a system clock, 12 is a signal indicating an effective area of input frame data, 13 is input frame data, 21 is frame data after rewriting in area B, 14 is an input frame length, and 19 is frame length information. Len is shown.

  Each procedure of the frame data processing method shown in FIG. 6 will be described below. In FIG. 6, step 501 is a procedure for calculating the CRC calculation time for the area A without rewriting, step 502 is a procedure for calculating the CRC calculation time 15 for the area B with rewriting, and step 503 is the CRC calculation time 15 for the entire frame. The procedure to calculate is shown. Here, the frame data processing method will be further described below with reference to the flowchart of FIG.

(1) In the frame data processing method according to the present embodiment, the input frame data 13 is read, and CRC calculation is performed on the area A that is not rewritten (step 101).
(2) The frame length information acquisition circuit 33 executes a frame length information acquisition procedure. Specifically, after the input frame data 13 is read, the frame length information 19 is acquired (step 102).
(3) The frame length information allocation circuit 35 performs a CRC calculation on the rewritten data for the area B with rewriting (step 103).
(4) CRC calculation is performed on the rewritten data with the frame length information 19 rewritten (step 104).
(5) Finally, the CRC calculation of the rewritten input frame data 13 is performed using the CRC calculation result of the area A without rewriting and the CRC calculation result of the area B after rewriting (step 105). Here, in each CRC calculation according to the present embodiment, for example, in the first CRC calculation to the third CRC calculation, the CRC calculation may be performed using the same generator polynomial.

  In the frame data processing method described above, the frame data separation procedure is performed in advance so that the CRC processing can be performed separately by dividing the variable region, which is a rewritten region, and the invariable region, which is a non-rewritten region. Of the data in the frame having a predetermined area, the data is separated into a variable area where data is rewritten and an invariable area where data is not rewritten. Specifically, in the frame data separation procedure, the period in which the signal 12 indicating the effective area of the frame data is “1” is counted, and the areas are separated according to the count number. For example, it is possible to realize separation into a variable area and an invariable area by dividing the variable area into a variable area when the count number is 0, and an invariant area when 1 to 8.

  FIG. 5 shows an example of the configuration of the frame data processing device 31 and the frame data receiving device 41 according to the present embodiment. The frame data processing device 31 includes a frame data separation circuit 32, a frame length information acquisition circuit 33, a first CRC calculation circuit 34, a frame length information allocation circuit 35, a second CRC calculation circuit 36, and a third CRC calculation / assignment circuit 37. On the other hand, in the frame data receiving apparatus 41, on the frame data receiving apparatus 41 side, the frame data separating circuit 42, the first CRC calculating circuit 43, the second CRC calculating circuit 44, and the third CRC calculating / checking circuit are provided. 45. The frame data is sent from the processing device 31 to the frame data receiving device 41 via the memory 40.

  Specifically, on the frame data receiving device 41 side, the frame data separation circuit 42 separates the frame data sent from the memory 40 into a rewrite area and a non-rewrite area, and the data separated into the non-rewrite area is the first data. Data sent to the CRC calculation circuit 43 and data separated into the area data to be rewritten are sent to the second CRC calculation circuit 44. The first CRC calculation circuit 43 performs CRC calculation on the data separated in the area not to be rewritten, and the second CRC calculation circuit 44 performs CRC calculation on the data separated in the area to be rewritten. The third CRC calculation / check circuit 45 checks the CRC calculation result calculated by the first CRC calculation circuit 43 and the second CRC calculation circuit 44.

In the configuration example of the frame data processing device 31 and the frame data receiving device 41 in FIG. 5, when frame data is acquired in the memory 40, a soft error that occurs in the memory 40 may be detected. Therefore, the frame data processing device 31 assigns a CRC in advance when writing the frame, and checks with the third CRC calculation / check circuit 45 when the frame data receiving device 41 reads the frame. Here, when the frame data receiving apparatus 41 reads a frame, information on the frame length is required, and the frame data needs to be rewritten. In the present embodiment, the CRC calculation can be shortened when the above-described rewriting occurs.
(Equation 3)
_Txn + _Tx2 + T _CRC (3)
The CRC calculation time 15 can be shortened to about ½ by the calculation process of the above expression 3 (when the rewritten area B is sufficiently small with respect to the input frame length 14).

Further, by increasing the rewriting area B, information other than the frame length information 19 can be rewritten. For example, assuming that the area B is m clocks, the CRC calculation result time in this case is shown in the following Expression 4.
(Equation 4)
T × n + T × (m + 1) + T _CRC (4)
The CRC calculation result time can be reduced by the calculation process of Expression 4 (when (m + 1) in (Expression 2) and (Expression 4) is smaller than n). Note that n in the 10G PON system is approximately 64-2000.

  The present invention can be applied to the information communication industry.

11: Clock 12: Valid area signal 13: Input frame data 14: Input frame length 15: CRC calculation time 16: Read request signal 17: Read enable signal 18: Read data 19: Frame length information 21: Rewritten frame data 31: Frame data processing devices 32, 42: Frame data separation circuit 33: Frame length information acquisition circuit 34, 43: First CRC calculation circuit 35: Frame length information allocation circuit 36, 44: Second CRC calculation circuit 37: Third CRC calculation / grant circuit 40: Memory 41: Frame data receiver 45: Third CRC calculation / check circuit

Claims (3)

Of the data in a frame having a predetermined area, a frame data separation procedure for separating data into a variable area where data is rewritten and an invariant area where data is not rewritten,
A frame length information acquisition procedure for acquiring frame length information of the frame separated by the frame data separation procedure;
A first CRC calculation procedure for performing a CRC (Cyclic Redundancy Check) operation on the data of the invariant area separated by the frame data separation procedure;
A frame length information allocation procedure for allocating the frame length information acquired in the frame length information acquisition procedure to the data in the variable region;
A second CRC calculation procedure for performing CRC calculation on the data in the variable area to which the frame length information is assigned in the frame length information assignment procedure;
A frame data processing method comprising: performing a third CRC calculation procedure for performing a CRC calculation on the calculation result of the first CRC calculation procedure and the calculation result of the second CRC calculation procedure. The frame data processing method according to claim 1, wherein the first CRC calculation procedure and the second CRC calculation procedure are performed within the same clock. A frame data separation circuit that separates data into a variable area in which data is rewritten, and an invariant area in which data is not rewritten, among data in a frame having a predetermined area;
A frame length information acquisition circuit for acquiring frame length information of the frame;
A first CRC calculation circuit for performing CRC calculation on the data of the invariant area;
A frame length information allocation circuit for allocating the frame length information to the data in the variable region;
A second CRC calculation circuit that performs a CRC calculation on the variable area data to which the frame length information is allocated by the frame length information allocation circuit;
A frame data processing apparatus comprising: a third CRC calculation circuit that performs a CRC calculation on the calculation result of the first CRC calculation circuit and the calculation result of the second CRC calculation circuit.

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