JP5849268B1 - Read transfer control method and auxiliary storage device controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform predictive prefetch processing in accordance with characteristics of data stored in an auxiliary storage device. When first reading from a NAND flash memory 22 as an auxiliary storage device (negative determination in step S101), the data size of a block of data to be read is grasped and registered in one entry of an N entry table 214. (S103). In the second and subsequent readings (affirmative determination in step S101), prediction prefetching processing according to the size is performed (S102). In addition, the more frequently read data is, the more entries are maintained in the N entry table 214 (S103), so that efficient predictive prefetching processing according to the size can be realized. [Selection] Figure 3

Description

  The present invention relates to a read transfer control method and an auxiliary storage device controller, and more particularly, read transfer that performs prefetch processing for predicting data to be read related to a next read request from a host device and reading the data from an auxiliary storage device in advance. The present invention relates to a control method and an auxiliary storage device controller.

  General-purpose devices such as personal computers and dedicated devices such as game machines often handle large volumes of data, but in such cases, such data is usually stored in an auxiliary (external) storage device and necessary. It is common to read and process data that is sometimes required. At that time, from the viewpoint of unification of the interface between the two, it is common to use a controller in between. A logical block diagram at that time is shown in FIG. Here, the host device 100 is a general-purpose device such as the above-mentioned personal computer or a dedicated device such as a game machine, and the auxiliary storage device 300 is an SSD (Solid State Device) represented by a hard disk or recently a NAND flash memory. ). In general, the controller 200 and the auxiliary storage device 300 are generally configured integrally. In many cases, the controller 200 and the auxiliary storage device 300 are built in an apparatus constituting the function of the host device 100. Specifically, as an interface between the host device 100 and the controller 200, ST-506, SCSI (Small Computer System Interface), IDE (Integrated Drive Electronics), ATA (Advanced Technology Attachment), SATA (Serial ATA), eSATA (External SATA).

Here, the latency due to the reading process of the auxiliary storage device 300 occurs after the host device 100 requests the auxiliary storage device 300 to transfer the data until the data is received. FIG. 7B is a diagram for explaining this latency. When the host device 100 issues a request [Read A ₀ ] (a request to read and send data from the address A ₀ ) to the auxiliary storage device 300, the controller 200 that has received the request stores the auxiliary storage based on the request. A read instruction is issued to the device 300. When the controller 200 receives the data D ₀ corresponding to the request [Read A ₀ ] from the auxiliary storage device 300, the controller 200 transfers the data D ₀ to the host device 100. The same applies to the request [Read A ₁ ] that is issued next after the host device 100 receives the data D ₀ . Such latency is, for example, several tens to several hundreds μs for a NAND flash memory.

  In other words, the host device 100 always takes a predetermined time from the time when the read request is made to the auxiliary storage device 300 until the data related to the request is received. As the imbalance between the processing speed and the reading speed of the auxiliary storage device 300 increases, the processing capacity (performance) of the host device 100 decreases. For example, in a moving image processing system, that is, a system in which moving image data stored in the auxiliary storage device 300 is read and the host device 100 performs image processing such as display, image processing such as decoding is interrupted. As a result, the moving image stops frequently or the resolution drops.

  In view of the problems as described above, after the controller 200 transfers data based on a certain read request from the host device 100, it is requested to read next before receiving the next read request from the host device 100. A technology has been developed that predicts data that will be read out and secured in advance from the auxiliary storage device 300. According to such a technique, if the prediction is correct, the next read request is received instead of receiving the next read request from the host device 100 and then instructing the auxiliary storage device 300 to read as usual. At this point, since the data that has been read and secured in advance can be transferred to the host device 100, the requested data can be returned to the host device 100 as much as that, and the processing capability of the host device 100 is affected. That can be suppressed. This temporal relationship is shown in FIG. This is the case where the thick line is predicted and the broken line is the case where the prediction is not performed.

  Patent Document 1 discloses such a prediction technique. That is, the HDC (51) in Patent Document 1 corresponds to the controller 200, and the prefetched data is stored in the disk cache (54) (paragraphs [0026] to [0027]). Further, in Patent Document 1, the configuration is a two-stage configuration, and intelligent prediction is performed by the HDC (31) in the HDC card (21), and the disk cache ( 34) (paragraphs [0029] to [0032]).

  Patent Document 2 gives a specific feature to such a prediction technique. That is, in this document, predictive prefetching is performed flexibly so that prefetching can be instructed also from the host computer (6) corresponding to the host device 100. Specifically, the host computer (6) issues a prefetch command including an address or a file name (paragraphs [0030], [0043] to [0046], FIGS. 4 and 5).

Japanese Patent Laid-Open No. 2001-125829 JP 2010-191983 A

  By the way, in the prediction prefetching technique, it may be preferable for the host device 100 to efficiently perform the prediction prefetching processing according to the size of a batch of data read continuously from the auxiliary storage device 300. In particular, when the data to be handled is image data, the auxiliary storage device 300 stores a plurality of image data of various sizes as a lump. Further, it may be preferable for the host device 100 to efficiently perform the predictive prefetching process according to the frequency of reading from the auxiliary storage device 300. In particular, in moving image processing, there are images that are frequently displayed (for example, data that is always displayed every frame) and images that are displayed very rarely, and efficient predictive prefetching processing that takes them into consideration is desired. However, in the above-described conventional prediction look-ahead technology, there is no technology that fulfills such a specific processing request.

  The present invention has been made for the above-described circumstances, and an object of the present invention is to provide a read transfer control method capable of efficiently performing a predictive prefetch process according to the characteristics of data stored in an auxiliary storage device. And providing an auxiliary storage device controller.

In order to achieve the above object, according to a read transfer control method of the present invention, in response to a read request from a host device, a plurality of pieces of desired chunk data are continuously obtained from a plurality of chunk data having different sizes stored in an auxiliary storage device. When reading in batches and transferring to the host device, the data related to the next read request is predicted and pre-read from the auxiliary storage device until the next read request is received from the host device. a read transfer control method in a controller to process, the controller, in response to said magnitude of said lump data to be read from the auxiliary storage device, in performing the predictive prefetching process, during the initial reading of the lump data , advance calculated its size, when the second and subsequent reading, aborting the predicted prefetch process according to their size The gist of the door.

  Specifically, for example, based on the read request address and the read request size included in the read request, the controller sets a value obtained by adding the read request size to the read request address to the next read request. The predicted read-ahead address is predicted, and when the predicted address exceeds the value obtained by adding the size to the head address of the lump data read from the auxiliary storage device, the predicted look-ahead is aborted.

In order to achieve the above object, the auxiliary storage device controller of the present invention continuously obtains desired block data from a plurality of block data of different sizes stored in the auxiliary storage device in response to a read request from the host device. When the data is read out in a plurality of times and transferred to the host device, the data related to the next read request is predicted before the next read request is received from the host device, and prefetched from the auxiliary storage device. An auxiliary storage device controller that performs processing in accordance with the size of the lump data read from the auxiliary storage device , the size of calculated; then, during the second and subsequent reading, to the gist of truncating the predicted prefetch process according to their size .

  At this time, each entry includes information on the number of readings for the lump data, and the controller invalidates the entry related to the lump data with a small number of readings when the plurality of entries are not available. It is preferable to assign to the newly read data block.

  Typically, the lump data is image data, and the auxiliary storage device is a NAND flash memory. Also, typically, the interface between the controller and the host device is SATA.

  In order to achieve the above object, the auxiliary storage device controller of the present invention continuously obtains a desired lump data from a plurality of lump data stored in the auxiliary storage device a plurality of times in response to a read request from the host device. When the data is read separately and transferred to the host device, the data related to the next read request is predicted in advance until the next read request is received from the host device and pre-read from the auxiliary storage device. The gist of the present invention is that the auxiliary storage device controller performs processing in accordance with the size of the block data read from the auxiliary storage device and the read frequency according to the read frequency.

  According to the read transfer control method and the auxiliary storage device controller of the present invention, by performing the predictive prefetching process according to the size of the lump data read from the auxiliary storage device and the read frequency, according to the characteristics of the data. Predictive prefetching processing can be performed efficiently.

It is a block diagram which shows the structure of the processing system with which one Embodiment of the read transfer control method of this invention is applied. 5 is a diagram for explaining details of an N entry table 214 and a read processing parameter storage unit 213. FIG. It is a flowchart which shows the outline | summary procedure of the read transfer process containing the prediction prefetch process which the control part 212 performs. It is a flowchart (a) which shows the detail of the read transfer process procedure containing the prediction prefetch process which the control part 212 performs. It is a flowchart (b) which shows the part which continues from the process of FIG. 3 among the details of the read transfer process procedure including the prediction prefetch process which the control part 212 performs. It is a figure for demonstrating the specific example of the process by the read transfer process in one Embodiment of this invention. It is a figure for demonstrating the prior art. It is a figure for demonstrating the prior art.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram showing a configuration of a processing system to which an embodiment of a read transfer control method of the present invention is applied. As shown in the figure, the processing system includes a host device 1 as a main body of a general-purpose device such as a personal computer or a dedicated device such as a game machine, and an auxiliary storage device 2 connected to the host device 1 through a predetermined interface. It consists of Examples of the predetermined interface include ST-506, SCSI, IDE, ATA, SATA, eSATA, and the like, but recently, SATA and eSATA have become mainstream.

  The auxiliary storage device 2 includes at least a plurality of NAND flash memories 22 as an example of an auxiliary storage device, a controller 21 that controls reading / writing of data with respect to the NAND flash memory 22, and the NAND flash memory 22. And a read buffer memory 23 for securing pre-read data. Note that the auxiliary storage device is not limited to the NAND flash memory 22, but when there is a read request from the host device 1 due to the relationship between the processing speed of the host device 1 and the read speed of the auxiliary storage device. It is premised on that the latency to the extent that the processing capability of the host device 1 is reduced occurs. Here, the capacity of the NAND flash memory 22 is, for example, 64 Gbits as a whole. The capacity of the read buffer memory 23 is preferably 8 kbytes to 32 kbytes. The NAND flash memory 22 contains data that is logically stored in a single area (hereinafter referred to as “a single piece of data”), and that is to be read at a time or continuously multiple times. Multiple items are stored. Here, the plurality of lump data have different sizes and read frequencies. As such lump data, there is image data.

  The controller 21 includes at least a host interface 211, a control unit 212, a read processing parameter storage unit 213, and an N entry table 214. The host interface 211 is an interface for exchanging with the host device 1 based on the above-described predetermined interface standard procedure.

  The N entry table 214 is “a group of data that has been read (hereinafter referred to as“ read data ”) in response to a read request from the host device 1 among a plurality of groups of data stored in the NAND flash memory 22. Is a table composed of N entries for storing information related to "." As shown in FIG. 2A, one entry includes a read data start address 214a, a read data size 214b, a read data read count 214c, and a valid / invalid flag 124d of the entry. Here, the read data start address 214 a corresponds to the head storage address of the corresponding read data on the NAND flash memory 22. The read data size 214b finally corresponds to the size of the corresponding read data. The read data read count 214c is literally information that is counted up each time the corresponding read data is read. The valid / invalid flag 214d of this entry is information indicating whether the entry is valid or invalid at that stage. The N entry table 214 is configured with SRAM or a register according to the number of N as hardware.

  The read processing parameter storage unit 213 is a parameter buffer for temporarily securing necessary information in the course of processing performed by the controller 21 in response to a read request from the host device 1. The read request address storage unit 213a and the read request size storage unit 213b are areas for temporarily storing a read request address and a read request size for each request included in the read request command from the host device 1, respectively. In addition, the predicted address storage unit 213c is an area in which a read request address related to a read request from the next host device 1 predicted by the controller 21 after data transfer in response to a read request from the host device 1 is stored. It is. The previous address storage unit 213d is an area for storing a read request address related to the previous request for each read request at the time of reading the lump data stored in the NAND flash memory 22 for the first time. The entry index storage unit 213e is an area in which the entry number corresponding to the read data being read for the first time is stored.

  Based on the read request received from the host device 1 via the host interface 211, the control unit 212 performs a rewrite operation on the read processing parameter storage unit 213 and the N entry table 214, and performs a predictive prefetch process described later. Execute read transfer processing including. In addition to the above-described configuration, the controller 21 includes various configurations, for example, an interface circuit with the NAND flash memory 22, but is omitted.

Next, the read transfer process including the predictive prefetch process executed by the control unit 212 of the controller 21 in the embodiment of the read transfer control method of the present invention will be described.
First, the policy of the predictive prefetch process in the present invention is as follows.
(A) Predictive look-ahead processing corresponding to the size of each block data is performed. Specifically, the data size is ascertained at the first reading, and prefetching according to the size is performed at the second and subsequent readings.
(B) Predictive look-ahead processing is performed according to the read frequency of each block of data. Specifically, the processing based on the policy (a) is preferentially performed for the lump data that is read frequently.

  FIG. 3 is a flowchart showing an outline procedure of a read transfer process including a predictive prefetch process executed by the control unit 212 based on the above policy. That is, when there is a data read request from the host device 1 for an arbitrary chunk of data, the control unit 212 reads the data for the second and subsequent times registered in any entry of the N entry table 214. It is determined whether or not to read (step S101). Even if it is a batch of data that has been read once, data that is not read frequently will be deleted from the entry as will be described later. Is not limited.

  When the data read is the second or subsequent data read registered in any entry of the N entry table 214 (Yes in step S101), the first of the multiple read requests related to the data read For this request, data is read from the NAND flash memory 22 and transferred to the host device 1, and thereafter, it is predicted and pre-read in the read buffer memory 23. If the second and subsequent requests are predicted, the data stored in the read buffer memory 23 is transferred (step S102). However, prefetching ends according to the size of the lump data. On the other hand, when the data read is not the second or subsequent data read registered in any entry of the N entry table 214 (No in step S101), any entry (if there is a vacancy is used). If not, delete the entry related to the lump data with low read frequency), and sequentially read the data from the NAND flash memory 22 and transfer it to the host device 1 based on the plurality of requests. Calculate the data size and register it in the entry. With this process, when the size and the read frequency of each of the plurality of lump data are significantly different, an efficient prediction prefetch process can be performed.

  4 and 5 are flowcharts showing details of the read transfer processing procedure including the prediction prefetch processing executed by the control unit 212. FIG. Hereinafter, the processing procedure shown in FIGS. 4 and 5 will be described in order with reference to FIGS. 1 and 2. In general, the process shown in FIG. 5 is a process at the time of reading a batch of data for the first time, and the process shown in FIG. 4 is a process at the time of the second and subsequent readings.

  Therefore, first, the control unit 212 of the controller 21 constantly monitors the read request from the host device 1 (step S1), and when the read request is received, the read request address and the read request size included in the read request are set. These are temporarily reserved in the read request address storage unit 213a and the read request size storage unit 213b, respectively (step S2). Next, it is determined whether or not there is a valid entry (according to the valid / invalid flag 214d) having a read data start address 214a that matches the read request address stored in the read request address storage unit 213a. (Step S3).

  If the determination in step S3 is affirmative, the read request is the first read request for the second or subsequent data read of the lump data relating to the entry (entry with the matching address). Therefore, in this case, based on the read request address and the read request size (addresses and sizes secured in the read request address storage unit 213a and the read request size storage unit 213b), data is read from the NAND flash memory 22 and the host device 1 (step S4). In addition, the read count 214c of the read data in the entry is incremented (+1) (step S5), and the read count is increased. Then, the process proceeds to step S6. On the other hand, when the determination in step S3 is negative, it is determined whether or not the read request address matches the predicted address stored in the predicted address storage unit 213c (step S9).

  If the determination in step S9 is negative, it can be determined that this is the first data read of a block of data, and the process proceeds to step S11. The processing after step S11 will be described later. On the other hand, if the determination in step S9 is affirmative, the read request is a second or subsequent read request for the second or subsequent data read of the lump data related to the entry. Therefore, in this case, since the data that has been predicted and read should be stored in the read buffer memory 23, the data is transferred to the host device 1 (step S10). Then, the process proceeds to step S6.

  In step S6, the read request size is added to the read request address and stored in the predicted address storage unit 213c as the next predicted address.

  Next, it is determined whether or not the predicted address obtained in step S6 is smaller than the read data start address 214a plus the read data size 214b in the entry (step S7). In this determination, if it is small (affirmative determination), it means that the end of the lump data has not been reached, so that it is determined that the prediction look-ahead is still valid. The data is read out and secured in the read buffer memory 23 (step S8). On the other hand, if it is not small (negative determination), it means that the end of the lump data has been exceeded, so that the prediction look-ahead is not valid at that time, so the next read request is awaited as it is.

  On the other hand, when it is determined in step S9 that the data is read for the first time for a certain block of data and the process proceeds to step S11, the read request address is set to the previous address stored in the previous address storage unit 213d. It is determined whether or not it matches the size (step S11).

  If the determination in step S11 is negative, the read request is the first read request for the first data read of arbitrary chunk data. Therefore, in that case, a new entry is registered in the N entry table 214 for reading the data. First, it is determined whether or not there is an empty entry in the N entry table 214 (step S16). This can be done by searching for an entry for which the valid / invalid flag 214d is invalid. If there is no empty entry (No in step S16), the entry having the smallest read data read count 214c is searched (step S17). In step S18, information related to the read request is stored in the entry if there is a space, or in the entry searched in step S17 if there is no space. That is, the read request address and the read request size related to the read request are stored as the read data start address 214a and the read data size 214b, respectively. Further, “1” is stored in the read count 214c of read data. The valid / invalid flag 214d is validated. Then, the process proceeds to step S13.

  On the other hand, if the determination in step S11 is affirmative, the read request is a second or subsequent read request for the first data read of arbitrary chunk data. Therefore, in this case, the read request size is added to the read data size 214b in the entry of the entry number stored in the entry index storage unit 213e (step S12). This process is a part that advances the calculation of the size of the lump data. Then, the process proceeds to step S13.

  In step S13, based on the read request address and the read request size, data is read from the NAND flash memory 22 and transferred to the host device 1. Then, the read request address is stored in the previous address storage unit 213d (step S14), the entry number is stored in the entry index storage unit 213e (step S15), and the next read request is issued. wait.

  Next, a specific example of processing by the above read transfer processing will be described. An example will be described in which image data A, which is a single block of data stored in the NAND flash memory 22, is read as shown in FIG. The image data A is stored at addresses 10000 to 1200 bytes in the NAND flash memory 22 (physically, sector management is normally performed). These address and size values are numerical values for convenience of explanation. Therefore, for example, it is assumed that a read request comes from the host device 1 every 400 bytes. FIG. 6B is a diagram showing the transition of the entry and the previous address in response to each read request at the time of the first read. FIG. 6C is a diagram showing a change in the number of readings and a change in the contents of the predicted address buffer memory in response to each reading request at the second and subsequent readings.

  As described above, according to an embodiment of the present invention, the efficiency depends on the size of the batch data continuously read from the NAND flash memory 22 and the frequency of reading from the NAND flash memory 22. Predictive prefetch processing can be performed.

  The read transfer control method of the present invention can be employed, for example, when reading image data stored in an auxiliary storage device.

1 Host Device 2 Auxiliary Storage Device 21 Controller 211 Host Interface 212 Control Unit 213 Read Processing Parameter Storage Unit 214 N Entry Table 22 NAND Flash Memory 23 Read Buffer Memory 100 Host Device 200 Controller 300 Auxiliary Storage Device

Claims (8)

In response to a read request from a host device, when reading desired chunk data from a plurality of chunk data of different sizes stored in an auxiliary storage device in a plurality of times and transferring them to the host device, A read transfer control method in a controller for processing to predict data related to a next read request and pre-read from the auxiliary storage device until a next read request is received from a host device,
Said controller, in response to said magnitude of said lump data read out from the auxiliary storage device, in performing the predictive prefetching process, during the initial reading of the lump data, advance calculated the size, the second and subsequent A read transfer control method characterized in that the read- ahead prediction process is terminated according to the size at the time of reading. The controller predicts, based on the read request address and the read request size included in the read request, a value obtained by adding the read request size to the read request address as a read request address related to the next read request. , the predicted address, when it exceeds the value obtained by the size added to the start address of the bloc data read from said auxiliary storage device, according to claim 1, characterized in that aborting the predicted prefetch Read transfer control method. The controller has a table including a plurality of entries, information on the size, along with information identifying the lump data according to read, to claim 1, characterized in that storing one entry The read transfer control method described. Each entry includes information on the number of readings for the lump data, and the controller invalidates the entry related to the lump data with a small number of readings when the plurality of entries are empty. 4. The read transfer control method according to claim 3 , wherein the read transfer control method is assigned to the lump data to be read.   2. The read transfer control method according to claim 1, wherein the lump data is image data.   2. The read transfer control method according to claim 1, wherein the auxiliary storage device is a NAND flash memory.   2. The read transfer control method according to claim 1, wherein an interface between the controller and the host device is SATA. In response to a read request from a host device, when reading desired chunk data from a plurality of chunk data of different sizes stored in an auxiliary storage device in a plurality of times and transferring them to the host device, an auxiliary storage device controller for processing from the host device as previously prefetched in anticipation of data according to the following read request until it receives the next read request from the auxiliary storage device,
Depending on the size of the lump data to be read from the auxiliary storage device, the size of the lump data is calculated at the time of the first reading of the lump data when performing the predictive prefetching process. The auxiliary storage device controller is characterized in that the prediction prefetching process is terminated according to the size .

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