JP5830834B2 - Inverter control device and determination method of phase failure - Google Patents

Description

  The present invention relates to an inverter control device and a method for determining a phase failure.

  The average value of each phase current of the polyphase AC output from the inverter device to the motor is taken, the average value of these phase currents is further averaged, and the difference between the average value of each phase current and the further averaged value is obtained. There is known a phase loss detection method for detecting a phase failure when the value exceeds a reference value (Patent Document 1).

JP-A-6-245301

  However, in the conventional phase loss detection method, in the state where current does not flow from the motor power source to each phase of the inverter device, the average value of each phase current cannot be calculated. It was difficult.

  The problem to be solved by the present invention is that an inverter control device and a determination of an open-phase fault that can determine an open-phase fault even when no current flows from each power source such as a motor to each phase of the inverter device Is to provide a method.

  The present invention solves the above problem by discharging the charge stored in the power storage means by controlling ON / OFF of the switching element, and determining the open phase failure based on the discharge voltage of the power storage means.

  According to the present invention, in order to determine the open phase failure based on the discharge voltage of the power storage means, which is discharged by controlling the ON / OFF of the switching element, the loss failure is detected without using the current flowing from the power source to each phase. Can be detected.

It is a block diagram of the drive power supply device containing the inverter control apparatus which concerns on embodiment of this invention. It is a circuit diagram which shows a part of circuit of FIG. It is a circuit diagram which shows a part of circuit of FIG. It is a circuit diagram which shows a part of circuit of FIG. It is a figure which shows the voltage characteristic with respect to the discharge time in the capacitor | condenser of FIG. It is a flowchart which shows the control procedure of the inverter control apparatus of FIG. It is a block diagram of the drive power supply device containing the inverter control apparatus which concerns on other embodiment of invention. It is a figure which shows the table stored in the controller of FIG. It is a figure which shows the voltage characteristic with respect to the discharge time in the capacitor | condenser of FIG. It is a figure which shows the characteristic of the gate signal input into a switching element. It is a figure which shows the characteristic of the gate signal input into a switching element. It is a figure which shows the characteristic of the gate signal input into a switching element. It is a figure which shows the characteristic of the gate signal input into a switching element. It is a figure which shows the voltage characteristic with respect to the discharge time in a capacitor | condenser in case the open phase failure has arisen in U phase and V phase. It is a figure which shows the voltage characteristic with respect to the discharge time in a capacitor | condenser in case the open phase failure has arisen in the U phase. It is a flowchart which shows the control procedure of the inverter control apparatus which concerns on other embodiment of invention. It is a flowchart which shows the control procedure of the inverter control apparatus which concerns on other embodiment of invention. It is a figure which shows the voltage characteristic with respect to the discharge time in a capacitor | condenser in case the open phase failure has arisen in the U phase. It is a figure which shows the voltage characteristic with respect to the discharge time in a capacitor | condenser in case the open phase failure has arisen in the U phase and the W phase. It is a flowchart which shows the control procedure of the inverter control apparatus which concerns on other embodiment of invention. It is a flowchart which shows the control procedure of the inverter control apparatus which concerns on other embodiment of invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<< First Embodiment >>
FIG. 1 is a block diagram showing a drive power supply device for an electric vehicle including an inverter control device according to an embodiment of the present invention. Although detailed illustration is omitted, the electric vehicle of this example is a vehicle that travels using a three-phase AC power permanent magnet motor 4 as a travel drive source, and the motor 4 is coupled to the axle of the electric vehicle. Hereinafter, an electric vehicle will be described as an example, but the present invention can also be applied to a hybrid vehicle (HEV).

  The electric vehicle of this example includes the above-described three-phase AC motor 4, the battery 1 that is a power source of the motor 4, the inverter 3 that converts the DC power of the battery 1 into AC power, the relay 2, and the charger 8. And an electronic control unit (ECU) 11.

  The battery 1 is connected to the inverter 3 via the relay 2. The battery 1 is mounted with a secondary battery such as a lithium ion battery. The relay 2 is driven to open and close by the ECU 11 in conjunction with an ON / OFF operation of a key switch (not shown) of the vehicle.

  The inverter 3 includes a plurality of switching elements (insulated gate bipolar transistors IGBTs) Q1 to Q6 and rectifying elements that are connected in parallel to the switching elements Q1 to Q6, and current flows in a direction opposite to the current direction of the switching elements Q1 to Q6. (Diodes) D <b> 1 to D <b> 6, which converts the DC power of the battery 1 into AC power and supplies it to the motor 4. In this example, three pairs of circuits in which two switching elements are connected in series are connected in parallel to the battery 1, and each pair of switching elements is electrically connected to the three-phase input portion of the motor 4. . The same switching element is used for each switching element Q1-Q6, for example, an insulated gate bipolar transistor (IGBT) is used.

  In the example shown in FIG. 1, switching elements Q1 and Q2, switching elements Q3 and Q4, switching elements Q5 and Q6 are connected in series, and between the switching elements Q1 and Q2 and the U phase of the motor 4, switching element Q3 And Q4 are connected to the V phase of the motor 4, and the switching elements Q5 and Q6 are connected to the W phase of the motor 4. The switching of the switching elements Q1 to Q6 is controlled by the controller 10. The details of the operations of the switching elements Q1 to Q6 by the controller 10 will be described later.

  The inverter 3 includes a capacitor 5, a resistor 6 and a voltage sensor 7. The capacitor 5, the resistor 6 and the voltage sensor 7 are connected between the relay 2 and the switching elements Q1 to Q6. The capacitor 5 is provided to smooth the DC power supplied from the battery 1. The voltage sensor 7 is a sensor that detects the voltage of the capacitor 5.

  The charger 8 is connected between the relay 2 and the inverter 3. When the relay 2 is closed, the charger 8 and the battery 1 are electrically connected, and the charger 8 charges the battery 1.

  The ECU 11 is a part that controls the electric vehicle of this example as a whole, and controls, for example, the rotational torque of the motor 4 and the gear ratio of a transmission (not shown). In addition to controlling the relay 2 to be turned on and off, the ECU 11 displays a failure state of the inverter 3 on a display unit (not shown) or the like based on a signal from the controller 10 to notify the user of the failure of the inverter 3.

  Next, the principle that the charge stored in the capacitor 5 is consumed by the parasitic capacitances of the switching elements Q1 to Q6 will be described with reference to FIGS. 2a to 2c. 2a to 2c show a part of the circuit of the inverter 3 and a parallel connection portion of the capacitor 5 and the series circuit of the switching element Q1 and the switching element Q2. 2a shows a state where the switching element Q1 is turned on and the switching element Q2 is turned off, FIG. 2b shows a state where the switching element Q1 is turned off and the switching element Q2 is turned on, and FIG. 2c shows a state where the switching element Q1 is turned on. A state in which the element Q2 is turned off is shown. Capacitor C1 and capacitor C2 connected to switching element Q1 and switching element Q2 respectively indicate the parasitic capacitances of switching element Q1 and switching element Q2.

  First, when power from the battery 1 is supplied to the inverter 3 with the relay 2 turned on, electric charge is stored in the capacitor 5 and the voltage of the capacitor 5 rises to a voltage corresponding to the specified capacity.

  Next, the relay 2 is turned off while the electric charge is accumulated in the capacitor 5, the switching element Q1 is turned on, and the switching element Q2 is turned off as shown in FIG. 2a. The charge accumulated in the capacitor 5 moves as a recovery current (Ir), and the charge flows through the switching element Q1 and is stored in the parasitic capacitance C2.

  Then, while maintaining the relay 2 in the OFF state, as shown in FIG. 2B, the switching element Q1 is turned off and the switching element Q2 is turned on. By closing the switching element Q2, a closed circuit is formed by the parasitic capacitance C2 and the switching element Q2. Therefore, the charge charged in the parasitic capacitance C2 is discharged by the resistance component of the switching element Q2. Further, since the switching element Q1 is in the OFF state, the recovery current (Ir) flows through the parasitic capacitance C1, and the charge of the capacitor 5 is reduced by the amount of charge charged in the parasitic capacitance C1.

  Thereafter, while maintaining the relay 2 in the OFF state, as shown in FIG. 2C, the switching element Q1 is turned on and the switching element Q2 is turned off. By closing the switching element Q1, a closed circuit is formed by the parasitic capacitance C1 and the switching element Q1, so that the charge charged in the parasitic capacitance C1 is discharged by the resistance component of the switching element Q1. Further, since the switching element Q2 is in the OFF state, the recovery current (Ir) flows through the parasitic capacitance C2, and the electric charge is charged to the parasitic capacitance C2, so that the electric charge of the capacitor 5 further decreases.

  Then, as shown in FIGS. 2a to 2c, the charge stored in the capacitor 5 is discharged by repeating the ON and OFF operations of the switching element Q1 and the switching element Q2. Similarly, with respect to switching elements Q3 to Q6, the pair of switching elements Q3 to Q6 are respectively turned on and off, whereby the charge stored in capacitor 5 is discharged.

  As described above, the electric charge stored in the capacitor 5 is discharged by controlling on and off of the switching elements Q1 to Q6. However, for example, it is assumed that an abnormality has occurred in the switching element Q1 and a phase failure has occurred in the U phase. In such a case, even if the pair of switching elements Q1 to Q6 including at least the switching element Q1 is controlled to be turned on and off, the charge of the capacitor 5 is not discharged. Therefore, the charge consumption of the capacitor 5 when the U phase is abnormal is reduced compared to the charge consumption of the capacitor 5 when all phases are normal. Therefore, with respect to the voltage of the capacitor 5 after discharging with respect to the voltage of the capacitor 5 before discharging, the voltage after discharging when a phase failure has occurred in the U phase is higher than the voltage when normal in all phases. Voltage. In addition, the discharge rate of charges when a phase failure occurs in the U phase, in other words, the voltage drop rate of the capacitor 5 per unit time is slower than the discharge rate when normal in all phases.

  In this example, as described above, the electric charge stored in the capacitor 5 is discharged by controlling on and off of the switching elements Q1 to Q6, and the discharge state is detected based on the detection voltage of the voltage sensor 7, Whether or not the inverter 3 is defective is detected according to the discharge state.

  Hereinafter, in this example, the control content for detecting a deficiency failure of the inverter 3 will be described.

  In the state where the relay 2 is off, the controller 10 detects the voltage of the capacitor 5 from the voltage sensor 7 while controlling on and off of the switching elements Q1 to Q6. Since each of the switching elements Q1 to Q6 is turned on and off by a pulse signal transmitted from the controller 10, the discharge time of the capacitor 5 is adjusted by the period of the pulse signal and the transmission time. The controller 10 calculates the voltage drop of the capacitor 5 with respect to time from the pulse signal that is a switching signal and the detection voltage of the voltage sensor 7.

  The controller 10 is preset with a determination voltage (Vc) for determining that all three phases are abnormal. The determination voltage (Vc) is a voltage value obtained by adding a voltage of about 30% to the voltage drop (Vco) of the capacitor 5 per unit time when all three phases have a phase failure. The drop voltage of the capacitor 5 when the three-phase is an open-phase failure affects the consumption amount due to the resistance value of the resistor 6, and the resistance value is a preset value. It depends on the stage. The added percentage is not necessarily 30%, and may be 10% or 20%, for example. Note that the voltage drop of the capacitor 5 when the three phases are defective is equivalent to the voltage drop of the capacitor 5 when all the switching elements Q1 to Q6 are off.

  The controller 10 compares the voltage drop (Vx) per unit time calculated based on the detection voltage of the voltage sensor 7 with the determination voltage (Vc). When the drop voltage is smaller than the determination voltage, the controller 10 determines that a defective failure has occurred in all phases because no discharge is performed by the switching elements Q1 to Q6.

The controller 10 determines whether or not an open phase failure has occurred in one phase after determining whether or not an open phase failure has occurred in all three phases. The controller 10 is set with a threshold voltage (Vs) for determining an open phase failure under the same conditions. The controller 10 determines the three-phase deficit failure using the detection voltage until the detection voltage of the voltage sensor 7 reaches the threshold voltage (Vs), and the detection voltage of the voltage sensor 7 becomes the threshold voltage (Vs). Using the detected voltage until _a predetermined time (t _a ) elapses from the point in time, a single-phase failure is determined. The voltage of the capacitor 5 at the start of discharge varies depending on the amount of stored charge, is not fixed, and has an arbitrary voltage value. For this reason, in this example, when detecting a one-phase open phase fault, a single-phase open phase fault is detected under the same condition by detecting the open phase fault using a discharge voltage based on the threshold voltage (Vs). A failure can be detected.

The controller 10 is preset with a determination voltage (Va) when two phases are normal and one phase is missing. Here, regarding the voltage drop per predetermined time with respect to a certain reference voltage, the voltage drop when the three phases are normal is larger than the voltage drop when one phase is missing. Further, the difference between the voltage drop when the three phases are normal and the voltage drop when one phase is missing increases with time. Therefore, based on the time when the detection voltage upon reaching the threshold voltage (Vs) (time t1) a predetermined time (t _a) has elapsed (time t2) of the voltage sensor 7, when the three-phase is normal capacitor The determination voltage (Va) is set as a voltage difference from the predicted voltage (Vt). The voltage (Vt) is a value set by the switching elements Q1 to Q6 and the resistor 6, and the normal switching elements Q1 to Q6 are turned on and off from the time when the voltage of the capacitor 5 is Vs. The predicted voltage of the capacitor 5 after _a predetermined time (ta) has elapsed. The determination voltage (Va) is a reference potential difference with respect to the expected voltage (Vt), and the number of phases in which a phase failure has occurred is set according to the magnitude of the determination voltage (Va). For example, when a one-phase open phase failure has occurred, the detection voltage at time t2 takes a voltage higher than the expected voltage (Vt), and when a two-phase open phase failure has occurred, time t2 The detection voltage is higher than the expected voltage (Vt). In this example, the determination voltage (Va) is a determination voltage for detecting a one-phase open phase failure.

  When the potential difference (Vy) between the predicted voltage (Vt) and the detected voltage of the capacitor 5 is smaller than the determination voltage (Va) at time (t2), the discharge is normal. On the other hand, when the potential difference (Vy) between the predicted voltage (Vt) and the detected voltage is larger than the determination voltage (Va) at time (t2), the discharge is not normal and the voltage drop of the capacitor 5 decreases. Is insufficient, and a defective failure occurs in at least one phase.

  Next, referring to FIG. 3, the method for detecting an open-phase fault in this example will be described while showing the voltage characteristics of the capacitor 5 with respect to the discharge time. FIG. 3 shows the voltage characteristics of the capacitor 5 with respect to the discharge time of the charge. Here, the description will be made on the assumption that an abnormality has occurred in the switching element Q1 and a phase failure has occurred in the U phase.

First the capacitor 5 are power storage charges, from the state the voltage of the capacitor 5 is V _1, it begins to discharge. Voltage of the capacitor 5 gradually drops from _{V 1,} reaches Vs at time t1 (see graph a). The controller 10 calculates the voltage drop (Vx) per unit time from the voltage difference between the voltage (V1) at the start of discharge and the threshold voltage (Vs) and the time (t1). Then, the controller 10 compares the drop voltage (Vx) with the determination voltage (Vc), and detects whether or not an open phase failure has occurred in all phases. The discharge voltage when a defect occurs in all phases is at least smaller than the discharge voltage when one phase is normal. For this reason, when a defect has occurred in all phases, the slope is smaller than that in the graph a, and when discharge is started from the time of the voltage V1, the transition is as shown in the graph b. The slope of the grab b corresponds to the drop voltage (Vco). Similarly, when the determination voltage (Vc) is set as a slope and the voltage characteristic with the voltage V1 as a reference is shown, it is shown by a graph c.

  That is, when the discharge voltage (Vx) per unit time is smaller than the determination voltage (Vc), the voltage drop is small, and the controller 10 determines that a defective failure has occurred in all phases. Here, since the discharge voltage (Vx) per unit time is larger than the determination voltage (Vc), the controller 10 determines that no defect has occurred in all phases.

Next, the controller 10 discharges the capacitor 5 until the time (t2) is reached. Time (t2) is the time at which _a predetermined time (t _a ) has elapsed from time (t1). The controller 10 calculates a voltage difference (Vy) between the detection voltage (V2) at the time (t2) and the predicted voltage (Vt), compares the voltage difference (Vy) with the determination voltage (Va), It is detected whether or not a phase failure has occurred in at least one phase. As shown in the graph d of FIG. 3, when the three phases are normal, the detection voltage of the capacitor 5 becomes the predicted voltage (Vt) at the time (t2). Here, since a phase failure has occurred in one phase, the discharge is not sufficient, and as shown in graph a, the detected voltage (V2) becomes higher than the predicted voltage (Vt) at time t2. The voltage difference between the detection voltage (V2) and the predicted voltage (Vt) is larger than the determination voltage (Va). Since the voltage difference at time (t2) is larger than the determination voltage (Va), the controller 10 determines that an open phase failure has occurred in at least one phase.

  Next, the control procedure of this example will be described with reference to FIG. FIG. 4 is a flowchart showing the control procedure of this example.

  First, in step S1, the ECU 11 determines whether or not the charging of the battery 1 is completed. If the charging is completed, the ECU 11 proceeds to step S2. In step S <b> 2, the ECU 11 turns off the relay 2 and transmits a control signal indicating that the relay is turned off to the controller 10. In step S <b> 3, the controller 10 controls the switching elements Q <b> 1 to Q <b> 6 to be turned on and off, and discharges the charge accumulated in the capacitor 5. In step S <b> 4, the controller 10 detects the voltage of the capacitor 5 by the voltage sensor 7 while discharging the electric charge.

  In step S5, the controller 10 detects a voltage drop (Vx) per unit time based on the detection voltage in step S4. In step S6, the controller 10 compares the voltage drop (Vx) with the determination voltage (Vc).

  When the drop voltage (Vx) is equal to or lower than the determination voltage (Vc), the controller 10 determines that an open-phase failure has occurred in all three phases (S61). In step S62, the controller 10 transmits an abnormality signal to the ECU 11, for example, as a control process when an abnormality occurs in the inverter 3, and the ECU 11 displays a warning light (not shown) to the user. Announce the abnormality. Moreover, when the ECU 11 receives an abnormality signal from the controller 10, the ECU 11 may notify the inverter 3 that an abnormality has occurred by sending a mail to the user. Accordingly, since the user can know the abnormality before boarding the vehicle, a user-friendly system can be provided to the user.

On the other hand, when the drop voltage (Vx) is larger than the determination voltage (Vc), the process proceeds to step S7. In step S7, the controller 10 determines whether or not the detected voltage has reached the threshold voltage (Vs) based on the detected voltage in step S4. If the detected voltage has not reached the threshold voltage (Vs), the process returns to step S4, and the controller 10 performs the control of steps S4 to S6. Then, when the detected voltage becomes equal to or lower than the threshold voltage (Vs), the process proceeds to step S8 in order to determine whether or not a one-phase open phase failure has occurred. In step S <b> 8, the controller 10 detects the capacitor 5 with the voltage sensor 7. In step S9, the controller 10 determines whether or not the discharge time has elapsed (t2). Here, the discharge time refers to the elapsed time from the start of discharge in step S3. Then, corresponds to the time when the detected voltage becomes voltage (Vs) is the time in step S7 (t1), the time obtained by adding a predetermined time _{(t a)} the time of the step S9 (t2) is the time (t1) Become. If it is determined in step S9 that the discharge time has not elapsed (t2), the process returns to step S8. If the discharge time has elapsed (t2), the process proceeds to step S10.

  In step S10, the controller 10 calculates a voltage difference (Vy) based on the detected voltage in step S8. Specifically, the controller 10 calculates the predicted voltage (Vt) with respect to time (t2) when the three phases are normal based on the detected voltage (V1 (= Vs)) with respect to time (t1). The potential difference (Vy) is calculated by taking the difference between the detected voltage (V2) corresponding to the discharge time (t2) and the predicted voltage (Vt) among the detected voltages in step S8.

  In step S11, the controller 10 compares the potential difference (Vy) in step S10 with the determination voltage (Vc). When the potential difference (Vy) is smaller than the determination voltage (Vc), the controller 10 determines that all three phases are normal (S12) and ends the control. On the other hand, if the potential difference (Vy) is greater than or equal to the determination voltage (Vc), the controller 10 determines that an open-phase failure has occurred in at least one phase (step S111). In step S112, the controller 10 performs a control process when an abnormality has occurred in the inverter 3, as in step S62.

  As described above, in this example, the switching elements Q1 to Q6 are controlled to be turned on and off, and the capacitor 5 is discharged. Then, the discharge voltage of the capacitor 5 is calculated by calculating the drop voltage (Vx) or the potential difference (Vy) according to the detection voltage of the voltage sensor 7, and the phase failure of the inverter 3 is detected based on the discharge voltage. to decide. As a result, this example can detect a phase failure without using the current flowing from the battery 1 to each phase, and the phase failure can be detected even when the motor 4 is not energized, such as after charging. Can be detected. In addition, since the phase failure can be performed before the user uses the vehicle, the user can also know the phase failure before using the vehicle. Further, since the phase failure can be detected without energizing the motor 4, the motor 4 can be excluded when specifying the failure location, and the determination time for determining the failure can be shortened.

  Further, in this example, the discharge state of each switching element Q1 to Q6 is detected from the voltage of the capacitor, which is changed by controlling on and off of the switching elements Q1 to Q6, and an open phase failure is detected according to the discharge state. Is detected. As a result, this example can detect a phase failure without using the current flowing from the battery 1 to each phase, and the phase failure can be detected even when the motor 4 is not energized, such as after charging. Can be detected.

  Further, in this example, the relay 2 is turned off and the switching elements Q1 to Q6 are turned on and off in a state where the electric power from the battery 1 is not supplied to the motor, thereby detecting a phase failure. Thereby, even if the battery 1 and the inverter 3 are in a state where they are not conductive, a phase failure can be detected.

  Further, in this example, the phase failure is detected based on the detection voltage detected by the voltage sensor 7 after the voltage of the capacitor 5 drops to the threshold voltage (Vs). The voltage of the capacitor 5 is an arbitrary voltage according to the charge amount of the capacitor 5 when the switching elements Q1 to Q6 are turned on and off. Therefore, when the disclosure of control of on / off of the switching elements Q1 to Q6 is set as the discharge start voltage and the voltage drop with respect to the discharge start voltage is calculated as the discharge voltage, the same condition may not always be ensured. In this example, since the reference voltage for calculating the discharge voltage is determined by the threshold voltage (Vs), the same condition can be ensured.

  In this example, the drop voltage (Vx) is compared with the determination voltage (Vc), and whether or not an open phase fault has occurred in all phases is detected according to the comparison result. Thereby, it is possible to detect an open-phase failure in all phases without using the current flowing from the battery 1 to each phase.

  Further, in this example, the potential difference (Vy) between the predicted voltage (Vt) and the voltage of the capacitor 5 is compared with the determination voltage (Va), and at least one phase failure occurs in accordance with the comparison result. Detect whether or not. Accordingly, at least one phase failure can be detected without using the current flowing from the battery 1 to each phase.

  In this example, the voltage difference (Vy) between the detected voltage (V2) at the time (t2) and the predicted voltage (Vt) is calculated, and the voltage difference (Vy) is compared with the determination voltage (Va). However, an open-phase fault may be detected by calculating a voltage drop per unit time and comparing it with a predetermined determination voltage. The reference voltage for calculating the potential difference is not necessarily the threshold voltage (Vs), and other voltage values may be used as the threshold.

  The discharge voltage according to the present invention includes the voltage drop of the capacitor 5 per time and the detection voltage of the voltage sensor 7 with respect to a certain reference voltage, and the voltage drop (Vx), the detection voltage (V2) and the predicted voltage (Vt). Is equivalent to the voltage difference (Vy).

  That is, since the voltage changed with respect to a certain reference voltage corresponds to the discharge amount of the stored charge of the capacitor 5, the discharge voltage in the present invention may be a magnitude based on time, The magnitude may be based on a certain voltage value.

  In this example, the control portion is divided into the controller 10 and the ECU 11, but may be a single control unit including the controller 10 and the ECU 11.

  The battery 1 of this example corresponds to the “DC power supply” of the present invention, the capacitor 5 is “storage means”, the voltage sensor 7 is “voltage detection means”, and the switching elements Q1 to Q6 are “multiple pairs of switching”. The controller 10 corresponds to “control means”.

<< Second Embodiment >>
FIG. 5 is a block diagram showing a drive power supply device for an electric vehicle including an inverter control device according to another embodiment of the invention. This example differs from the first embodiment described above in that a temperature sensor 9 that detects the temperature of the battery 1 is provided. Since the other configuration is the same as that of the first embodiment described above, the description thereof is incorporated.

  The electric vehicle of this example further includes a temperature sensor 9 that detects the temperatures of the switching elements Q1 to Q6. The temperature sensor 9 is provided for each of the switching elements Q1 to Q6 and is controlled by the controller 10.

  The controller 10 stores in advance a table shown in FIG. The table shows a correspondence relationship between the predicted voltage (Vt) and the determination voltage (Va) with respect to the average temperature of the switching elements Q1 to Q6. FIG. 6 shows a table stored in the controller 10.

Here, when the switching elements Q1 to Q6 are mounted on the electric vehicle of this example, the temperature range that the switching elements Q1 to Q6 can take is set to be T _min or more and T _max or less. The detected temperature stored in the table of FIG. 5 is a discrete detected value for each predetermined temperature interval in a range from T _min to T _max . The detected temperature (T _n ) is higher than the temperature (T _min ) and lower than the temperature (T _max ). However, n is an arbitrary natural number.

The controller 10 extracts a plurality of detected temperatures from the temperature sensor 9 provided in each of the switching elements Q1 to Q6, and calculates an average temperature from the plurality of detected temperatures. The controller 10 refers to the table of FIG. 5 and extracts a predicted voltage (Vt) and a determination voltage (Va) corresponding to the average temperature. For example, when the average temperature of each switching element Q1~Q6 is _{T n,} the controller 10, as expected voltage Vtn (Vt), as Van determination voltage (Va), extracted. That is, the controller 10 corrects the predicted voltage (Vt) and the determination voltage (Va) by extracting the predicted voltage (V _tn ) and the determination voltage (V _an ) based on the table.

Then, similarly to the control of the first embodiment, the controller 10 calculates the potential difference (V _yn ) by taking the difference between the detected voltage corresponding to the discharge time (t 2) and the corrected predicted voltage (V _tn ), The potential difference (V _yn ) is compared with the corrected determination voltage (V _an ), and it is determined whether at least one phase is an open-phase failure according to the comparison result.

  Incidentally, the discharge characteristics of the capacitor 5 with respect to the switching elements Q1 to Q6 have temperature dependence as shown in FIG. FIG. 7 shows the voltage characteristics of the capacitor 5 with respect to the charge discharge time.

  The discharge characteristics of the capacitor 5 contribute to the temperature characteristics of the switching elements Q1 to Q6. When the temperature of the switching elements Q1 to Q6 is high, the discharge amount of the accumulated charge of the capacitor 5 increases, and the switching elements Q1 to Q6 When the temperature is low, the discharge amount of the accumulated charge in the capacitor 5 is reduced.

Here, the temperature range that the switching elements Q1 to Q6 can take is T _min or more and T _max or less, each switching element Q1 to Q6 is normal, and no defect occurs in all three phases. And Under such conditions, when the controller 10 controls on and off of the switching elements Q1 to Q6 to discharge the accumulated charge of the capacitor 5, the voltage characteristics of the capacitor 5 with respect to the discharge time are as shown in FIG. Become a characteristic. However, in FIG. 7, graph e1 is a discharge characteristic at the temperature (T _max ) of each switching element Q1 to Q6, and graph e2 is a discharge characteristic at a temperature (Tn) of each switching element Q1 to Q6. e3 denotes a discharge characteristic at the temperature of each of the switching elements Q1~Q6 _{(T min).}

As shown in FIG. 7, when the temperature of each of the switching elements Q1 to Q6 is T _max , the amount of electric charge discharge is large, so the voltage drop of the capacitor 5 per unit time is large, and the graph having the largest inclination It becomes. And when the temperature of each switching element Q1-Q6 is Tn, the voltage drop of the capacitor | condenser 5 per unit time becomes the 2nd highest, and becomes a graph with the 2nd largest inclination. Then, when the temperature of the switching elements Q1~Q6 is T _min, since the discharge amount of the charge is small, the voltage drop of the capacitor 5 per unit time becomes the smallest, the most inclination smaller graph.

Next, the influence of the temperature of switching elements Q1 to Q6 in the control of Embodiment 1 will be described with reference to FIG. The predicted voltage (time t2) when _a predetermined time (ta) elapses from the time (time t1) when the switching elements Q1 to Q6 are normal and the voltage of the capacitor 5 reaches the threshold voltage (Vs) ( As described above, Vt) varies according to the temperature of each switching element Q1 to Q6. The potential difference (Vy) also varies depending on the switching elements Q1 to Q6.

  Therefore, this example corrects the predicted voltage (Vt) and the determination voltage (Va) according to the temperature detected by the temperature sensor 9, so that an open-phase failure is detected with respect to the temperature change of each switching element Q <b> 1 to Q <b> 6. Judgment accuracy is improved.

  As described above, in this example, the predicted voltage (Vt) and the determination voltage (Va) are corrected according to the temperature detected by the temperature sensor 9. Thereby, this example can prevent the erroneous detection of the open phase failure due to the difference in the temperature condition of the inverter 3, and can improve the detection accuracy.

  In this example, the expected voltage (Vt) and the determination voltage (Va) are corrected according to the average temperature detected by the temperature sensor 9 provided in each of the switching elements Q1 to Q6. Need not be. For example, the controller 10 may perform correction based on the lowest temperature or the highest temperature among a plurality of detected temperatures corresponding to each of the switching elements Q1 to Q6.

  Further, in this example, the determination voltage (Vc) may be corrected according to the average temperature detected by the temperature sensor 9 provided in each of the switching elements Q1 to Q6, and the third embodiment described below. The determination voltage of the fourth embodiment may be used.

  The temperature sensor 9 of this example corresponds to the “temperature detection means” of the present invention.

<< Third Embodiment >>
An electric vehicle including an inverter control device according to another embodiment of the invention will be described. In this example, part of the control content of the controller 10 is different from the first embodiment described above. Since the other configuration is the same as that of the first embodiment described above, the description thereof is incorporated. 8 to 11 show waveforms of gate signals input to the switching elements Q1 to Q6.

  As shown in FIGS. 8 to 11, the controller 10 inputs four kinds of gate signals to the switching signals Q1 to Q6, respectively. 8 to 11, D indicates a period of the switching element, and DT is a period in which the high-side switching elements Q1, Q3, and Q5 are turned off and a period in which the low-side switching elements Q2, Q4, and Q6 are turned off. Yes, indicating dead time.

The controller 10 first controls the switching elements Q1 to Q6 with the gate signal shown in FIG. 8 while being stored in the capacitor 5, and sequentially switches the switching elements Q1 to Q6 with the gate signals of FIG. 9, FIG. 10, and FIG. To control. The time for inputting the gate signals in FIGS. 9, 10 and 11 is a predetermined time (t _p ), which is the same time.

  Further, the controller 10 calculates the voltage drop of the capacitor 5 per time from the detection voltage of the voltage sensor 7 while controlling the switching elements Q1 to Q6 with the gate signals of FIGS. Then, the controller 10 detects an open phase failure of each phase from the calculated voltage drop.

  When the gate signal shown in FIG. 8 is input to the switching elements Q1 to Q6, the charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q1 to Q6. At this time, the controller 10 calculates the voltage drop (Vx) per time of the capacitor 5 and compares it with the determination voltage (Vc) as in the first embodiment. When the drop voltage (vx) is larger than the determination voltage (Vc), the controller 10 determines that no phase failure has occurred in all phases. On the other hand, when the voltage drop (Vx) is smaller than the determination voltage (Vc), the controller 10 determines that an open phase failure has occurred in all phases.

When the gate signal shown in FIG. 9 is input to the switching elements Q1 to Q6, the charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q1 to Q4. The controller 10 inputs the gate signal of FIG. 8 for a predetermined time (t _p ), and calculates the voltage drop (V _uv ) of the capacitor 5. The voltage drop (V _uv ) is the difference between the detection voltage at the time when the gate signal in FIG. 9 is input (time t1) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t1) (time t2). Is calculated from

When the gate signal shown in FIG. 10 is input to the switching elements Q1 to Q6, the charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q1, Q2, Q5, and Q6. The controller 10 inputs the gate signal of FIG. 10 for a predetermined time (t _p ), and calculates a voltage drop (V _uw ) of the capacitor. The voltage drop (V _uw ) is the difference between the detection voltage at the time when the gate signal in FIG. 10 is input (time t2) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t2) (time t3). Is calculated from

When the gate signal shown in FIG. 11 is input to the switching elements Q1 to Q6, the charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q3 to Q6. The controller 10 inputs the gate signal of FIG. 11 for a predetermined time (t _p ), and calculates a voltage drop (V _vw ) of the capacitor. The voltage drop (V _vw ) is the difference between the detection voltage at the time when the gate signal in FIG. 11 is input (time t3) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t3) (time t4). Is calculated from

When the gate signals in FIGS. 9 to 11 are input, if the switching elements corresponding to two of the three phases are respectively discharged and no phase failure occurs in all phases, the voltage drop of the capacitor 5 ( V _uv ), drop voltage (V _uw ), and drop voltage (V _vw ) are equal to each other. On the other hand, when a failure has occurred in at least one switching element Q1 to Q6, discharge is not performed even if the on and off of the switching elements Q1 to Q6 are controlled. Therefore, the voltage drop when the gate signal is input to the switching elements Q1 to Q6 of the phase including the failed switching elements Q1 to Q6 is different from the switching elements Q1 to Q6 of the phase not including the failed switching elements Q1 to Q6. Therefore, it becomes smaller than the voltage drop when inputting the gate signal. Therefore, when discharging in a certain phase, the drop voltage differs depending on whether or not the switching elements Q1 to Q6 that have failed in the phase are included.

  With reference to FIG. 12, the characteristics of each drop voltage will be described by taking as an example a case where an open-phase failure has occurred in the U phase and the V phase. FIG. 12 is a graph showing the characteristics of the capacitor 5 voltage with respect to the discharge time when an open-phase failure has occurred in the U phase and the V phase.

When a phase failure occurs in the U phase and the V phase, the drop voltage (V _vw ) is equal to the drop voltage (V _uw ), and the drop voltage (V _uv ) is the drop voltage (V _vw ) and drop. It becomes smaller than the voltage (V _uw ), and the relationship of (Equation 1) is established.

V _uv << V _uw ≒ V _vw (Formula 1)
Further, as shown in FIG. 12, since each fall voltage that corresponds to the slope, the slope indicating the voltage drop (V _uv) is smaller than the slope indicating the slope and voltage drop (V _uw) shows the voltage drop (V _uv) Become.

  The characteristics of each drop voltage will be described with reference to FIG. 13 by taking as an example a case where a phase failure has occurred in the U phase. FIG. 13 is a graph showing the characteristics of the capacitor 5 voltage with respect to the discharge time when a phase failure occurs in the U phase.

For example, when a phase failure occurs in the U phase, the drop voltage (V _uv ) is equal to the drop voltage (V _uw ), and the drop voltage (V _vw ) is equal to the drop voltage (V _uv ) and the drop voltage ( V _uw ), and the relationship of (Expression 2) is established.

_{V uv ≒ V uw ≒ (1/2} ) × V vw ( Equation 2)
In this example, the controller 10 is preset with a determination voltage (Vd) for determining that all three phases are abnormal. Determination voltage (Vd) is a for a given time (t _a) per drop voltage of the capacitor 5 when all phases of the three phases is phase loss fault, the voltage value obtained by adding a voltage of about 30% . The added percentage is not necessarily 30%, and may be 10% or 20%, for example. Note that the voltage drop of the capacitor 5 when the three phases are defective is equivalent to the voltage drop of the capacitor 5 when all the switching elements Q1 to Q6 are off.

Then, the controller 10 _{compares the} voltage drop (V _uv ), the voltage drop (V _uw ), the voltage drop (V _vw ), and the determination voltage (Vd) to determine _{how many} minimum voltage drops (Vmin) are included. Here, the minimum drop voltage (Vmin) indicates a voltage having the smallest drop voltage among the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ). In order to widen the range of the smallest voltage to some extent, the minimum voltage drop (Vmin) may include a voltage drop that is a predetermined voltage difference with respect to the voltage with the smallest voltage drop.

When one minimum drop voltage (Vmin) is extracted among the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ), the controller 10 performs one extracted drop. The voltage is compared with the determination voltage (Vd). When the extracted one drop voltage is smaller than the determination voltage (Vd), the controller 10 calculates a drop voltage lower than the determination voltage (Vd), and the gate signal of the on / off cycle is input. It is determined that a phase failure has occurred in the switching element.

For example, an open-phase failure has occurred in the U phase and the V phase, and when the switching elements Q1 to Q6 are controlled by the gate signal in FIG. 9, the switching elements Q1 to Q4 corresponding to the U phase and the V phase are turned on / off. Even when the off-period gate signal is input, the switching elements Q1 to Q4 are not discharged. Since no gate signal including an ON period is input to the switching elements Q5 and Q6 corresponding to the W phase, the switching elements Q5 and Q6 are not discharged. Therefore, when the gate signal of FIG. 9 is input, since no discharge is performed in all the switching elements Q1 to Q6, the drop voltage (V _uv ) is a drop voltage corresponding to the discharge by the resistor 6 and is determined. The voltage is smaller than the voltage (Vd). That is, in FIG. 11, the drop voltage (V _uv ) is indicated by a graph f1, and the determination voltage (Vd) is indicated by a graph f2. The slope of the graph f1 is smaller than the slope of the graph f2.

When two minimum drop voltages (Vmin) are extracted from the drop voltage (V _uv ), drop voltage (V _uw ), and drop voltage (V _vw ), the controller 10 defines the extracted drop voltage. The determination voltage (Ve) is calculated and set by multiplying by a multiple of (for example, 1.5 times). The controller 10 compares the determination voltage (Ve) with the voltage drop (Vr) that is not the minimum voltage drop (Vmin) that has not been extracted. When the voltage drop (Vr) not extracted is larger than the determination voltage (Ve), the controller 10 is a switching element to which a gate signal is commonly input when calculating the extracted voltage drop. Judge that an open-phase failure has occurred.

For example, when an open-phase failure has occurred in the U phase, even if a gate signal having an on / off cycle is input to the switching elements Q1 and Q2 corresponding to the U phase, the switching elements Q1 and Q2 are discharged. Absent. Therefore, among the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ), the drop voltage (V _uv ) and the drop voltage (V _uw ) are two drop voltages having a small voltage. The determination voltage (Ve) is a value obtained by multiplying the drop voltage (V _uv ) or the drop voltage (V _uw ) by a specified multiple. The drop voltage (V _vw ) is a discharge voltage when a gate signal having an on / off period is input to a normal switching element, and the drop voltage (V _uv ) or the drop voltage (V _uw ) is about 2.0 times. Since the value is multiplied, the value is higher than the determination voltage (Ve).

That is, in FIG. 13, the drop voltage (V _vw ) is indicated by a graph g2, and the determination voltage (Ve) is indicated by a graph g1. The slope of the graph g2 is larger than the slope of the graph g1.

On the other hand, for example, when the voltage drop (V _uv ), the voltage drop (V _uw ), and the voltage drop (V _vw ) have different voltage values due to variations in the switching elements Q1 to Q6 of each phase, the voltage drop (Vr ) And the minimum drop voltage (Vmin) is a difference due to variations in switching elements, and thus the drop voltage (Vr) is smaller than the determination voltage (Ve). Therefore, when the voltage drop (Vr) is smaller than the determination voltage (Ve), the controller 10 determines that no phase failure has occurred.

  Next, the control procedure of this example will be described with reference to FIGS. 14a and 14b. 14a and 14b are flowcharts showing the control procedure of this example.

  Steps S21 to S27 are the same as Steps S1 to S7 in FIG. 4, and Steps S261 and S262 are the same as Steps S61 and S62 in FIG. In step S23, the controller 10 inputs the gate signal (gate signal A) shown in FIG. 8 to the switching elements Q1 to Q6, and discharges the capacitor 5.

  When the detected voltage becomes the voltage (Vs) at the discharge time (t1) in step S27, the gate signal (gate signal B) shown in FIG. 9 is input to each of the switching elements Q1 to Q6 in step S28, and the capacitor 5 is connected. Discharge. In step S <b> 29, the controller 10 detects the voltage of the capacitor 5 from the voltage sensor 7. In step S30, if the discharge time is not time t2, the process returns to step S29, the voltage of the capacitor 5 is detected, and if the discharge time is time t2, the process proceeds to step S31. Thereby, between time t1 and time t2, the controller 10 detects the voltage of the capacitor 5 while discharging the capacitor 5 by the gate signal of FIG.

In step S31, the gate signal (gate signal C) shown in FIG. 10 is input to the switching elements Q1 to Q6, and the capacitor 5 is discharged. In step S <b> 32, the controller 10 detects the voltage of the capacitor 5 from the voltage sensor 7. In step S33, if the discharge time is not time t3, the process returns to step S32, the voltage of the capacitor 5 is detected, and if the discharge time is time t3, the process proceeds to step S34. Time t3 is a time after _a predetermined time (t _a ) has elapsed from time t2. Thereby, between time t2 and time t3, the controller 10 detects the voltage of the capacitor 5 while discharging the capacitor 5 by the gate signal of FIG.

In step S34, the gate signal (gate signal D) shown in FIG. 11 is input to the switching elements Q1 to Q6, and the capacitor 5 is discharged. In step S <b> 35, the controller 10 detects the voltage of the capacitor 5 from the voltage sensor 7. In step S36, if the discharge time is not time t4, the process returns to step S35, the voltage of the capacitor 5 is detected, and if the discharge time is time t4, the process proceeds to step S37. The time t4 is a time after _a predetermined time (ta) has elapsed from the time t3. Thereby, between time t3 and time t4, the controller 10 detects the voltage of the capacitor | condenser 5, discharging the capacitor | condenser 5 with the gate signal of FIG.

In step _{S <b> 37} , the controller 10 calculates a drop voltage (V _uv ), a drop voltage (V _uw ), and a drop voltage (V _vw ) during a predetermined time (t _p ) based on the detection voltage of the capacitor 5. (See FIGS. 12 and 13). That is, the controller 10 calculates a drop voltage (V _uv ) from the difference between the detection voltage at time t1 and the detection voltage at time t2, and drops the voltage (V _uw ) from the difference between the detection voltage at time t2 and the detection voltage at time t3. And a drop voltage (V _vw ) is calculated from the difference between the detection voltage at time t3 and the detection voltage at time t4.

In step S38, the controller 10 extracts the minimum voltage drop (Vmin) from the voltage drop (V _uv ), the voltage drop (V _uw ), and the voltage drop (V _vw ). That is, the controller 10 compares the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ), and extracts the drop voltage having the smallest value. When there is one voltage drop having the smallest value, there is one minimum voltage drop (Vmin). When there are two voltage drops with the smallest value, there are two minimum voltage drops (Vmin). At this time, the phrase “there are two voltage drops with the smallest value” includes the case where the values of the two voltage drops are equal, or the case where each value is within a predetermined range. When all the drop voltages have the same value, there is no minimum drop voltage (Vmin).

  If there is one minimum voltage drop (Vmin) in step S39, the process proceeds to step S391. If the number of minimum voltage drops (Vmin) is not one, the process proceeds to step S40. In step S391, the controller 10 compares the minimum voltage drop (Vmin) with the determination voltage (Vd). If the minimum voltage drop (Vmin) is equal to or higher than the determination voltage (Vd), the controller 10 determines that it is normal (S394), and ends the control of this example. On the other hand, when the minimum voltage drop (Vmin) is smaller than the determination voltage (Vd), in the switching elements Q1 to Q6 corresponding to two phases to which the gate signal is input when calculating the minimum voltage drop (Vmin), An open-phase failure has occurred, and the controller 10 determines that an open-phase failure has occurred in the switching elements Q1 to Q6 corresponding to the two phases (step S392). In step S393, similarly to step S262, the controller 10 performs a control process when an abnormality has occurred in the inverter 3, and ends the control process of this example.

In step S40, when there are two minimum voltage drops (Vmin), the process proceeds to step S401, and when the number of minimum voltage drops (Vmin) is not two, the process proceeds to step S41. In step S401, the controller 10 includes three voltage drop _{(V uv, V uw, V} vw) minimum voltage drop (Vmin) is not a voltage drop in the (Vr), in other words, three drop voltage _{(V uv} , V _uw , V _vw ), the voltage drop (Vr) remaining without being extracted in step S38 is compared with the determination voltage (Ve). Here, the determination voltage (Ve) is a voltage obtained by multiplying the minimum drop voltage (Vmin) by a specified multiple by the controller 10. If the voltage drop (Vr) is equal to or lower than the determination voltage (Ve), the controller 10 determines that it is normal (S404), and the control of this example is terminated. On the other hand, when the drop voltage (Vr) is larger than the determination voltage (Ve), a common one of the two phases to which the gate signal is input when calculating the two minimum drop voltages (Vmin). In the switching elements Q1 to Q6 corresponding to, a phase failure has occurred, and the controller 10 determines that a phase failure has occurred in the switching elements Q1 to Q6 corresponding to the one phase (S402). In step S403, similarly to step S262, the controller 10 performs control processing when an abnormality has occurred in the inverter 3, and ends the control processing of this example.

  If there are two minimum voltage drops (Vmin) in step S40, the controller 10 determines that each phase is normal (S41), and ends the control processing of this example.

As described above, in this example, the switching elements Q5 and Q6 corresponding to the W phase are turned off, and the switching elements Q1 to Q4 corresponding to the U phase and the V phase are controlled to turn on and off, thereby reducing the voltage drop ( V _uv ) is calculated, and the switching elements Q3, Q4 corresponding to the V phase are turned off, and the switching elements Q1, Q2, Q5, Q6 corresponding to the V phase and the W phase are controlled to turn on and off. The voltage (V _uw ) is calculated, and the switching elements Q1 and Q2 corresponding to the U-phase are turned off, and the switching elements Q3 to Q6 corresponding to the V-phase and the W-phase are controlled to turn on and off to reduce the voltage drop ( V _vw ) is calculated. Then, the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ) are respectively compared to detect a phase failure in the U, V, and W phases. As a result, by comparing a plurality of discharge voltages, the temperature that is the cause of variation is compared under the same conditions, so that the detection accuracy of the phase failure can be improved.

In addition, in this example, when one drop voltage extracted from the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ) is smaller than the determination voltage (Vd), the extraction is performed. It is determined that an open-phase failure has occurred in two phases corresponding to the one dropped voltage. Thereby, in this example, it is possible to detect which two phases out of the three phases cause the phase loss.

In addition, in this example, when two drop voltages are smaller than the remaining one drop voltage among the drop voltage (V _uv ), the drop voltage (V _uw ), and the drop voltage (V _vw ), the two drops A voltage obtained by multiplying one drop voltage of the voltage by a specified multiple is set as a determination voltage (Ve). When the remaining one drop voltage is larger than the determination voltage (Ve), it is determined that an open phase failure has occurred in one common phase among the phases corresponding to the two drop voltages. Thereby, this example can detect which phase has a phase failure out of the three phases.

  In this example, the value obtained by multiplying the drop voltage by the specified multiple is used as the determination voltage (Ve). Therefore, there is a possibility that a difference in drop voltage due to variations of the switching elements Q1 to Q6 is erroneously determined as a phase failure. Can be suppressed.

In this example, in step S38 to step S40, step S391 to step S393, and step S401 to step S403, the minimum voltage drop (Vmin) is extracted, and the voltage drop and the determination voltage (Vd) or the determination voltage (Ve) are extracted. Is detected in which phase the phase failure has occurred, but depending on whether the voltage drop in step S38 satisfies the relationship of (Equation 1) or (Equation 2), It may be detected whether a failure has occurred. For example, when the drop voltage (V _uw ) and the drop voltage (V _vw ) are equal and the drop voltage (V _uv ) is smaller than the drop voltage (V _vw ) or the drop voltage (V _uw ), the condition of (Equation 1) In order to satisfy the above, the controller 10 determines that a phase failure has occurred in the U phase and the V phase. Further, for example, the voltage drop _{(V uv)} and voltage drop _{(V uw)} is equal, if the voltage drop _{(V vw)} is equal to half the voltage of the voltage drop _{(V uv)} is the condition of (Equation 2) In order to satisfy this condition, the controller 10 determines that a phase failure has occurred in the U phase.

  Thereby, this example can detect which phase failure has occurred in which two phases or which one phase among the three phases.

  In this example, an open-phase failure is detected in the inverter 3 formed in three phases, but it is not always necessary to have three phases, and may be two phases or four or more phases.

  For example, in the inverter 3 formed in two phases, in this example, the switching element corresponding to one of the two phases is turned off, and the switching element corresponding to the other phase is controlled on and off. Then, the capacitor 5 is discharged, and a first drop voltage (first discharge voltage) per time is calculated. Further, in this example, with the switching element corresponding to the other phase turned off, the switching element corresponding to one phase is controlled to be turned on and off, and the capacitor 5 is discharged. The second voltage drop (second discharge voltage) is calculated. In this example, the controller 10 compares the first drop voltage and the second drop voltage. When the first discharge voltage is smaller than the second discharge voltage, the discharge in one phase is not sufficient, and therefore this example determines that an open phase failure has occurred in one phase.

The present example, as the voltage drop per predetermined time _{(t a),} the voltage drop _{(V uv),} but calculates the voltage drop _{(V uw)} and voltage drop _{(V vw),} necessarily, the predetermined time _{(t a} For example, it may be calculated as a voltage drop per sampling period of the voltage sensor 7 and control in this example may be performed.

  Further, in this example, when the discharge time (t2, t3, t4) has elapsed in step S30, step S33, and step S36, the process proceeds to the next step. For example, from a predetermined time when the discharge time becomes a threshold value If it is long, the control process when the inverter is abnormal may be performed similarly to step S393, and the control process of this example may be terminated. In the inverter 3, when a phase failure occurs, the discharge time becomes longer than when the discharge time is normal. For this reason, when the discharge time is longer than the predetermined time, the controller 10 determines that a defect occurs and performs control processing when the inverter is abnormal. Thereby, this example can detect an open phase failure early.

<< 4th Embodiment >>
An electric vehicle including an inverter control device according to another embodiment of the invention will be described. In this example, part of the control content of the controller 10 is different from the first embodiment and the third embodiment described above. Since the configuration other than this is the same as the first embodiment and the third embodiment described above, the description thereof is incorporated.

  The controller 10 controls the switching elements Q1 to Q6 with the gate signal shown in FIG. After the control by the gate signal in FIG. 8, the controller 10 inputs a gate signal for periodically turning on and off the switching elements Q1 and Q2 in order to control only the U-phase switching elements Q1 and Q2 on and off. The switching elements Q3 to Q6 are turned off. Next, in order to turn on and off only the V-phase switching elements Q3 and Q4, the controller 10 inputs a gate signal for periodically turning on and off the switching elements Q3 and Q4, and the switching elements Q1, Q2, Q5 and Q6 are turned off. Next, in order to turn on and off only the W-phase switching elements Q5 and Q6, the controller 10 inputs a gate signal that periodically turns on and off the switching elements Q5 and Q6, and turns on the switching elements Q1 to Q4. Turn off.

  When the gate signal shown in FIG. 8 is input to the switching elements Q1 to Q6, as in the first embodiment or the third embodiment, a voltage drop (Vx) per time is calculated and the voltage drop is calculated. (Vx) is compared with the determination voltage (Vc). Then, the controller 10 determines whether or not a phase failure has occurred in all phases according to the comparison result.

When the on and off gate signals are input to the U-phase switching elements Q1 and Q2, the stored charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q1 and Q2. The controller 10 inputs the gate signal for a predetermined time (t _p ), and calculates a voltage drop (V _u ) of the capacitor 5. The drop voltage (V _u ) is calculated from the difference between the detection voltage at the time when the gate signal is input (time t1) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t1) (time t2). (See FIGS. 15 and 16).

When the on and off gate signals are input to the V-phase switching elements Q3 and Q4, the stored charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q3 and Q4. The controller 10 inputs the gate signal for a predetermined time (t _p ), and calculates a voltage drop (V _v ) of the capacitor 5. The drop voltage (V _v ) is calculated from the difference between the detection voltage at the time when the gate signal is input (time t2) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t2) (time t3). (See FIGS. 15 and 16).

When the on and off gate signals are input to the W-phase switching elements Q5 and Q6, the stored charge of the capacitor 5 is discharged by the resistor 6 and the switching elements Q5 and Q6. The controller 10 inputs the gate signal for a predetermined time (t _p ), and calculates a voltage drop (V _w ) of the capacitor 5. The drop voltage (V _w ) is calculated from the difference between the detection voltage at the time when the gate signal is input (time t3) and the detection voltage when the predetermined time (t _p ) has elapsed from time (t3) (time t4). (See FIGS. 15 and 16).

When an on / off gate signal is input only to the one-phase switching elements Q1 to Q6, discharge is performed by the two switching elements Q1 to Q6, and no discharge is performed in the remaining switching elements Q1 to Q6. Therefore, when the switching elements Q1 to Q6 are normal, the drop voltage (V _u ), drop voltage (V _v ), and drop voltage (V _w ) are equal. On the other hand, when at least one of the switching elements Q1 to Q6 is out of order, the drop voltage (V _u ), drop voltage (V _v ), and drop voltage (V _w ) are not equal. Therefore, in this example, the controller 10 compares the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ), and identifies the phase in which the open phase failure occurs according to the comparison result. Meanwhile, a phase failure of the inverter 3 is detected.

  Hereinafter, the detection method of the phase failure of the inverter 3 in this example will be described.

First, the controller 10 compares the drop voltage (V _u ), the drop voltage (V _v ), the drop voltage (V _w ) with the determination voltage (Vd), and determines a voltage (Vf) smaller than the determination voltage (Vd). Know how many are included.

When one voltage (Vf) is included in the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ), the controller 10 determines the voltage (Vf) by a specified multiple (for example, Multiply by (1.5 times) to calculate and set the judgment voltage (V _F ). Further, the controller 10 extracts a smaller voltage (V _r1 ) from a voltage drop larger than the determination voltage (Vd), in other words, two voltage drops that are not the voltage (Vf) among the three voltage drops. The judgment voltage (V _R1 ) is calculated and set by multiplying by a specified multiple. Then, the controller 10, the voltage drop _(V u), does not correspond to the voltage (Vf) and the voltage _{(V r1)} in the voltage drop _{(V v)} and the voltage drop _{(V w),} the remaining one voltage (V _r2 ) is compared with the determination voltage (V _F ) and the determination voltage (V _R1 ). When the voltage (V _r2 ) is larger than the determination voltage (V _F ) and the voltage (V _r2 ) is smaller than the determination voltage (V _R1 ), the controller 10 calculates a drop voltage corresponding to the voltage (Vf). In this case, it is determined that a phase failure has occurred in the switching element to which the gate signal having the on / off period is input. That is, the controller 10 determines that an open phase failure has occurred in one phase.

  The above detection method will be described with reference to FIG. 15 by taking as an example a case where an open phase failure has occurred only in the U phase. FIG. 15 is a graph showing the characteristics of the capacitor 5 voltage with respect to the discharge time when a phase failure occurs in the U phase.

In the case where the U-phase has an open-phase failure, no discharge is performed even if a gate signal is input, and therefore no discharge is performed in all the switching elements Q1 to Q6. Therefore, the drop voltage (V _u ) is smaller than the determination voltage (Vd). Since the V phase and the W phase are normal, the drop voltage (V _v ) and the drop voltage (V _w ) are larger than the determination voltage (Vd). The controller 10 determines that the voltage (Vf) smaller than the determination voltage (Vd) among the drop voltage (V _u ), drop voltage (V _v ), and drop voltage (V _w ) is the drop voltage (V _u ). It is determined that one voltage (Vf) is included.

The determination voltage (V _F ) is a value obtained by multiplying the drop voltage (V _u ) by a specified multiple. For determination voltage _{(V R1),} the voltage drop _{(V w)} is assumed to drop voltage _{(V v)} is less than, the voltage drop _{(V w)} a voltage _{(V r1),} and the determination voltage _{(V R1)} is the drop The voltage (V _w ) is multiplied by a specified multiple. Since the drop voltage (V _u ) is a drop voltage when not discharged by the switching elements Q1 to Q6, even if the drop voltage (V _u ) is multiplied by a specified multiple, it is discharged by at least two switching elements. It becomes a voltage smaller than the drop voltage at the time. Like the drop voltage (V _v ), the drop voltage (V _w ) is a drop voltage when discharged by the two switching elements Q5 and Q6, and therefore the difference from the drop voltage (V _v ) is slight. . Therefore, as shown in FIG. 13, the voltage drop (V _v ) corresponding to the voltage (V _r2 ) that is not the voltage (Vf) and the voltage (V _r1 ) is larger than the determination voltage (Vf), and the determination voltage (V _R1). ) Smaller. On the other hand, when the drop voltage (V _v ) does not become larger than the determination voltage (Vf), or when the drop voltage (V _v ) does not become smaller than the determination voltage (V _R1 ), it contradicts the above-described detection logic.

  If the controller 10 contradicts the detection logic, the controller 10 determines that the detection logic is abnormal, ends the control processing of this example without outputting the determination result of the phase failure, and detects the voltage of the capacitor 5 again. Fix and run detection logic.

In the case of including two voltages (Vf) among the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ), the controller 10 is a specified multiple of the two voltages (Vf). The determination voltage (V _F1 ) and the determination voltage (V _F2 ) are calculated and set by multiplying each (for example, 1.5 times). The controller 10 includes the remaining voltage (V _r ) that does not correspond to the voltage (Vf) among the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ), and the determination voltage (V _R1 ) and the determination voltage (V _R2 ) are compared. When the voltage (V _r ) is smaller than the determination voltage (V _F1 ) and the voltage (V _r ) is smaller than the determination voltage (V _F2 ), the controller 10 calculates a drop voltage corresponding to the voltage (Vf). In this case, it is determined that a phase failure has occurred in the switching element to which the gate signal having the on / off period is input. That is, the controller 10 determines that a phase failure has occurred in two phases.

  The above detection method will be described with reference to FIG. 16 by taking as an example a case where an open phase failure has occurred in the U phase and the W phase. FIG. 16 is a graph showing the characteristics of the capacitor 5 voltage with respect to the discharge time when an open-phase failure has occurred in the U phase and the W phase.

When the U-phase and W-phase fail in phase failure, no discharge occurs even when a gate signal is input. Therefore, all the switching elements are between time t1 and time t2 and between time t3 and time t4. No discharge is performed in Q1 to Q6. Therefore, the drop voltage (V _u ) and the drop voltage (V _W ) are smaller than the determination voltage (Vd). Among the drop voltage (V _u ), drop voltage (V _v ), and drop voltage (V _w ), the controller 10 determines that a voltage smaller than the determination voltage (Vd) is a drop voltage (V _u ) and a drop voltage (V _w ). And it is determined that two voltages (Vf) are included.

The determination voltage (V _F1 ) and the determination voltage (V _F2 ) are values obtained by multiplying the drop voltage (V _u ) and the drop voltage (V _w ) by specified multiples, respectively. Since the drop voltage (V _u ) and the drop voltage (V _w ) are the drop voltages when not being discharged by the switching elements Q1 to Q6, a specified multiple of the drop voltage (V _u ) and the drop voltage (V _w ). Is multiplied by a voltage lower than the voltage drop when the two switching elements Q3 and Q4 are discharged. Therefore, as shown in FIG. 16, the drop voltage (V _v ) corresponding to the voltage (V _r ) that is not the two voltages (Vf) is larger than the determination voltage (V _F1 ) and the determination voltage (V _F2 ). On the other hand, when the drop voltage (V _v ) is smaller than the determination voltage (V _F1 ), or when the drop voltage (V _v ) is smaller than the determination voltage (V _F2 ), it contradicts the detection logic described above. If there is a contradiction with the detection logic, the controller 10 determines that the detection logic is abnormal as described above.

  Next, the control procedure of this example will be described with reference to FIGS. 17a and 17b. 17a and 17b are flowcharts showing the control procedure of this example.

  Steps S51 to S67 are basically the same as steps S21 to S37 shown in FIGS. 14a and 14b, and different steps (S58, S61, S64 and step S67) will be described below. Step S561 and step S562 are the same as step S261 and step S262 shown in FIG. 14a.

  In step S58, the controller 10 inputs to the switching elements Q1 and Q2 a gate signal E that controls on and off only the switching elements Q1 and Q2 corresponding to the U phase.

  In step S61, the controller 10 inputs, to the switching elements Q3 and Q4, a gate signal F that controls on and off only the switching elements Q3 and Q4 corresponding to the V phase.

  In step S64, the controller 10 inputs to the switching elements Q5 and Q6 a gate signal G that turns on and off only the switching elements Q5 and Q6 corresponding to the W phase.

In step S67, the controller 10 calculates a drop voltage (V _u ), a drop voltage (V _v ), and a drop voltage (V _w ) for a predetermined time (t _p ) based on the detection voltage of the capacitor 5. (See FIGS. 15 and 16).

In step S68, the controller 10 extracts a voltage smaller than the determination voltage (Vd) from the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ). _{Let the} extracted voltage be a voltage (V _f ).

In step S69, the controller 10 is extracted voltage _{(V f)} it is determined whether one is,遷Ri to step S691 if the voltage _{(V f)} there is one, the voltage _{(V f} ), The process proceeds to step S70. In step S691, the controller 10 calculates a determination voltage (V _F ) and a determination voltage (V _R1 ). The determination voltage (V _F ) is calculated by multiplying the voltage (V _f ) by a specified multiple. The determination voltage (V _R1 ) is a voltage drop (V _r1 , V _r2 ) that is not a voltage (V _f ) among the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ). Of these, it is calculated by multiplying one drop voltage (V _r1 ) by a specified multiple. Here, the drop voltage (V _r1 ) is a small drop voltage of the two drop voltages (V _r1 , V _r2 ). When the two drop voltages (V _r1 , V _r2 ) are equal, one of the drop voltages is the drop voltage (V _r1 ).

In step S692, the controller 10 compares the drop voltage (V _r2 ) with the determination voltage (V _F ) and the determination voltage (V _R1 ). When the voltage drop (V _r2 ) is larger than the determination voltage (V _F ) and the voltage drop (V _r2 ) is smaller than the determination voltage (V _R1 ), in step S693, the controller 10 When calculating the drop voltage (V _u , V _v or V _w ) corresponding to (V _f ), a failure has occurred in the switching elements Q1 to Q6 to which the gate signal is input, and an open phase failure has occurred in one phase. Judge that In step S694, the controller 10 performs a control process when an abnormality has occurred in the inverter 3, and ends the control process of this example.

On the other hand, if the voltage drop (V _r2 ) is greater than the determination voltage (V _F ) and the voltage drop (V _r2 ) is less than the determination voltage (V _R1 ), the controller 10 determines in step S695. Determines that the detection logic is abnormal, and ends the control processing of this example.

In step S70, the controller 10 determines whether or not there are two extracted voltages (V _f ). If there are two voltages (V _f ), the process proceeds to step S701. In step S701, the controller 10 calculates a determination voltage (V _F1 ) and a determination voltage (V _F2 ). The determination voltage (V _F1 ) is calculated by multiplying one of the two voltages (V _f ) by a specified multiple, and the determination voltage (V _F1 ) is calculated by multiplying the other voltage by a specified multiple.

In step S702, the controller 10 compares the drop voltage (V _r ) with the determination voltage (V _F1 ) and the determination voltage (V _F2 ). The drop voltage (V _r ) is the remaining drop voltage that is not the voltage (V _f ) among the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ). When the voltage drop (V _r ) is larger than the determination voltage (V _F1 ) and the voltage drop (V _r ) is larger than the determination voltage (V _F2 ), in step 703, the controller 10 When the drop voltage (V _u , V _v or V _w ) corresponding to one voltage (V _f ) is calculated, a failure has occurred in the switching elements Q1 to Q6 to which the gate signal is input, and a two-phase failure has occurred. Is determined to have occurred. In step S704, the controller 10 performs control processing when an abnormality has occurred in the inverter 3, and ends the control processing of this example.

On the other hand, if the voltage drop (V _r ) is larger than the determination voltage (V _F1 ) and the voltage drop (V _r ) is not larger than the determination voltage (V _F2 ), the controller 10 determines in step S705. Does not detect a phase failure using the discharge voltage calculated in step S67, determines that the detection logic is abnormal, and ends the control processing of this example.

If the extracted voltage (V _f ) is not two in step S70, the controller 10 determines that each phase is normal (step S71), and ends the control processing of this example. Here, the extracted voltage (V _f ) is not two means that all the drop voltages (V _u , V _v and V _w ) are larger than the determination voltage (Vd). Thus, the discharge is normally performed.

As described above, in this example, the switching elements Q3 to Q6 corresponding to the V phase and the W phase are turned off, and the on / off of the switching elements Q1 and Q2 corresponding to the U phase is controlled to reduce the voltage drop ( V _u ) is calculated, and the switching elements Q1, Q2, Q5, and Q6 corresponding to the U phase and the W phase are turned off, and the switching elements Q3 and Q4 corresponding to the V phase are controlled to turn on and off. The voltage (V _v ) is calculated, and the switching elements Q1 to Q4 corresponding to the U phase and the V phase are turned off, and the switching elements Q5 and Q6 corresponding to the W phase are controlled to be turned on and off to reduce the voltage drop ( V _w ) is calculated. Then, the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ) are respectively compared to detect a phase failure in the U, V, and W phases. As a result, by comparing a plurality of discharge voltages, the temperature that is the cause of variation is compared under the same conditions, so that the detection accuracy of the phase failure can be improved.

In this example, one drop voltage (V _u , V _v, or V _w ) is determined from the determination voltage (Vd) among the drop voltage (V _u ), the drop voltage (V _v ), and the drop voltage (V _w ). If it is smaller, it is determined that a phase failure has occurred in the phase corresponding to the one voltage drop.

  When an open phase failure occurs in one phase, the voltage drop of the phase in which the open phase failure occurs is smaller than the determination voltage (Vd). It can be determined that a defect failure has occurred. Then, in the flow shown in FIG. 17b, instead of steps S691 to S695, a step of determining that a phase failure has occurred in the phase corresponding to the voltage (Vf) may be provided. Thereby, this example can detect which phase has a phase failure out of the three phases.

In addition, in this example, two voltage drops (V _u , V _v, or V _w ) are determined from the determination voltage (Vd) among the voltage drop (V _u ), the voltage drop (V _v ), and the voltage drop (V _w ). If it is smaller, it is determined that a phase failure has occurred in the phases corresponding to the two voltage drops.

  When a phase failure has occurred in two phases, the voltage drop of the phase in which the phase failure has occurred is smaller than the determination voltage (Vd), so the phase corresponding to the voltage drop that is smaller than the determination voltage (Vd). It can be determined that a defect failure has occurred. Then, in the flow shown in FIG. 17b, a step of determining that an open phase failure has occurred in the phase corresponding to the voltage (Vf) may be provided instead of steps S701 to S705. Thereby, in this example, it is possible to detect which two phases out of the three phases cause the phase loss.

In this example, the determination voltage (Vd), the determination voltage determination voltage (V _F ), and the determination voltage (V _R1 ) are set, and the drop voltage (V _r2 ) is smaller than the determination voltage (V _F ) When the voltage (V _r2 ) is larger than the determination voltage (V _R1 ), the output of the determination result of the phase failure is prohibited. When the drop voltage (V _r2 ) is smaller than the judgment voltage (V _F ) or when the drop voltage (V _r2 ) is larger than the judgment voltage (V _R1 ), a contradiction occurs in the logic of the open phase fault in this example. Therefore, there is a possibility that the detection accuracy of the open-phase fault based on the voltage drop of the capacitor 5 is lowered. In this example, when there is a contradiction in the logic of the phase failure, the output of the determination result of the phase failure is prohibited, so that the detection accuracy of the phase failure can be improved.

In this example, the determination voltage (Vd), the determination voltage (V _F1 ), and the determination voltage (V _F2 ) are set, and the drop voltage (V _r ) is smaller than the determination voltage (V _F1 ) or the drop voltage ( When V _r ) is smaller than the determination voltage (V _F2 ), the output of the determination result of the phase failure is prohibited. If the drop voltage (V _r ) is smaller than the judgment voltage (V _F1 ), or if the drop voltage (V _r ) is smaller than the judgment voltage (V _F2 ), a contradiction will occur in the logic of the phase failure in this example. Therefore, there is a possibility that the determination accuracy of the phase failure based on the voltage drop of the capacitor 5 is lowered. In this example, when there is a contradiction in the logic of the phase failure, the output of the determination result of the phase failure is prohibited, so that the accuracy of determination of the phase failure can be improved.

In this example, the drop voltage (V _u ), drop voltage (V _v ) and drop voltage (V _w ) are compared, the two drop voltages are equal, and the remaining one drop voltage is greater than the two drop voltages. If it is smaller, it may be determined that a phase failure has occurred in the phase corresponding to the one drop voltage. As shown in FIG. 15, when a phase failure occurs in the U phase, the drop voltage (V _v ) and the drop voltage (V _w ) are equal, and the drop voltage (V _u ) is the drop voltage (V _v ). Smaller than. Therefore, in this example, after calculating the drop voltage in step S67, the respective drop voltages are compared, and when the two drop voltages are equal and the remaining one drop voltage is smaller than the two drop voltages, one is calculated. It is determined that a phase failure has occurred in the phase. Thereby, this example can detect which phase has a phase failure out of the three phases.

This example also compares the drop voltage (V _u ), drop voltage (V _v ), and drop voltage (V _w ), the two drop voltages are equal, and the remaining one drop voltage is more than the two drop voltages. If it is larger, it may be determined that a phase failure has occurred in the phases corresponding to the two voltage drops. As shown in FIG. 16, when a phase failure occurs in the U phase and the W phase, the drop voltage (V _u ) and the drop voltage (V _w ) are equal, and the drop voltage (V _v ) is the drop voltage ( _Less than V _u ). Therefore, in this example, after calculating the drop voltage in step S67, the respective drop voltages are compared, and when the two drop voltages are equal and the remaining one drop voltage is greater than the two drop voltages, the two drop voltages are compared. It is determined that a phase failure has occurred in the phase. Thereby, in this example, it is possible to detect which two phases out of the three phases cause the phase loss.

DESCRIPTION OF SYMBOLS 1 ... Battery 2 ... Relay 3 ... Inverter 4 ... Motor 5 ... Capacitor 6 ... Resistance 7 ... Voltage sensor 8 ... Charger 9 ... Temperature sensor 10 ... Controller 11 ... ECU
Q1, Q2, Q3, Q4, Q5, Q6 ... switching elements

Claims (23)

Power storage means connected to a DC power source;
Voltage detection means for detecting the voltage of the power storage means;
A plurality of pairs of switching elements respectively connected to both terminals of the power storage means;
Control means for controlling ON / OFF of the switching element to convert DC power of the DC power source into AC power;
The control means includes
Controlling ON / OFF of the switching element to lower the voltage of the power storage means to a threshold voltage;
A discharge voltage of the power storage unit is calculated based on a detection voltage detected by the voltage detection unit after dropping to the threshold voltage, and an open phase failure is determined based on the discharge voltage.
An inverter control device characterized by that. The plurality of pairs of switching elements are connected to form a plurality of phases;
The control means includes
An operation of turning on one switching element of the pair of switching elements corresponding to at least one phase of the plurality of phases and turning off the other switching element, and turning off the one switching element and turning on the other switching element By repeatedly performing the operation in a predetermined discharge time to discharge the charge stored in the power storage means, and based on the voltage detected by the voltage detection means, the discharge voltage of the power storage means during the discharge time The inverter control device according to claim 1, wherein the inverter control device calculates and determines a phase failure based on the discharge voltage . A motor driven by the power of the DC power supply and further electrically connected to the plurality of pairs of switching elements;
The control means includes
The open phase failure is determined by controlling ON / OFF of the switching element in a state where the electric power is not supplied to the motor.
The inverter control device according to claim 1 . The control means includes
The inverter control according to claim 1, wherein ON / OFF of the switching element is controlled, and a voltage drop of the power storage unit due to discharge per predetermined time is calculated as the discharge voltage. apparatus. The control means includes
4. The inverter control device according to claim 1, wherein ON / OFF of the switching element is controlled, and a potential difference between a reference voltage and a voltage of the power storage unit is calculated as the discharge voltage. 5. . The control means includes
The inverter control device according to claim 1, wherein the open-phase failure is determined according to a comparison result between the discharge voltage and a predetermined determination voltage. The control means includes
A voltage that is equal to or higher than the discharge voltage of the power storage means that is discharged in a state where all of the plurality of pairs of switching elements are turned off is set as the determination voltage;
The inverter control device according to claim 6, wherein an open-phase fault of all phases corresponding to the plurality of pairs of switching elements is determined according to a result of comparing the discharge voltage and the determination voltage. . The control means includes
A discharge voltage of the power storage means that is discharged by another pair of switching elements in a state where at least one pair of switching elements is turned off among the plurality of pairs of switching elements is set as the determination voltage,
The phase failure of at least one of a plurality of phases corresponding to the plurality of pairs of switching elements is determined according to a result of comparing the discharge voltage and the determination voltage. The inverter control device described. Power storage means connected to a DC power source;
Voltage detection means for detecting the voltage of the power storage means;
A plurality of pairs of switching elements respectively connected to both terminals of the power storage means;
Control means for controlling ON / OFF of the switching element to convert DC power of the DC power source into AC power;
Temperature detecting means for detecting the temperature of the plurality of pairs of switching elements,
The control means includes
Controlling the ON / OFF of the switching element to discharge the charge stored in the power storage means;
Based on the voltage detected by the voltage detection means, the discharge voltage of the power storage means is calculated,
According to a comparison result between the discharge voltage and a predetermined determination voltage, a phase failure is determined,
An inverter control device, wherein the determination voltage is corrected based on a temperature detected by the temperature detection means. The plurality of pairs of switching elements are connected to form at least two phases;
The control means includes
The first discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the other of the two phases with the switching element corresponding to one of the two phases turned OFF. And
With the switching element corresponding to the other phase turned OFF, the second discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the one phase,
The inverter control device according to any one of claims 1 to 3, wherein the open-phase fault is determined according to a result of comparing the first discharge voltage and the second discharge voltage. . The plurality of pairs of switching elements are connected to form at least three phases;
The control means includes
With the switching element corresponding to the first phase among the three phases turned OFF, the ON / OFF of the switching element corresponding to the second phase and the third phase among the three phases is controlled. Calculating a first discharge voltage;
The second discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the first phase and the third phase in a state where the switching element corresponding to the second phase is turned OFF. And
A third discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the first phase and the second phase in a state where the switching element corresponding to the third phase is turned OFF. And
4. The phase failure is determined according to a result of comparing the first discharge voltage, the second discharge voltage, and the third discharge voltage. 5. The inverter control device described in 1. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
A voltage equal to or higher than the voltage drop of the power storage means due to the discharge per predetermined time with all the plurality of pairs of switching elements turned OFF is set as a determination voltage,
12. The method according to claim 11, wherein when the first discharge voltage is smaller than the determination voltage, it is determined that the phase failure has occurred at least in the second phase and the third phase. Inverter control device. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
When the second discharge voltage and the third discharge voltage are smaller than the first discharge voltage, the second discharge voltage or a voltage obtained by multiplying the third discharge voltage by a specified multiple is determined as a determination voltage. Set as
The inverter control device according to claim 11, wherein when the first discharge voltage is larger than the determination voltage, it is determined that a phase failure has occurred in the first phase. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
When the first discharge voltage is equal to the second discharge voltage, and the third discharge voltage is equal to half the voltage of the first discharge voltage, the phase loss fault occurs in the third phase. The inverter control device according to claim 11, wherein it is determined that the error occurs. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
When the second discharge voltage is equal to the third discharge voltage, and the first discharge voltage is smaller than the third discharge voltage, the second phase and the third phase have the missing voltage. 12. The inverter control device according to claim 11, wherein it is determined that a phase failure has occurred. The plurality of pairs of switching elements are connected to form at least three phases;
The control means includes
With the switching elements corresponding to the first phase and the second phase among the three phases turned OFF, the ON / OFF of the switching element corresponding to the third phase among the three phases is controlled. Calculating a first discharge voltage;
The second discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the first phase in a state where the switching elements corresponding to the second phase and the third phase are turned OFF. And
A third discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the second phase in a state where the switching element corresponding to the third phase and the first phase is turned OFF. And
4. The phase failure is determined according to a result of comparing the first discharge voltage, the second discharge voltage, and the third discharge voltage. 5. The inverter control device described in 1. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
A voltage equal to or higher than the voltage drop of the power storage means due to the discharge per predetermined time with all the plurality of pairs of switching elements turned OFF is set as a determination voltage,
17. The inverter control device according to claim 16, wherein when the first discharge voltage is smaller than the determination voltage, it is determined that a phase failure has occurred in the third phase. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
A voltage equal to or higher than the voltage drop of the power storage means due to the discharge per predetermined time with all the plurality of pairs of switching elements turned OFF is set as a determination voltage,
When the first discharge voltage and the second discharge voltage are smaller than the determination voltage, it is determined that a phase failure has occurred in the third phase and the second phase. The inverter control device according to claim 16. Power storage means connected to a DC power source;
Voltage detection means for detecting the voltage of the power storage means;
A plurality of pairs of switching elements respectively connected to both terminals of the power storage means;
Control means for controlling ON / OFF of the switching element to convert DC power of the DC power source into AC power;
The plurality of pairs of switching elements are connected to form at least three phases;
The control means includes
Controlling the ON / OFF of the switching element to discharge the charge stored in the power storage means;
Based on the voltage detected by the voltage detection means, the discharge voltage of the power storage means is calculated,
With the switching elements corresponding to the first phase and the second phase among the three phases turned OFF, the ON / OFF of the switching element corresponding to the third phase among the three phases is controlled. Calculating a first discharge voltage;
The second discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the first phase in a state where the switching elements corresponding to the second phase and the third phase are turned OFF. And
A third discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the second phase in a state where the switching element corresponding to the third phase and the first phase is turned OFF. And
According to a result of comparing the first discharge voltage, the second discharge voltage, and the third discharge voltage, a phase failure is determined,
A voltage that is equal to or higher than the voltage drop of the power storage means due to discharge per predetermined time with all the plurality of pairs of switching elements turned OFF is set as a first determination voltage,
When the first discharge voltage is smaller than the first determination voltage, a voltage obtained by multiplying the first discharge voltage by a specified multiple is set as a second determination voltage;
A voltage obtained by multiplying the third discharge voltage by a specified multiple is set as a third determination voltage;
When the second discharge voltage is smaller than the second determination voltage, or when the second discharge voltage is larger than the third discharge voltage, the output of the determination result of the phase failure is prohibited. ,
The inverter control device according to claim 1, wherein the first discharge voltage, the second discharge voltage, and the third discharge voltage are a voltage drop of the power storage unit due to discharge per predetermined time. Power storage means connected to a DC power source;
Voltage detection means for detecting the voltage of the power storage means;
A plurality of pairs of switching elements respectively connected to both terminals of the power storage means;
Control means for controlling ON / OFF of the switching element to convert DC power of the DC power source into AC power;
The plurality of pairs of switching elements are connected to form at least three phases;
The control means includes
Controlling the ON / OFF of the switching element to discharge the charge stored in the power storage means;
Based on the voltage detected by the voltage detection means, the discharge voltage of the power storage means is calculated,
With the switching elements corresponding to the first phase and the second phase among the three phases turned OFF, the ON / OFF of the switching element corresponding to the third phase among the three phases is controlled. Calculating a first discharge voltage;
The second discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the first phase in a state where the switching elements corresponding to the second phase and the third phase are turned OFF. And
A third discharge voltage is calculated by controlling ON / OFF of the switching element corresponding to the second phase in a state where the switching element corresponding to the third phase and the first phase is turned OFF. And
According to a result of comparing the first discharge voltage, the second discharge voltage, and the third discharge voltage, a phase failure is determined,
A voltage that is equal to or higher than the voltage drop of the power storage means due to discharge per predetermined time with all the plurality of pairs of switching elements turned OFF is set as a first determination voltage,
When the first discharge voltage and the second discharge voltage are smaller than the first determination voltage, a voltage obtained by multiplying the first discharge voltage by a specified multiple is used as the second determination voltage. A voltage obtained by multiplying the discharge voltage of 2 by a specified multiple is set as the third determination voltage,
When the third discharge voltage is smaller than the determination voltage of 2, or when the third discharge voltage is smaller than the determination voltage of 3, the output of the determination result of the phase failure is prohibited,
The inverter control device according to claim 1, wherein the first discharge voltage, the second discharge voltage, and the third discharge voltage are a voltage drop of the power storage unit due to discharge per predetermined time. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
When the first discharge voltage and the second discharge voltage are equal and the third discharge voltage is smaller than the first discharge voltage, the phase failure occurs in the second phase. The inverter control device according to claim 16, wherein the inverter control device is determined. The first discharge voltage, the second discharge voltage, and the third discharge voltage are voltage drops of the power storage means due to discharge per predetermined time,
The control means includes
When the first discharge voltage is equal to the second discharge voltage, and the third discharge voltage is greater than the first discharge voltage, the first phase and the third phase have the missing voltage. The inverter control device according to claim 16, wherein it is determined that a phase failure has occurred. Detecting the voltage of the power storage means connected to the DC power source by the voltage detection means;
A step of controlling ON / OFF of a plurality of pairs of switching elements connected to form a plurality of phases while being connected to both terminals of the power storage means to convert the DC power of the DC power source into AC power; and
Controlling ON / OFF of the switching element to lower the voltage of the power storage means to a threshold voltage;
Calculating a discharge voltage of the power storage unit based on a detection voltage detected by the voltage detection unit after dropping to the threshold voltage, and determining an open phase failure based on the discharge voltage. To determine the inverter phase failure.

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