JP5830124B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachislot machine.

  Conventionally, a game machine called a so-called pachislot is known. In such a gaming machine, a plurality of reels each having a plurality of symbols arranged on each surface, a gaming medal, a coin, etc. (hereinafter referred to as “medal etc.”) are inserted, and a start lever is operated by the player. And a start switch that requests the start of rotation of a plurality of reels and a stop button provided corresponding to each of the plurality of reels is detected by the player, and rotation of the corresponding reels is detected. And a stop switch for outputting a signal requesting the stop.

  Further, such a gaming machine is provided corresponding to each of the plurality of reels, and based on a stepping motor that transmits each driving force to each reel and a signal output by the start switch and the stop switch. And a reel control unit that controls the operation of the motor and rotates and stops each reel.

  With this configuration, when the gaming machine detects that the start lever has been operated, a lottery is performed based on the random number value, and the result of the lottery (hereinafter referred to as “internal winning combination”) and the stop button are operated. The rotation of the reel is stopped on the basis of the timing at which is detected.

  In recent years, as a gaming machine of this type, after the completion of a big bonus (hereinafter referred to as “BB”) in which a game that gives a relatively large profit to a player can be performed a predetermined number of times, replay related to replaying has been determined as an internal winning combination. There is known one that operates a gaming state (hereinafter referred to as “high RT”) with a high probability (see, for example, Patent Document 1).

  Further, in this gaming machine, when the number of medals paid out during the operation of the BB is equal to or more than a predetermined number, in combination with the above-mentioned high RT, a specific internal winning combination (hereinafter referred to as “small role”) related to the medals being paid out. The assist time (hereinafter referred to as “AT”) for notifying “)” is activated. Such a state in which both high RT and AT are operated is referred to as ART.

  According to the gaming machine, during the operation of ART, the probability that the winning combination will be lost is lower than in the general gaming state, and in contrast, the probability that the small combination will win increases, so the number of medals to be paid out increases. Can be made. For this reason, an interest of a player can be attracted and the game nature can be improved.

  Also, in recent years, a predetermined number of special games (hereinafter referred to as chance zones) that are advantageous to the player are generated with a predetermined probability by internally winning a predetermined small role (for example, cherry) during general games. A gaming machine is known in which a predetermined number of chance zones are added with a predetermined probability by internally winning a predetermined small role in the chance zone (see, for example, Patent Document 2). According to the gaming machine, the interest of the player can be maintained by appropriately extending the number of continued games in the chance zone advantageous to the player.

  On the other hand, important processing of the gaming machine, such as control of the rotating reel of the gaming machine, internal winning combination processing, winning determination processing, and medal payout processing are performed by the CPU of the main control circuit, and the CPU performs these processing. The program is executed according to a program stored in advance in the ROM.

  The internal winning combination is determined based on the random number and the internal lottery table, and the rotation of each reel is stopped based on the determined internal winning combination and the timing at which the reel stop operation is detected. At this time, the extracted random value is stored in a random value storage area of the RAM, and an internal winning combination is determined in the internal lottery process based on the stored random value.

  Further, the sub control circuit performs various processes such as determination and execution of effect data based on various commands output from the main control board such as a start command. For this reason, the sub-control circuit also includes a RAM, and in the RAM, various information obtained by processing of the CPU of the main control board, for example, the extracted random number value, the gaming state, the internal winning combination, the number of payouts , Information for specifying the bonus carryover status, setting value, and the like, various counters, flags, and the like are stored.

  Further, the sub-control circuit is connected to a sub-device such as a scaler device that enlarges a picture displayed on the display device of the gaming machine in order to enhance the effect (see, for example, Patent Document 3 and Patent Document 4).

  In such a device, when a parameter request command is transmitted from the scaler device to the sub-control circuit, the sub-control circuit transmits a command with a parameter added to the scaler device. At this time, if the scaler device does not transmit a parameter request command to the sub-control circuit within a predetermined time of 5 s, for example, after starting, the sub-control circuit determines that communication has been interrupted and registers it as an error history. Then, the communication task with the scaler device is completed.

JP 2009-5978 A JP 20042366763 A JP 2001-58021 A JP 2011-11035 A

  However, if the sub-control circuit ends the communication task, it cannot communicate with the scaler device even if the scaler device resumes communication. Further, the sub control circuit cannot recognize that the scaler device has resumed communication. Further, the sub control circuit cannot recognize that the scaler device has lost communication.

  The present invention has been made in view of the circumstances as described above, and when there is no communication from the scaler device to the sub control circuit for a predetermined time, the sub control circuit determines that the communication has been interrupted and registers it as an error history. An object of the present invention is to provide a gaming machine that does not end a communication task and registers communication resumption as an error history when communication is resumed from a scaler device and resumes communication with the scaler device.

Therefore, the gaming machine according to the present invention selects a main control unit that executes processing relating to the progress of the game, a display unit that displays predetermined information, and the size of the original information of the predetermined information displayed on the display unit A scaler control board that can be controlled, and a sub-control part that controls an effect according to the progress of the game based on a command output from the main control part, wherein the sub-control part is the scaler control board Sub-device reception interrupt means for receiving transmission data from the device and a case where there is no communication from the scaler control board for a predetermined time is detected as a communication disconnection error different from the case where there is an abnormality in the reception data from the scaler control board Sub-device error detection means, and the communication disconnection error detected by the sub-device error detection means is stored as communication disconnection error information. After detection subdevice error detecting means of the communication interruption error, the sub control unit, when receiving a communication from the scaler control board, that it has received the communication, the case from the scaler control board do not have a predetermined time communication And a storage unit having an error information history storage area for storing as communication return error information different from the case where there is an abnormality in the received data from the scaler control board, and the sub-device reception interrupt means includes the scaler control board If there is a physical layer error in the transmission data from the received data, the received data is discarded without being saved, and the sub-device error detecting means also includes the scaler even when the sub-device receiving interrupt means discards the received data. It is determined that there is no communication from the control board, and the sub-device error detection means is connected to the scaler control board. After detecting when there is no constant-time communication as the communication interruption error, it stores the communication interruption error information to the error information history storage area, the sub control unit, continuously, from the scaler control board follows Determining whether there is communication, and when determining that the next communication has occurred from the scaler control board, error information history storage means for storing the communication return error information in the error information history storage area; and And an error information history display means for displaying the communication disconnection error information and the communication return error information stored by the error information history storage means on the display unit.

  According to this gaming machine, when there is no communication from the scaler device to the sub-control circuit for a predetermined time, the sub-control circuit determines that the communication is interrupted and registers it as error information in the error history and does not end the communication task. In addition, when communication is resumed from the scaler device, the communication resumption is registered in the error history as communication return error information, and communication with the scaler device can be resumed. A communication return error can be displayed on the display unit. Even if there is communication from the scaler device to the sub-control circuit within a predetermined time, if there is an error in the data transmitted by the scaler device, the sub-control circuit discards the received data and communicates from the scaler device. By determining that no data has been received, even if normal data is not received within a predetermined time, it is determined that communication has been interrupted and can be registered in the error history as communication disconnection error information.

  According to the present invention, when there is no communication from the scaler device to the sub-control circuit for a predetermined time, the sub-control circuit determines that communication is interrupted, registers it as an error history, and does not end the communication task. When communication is resumed from the scaler device, it is possible to provide a gaming machine that registers the communication resumption as an error history and resumes communication with the scaler device.

It is an external view of the gaming machine in the present embodiment. It is a figure which shows the symbol display area and winning line of the game machine in this Embodiment. It is a figure which shows the symbol arrangement | positioning table of the game machine in this Embodiment. It is a figure which shows the front upper part of the game machine in this Embodiment. It is a figure which shows the cross section of the display panel unit vicinity of the game machine in this Embodiment. It is a figure which shows the display panel of the game machine in this Embodiment. (A) is a figure which shows the left decoration panel and left infrared sensor of the game machine in this Embodiment. (B) is a figure which shows the left infrared sensor of the game machine in this Embodiment. It is a figure which shows the structure of the main control circuit of the game machine in this Embodiment. It is a figure which shows the structure of the sub control circuit of the game machine in this Embodiment. It is a figure which shows the example of a transition of the game state of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table determination table of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table for RB1 gaming states of the game machine in this Embodiment. It is a figure which shows the example of the internal lottery table for RB2 game states of the game machine in this Embodiment. It is a figure which shows the example of RT transition table of the game machine in this Embodiment. It is a figure which shows the example of the internal winning combination determination table for bonus of the gaming machine in this Embodiment. It is a figure which shows the example of the internal winning combination determination table for a small combination and replay of the game machine in this Embodiment. It is a figure which shows the example of the symbol combination table of the game machine in this Embodiment. It is a figure which shows the example of the table at the time of the bonus action | operation of the game machine in this Embodiment. It is a figure which shows the example of the drawing-in priority order table A of the gaming machine in this Embodiment. It is a figure which shows the example of the drawing-in priority order table B of the gaming machine in this Embodiment. It is a figure which shows the example of the stop table of the game machine in this Embodiment. It is a figure which shows the example of the internal winning combination storing area | region of the game machine in this Embodiment. It is a figure which shows the example of the display combination storage area | region of the game machine in this Embodiment. It is a figure which shows the example of the carryover combination storage area | region of the game machine of this Embodiment. It is a figure which shows the example of the game state flag storage area | region of the gaming machine of this Embodiment. It is a figure which shows the example of storage of the symbol storage area A of the game machine in this Embodiment. It is a figure which shows the example of storage of the symbol storage area B of the game machine in this Embodiment. It is a figure which shows the example of the navigation mode transfer lottery table A of the gaming machine in the present embodiment. It is a figure which shows the example of the navigation mode transfer lottery table B of the gaming machine in the present embodiment. It is a figure which shows the example of the navigation mode transfer lottery table C of the gaming machine in the present embodiment. It is a figure which shows the example of the navigation game state transfer waiting | standby number lottery table of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 transfer waiting | standby number lottery table of the gaming machine in the present embodiment. It is a figure which shows the example of the navigation game state 3 addition game number lottery table A of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition game number lottery table B of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition game number lottery table C of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition game number lottery table D of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition lottery mode lottery table A of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition lottery mode lottery table B of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition lottery mode lottery table C of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 addition lottery mode lottery table D of the game machine in this Embodiment. It is a figure which shows the example of the navigation set number lottery table of the game machine in this Embodiment. It is a figure which shows the example of the navigation game state 3 navigation game number addition lottery table of the game machine in this Embodiment. It is a figure which shows the example of the navigation game number special addition lottery table of the game machine in this Embodiment. It is a figure which shows the example of the billy get challenge generation lottery table of the gaming machine in the present embodiment. It is a figure which shows the example of the billy get challenge control counter lottery table of the gaming machine in the present embodiment. It is a figure which shows the example of the billy get challenge correct answer lottery table of the gaming machine in the present embodiment. It is a figure which shows the example of the lottery table at the time of no billy get challenge selection of the game machine in this Embodiment. It is a figure which shows the flowchart of the reset interruption process by the main CPU performed by the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus action | operation monitoring process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the internal lottery process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the reel stop control process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the display combination search process performed in the main control circuit in this Embodiment. It is a figure which shows the flowchart of RT control processing performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus completion | finish check process performed in the main control circuit in this Embodiment. It is a figure which shows the flowchart of the bonus operation | movement check process performed with the main control circuit in this Embodiment. It is a figure which shows the flowchart of the interruption process (1.1173 ms) by the main CPU performed by the main control circuit in this Embodiment. It is a figure which shows the flowchart of the effect registration process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the effect content determination process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the process at the time of the start command reception performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the process at the time of the start command reception performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the process in BB performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the lottery process in BB4 performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the billy get challenge process performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state 3 addition game number and lottery mode lottery processing performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the ART time process performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transfer process in standby state performed by the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transition process in the navigation game state 1 performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transition process in the navigation game state 2 performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transition process in the navigation game state 2 performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state 3 transition process in the navigation game state 2 performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transition process in the navigation game state 3 performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game number addition process performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the billy get challenge lottery process performed in the sub-control circuit in this Embodiment. It is a figure which shows the flowchart of the billy get challenge determination process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the navigation game state transfer process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the process at the time of the display command reception performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the process at the time of the bonus end command reception performed by the sub-control circuit in this Embodiment. It is a figure which shows the example of a change of LED brightness at the time of the display panel unit presentation in this Embodiment. It is the schematic which shows the whole management system of the game machine in this Embodiment. It is the schematic which shows the menu screen of the game machine in this Embodiment. It is the schematic which shows the error information log | history screen of the game machine in this Embodiment. It is explanatory drawing which shows the content of the information of the two-dimensional code used for the management system of the game machine in this Embodiment. It is explanatory drawing which shows the code number of the reception command used for the game machine in this Embodiment, a classification, and a parameter. It is explanatory drawing which shows the recording image of the information of the two-dimensional code when a COM error occurs in the gaming machine in the present embodiment, (a) is an accidental occurrence during a normal game, (b) is When the setting is changed due to the goto action, (c) shows the case where the lever continuous transmission is performed. It is explanatory drawing which shows the ring buffer area | region for communication log collection in the sub RAM of the sub control circuit in this Embodiment. It is explanatory drawing which shows the communication error preservation | save area | region in sub RAM of the sub control circuit in this Embodiment. In the gaming machine in the present embodiment, when there is a RAM destruction, it is a diagram showing an example of notifying the liquid crystal display area of it. It is a figure which shows the flowchart of the main board | substrate communication reception interruption process by sub CPU performed by the sub control circuit in this Embodiment. It is a figure which shows the detailed flowchart of the main board | substrate communication task performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception data log preservation | save process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception data log temporary area | region preservation | save process performed by the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication error log | history data preservation | save process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the main board | substrate communication reception command check process performed with the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the COM error check process performed with the sub control circuit in this Embodiment. It is a figure which shows the area | region image in the sub ROM of the sub control circuit in this Embodiment. It is a figure which shows the area | region image in the sub-RAM of the sub-control circuit in this Embodiment. It is a figure which shows the area | region image in the backup RAM of the sub control circuit in this Embodiment. It is a figure which shows the transmission / reception command data format between the sub control circuit and subdevice in this Embodiment. It is a figure which shows the content of the transmission / reception data between the sub control circuit and subdevice in this Embodiment. It is a figure which shows the subdevice communication data consistency check table in this Embodiment. It is a figure which shows an example of the structure of the error information log | history storage area in the sub RAM of the sub control circuit in this Embodiment. It is a figure which shows an example of the content of the data stored in the error information log | history storage area in the sub RAM of the sub control circuit in this Embodiment. It is a figure which shows an example of the content of the other data stored in the error information log | history storage area in the sub RAM of the sub control circuit in this Embodiment. It is a figure which shows the flowchart for demonstrating the process at the time of power activation of the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the power supply interruption process of the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the mother task which performs the various task starting request | requirement performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the RTC starting task performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the sub RAM management process performed by the sub CPU of the sub control circuit in this Embodiment. It is a figure which shows the flowchart of the backup creation process in the sub RAM management process shown in FIG. It is a figure which shows the flowchart of the communication control task between subdevices performed by subCPU of the subcontrol circuit in this Embodiment. It is a figure which shows the flowchart of the sub device serial reception interruption process performed by the sub CPU of the sub control circuit in this Embodiment. FIG. 106 is a diagram showing a flowchart of sub-device command reception processing in the inter-sub-device communication control task shown in FIG. 105. FIG. 106 is a diagram showing a flowchart of processing upon reception of subdevice communication in the intersubdevice communication control task shown in FIG. 105. FIG. 109 is a diagram showing a flowchart of processing at the time of receiving a scaler control command in the processing at the time of receiving sub-device communication shown in FIG. 108. FIG. 110 is a diagram showing a flowchart of a scaler control setting process in the scaler control command reception process shown in FIG. 109. FIG. 110 is a diagram showing a flowchart of sub-device reception data determination processing in the processing at the time of scaler control command reception shown in FIG. 109. FIG. 106 is a diagram showing a flowchart of sub-device communication disconnection processing in the inter-sub-device communication control task shown in FIG. 105. FIG. 106 is a diagram showing a flowchart of sub-device communication return processing in the inter-sub-device communication control task shown in FIG. 105. It is a figure which shows the flowchart of the scaler main task performed by the scaler control board of the sub control circuit in this Embodiment. FIG. 115 is a diagram showing a flowchart of sub-control reception processing in the scaler control main task shown in FIG. 114. FIG. 116 is a diagram showing a flowchart of resolution conversion LSI setting processing in the sub-control reception processing shown in FIG. 115. FIG. 115 is a diagram showing a flowchart of sub-control transmission processing in the scaler control main task shown in FIG. 114. It is a figure which shows the flowchart of the operating state determination process in the scaler control main task shown in FIG. It is a perspective view which shows the external appearance of the game machine in other embodiment of this invention. It is a front view which shows the external appearance of the game machine in other embodiment of this invention. It is a disassembled perspective view which shows the structure of the outline of the game machine in other embodiment of this invention. It is a front view which shows the structure of the outline of the game board of the game machine in other embodiment of this invention. It is a block diagram which shows the structure of the main control circuit and sub control circuit of the game machine in other embodiment of this invention.

[Configuration of pachislot machines]
The gaming machine of the present invention will be specifically described below with reference to the drawings. In the following embodiment, as a gaming machine of the present invention, a gaming machine having three rotating reels that variably display symbols, in addition to coins, medals or tokens, etc. A description will be given using a game machine capable of playing using a game value such as a card, a so-called pachislot machine. In the following embodiments, a pachislot gaming machine will be described as an example. However, the gaming machine of the present invention is not limited, and a pachinko machine or a slot machine may be used. An example of a pachinko machine will be described later.

  First, an overview of the pachislot machine according to the present embodiment will be described with reference to FIG. FIG. 1 is a perspective view of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 1, the gaming machine 1 includes a housing 1a that houses reels 3L, 3C, and 3R, a main control circuit 60 (see FIG. 8) that will be described later, and the like. The housing 1a includes a front door 1b that can be opened and closed. Furthermore, the gaming machine 1 includes a lock mechanism that switches the front door 1b to a locked state or an unlocked state with the front door 1b closed. This lock mechanism is operated by inserting the door key 2 into the door key hole 1 c and rotating the door key 2.

  When the door key 2 is inserted into the door key hole 1c and rotated to the right, for example, the front door 1b can be opened and closed, and when rotated to the left, the main control circuit 60 and the like are electrically reset. Yes. That is, the door key 2 has a reset function for electrically resetting the gaming machine 1 in addition to the operation of the lock mechanism.

  A symbol display region 4L, 4C, 4R as a substantially vertical surface and a liquid crystal display region 23 are formed in front of the central portion of the front door 1b. Three reels 3L, 3C, 3R are rotatably provided in a horizontal row inside the front of the central portion of the cabinet 1a. On the three reels 3L, 3C, 3R, a symbol row composed of a plurality of types of symbols is drawn on each outer peripheral surface.

  The symbols of the reels 3L, 3C, 3R can be seen through the symbol display areas 4L, 4C, 4R. Each reel 3L, 3C, 3R is controlled by a later-described main control circuit 60 (see FIG. 8) so as to rotate at a constant speed (for example, 80 revolutions / minute), and within the symbol display areas 4L, 4C, 4R. The symbols drawn on the displayed reels 3L, 3C, 3R vary as the reels rotate.

  A substantially horizontal base 10 is formed below the liquid crystal display area 23. On the left side of the pedestal 10, a C / P button 14 that switches between credit (Credit) / payout (Pay) of medals acquired by the player and bet the credited medals by operating a push button. The maximum BET button 13 is provided.

  The payout mode or the credit mode is switched by the player's operation on the C / P button 14. In the credit mode, when a winning is established, medals for the number of payouts corresponding to the winning are credited.

  In the payout mode, when a winning is established, medals for the number of payouts corresponding to the winning are paid out from the medal payout port 15 at the lower front, and the medals paid out from the medal payout port 15 are sent to the medal receiving unit 16. Accumulated.

  Note that winning means that a combination of symbols relating to a small combination is stopped on the active line. The small role is a role in which medals are paid out when established.

  Further, by the player's operation on the maximum BET button 13, among the credited medals, the maximum number of medals that can be inserted at that time is inserted. By operating the maximum BET button 13, a winning line described later is activated.

  On the right side of the pedestal portion 10, a medal slot 22 is provided. In accordance with the medal inserted into the medal slot 22, a pay line described later is activated.

  On the left side of the medal slot 22, a selection button 24 and a determination button 25 are provided. The player can input to the menu screen displayed in the liquid crystal display area 23 using the selection button 24 and the determination button 25.

  Speakers 21 </ b> L and 21 </ b> R are provided on the left and right above the medal receiving portion 16. The speakers 21L and 21R output game sounds such as performance sounds and notification sounds according to the game situation.

  A start lever 6 is provided on the left side of the front surface of the pedestal 10. The start lever 6 rotates the reels 3L, 3C, and 3R by the player's start operation, and starts changing the symbols displayed in the symbol display areas 4L, 4C, and 4R.

  Three stop buttons 7L for stopping the rotation of the three reels 3L, 3C, and 3R by the player's pressing operation (stopping operation) are provided on the right side of the start lever 6 at the center of the front surface portion of the base 10. , 7C, 7R are provided.

  Here, when the three reels 3L, 3C, and 3R are rotating, the first stop of the rotation of the reels is referred to as a first stop, which is performed after the first stop and the two reels are rotated. The second stop of the rotation of the reel that is performed when the operation is performed is referred to as the second stop, which is performed after the second stop, and is performed last when the rotation of the remaining one reel is performed. Stopping the rotation of the reel is referred to as a third stop.

  The stop operation for the player to stop for the first time is referred to as a first stop operation. Similarly, a stop operation for the player to stop the second stop is referred to as a second stop operation, and a stop operation for the third stop is referred to as a third stop operation.

  A light transmissive upper panel 101 is provided on the upper part of the front door 1b, and an upper panel LED (Light Emitting Diode) 111 (other light emitters may be used in place of the LED) on the inner side. Is provided. The LED 101 for the upper panel emits light according to the contents of effects described later.

  The liquid crystal display area 23 is disposed on the front side of the reels 3L, 3C, and 3R when viewed from the front side, displays images, and is drawn on the reels 3L, 3C, and 3R in the symbol display areas 4L, 4C, and 4R. The displayed design is displayed transparently. The transmittance in the symbol display areas 4L, 4C, 4R can be changed.

  The liquid crystal display area 23 displays the number of medals stored (credited) or displays the number of medals paid out when winning is established. In addition, the liquid crystal display area 23 displays a frame image having a predetermined shape so as to surround the symbol display areas 4L, 4C, and 4R, and a predetermined image corresponding to the contents of effects described later.

  A lower panel 102 is provided below the liquid crystal display area 23 and above the pedestal 10, and a lower panel LED 102 (other light emitters may be used instead of LEDs) inside the lower panel 102. Is provided. The lower panel 102 emits light according to the contents of effects described later.

  A light-transmitting waist panel 103 is provided below the pedestal 10, and a waist panel LED 103 (other light emitters may be used in place of the LEDs) is provided on the inside thereof. The waist panel LED 103 emits light in accordance with the contents of effects described later.

  One symbol is displayed in each of the upper, middle, and lower regions in each of the vertically long rectangular symbol display areas 4L, 4C, and 4R. Each symbol display area 4L, 4C, and 4R has a corresponding reel peripheral surface. Three symbols of the arranged symbols are displayed. That is, the symbol display areas 4L, 4C, and 4R have a function as a so-called display window.

  Next, the winning line will be described with reference to FIG. In the symbol display areas 4L, 4C, 4R, five winning lines (center line 8c, bottom line 8d, cross) connecting any one of the upper, middle, and lower stages in each of the symbol display areas 4L, 4C, 4R described above. An up line 8a, a cross down line 8e, and an RB middle special line 8f) are provided.

  When the rotation of the reels 3L, 3C, 3R is stopped, the gaming machine 1 determines whether the winning combination is established or not based on the combination of symbols displayed on the activated winning line. Hereinafter, the activated winning line is referred to as an activated line, and the activated winning line is referred to as an inactivated line.

  As shown in FIG. 2, the center line 8c is a line formed by connecting the left / middle stage region D, the middle / middle stage region E, and the right / middle stage region F, respectively. The bottom line 8d is a line formed by connecting the left / lower region G, the middle / lower region H, and the right / lower region I, respectively.

  The cross-up line 8a is a line formed by connecting the left / lower region G, the middle / middle region E, and the right / upper region C, respectively. The cross-down line 8e is a line formed by connecting the left / upper region A, the middle / middle region E, and the right / lower region I, respectively. The RB middle special line 8f is a line formed by connecting the left / middle stage area D, the middle / lower stage area H, and the right / upper stage area C, respectively.

  In the present embodiment, in the BB gaming state (RB gaming state), only the special line 8f during RB becomes an effective line by inserting two medals. On the other hand, in a game state other than the BB game state (RB game state), four winning lines including the center line 8c, the bottom line 8d, the cross-up line 8a, and the cross-down line 8e are activated as three medals are inserted. Become.

  In some cases, the BB1 gaming state to the BB4 gaming state are collectively referred to as the BB gaming state. In addition, the RB1 gaming state to the RB2 gaming state may be collectively referred to as an RB gaming state.

  Next, the symbol sequence arranged on the reels 3L, 3C, 3R will be described with reference to the symbol arrangement table shown in FIG. FIG. 3 is a diagram showing an arrangement of symbols drawn on the outer peripheral surface of the reels 3L, 3C, 3R of the gaming machine 1 according to the present embodiment.

  On the outer peripheral surfaces of the reels 3L, 3C, 3R, a symbol row in which 21 types of symbols are arranged is drawn. Specifically, a symbol sequence consisting of 7 red symbols, 1 don symbol, 2 don symbols, BAR symbol, wave symbol, 1 bell symbol, 2 bell symbols, 1 cherry symbol, 2 cherry symbols, and a replay symbol is drawn. ing.

  The symbol arrangement table is stored in the main ROM 32 of the main control circuit 60 described later. As shown in FIG. 3, in the symbol arrangement table, the reels 3L, 3C, and 3R are rotated 1/21 times in order to associate the rotation positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel. Symbol positions from “0” to “20” that are sequentially assigned to each are defined.

  Next, the upper part of the gaming machine will be described with reference to FIGS. FIG. 4 is a view showing the upper front of the gaming machine 1. FIG. 5 is a view showing a cross section in the vicinity of the display panel unit 110 of the gaming machine 1. FIG. 6 is a view showing the display panels 110Pa to 110Pd of the gaming machine 1. FIG. 7A is a diagram showing the left decorative panel 121L and the left infrared sensor 120L of the gaming machine 1, and FIG. 7B is a diagram showing the left infrared sensor 120L of the gaming machine 1.

  As shown in FIG. 4, a display panel unit 110 is provided in the upper center of the liquid crystal display area 23. A left selection panel 151L and a right selection panel 151R are provided on the left and right sides of the display panel unit 110. A left decorative panel 121L and a right decorative panel 121R are provided on the upper left and right of the display panel unit 110.

  As shown in FIG. 5, the display panel unit 110 has four display panels 110Pa, 110Pb, 110Pc, and 110Pd that have high light transmittance and excellent light guiding properties (the display panels 110Pa to 110Pd are collectively referred to as a display panel 110P). And four LEDs 111, 112, 113, 114.

  Each of the display panels 110Pa to 110Pd is installed in a state of being overlapped with a gap. Each of the display panels 110Pa to 110Pd is drawn with a symbol, and the LEDs 111 to 114 provided individually emit light so that the player can visually recognize the symbol.

  Moreover, as shown in FIG. 6, the character design is drawn on each of the display panels 110Pa to 110Pd. Specifically, as shown in FIGS. 6A to 6D, characters are drawn larger as the display panels 110Pa to 110Pd provided in front of the player.

  The symbols drawn on the display panels 110Pa to 110Pd can be clearly seen by the player as the brightness of the LED corresponding to the display panel 110P increases. The luminance of the LEDs 111 to 114 is controlled by the sub CPU 71 in the sub control circuit 70 described later.

  For example, from the LED 114 corresponding to the display panel 110Pd provided on the back side when the sub CPU 71 is viewed from the player, the LED 113 corresponding to the display panel 110Pc, the LED 112 corresponding to the display panel 110Pb, and the LED 111 corresponding to the display panel 110Pa. By increasing the brightness (that is, causing the LED to emit light), it appears to the player that the character is approaching him.

  In addition, regarding the control of the LEDs 111 to 114, from the LED 111 corresponding to the display panel 110Pa provided on the near side as viewed from the player, the LED 112 corresponding to the display panel 110Pb, the LED 113 corresponding to the display panel 110Pc, and the display panel 110Pd. By increasing the brightness in the order of the corresponding LEDs 114, it is possible to make the character appear to move away from the player.

  Thus, when changing the brightness | luminance of LED111-114 in order, it is preferable to make it difficult to see a pattern overlappingly. For example, when increasing the brightness of the LED 112 after increasing the brightness of the LED 111, if the brightness of a certain LED is increased, such as decreasing the brightness of the LED 111, the LED whose brightness has been increased before that. It is preferable to reduce the brightness of the.

  In addition, as for the symbols, the character may be drawn as small as the display panel 110P provided in front of the player, and as large as the display panel 110P in the back. Further, a liquid crystal display device is provided in the back of the display panel unit (or the display portion of the liquid crystal display device 5 is enlarged) so that the player can see the image displayed by the liquid crystal display device through the display panels 110Pa to 110Pd. It may be.

  As shown in FIG. 7A, a left infrared sensor 120L is provided in the back of the left decorative panel 121L. Although not shown, the right infrared sensor 120R is also provided behind the right decorative panel 121R. Hereinafter, the description of the left decorative panel 121L and the left infrared sensor 120L is the same for the right decorative panel 121R and the right infrared sensor 120R.

  The infrared sensors 120L and 120R are so-called reflective infrared sensors, and can detect whether an object (for example, a player's hand) is present or approached in the direction in which the infrared beam is output.

  As shown in FIG. 7B, the left infrared sensor 120L outputs an infrared beam in the direction of the arrow AR, and receives the reflected infrared beam, so that a player's hand or the like has come close to the left selection panel 151L. Detect that. Similarly, the right infrared sensor 120R detects whether the player's hand or the like has approached the right selection panel 151R.

  The infrared sensors 120L and 120R do not always operate, but operate when a billy get challenge effect described later is executed.

  In this embodiment, a reflective infrared sensor is used. However, other sensors that can detect that a player's hand or the like has come close to the left selection panel 151L and the right selection panel 151R are used. It is good. The left selection panel 151L and the right selection panel 151R themselves may be so-called touch sensors.

[Circuit configuration of gaming machine]
Next, referring to FIG. 8, the circuit configuration of the gaming machine 1 including a main control circuit 60, a sub control circuit 70 as a control unit, a main control circuit 60, or peripheral devices electrically connected to the sub control circuit 70. Will be described. FIG. 8 is a diagram showing a circuit configuration of the gaming machine 1.

  The main control circuit 60 controls the progress of a series of games such as determination of an internal winning combination and reel rotation control. The main control circuit 60 includes a microcomputer 30 disposed on a circuit board as a main component, and is added to a circuit for random number sampling. The microcomputer 30 includes a main CPU 31, a main ROM 32 and a main RAM 33.

  The main CPU 31 is connected to a clock pulse generation circuit 34, a frequency divider 35, a random number generator 36, and a sampling circuit 37.

  The main CPU 31 determines an internal winning combination based on a random number value and an internal lottery table which will be described later, and stops the rotation of the reels 3L, 3C, 3R based on the internal winning combination and the timing when the stop operation is detected. Let

  Further, when the main CPU 31 stops the rotation of the reels 3L, 3C, and 3R, it determines whether or not a winning combination has been established based on the combination of symbols displayed in the symbol display areas 4L, 4C, and 4R. If established, the player is given a profit such as paying out medals according to the established combination.

  The clock pulse generation circuit 34 and the frequency divider 35 generate a reference clock pulse. The random number generator 36 generates a random number in the range of “0” to “65535”. The sampling circuit 37 extracts (samples) one random number value from the random number generated by the random number generator 36.

  In the gaming machine 1, the extracted random number value is stored in a random value storage area of the main RAM 33 described later. Then, for each game, based on the random number value stored in the random value storage area of the main RAM 33, an internal winning combination is determined in an internal lottery process described later.

  In addition, as a means for random number sampling, you may make it the structure which performs random number sampling within the microcomputer 30, ie, on the operation program of the main CPU31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The main ROM 32 of the microcomputer 30 stores programs related to the processing of the main CPU 31, various tables, and the like.

  Various information obtained by processing of the main CPU 31 is set in the main RAM 33. For example, information for identifying the extracted random number value, gaming state, internal winning combination, number of payouts, bonus carryover status, setting value, etc., various counters and flags are set. Some of these pieces of information are transmitted to the sub-control circuit 70 by the above-described command.

  Examples of main peripheral devices whose operation is controlled by a control signal from the microcomputer 30 include a hopper 40, stepping motors 49L, 49C, and 49R. The exchange of signals between these actuators and the main CPU 31 is performed via the I / O port 38.

  In addition, the output unit of the microcomputer 30 is connected to each circuit for receiving the control signal output from the main CPU 31 and controlling the operation of each peripheral device described above. Each circuit includes a motor drive circuit 39 and a hopper drive circuit 41.

  The hopper drive circuit 41 drives and controls the hopper 40. Thereby, the medal accommodated in the hopper 40 is paid out.

  The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R. As a result, the reels 3L, 3C, and 3R are rotated and stopped.

  In addition, each switch and each circuit for generating an input signal that triggers the output of a control signal to each circuit and each peripheral device are connected to the input unit of the microcomputer 30. As each switch and each circuit, there are a start switch 6S, stop switches 7LS, 7CS, 7RS, a maximum BET switch 13S, a C / P switch 14S, a medal sensor 22S, a reel position detection circuit 50, and a payout completion signal circuit 51. Note that the stop switches 7LS, 7CS, and 7RS are collectively referred to as the stop switch 7S.

  The start switch 6S detects a player's start operation on the start lever 6 and outputs a start signal instructing the start of the game to the microcomputer 30.

  The stop switches 7LS, 7CS, and 7RS detect the player's stop operation on the stop buttons 7L, 7C, and 7R, respectively, and stop the rotation of the reels 3L, 3C, and 3R corresponding to the detected stop buttons 7L, 7C, and 7R. A stop signal to be commanded is output to the microcomputer 30.

  The maximum BET switch 13 </ b> S detects a player's insertion operation (pressing operation) on the maximum BET button 13 and outputs a signal for instructing insertion of a medal from a credited medal to the microcomputer 30.

  The C / P switch 14S detects a player's switching operation on the C / P button 14, and outputs a signal for switching the credit mode or the payout mode to the microcomputer 30. When the credit mode is switched to the payout mode, a signal for instructing the payout of medals credited to the gaming machine 1 is output to the microcomputer 30.

  The medal sensor 22S detects medals inserted into the medal insertion slot 22 by the player's insertion operation, and outputs a signal indicating that a medal has been inserted to the microcomputer 30.

  The reel position detection circuit 50 detects a pulse signal from the reel rotation sensor and generates a signal for detecting the position of the symbol on each reel 3L, 3C, 3R.

  The payout completion signal circuit 51 indicates that the payout of medals has been completed when the number of medals detected by the medal detection unit 40S (that is, the number of medals paid out from the hopper 40) reaches the designated number. Generate a signal to indicate.

  The sub control circuit 70 performs various processes such as determination and execution of effect data based on various commands output from the main control circuit 60 such as a start command described later. The sub control circuit 70 does not input commands, information, or the like to the main control circuit 60, and communication is performed in one direction from the main control circuit 60 to the sub control circuit 70.

  The main peripheral devices whose operation is controlled by a control signal from the sub-control circuit 70 include a liquid crystal display device 5 as display means for displaying an image on the liquid crystal display area 23, speakers 21L and 21R, LEDs 101 to 103, a display There exist LED111-114 which the panel unit 110 has, and infrared sensor 120L, 120R.

  The sub-control circuit 70 determines and displays an image displayed on the liquid crystal display device 5 based on the determined effect data, determines and outputs the light emission patterns of the various LEDs 101 to 103 and 111 to 114, and the infrared sensors 120L and 120R. The control of the determination and output of the effect sound and the sound effect output from the speakers 21L and 21R, such as the determination of the operation timing, is performed.

  Details of the configuration of the sub control circuit 70 in the present embodiment will be described later.

  In the gaming machine 1, when a signal for starting a game is output from the start switch 6S by a player's operation on the start lever 6 on condition that a medal is inserted, a control signal is output to the motor drive circuit 39, and the stepping motor The rotation of the reels 3L, 3C, and 3R is started by the drive control of 49L, 49C, and 49R (for example, excitation to each phase).

  At this time, the number of pulses output to the stepping motors 49L, 49C, 49R is counted, and the counted value is set as a pulse counter in a predetermined area of the main RAM 33.

  In the gaming machine 1, when the “16” pulse is output, the reels 3L, 3C, and 3R move by one symbol. The number of symbols moved is counted, and the counted value is set in a predetermined area of the main RAM 33 as a symbol counter. That is, every time the pulse counter counts “16”, the symbol counter is updated by “1”.

  In addition, the symbol (refer FIG. 3) of the symbol position which the value of a symbol counter shows corresponds to the symbol located on the center line 8c. For example, when the symbol counter of the left reel 3L is “0”, the bell at the symbol position “0” in the symbol arrangement table shown in FIG. 3 is located on the center line 8c.

  A reel index is obtained from the reels 3L, 3C, and 3R for each rotation and is output to the main CPU 31 via the reel position detection circuit 50. By the output of the reel index, the pulse counter and the symbol counter set in the main RAM 33 are cleared to “0”.

  In this way, the symbol position within one rotation range is specified for each reel 3L, 3C, 3R. The distance that each symbol moves by one symbol by the rotation of the reel is called one frame. That is, moving the symbol by one frame corresponds to updating the symbol counter by “1”.

  In order to associate the rotational positions of the reels 3L, 3C, and 3R with the symbols drawn on the outer peripheral surface of the reel, a symbol arrangement table is stored in the main ROM 32. This symbol arrangement table includes code numbers from “00” to “20” that are sequentially assigned at fixed rotation pitches of the reels 3L, 3C, and 3R with reference to the position where the reel index is output. A symbol code for identifying the type of symbol provided corresponding to each code number is associated with each other.

  When a start signal is output from the start switch 6S, a random number value is extracted by the random number generator 36 and the sampling circuit 37. In the gaming machine 1, when the random value is extracted, it is stored in the random value storage area of the main RAM 33. Then, an internal winning combination is determined based on the random value stored in the random value storage area.

  After the reels 3L, 3C, 3R have reached constant speed rotation, when a stop signal is output from the stop switches 7LS, 7CS, 7RS by a stop operation, based on the output stop signal and the determined internal winning combination, A control signal for stopping and controlling the reels 3L, 3C, 3R is output to the motor drive circuit 39. The motor drive circuit 39 drives and controls the stepping motors 49L, 49C, 49R, and stops the rotation of the reels 3L, 3C, 3R.

  The gaming machine 1 stops the rotation of the reel 3 by drawing in the symbols related to the establishment of the internal winning combination for the maximum number of sliding frames, that is, four frames from the time when the stop operation is performed. Specifically, the gaming machine 1 determines whether or not there is a symbol related to the establishment of an internal winning combination within 4 frames after the stop operation is detected by the stop switches 7LS, 7CS, and 7RS. When there is a symbol related to the establishment of an internal winning combination within four frames, the number of sliding symbols is determined so that the symbol is stopped and displayed on the active line, and the corresponding reel is stopped.

  In addition, in the case where a plurality of winning combinations are determined as internal winning combinations, the gaming machine 1 relates to an internal winning combination having a higher priority when there are a plurality of symbols related to establishment of the internal winning combination within 4 frames. The number of sliding symbols is determined so that the symbols are stopped and displayed on the active line.

  Basically, the first priority (highest priority) is a symbol combination related to replay, and the second priority is a symbol combination related to a small role. Next, the third highest priority is a combination of symbols related to the bonus.

  When the stop operation is detected by the stop switches 7LS, 7CS, 7RS, the symbol position corresponding to the symbol counter of the corresponding reel 3, that is, the symbol position at which the rotation of the reel 3 is stopped is set as “stop start position”. The symbol position obtained by adding the determined number of sliding symbols (numerical range “0” to “4”) to the stop start position, that is, the symbol position at which the rotation of the reel 3 is stopped is referred to as “scheduled stop position”. The number of sliding symbols is the amount of rotation of the reel 3 until the corresponding reel 3 stops rotating after the stop operation is detected by the stop switches 7LS, 7CS, 7RS. 4 ”.

  When the rotation of all the reels 3L, 3C, and 3R is stopped, the display combination retrieval process, that is, the determination process of the formation / non-establishment of the combination is performed based on the combination of symbols displayed on the effective line. The search for the display combination is performed based on a later-described symbol combination table stored in the main ROM 32. In this symbol combination table, a symbol combination related to a display combination and a corresponding payout are set.

  When it is determined by the display combination search that a combination of symbols related to winning is displayed, a control signal is output to the hopper driving circuit 41 and the hopper 40 is driven to pay out medals.

  At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the count value reaches the designated number, the payout completion signal circuit 51 outputs a signal indicating completion of the medal payout. . Thereby, a control signal is output to the hopper drive circuit 41, and the drive of the hopper 40 is stopped.

  When the credit mode is switched by the C / P switch 14S, if it is determined that the symbol combination related to winning is displayed, the payout amount corresponding to the symbol combination related to winning is displayed in the main RAM 33. Add to credit counter.

  Further, the number of medals paid out is transmitted to the sub-control circuit 70, and based on this, the number of medals paid out and the updated number of credits are displayed in the liquid crystal display area 23. Here, there is a case where a medal payout or a credit performed when a symbol combination related to winning is displayed is simply referred to as “payout”.

  Next, the circuit configuration of the sub control circuit 70 will be described with reference to FIG. FIG. 9 is a diagram showing a circuit configuration of the sub control circuit 70 of the gaming machine 1.

  The sub-control circuit 70 performs control for performing effects related to games using video, sound, light, and the like. The sub control circuit 70 determines effect data and performs various effect processes based on various commands transmitted from the main control circuit 60 and input information from the selection switch 24S and the determination switch 25S.

  The sub control circuit 70 includes a sub CPU 71 as processing means, a sub ROM 72 functioning as processing information storage means, a DRAM 73-1 functioning as control information storage means (also referred to as “sub RAM 73-1”), an SRAM 73-2, a GPU 74, A VRAM 75, an A / D converter 78, and an amplifier 79 are included. In addition, a scaler control board 77 is connected to the sub CPU 71 via a serial communication relay board 76, and the size of the original image displayed on the liquid crystal display device 5 can be selected.

  The scaler control board 77 is one of the sub devices that can be connected to the sub CPU, and includes a scaler control LSI and a resolution conversion LSI (not shown) incorporating a ROM and a RAM. The ROM functions as processing information storage means in which processing information is stored, and the RAM functions as control information storage means capable of reading and writing control information. The sub-control circuit 70 and the serial communication relay board 76 are connected by UART, and data conversion is performed between them. The serial communication relay board 76 and the scaler control LSI of the scaler control board 77 are also connected by UART, and data conversion is performed between them.

  In FIG. 9, the sub CPU 71 and the serial communication relay board 76 and the serial communication relay board 76 and the scaler control board 77 are shown as being connected by one line. However, the control line and the data line are composed of separate lines, and the input and output lines are composed of separate lines. Between the devices to which the data line is connected, the TxD terminal and the RxD terminal of the data line are connected to each other.

  The selection switch 24S detects a player's operation on the selection button 24 and moves, for example, a display (for example, an icon) indicating which of the items to be selected displayed on the menu screen or the like is in a selected state. Is output to the sub CPU 71.

  In addition, the determination switch 25S detects the player's operation on the determination button 25, and outputs, for example, a signal indicating that the player has selected an item in the selected state to the sub CPU 71. That is, the player can select an item on the menu screen or the like by pressing the selection button 24 until the item to be selected is selected, and then pressing the enter button.

  The sub CPU 71 performs display control of the liquid crystal display device 5, output control of the speakers 21 </ b> L and 21 </ b> R, light emission control of various LEDs 101 to 103, 111 to 114, and the like based on a program stored in the sub ROM 72. Specifically, the sub CPU 71 receives various commands and the like from the main control circuit 60 and stores various information included in the commands in the sub RAM 73-1.

  The sub CPU 71 is connected to an SRAM 73-2 (also referred to as “backup RAM 73-2”) described later. The backup RAM 73-2 is backed up with data copied to the sub RAM 73-1 when the power is turned on.

  All information in the main control circuit 60 is transmitted by a command, and the sub control circuit 70 can determine the state of the main control circuit 60 step by step. The sub CPU 71 executes the program while referring to the game state information, the internal winning combination information and the like stored in the DRAM 73-1, so that the liquid crystal display device 5, the speakers 21L and 21R, and the various LEDs 101 to 103 and 111 to 114 are executed. The content of the production to be performed by the production device is determined.

  Further, the sub CPU 71 controls the liquid crystal display device 5 via the GPU 74 based on the determined effect data, and controls the sound output from the speakers 21L and 21R and the light emission of the various LEDs 101 to 103 and 111 to 114. To do.

  The upper panel LED 101, the lower panel LED 102, and the lower panel LED 103 are actually composed of a plurality of LEDs, and these are controlled by input / output processing of ports (not shown) provided individually. Is done. Therefore, light emission can be individually controlled by each port.

  Further, the sub CPU 71 executes a random number acquisition program stored in the sub ROM 72, thereby acquiring a random value used when determining effect data and the like. However, when a random number generator and a sampling circuit are provided in the sub-control circuit 70 as in the main control circuit 60, this processing is not necessary.

  As shown in FIG. 97A, the sub ROM 72 has an OS area 72a for storing an operating system, a sub control program storage area 72b for storing a program executed by the sub CPU 71, a game initialization setting data area 72c, and a staff operation initial stage. A setting data area 72d, various program table areas 72e for storing various tables, a program management data area 72f, an image data (still image / moving image) area 72g, a sound data area 72h, and an accessory movable data area 72i. And have.

  The sub-control program storage area 72b is based on the LED 101 based on the device driver, inter-board communication processing for controlling communication with the main control circuit 60, production registration processing for determining the content of the production, and registered LED data. 103, 111-114, LED control task for controlling light output, sound control task for controlling sound output by speakers 21L, 21R based on registered sound data, based on registered animation data Then, a drawing control task for controlling video display by the liquid crystal display device 5 is stored.

  The various program table area 72e stores an effect lottery table, a sub control circuit error code table shown in FIG. 98B, a sub device error code table shown in 98C, a sub device communication check table shown in FIG. 97F, and the like. The program management data area 72f stores a magic code, a program version, and the like. The image data (still image / moving image) area 72g stores animation data such as character object data. The sound data area 72h stores sound data such as BGM and sound effects. Further, the accessory movable data area 72i stores, for example, LED control data for performing a light lighting pattern or the like.

  As shown in FIG. 97B, the sub RAM 73-1 has a sub control game data area 73a-1 as a game data storage area, a sub control game data sum value area 73b-1, an area 73c-1, and a staff operation setting. A data area 73g-1, an error information history storage area 73d-1, a communication log collection ring buffer area 73e-1, and a communication error storage area 73f-1. The clerk operation setting data registered in the clerk operation setting data area 73g-1 is data in which setting items on the menu screen are stored.

  The sub-control game data area 73a-1 stores data stored in the sub-RAM 73-1 among the game data related to the progress of the game. The sub-control game data sum value area 73b-1 stores a check-sum value for the checksum of the game data stored in the sub-control game data area 73a-1. The area 73c-1 stores data in various processes.

  The sub control game data area 73a-1 and the work area 73c-1 are used as temporary storage means for work when the sub CPU 71 executes each program. The sub-control game data area 73a-1 includes, for example, commands transmitted from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters, 4 bytes to 8 bytes. Information such as an arbitrary magic code and various flags is stored.

  The error information history storage area 73d-1 is an error code indicating all error information detected by the communication error detecting means 71a, the procedure detecting means 71b, the data destruction detecting means 71c, the sub device error detecting means 71h, etc. (FIG. 98A, 98B and 98C). In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  In the error information history storage area 73d-1, the error detected by the communication error detecting means 71a is stored as a COM error, and the error detected by the procedure detecting means 71b is stored as a procedure abnormal error. The error detected by the data destruction detection means 71c is stored as a data destruction error, and the error detected by the sub device error detection means 71h is stored as a scaler error.

  As shown in FIG. 97C, the backup RAM 73-2 has a backup data 1 area 73a-2, a backup data 1 sum value area 73b-2, and a backup data 2 area 73c- which is a mirroring of the backup data 1 area 73a-2. 2, backup data 2 sum value area 73 d-2, clerk backup data area 73 e-2, error information history storage area 73 f-2, and clerk backup data sum value area 73 g-2.

  The backup data 1 area 73a-2 and the backup data 2 area 73c-2 each include an arbitrary magic code of 4 to 8 bytes.

  Here, with reference to FIG. 97D and FIG. 97E, the data format of the transmission / reception command between the sub CPU 71 and the sub device such as the scaler control board 77 and the content of the transmission / reception data will be described.

  FIG. 97D shows an example of a transmission / reception command data format. “STX” indicates a start text, “ADR” indicates a transmission source ID and a transmission destination ID, “CMD” indicates a command, and “DATA1” to “DATA256” indicate a data group of up to 256 bytes corresponding to the command. “ETX” indicates the end text, and “SUM” indicates the sum value up to the end text.

  FIG. 97E is a table showing the contents of the transmission / reception command data format from “STX” to “SUM”. For example, “ADR” of command data transmitted from the scaler control board 77 to the sub CPU 71 is “01h” of the ID of the scaler control board 77 as the transmission source and “02h” of the ID of the sub CPU 71 as the transmission destination. , “CMD” indicates “82h”, and “DATA1” indicates the program version, the command data is sent from the scaler control board 77 to the sub CPU 71 as a parameter request for a predetermined program version. Indicates that the

  FIG. 97F shows a check table for sub-device communication. This table is for determining whether the command type and command packet size of the data received by the scale control board 77 are correct. As the determination 1, it is determined whether the CMD is an activation parameter request of 81h and the DATA is 2 bytes. When the determination 1 is completed, the determination is shifted to the determination 2. This table is used in the sub-device reception data determination process shown in FIG.

  As shown in FIG. 98A, the error information history storage area 73d-1 of the sub RAM 73-1 has an error code (ERROR CODE in the figure), an error occurrence time (in the figure, “occurrence”), and an error release time ( In the drawing, “cancel”) can be stored as one set, and 128 sets can be stored.

  The error code is 1-byte data, and the error code related to the sub control circuit includes, as shown in FIG. 98B, a communication error (“COM error” in the figure) or a procedure error (“procedure error” in the figure). ”), Data destruction errors (“ Sum Abnormal ”in the figure), and other errors. The error occurrence time and error release time are both composed of a 2-byte data year, 1-byte data month, 1-byte data day, 1-byte data hour, 1-byte data minute, and 1-byte data second. Yes.

  Further, as shown in FIG. 98C, the error code related to the sub device includes an error when the sub device ID does not exist (“SD COM DVC” in the figure) and an error when the sub device is reset. ("SD RST" in the figure), errors when the data size exceeds 256 bytes ("SD COM SIZ" in the figure), communication between the sub CPU 71 and the sub device is interrupted, Error when restarting ("SD DSC" or "SCL RSM" in the figure), error when brightness, contour or interpolation settings are abnormal ("SD SET ERR1" to "SD SET ERR3" in the figure) Including other errors.

  As shown in FIG. 87, the communication log collection ring buffer area 73e-1 stores an appropriate number of data groups each consisting of 256 command and parameter data sets and one corresponding buffer index. It functions as a buffer. As shown in FIG. 88, the communication error storage area 73f-1 stores 1024 data groups including 256 command and parameter data sets and one corresponding buffer index. The communication error storage area 73f-1 is provided with one buffer selection index indicating which buffer index is selected from among the 1024 buffer indexes.

  Further, as shown in FIG. 9, the sub CPU 71 includes a communication error detection means 71a, a procedure detection means 71b, a data destruction detection means 71c, an error information registration means 71d, a received data log storage means 71e, and error information. A history display means 71f, a two-dimensional code conversion means 71g, and a sub device error detection means 71h are provided.

  The communication error detection means 71a detects that a communication error has occurred between the main control circuit 60 and the sub control circuit 70 by executing a COM error check process shown in FIG. 96 described later. .

  The procedure detecting means 71b detects the progress of the game in a procedure different from the normal game procedure, that is, an abnormal procedure by executing a main board communication reception command check process shown in FIG. It has become.

  The data destruction detection means 71c executes the sum check process of the sub-control game data storage area shown in FIG. 91, which will be described later, to thereby destroy the data in the sub-control game data area 73a-1 (see FIG. 97B) of the sub RAM 73-1. In particular, it is possible to detect data destruction related to information such as commands received from the main control circuit 60, effect data information, game state information, internal winning combination information, display combination information, various counters and various flags.

  The error information registration unit 71d stores the error code of the detected error in the error information history storage area 73d-1 of the sub RAM 73-1, when the occurrence of an error is detected by the error detection unit. Yes.

  Specifically, the error information registration unit 71d stores a COM error error code (COM ERR ALM) in the error information history storage area 73d-1 when the occurrence of a communication error is detected by the communication error detection unit 71a. It is supposed to be.

  When the procedure detection unit 71b detects the occurrence of a procedure abnormality error, the error information registration unit 71d stores a procedure abnormality error code (for example, BLS123PE) in the error information history storage area 73d-1. Yes.

  The error information registration unit 71d stores a sum abnormality error code (MEM ERR ALM) in the error information history storage area 73d-1 when the occurrence of a sum abnormality error is detected by the data destruction detection unit 71c. ing.

  Further, the error information registration unit 71d, for example, when the sub device error detection unit 71h detects an error in the scaler brightness setting error, the error information registration unit 71d stores the error code (SCL SET ERR1) in the error information history storage area 73d-1. ) Is memorized.

  In the error information history storage area 73d-1, an error information history is created by sequentially storing error codes.

  The reception data log storage unit 71e collects information about a reception log (hereinafter also referred to as a communication log) by executing a main board communication reception data log storage process shown in FIG. By executing the main board communication reception data log temporary area saving process shown, only one communication log is temporarily stored in the communication log collection ring buffer area 73e-1.

  Further, the received data log storage unit 71e stores a communication error when the occurrence of a communication error is detected by the communication error detection unit 71a by executing a main board communication error history data storage process shown in FIG. Up to 1024 communication logs related to communication errors (hereinafter referred to as communication error logs) are stored in the buffer area 73f-1.

  The error information history display means 71f displays the error information history stored in the error information history storage area 73d-1 on the liquid crystal display device 5 when the door key 2 is operated in a predetermined manner.

  The two-dimensional code converting means 71g, when the occurrence of a communication error is detected by the communication error detecting means 71a, the communication error log related to the communication error stored in the communication error storage buffer area 73f-1 and the data management as the transmission destination The domain of the server 500 is converted into two-dimensional code 300 as transmission information and transmitted to the error information history display means 71f.

  When the sub device error detecting unit 71h detects that a reset has occurred in a sub device such as the scaler control board 77, for example, an error code (SCL RST) is generated in the error information history storage area 73d-1. ) Is memorized.

  Then, as shown in FIG. 83, the error information history display means 71f displays the “COM error alarm” item 23b when the “COM error alarm” item 23b is selected in the liquid crystal display area 23 where the error information history is displayed. A two-dimensional code 300 corresponding to the communication error is displayed on the right side.

  Here, as shown in FIG. 84, the transmission information included in the two-dimensional code 300 created by the two-dimensional code conversion means 71g consists of 192 bytes. The transmission information has a general-purpose configuration so that error information recorded in not only the gaming machine 1 of the model described in the present embodiment but also other types of gaming machines can be transmitted. Alternatively, a player's game record may be included in the transmission information. Hereinafter, items included in the transmission information will be described.

  Data indicating the domain of the data management server 500 and a request to the data management server 500 is set in the 0th to 28th bytes of the transmission information. A case-specific code for identifying the gaming machine 1 is set in the 29th to 39th bytes of the transmission information.

  The 40th to 61st bytes of the transmission information are reserved areas. The transmission information generation time is set in the 62nd to 67th bytes of the transmission information. A model code indicating the type of the gaming machine 1 is set in the 68th to 71st bytes of the transmission information.

  A type number is set in the 72nd to 73rd bytes of the transmission information. Here, both the 72nd byte and the 73rd byte are set to 3FH.

  The error type is set in the 74th to 75th bytes of the transmission information. Error information is set in the 76th to 188th bytes of the transmission information. A checksum is set from the 189th byte to the 191st byte of the transmission information.

  The error information set in the 76th to 188th bytes of the transmission information has a command type consisting of one character (6 bits). If the command type is accompanied by a parameter, it is also provided with a parameter consisting of two characters (12 bits) after the one-character command type. FIG. 85 shows examples of command types and parameters.

  In the present embodiment, a door key switch 2S and a setting key switch 20S are connected to the sub CPU 71. The door key switch 2S detects that the door key 2 has been rotated in the left direction and outputs it to the sub CPU 71.

  Here, the error of the gaming machine 1 is reset when the door key 2 is rotated leftward. Further, the setting key switch 20S detects that the setting key for operating the setting value of the game has been operated, and outputs it to the sub CPU 71.

  When the occurrence of a communication error is detected by the communication error detection means 71a, the error information registration means 71d stores the error code of the communication error in the error information history storage area 73d-1 of the sub RAM 73-1. The received data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73e-1, and stores the communication error log in the communication error storage area 73f-1.

  If the occurrence of an error other than a communication error is detected by the procedure detection means 71b other than the communication error detection means 71a, the data destruction detection means 71c, or other error detection means, the error information registration means 71d The code is stored in the error information history storage area 73d-1 of the sub RAM 73-1. The received data log storage unit 71e stores the communication log in the communication log collection ring buffer area 73e-1, but does not store the communication error storage area 73f-1.

  Then, when the door key 2 is operated in a predetermined manner, the error information history display means 71f causes the liquid crystal display device 5 to display the error information history stored in the error information history storage area 73d-1. In this case, as shown in FIG. 83, when the “COM error alarm” item 23b is selected in the liquid crystal display area 23, the error information history display means 71f displays the communication information on the right side of the “COM error alarm” item 23b. A two-dimensional code 300 corresponding to the error is displayed.

  In the present embodiment, in order to display the error information history shown in FIG. 83 on the liquid crystal display device 5, two types of operation methods, a normal operation by a staff member and a simple operation, are employed.

  In the normal operation, the attendant turns the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and the liquid crystal display area 23 is shown in FIG. The menu screen is displayed. Then, when the clerk operates the operation key and selects the “error information history” item 23a, the error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23.

  On the other hand, in the simple operation, the clerk turns the door key 2 counterclockwise to reset the error, and holds the state for a predetermined time, for example, 5 seconds or more, so that the error information history screen shown in FIG. It is displayed.

  The sub device error detection unit 71 h detects the presence or absence of a communication error or other errors between the sub CPU 71 and a sub device such as the scaler control board 77. For example, an error detected by executing a sub-device command reception process shown in FIG. 107 to be described later is stored in the error information history storage area 73d-1 by the error information registration unit 71d according to the error content, for example, The head is stored as an error code (SD COM STX) other than STX or not received by ETX.

  The error code is included in the error information history created in the error information history storage area 73d-1.

  Further, the sub CPU 71 incorporates an RTC 70a which is a dedicated clock circuit. An external RTC 70c is connected to the sub CPU 71 for backup of the built-in RTC 70a. A battery 70b is connected to the external RTC 70c and the SRAM 73-2. The internal RTC 70a and the external RTC 70c are processed by an RTC control task shown in FIG.

  The GPU 74 performs a process for displaying an image on the liquid crystal display device 5 based on an image display command received from the sub CPU 71. Data necessary for processing performed by the GPU 74 is expanded in the VRAM 75 at the time of activation. The GPU 74 superimposes the image data developed in the VRAM 75 in order from the background image located at the rear to the image located at the front, generates image data, and supplies the image data to the liquid crystal display device 5 via the scaler control board 77. As a result, an image corresponding to the effect data determined by the sub CPU 71 is displayed on the liquid crystal display area 23 by the liquid crystal display device 5. The size of the original image of the displayed image can be selected by the scaler control board 77.

  The VRAM 75 has two frame buffers, a writing image data area and a display image data area. The writing image data area stores image data generated by the GPU 74, and the display image data area includes Image data to be displayed on the liquid crystal display device 5 is stored. The GPU 74 causes the liquid crystal display device 5 to sequentially display image data by alternately switching these frame buffers (that is, switching banks).

  The A / D converter 78 converts the digital sound data selected by the sub CPU 71 based on the effect data into analog sound data, and transmits the analog sound data to the amplifier 79. The amplifier 79 amplifies the analog-format sound data received from the A / D converter 78 based on the volume adjusted by a volume adjustment knob (not shown) provided in the gaming machine 1, and the speakers 21L and 21R. Send to. As a result, sounds corresponding to the effect data determined by the sub CPU 71 are output from the speakers 21L and 21R.

[Game state]
Next, the transition of the gaming state will be described with reference to FIG. The main gaming state managed by the main control circuit 60 includes a general gaming state, an RT1 gaming state, an RT2 gaming state, an RT3 gaming state, an RT4 gaming state, and a BB gaming state (a general term of BB1 gaming state to BB4 gaming state). Although not shown, there is an SB gaming state in which only one game coexists with other gaming states, an RB1 gaming state that operates in the BB1 gaming state to the BB3 gaming state, and an RB2 gaming state that operates in the BB4 gaming state.

  First, in the general gaming state, the SB spilled eyes (SB spilled eyes 1 to SB spilled eyes 12) are displayed on the active line, thereby transitioning to the RT1 gaming state. Next, in the RT1 gaming state, the raised one-step lip 1 is displayed on the active line, thereby transitioning to the RT2 gaming state. Next, in the RT2 gaming state, the two-step up lip (up two-step lip 1, up two-step lip 2) and the second up (up two to one up two) are displayed on the active line, so that RT3 Transition to the gaming state.

  Further, in the RT2 gaming state or the RT3 gaming state, the SB spilling eyes (SB spilling eyes 1 to SB spilling eyes 12) are displayed on the active line, thereby transitioning to the RT1 gaming state. In the RT1 gaming state to the RT3 gaming state, the push order bell failure (push order bell failure 1 to push order bell failure 4) is displayed on the active line, thereby transitioning to the general gaming state.

  In the general gaming state, the RT1 gaming state to the RT3 gaming state, the BB (BB1 to BB4) is determined as the internal winning combination, thereby transitioning to the RT4 gaming state. In the RT4 gaming state, BB (BB1 to BB4) is displayed, thereby transitioning to the BB gaming state. When a predetermined number (270 or 60) of medals are paid out in the BB gaming state, a transition is made to the general gaming state.

  Next, an internal lottery table determination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 11 is a diagram showing an example of an internal lottery table determination table of the gaming machine 1 in the present embodiment.

  In the internal lottery table determination table, an internal lottery table used for determining an internal winning combination in an internal lottery process described later corresponding to a gaming state (on / off of each game state flag described later), and the number of lotteries Is stipulated. Thereby, for example, when only the SB gaming state flag and the RT1 gaming state flag are “1 (ON)”, “the internal lottery table for RT1 gaming state during SB” is selected as the number of lotteries. “49” is selected.

  Next, an internal lottery table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 12 is a diagram in which examples of the general lottery state internal lottery table, RT1 gaming state internal lottery table to RT4 gaming state internal lottery table of the gaming machine 1 according to the present embodiment are summarized.

  FIG. 13 is a diagram illustrating an example of the internal lottery table for the RB1 gaming state of the gaming machine 1 according to the present embodiment.

  FIG. 14 is a diagram showing an example of the internal lottery table for RB2 gaming state of the gaming machine 1 in the present embodiment. Note that, in the internal lottery table for general gaming state during SB, the internal lottery table for RT1 gaming state during SB to the internal lottery table for RT4 gaming state during SB, the lottery value corresponding to the winning number “1” in FIG. The difference is only “1001”, not “”.

  The internal lottery table is a table used when performing internal lottery in an internal lottery process described later, that is, when determining an internal winning combination. In the internal lottery table, lottery values and data pointers are defined for each winning number. The lottery value is a numerical value used to determine the data pointer. There are two types of data pointers, a small combination / replay data pointer and a bonus data pointer, which correspond to one or more internal winning combinations.

  The right column of the winning number in the internal lottery table shown in FIGS. 12 to 14 shows an abbreviation of the internal winning combination corresponding to the data pointer. In addition, on the right side of each internal lottery table shown in FIGS. 13 and 14, symbols that can be stopped and displayed on the line connecting the upper stage, the line connecting the middle stage, or the line connecting the lower stage corresponding to the data pointer. The stop form is shown.

  For example, in the RB1 gaming state, when “25” is determined as the small role / replay data pointer, a stop operation is performed at a timing at which a don symbol can be stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C. If it is performed, the don symbol is stopped and displayed on the lower stage of the left reel 3L and the lower stage of the middle reel 3C, but the stop operation was performed at a timing at which the don symbol can be stopped and displayed on the lower stage of the right reel 3R. Even in this case, the don symbol is not stopped and displayed in the lower stage of the right reel 3R.

  On the other hand, if “28” is determined as the small role / replay data pointer, the stop operation is performed at a timing at which a don symbol can be stopped and displayed on the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. As a result, the don symbol is stopped and displayed on the line connecting the lower stages of the reels.

  In addition, in the stop form of the symbols aligned on the winning line in FIG. 13, “tempered losing” means that even if the stop operation is performed at a timing at which the don symbol can be stopped and displayed on the corresponding line, "Don symbol-Don symbol-Don symbol" means a stop type that is not stopped and displayed on a line connecting the upper stage of each reel, a line connecting the middle stage, and a line connecting the lower stage.

  On the other hand, “per tempering” is a line in which “Don symbol-Don symbol-Don symbol” connects the upper stages of each reel by performing a stop operation on the corresponding line at a timing at which the Don symbol can be stopped and displayed. , Means a stop form that is stopped and displayed on a line connecting the middle stages or a line connecting the lower stages.

  Next, a method for determining a data pointer using a lottery value, that is, an internal lottery method will be described. In the internal lottery, first, a random number value is extracted from a predetermined numerical range “0 to 65535”, and a lottery value corresponding to each winning number is sequentially subtracted from the extracted random number value and a digit is performed. This is done by determining whether or not. Digit is performed when the numerical value to be subtracted is smaller, in other words, when the result of subtraction is negative.

  For example, when the internal lottery table for the general gaming state is determined to be the internal lottery table, when the extracted random number value is “1500”, the main CPU 31 first corresponds to the winning number “1” from “1500”. The lottery value “1000” to be subtracted is subtracted. The subtraction result is “1500−1000 = 500”, which is positive.

  Next, the main CPU 31 subtracts the lottery value “2100” corresponding to the winning number “2” from the subtracted value “500”. The subtraction result is “500-2100 = −1600”, which is negative. Therefore, the main CPU 31 determines the winning number “2” as the internal winning combination, that is, “13” as the small combination / replay data pointer and “0” as the bonus data pointer.

  According to this internal lottery method, the larger the numerical value defined as the lottery value, the higher the possibility that the data pointer of the corresponding winning number will be determined. The winning probability of each winning number is “the lottery value corresponding to each winning number / the number of all random values that may be extracted (“ 65536 ”)”.

  Note that various types of lottery performed using lottery values, which will be described later, are the same as those for determining the data pointer. That is, lottery values are defined in the various lottery tables in association with items (for example, winning numbers) that may be selected by lottery. Hereinafter, the various lottery methods based on the lottery value are the same as the internal lottery method, and thus description thereof is omitted.

  Next, the RT transition table will be described with reference to FIG. The RT transition table is a table used when a gaming state flag is updated in an RT control process to be described later. As shown in FIG. 15, in the RT transition table, the display combination and the control contents for the game state flag are defined correspondingly.

  Specifically, when the combination of symbols related to any one of push order bell failure 1 to push order bell failure 4 is stopped and displayed on the active line, all the game state flags are turned off. That is, the general gaming state is activated. In addition, when the combination of symbols related to any one of the SB spilled eyes 1 to 12 is stopped and displayed on the active line, the RT1 gaming state flag is turned on. In addition, when the combination of symbols related to the raising 1-step lip 1 is stopped and displayed on the active line, the RT2 gaming state flag is turned on. In addition, when the combination of symbols related to any one of the raising 2 stage lip 1, the raising 2 stage lip 2, and the second raising 1 to the second raising 3 is stopped on the active line, the RT3 gaming state flag is turned on. To do.

  In addition, push order bell failure 1-push order bell failure 4, SB spilled eyes 1-SB spilled eyes 12, raised 1 stage lip 1, raised 2 stage lip 1, raised 2 stage lip 2, raised 2 stage 1-raised 2nd stage 3 is a case where a predetermined combination is determined as an internal winning combination, and when a stop operation is performed according to a predetermined stop operation sequence, the stop operation is stopped in a stop operation sequence different from the predetermined stop operation sequence. This is a display combination that may be stopped and displayed on the active line when an operation is performed or when a stop operation is not performed at an appropriate timing, which will be described in detail later.

  Next, the bonus internal winning combination determination table and the small winning combination / replay internal winning combination determination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 16 is a diagram showing an example of a bonus internal winning combination determination table for the gaming machine 1 in the present embodiment. FIG. 17 is a diagram showing an example of a small combination / replay internal winning combination determination table of the gaming machine 1 according to the present embodiment. Hereinafter, the bonus internal winning combination determination table and the small winning combination / replay internal winning combination determination table are collectively referred to as an internal winning combination determination table.

  The internal winning combination determination table is a table used when determining an internal winning combination based on a data pointer in an internal lottery process described later. Each winning combination determined as an internal winning combination corresponding to the data pointer is defined in the internal winning combination determination table. Each combination corresponds to each bit stored in an internal winning combination storage area described later. Therefore, it is possible to identify which combination is an internal winning combination by determining which bit in the internal winning combination storing area is “1”.

  In the bonus internal winning combination determination table shown in FIG. 16, internal winning combinations corresponding to bonus data pointers “1” to “5” are defined. When “5” is determined as the bonus data pointer, the combination of symbols related to SB is stopped and displayed on the active line depending on whether or not the stop operation is performed in a predetermined stop order, or The combination of symbols related to any of the SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the effective line.

  In the small winning combination / replay internal winning combination determining table shown in FIG. 17, internal winning combinations corresponding to the small winning combination / replay data pointers “1” to “31” are defined. For example, when “1” is determined as the small combination / replay data pointer, the normal lip 1 and the raised one-stage lip 1 become the internal winning combination.

  When “2” is determined as the small role / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the second stop operation is performed on the right reel 3R. Only when the 3 stop operation is performed, the combination of symbols related to the raised 1-step lip 1 is stopped and displayed on the active line. On the other hand, when the stop operation is performed in the other stop operation order, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  Also for the small role / replay data pointers “3” to “6”, a stop operation sequence in which the combination of symbols related to the raised 1-step lip 1 is stopped and displayed on the active line is determined in advance. When the stop operation is performed in a stop operation order other than the above, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  Specifically, when the small role / replay data pointer “3” is determined, the first stop operation for the left reel 3L, the second stop operation for the right reel 3R, and the middle reel 3C Only when the third stop operation is performed, the combination of symbols related to the one-step lip 1 is stopped and displayed on the active line.

  When the small role / replay data pointer “4” is determined, the first stop operation is performed on the middle reel 3C, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the right reel 3R. The symbol combination related to the one-step lip 1 is stopped and displayed on the active line only when the operation is performed.

  When the small role / replay data pointer “5” is determined, the first stop operation is performed on the middle reel 3C, the second stop operation is performed on the right reel 3R, and the third stop operation is performed on the left reel 3L. The symbol combination related to the one-step lip 1 is stopped and displayed on the active line only when the operation is performed.

  When the data pointer “6” for the small role / replay is determined, the combination of symbols related to the one-step lip 1 is stopped on the effective line only when the first stop operation is performed on the right reel 3L. Is displayed.

  In addition, when “7” is determined as the small role / replay data pointer, only when the first stop operation is performed on the left reel 3L, the raised two-step lip 1, the raised two-step lip 2, The combination of symbols relating to any one of the raised second eye 1, the raised second eye 2, and the raised second eye 3 is stopped and displayed on the active line.

  In addition, when the raised second 1, raised second 2, and raised second 3 are stopped and displayed on the effective line, the normal lip 1 or the raised one-step lip 1 is simultaneously stopped and displayed on the effective line. On the other hand, when the stop operation is performed in the other stop operation order, the symbol combination related to the normal lip 1 is stopped and displayed on the active line.

  For the data pointers “8” to “11” for the small role / replay, the combination of the symbols related to the two-step-up lip 1, the two-step lip-up 2, the second-up 1, the second-up 2, and the second-up 3 is effective. The stop operation order to be stopped and displayed on the line is determined in advance, and when the stop operation is performed in a stop operation order other than this stop operation order, the combination of symbols related to the normal Lip 1 is on the active line. Stopped display.

  Specifically, when the small role / replay data pointer “8” is determined, the first stop operation for the middle reel 3C, the second stop operation for the left reel 3L, and the right reel 3R Only when the third stop operation is performed, the combination of symbols related to any one of the two-step raising lip 1, the raising two-step lip 2, the raising second eye 1, the raising second eye 2, and the raising second eye 3 is on the effective line. Is stopped.

  When the small role / replay data pointer “9” is determined, the first stop operation is performed on the middle reel 3C, the second stop operation is performed on the right reel 3R, and the third stop operation is performed on the left reel 3L. The combination of symbols related to any one of the two-step raising lip 1, the two-step lip raising 2, the second raising 1, the second raising 2, and the second raising 3 is stopped and displayed on the active line. .

  When the small role / replay data pointer “10” is determined, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. The combination of symbols related to any one of the two-step raising lip 1, the two-step lip raising 2, the second raising 1, the second raising 2, and the second raising 3 is stopped and displayed on the active line. .

  When the small role / replay data pointer “11” is determined, the first stop operation is performed on the right reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop operation is performed on the left reel 3L. The combination of symbols related to any one of the two-step raising lip 1, the two-step lip raising 2, the second raising 1, the second raising 2, and the second raising 3 is stopped and displayed on the active line. .

  When “12” is determined as the small role / replay data pointer, the symbol related to the bell is stopped and displayed in the middle of the middle reel 3C regardless of the stop operation order.

  When “13” is determined as the small role / replay data pointer, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, and the third stop is performed on the right reel 3R. Only when the operation is performed, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C.

  On the other hand, when the stop operation is performed in the other stop operation order, the combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line. When the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C, any one of the center line 8c, the cross-up line 8a, and the cross-down line 8e indicates "Bell 1 symbol (Bell 2 symbol)-Bell 1 symbol-" "Bell 1 symbol" is stopped and displayed.

  Further, when the combination of symbols relating to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line, the lower stage of the left reel 3L, the lower stage of the middle reel 3C, and the lower stage of the right reel 3R. "Bell 1 symbol (Bell 2 symbol)-Bell 1 symbol-Bell 1 symbol" is stopped and displayed.

  As for the small role / replay data pointers “14” to “17”, a stop operation order in which symbols related to the bell are stopped and displayed in the middle stage of the middle reel 3C is determined in advance, and stop operations other than this stop operation order are performed. When the stop operation is performed in order, the combination of symbols related to any one of the push order bell failure 1 to the push order bell failure 4 is stopped and displayed on the active line.

  Specifically, when the small role / replay data pointer “14” is determined, the first stop operation for the left reel 3L, the second stop operation for the right reel 3R, and the middle reel 3C Only when the third stop operation is performed, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C.

  When the small role / replay data pointer “15” is determined, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C only when the first stop operation is performed on the middle reel 3C. .

  When the small / replay data pointer “16” is determined, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. The symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C only when the above is performed.

  When the small role / replay data pointer “17” is determined, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. The symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C only when the above is performed.

  In addition, in the internal lottery table, when the small role / replay pointer that indicates the stop operation order (push order) for the reel is determined, the suggested push order is the so-called correct push order, When the stop operation is performed in the pushing order, each reel 3 is stopped so that the player is advantageous.

  For example, when the small role / replay pointer “2” (abbreviation “left middle right bell”) is determined, the first stop operation is performed on the left reel 3L, the second stop operation is performed on the middle reel 3C, Only when the third stop operation is performed on the right reel 3R, the symbol related to the bell is stopped and displayed on the middle stage of the middle reel 3C (payout number: 4 sheets × 3 lines = 12 sheets). If it is, the symbol related to the bell is stopped and displayed on the lower stage of the middle reel 3C (paid-out number: 4 sheets × 1 line = 4 sheets). Note that the small role / replay pointers whose abbreviations indicate the stop operation order (pushing order) for the reels are “2” to “11” and “13” to “17”.

  Next, the symbol combination table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 18 is a diagram showing an example of the symbol combination table of the gaming machine 1 in the present embodiment.

  In the symbol combination table, a combination of symbols related to the privilege display displayed on the active line, or a combination of symbols related to the transition of the gaming state, data indicating a display combination corresponding to the symbol combination, and a storage area type , And the number of payouts. The data indicating the display combination is any one of a display combination storage area 1 to a display combination storage area 7 each of which will be described later (display combination storage area 1 to display combination storage area 7 are collectively referred to as a display combination storage area). Is stored in the data. Further, in which display combination storage area the data is stored is defined by the storage area type.

  In the symbol combination table, BB1 to BB4, SB, normal lip 1, raised 1 stage lip 1, raised 2 stage lip 1, raised 2 stage lip 2, control lip 1 to control lip 3, bell, ice 1 Cherry 1-Cherry 12, Control role 1-Control role 3, BB middle role 1-BB middle role 5, Raise 2-1, Raise 2, Push order bell failure 1-Push order bell failure 4, Spilled eyes 1 to SB spilled eyes 12 are defined.

  For example, the normal lip 1 is established by displaying “replay symbol-replay symbol-replay symbol” on the active line. When any of the various replays (normal lip 1, raising 1-step lip 1, raising 2-step lip 1, raising 2-step lip 2, control lip 1 to control lip 3) is established, re-playing is performed in the next game. Is called. That is, the same number of medals as the number inserted in the game in which any of the various replays is established is automatically inserted in the next game without being based on the player's input operation.

  Thereby, the player can play the next game without consuming medals. Here, the above-mentioned medal payout and re-game are examples of giving game value. The bell is established by displaying “ANY symbol-Bell 1 symbol-ANY symbol” on the active line. “ANY” represents that any symbol may be used.

  Next, a bonus operation time table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 19 is a diagram showing an example of the bonus operation time table of the gaming machine 1 in the present embodiment.

  The bonus operating time table is a table used when setting conditions for ending the BB gaming state and the RB gaming state. In the bonus operation time table, end conditions relating to the BB1 gaming state to the BB4 gaming state, the RB1 gaming state, and the RB2 gaming state are defined. Specifically, in the bonus operation time table, “270” is defined for the value of the bonus end number counter as the end condition of the BB1 gaming state to the BB3 gaming state.

  Further, “60” is defined for the value of the bonus end number counter as an end condition of the BB4 gaming state. In the BB1 gaming state to the BB3 gaming state, the RB1 gaming state operates, and in the BB4 gaming state, the RB2 gaming state operates. Further, in the bonus operation time table, “12” and “8” are defined for the values of the number of possible games and the number of possible winnings, respectively, as termination conditions for the RB1 gaming state and the RB2 gaming state.

  Next, the pull-in priority order table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIGS. FIG. 20 is a diagram illustrating an example of the pull-in priority table A of the gaming machine 1 in the present embodiment, and FIG. 21 illustrates an example of the pull-in priority table B of the gaming machine 1 in the present embodiment. FIG. Hereinafter, the pull-in priority table A and the pull-in priority table B are collectively referred to as a pull-in priority table.

  When multiple winning combinations are determined as internal winning combinations, when the multiple winning combinations can be drawn on the active line, the drawing priority order table gives priority to the symbol related to any combination on the active line. Specifies whether to stop. As described above, basically, replay from the highest priority order, small role (the higher the payout number, the higher the priority order. In the case of JAC1 (seven in BB), priority is given), and bonus order It has become.

  However, in the present embodiment, there are a plurality of types of replays, and the priority order of each replay differs depending on the conditions. Therefore, a pull-in priority table A and a pull-in priority table B are provided for each condition.

  The pull-in priority table A is a table that is used during normal times (including during BB) or so-called correct push order, and the priority of each replay is raised two-step Lip 1, raised two-step Lip 2> up one-step Lip 1 > Normal Lip 1> Control Lip 1-Control Lip 3

  On the other hand, the pull-in priority table B is a table used at the time of so-called incorrect push order, and the priority of each replay is normal lip 1> up 2 step lip 1, up 2 step lip 2, up 1 step lip 1> control. Lip 1-control Lip 3 is in this order.

  Although not shown, when two or more combinations related to the transition of the RT gaming state simultaneously become display combinations, it is determined in advance which one is to be prioritized. In the present embodiment, in the order of higher priority, the two-step raising lip 1, the two-step raising lip 2, the second raising 1-the second raising 3> the first raising lip 1> SB spilling 1-SB spilling Eye 12> Pushing order bell failure 1-pushing order bell failure 4

  Next, the stop table stored in the main ROM 32 of the main control circuit 60 will be described with reference to FIG. FIG. 22 is a diagram showing an example of a stop table for the first stop of the middle reel when the small role / replay data pointer “15” is won. The stop table defines line data and stop data corresponding to symbol positions “0” to “20”. The symbol position is a symbol position located in the middle of the symbol display area when a stop operation is detected, and is a symbol position at which rotation of the reel starts to be stopped.

  Although not shown, the main ROM 32 of the main control circuit 60 stores a small role / replay data pointer and a plurality of stop tables corresponding to the stop operation order of the player. For example, when “5” is determined as the bonus data pointer, the first stop operation is performed on the right reel 3R, the second stop operation is performed on the left reel 3L, and the third stop operation is performed on the middle reel 3C. Only when the operation is performed, a stop table in which the number of sliding frames is defined so that none of the SB spilled eyes 1 to SB spilled eyes 12 is stopped and displayed on the active line is selected.

  On the other hand, when the stop operation is performed in a stop operation order other than the stop operation order, when the stop operation is performed on each reel at a timing at which the combination of symbols relating to SB is not stopped and displayed, SB spill 1 A stop table in which the number of sliding frames is defined so that the combination of symbols relating to any one of the SB spilled eyes 12 is stopped and displayed on the active line is selected.

  Next, an internal winning combination storing area, a display combination storing area, and a carryover combination storing area allocated to the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 23 is a diagram showing an example of the internal winning combination storing area of the gaming machine 1 in the present embodiment. FIG. 24 is a diagram showing an example of the display combination storing area of the gaming machine 1 in the present embodiment. FIG. 25 is a diagram illustrating an example of the carryover combination storage area of the gaming machine 1 according to the present embodiment.

  As shown in FIG. 23, the internal winning combination storing area is composed of an internal winning combination storing area 1 to an internal winning combination storing area 5. The internal winning combination storing area 1 to the internal winning combination storing area 5 are 8-bit data areas allocated on the main RAM 33, and store internal winning combination information. Each internal winning combination storing area indicates which combination is an internal winning combination by storing data of “0” or “1” in the area of bits “0” to “7”.

  As shown in FIG. 24, the display combination storage area is composed of a display combination storage area 1 to a display combination storage area 7. The display combination storage area 1 to the display combination storage area 7 are 8-bit data areas allocated on the main RAM 33 and store display combination information. Each display combination storage area indicates which combination is a display combination by storing data of “0” or “1” in an area of bits “0” to “7”.

  As shown in FIG. 25, the carryover combination storage area is an 8-bit data area allocated on the main RAM 33 and stores carryover combination information. The carryover combination storage area indicates which combination is a carryover combination by storing data of “0” or “1” in an area of bits “0” to “3”.

  Next, with reference to FIG. 26, the game state flag storage area allocated to the main RAM 33 of the main control circuit 60 will be described. FIG. 26 is a diagram showing an example of the game state flag storage area of the gaming machine 1 in the present embodiment.

  As shown in FIG. 26, the gaming state flag storage area includes a gaming state flag storage area 1 and a gaming state flag storage area 2. The gaming state flag storage area is an 8-bit data area allocated on the main RAM 33, and indicates whether each gaming state flag is on or off. Further, when all the data in each area of the game state flag storage area is “0”, it indicates that the game state is a general game state.

  Next, the symbol storage area in the main RAM 33 of the main control circuit 60 will be described with reference to FIGS. FIG. 27 is a diagram showing a storage example (when the symbol position data of each reel is “0”) in the symbol storage area A (non-RB) of the gaming machine 1 in the present embodiment. FIG. 28 shows a storage example of the symbol storage area B (in RB) of the gaming machine 1 according to the present embodiment (when the symbol position data of each reel is “9”, “8”, “9” from the left reel). ).

  The symbol storage area is an area for storing a corresponding symbol code in the symbol display areas 4L, 4C, and 4R constituting each effective line, and is provided for each effective line. For example, when the gaming state is a gaming state other than the RB gaming state, it corresponds to each of the middle stage of the left symbol display area 4L, the middle stage of the middle symbol display area 4C, and the middle stage of the right symbol display area 4R constituting the center line 8c. Stores the symbol code.

  Such symbol storage areas are also provided for the other effective lines (cross down line 8e, bottom line 8d, cross up line 8a). When the gaming state is the RB gaming state, the effective line is only one line (RB special line 8f), and the RB special line 8f is configured in the symbol storage area corresponding to the RB special line 8f. The symbol codes corresponding to the middle part of the left symbol display area 4L, the lower part of the middle symbol display area 4C, and the upper part of the right symbol display area 4R are stored.

  The symbol storage area shown in FIG. 27 indicates the symbol storage area when the symbol code is stored when the symbol position data of each reel is “0”. The case where the symbol position data is “0” means that the symbol position “0” of each reel 3L, 3C, 3R (red 7 symbol for left reel 3L, red 7 symbol for middle reel 3C, red for right reel 3R) 7 symbols) are displayed in the middle of the left symbol display area 4L, the middle of the middle symbol display area 4C, and the middle of the right symbol display area 4R, respectively.

  Therefore, in this case, the symbol storage area corresponding to the upper symbol display area 4L has a symbol position “1” (wave symbol), and the symbol storage area corresponding to the lower symbol display area 4L has a symbol position “ The symbol code indicating the symbol “20” (replay symbol) is stored. The symbol storage area corresponding to the upper part of the middle symbol display area 4C has a symbol position “1” (replay symbol), and the symbol storage area corresponding to the lower part of the middle symbol display area 4C has symbol position “20”. A symbol code indicating a symbol (cherry 1 symbol) is stored.

  Furthermore, in the symbol storage area corresponding to the upper part of the right symbol display area 4R, the symbol at the symbol position “1” (cherry 1 symbol), and in the symbol storage area corresponding to the lower part of the right symbol display area 4R, the symbol position “20”. The symbol code indicating the symbol (bell 1 symbol) is stored.

  Next, various lottery tables stored in the sub ROM 72 of the sub control circuit 70 will be described with reference to FIGS. Each lottery table has a lottery value (for each table depending on the condition), and lottery is performed in the same manner as the lottery process in the internal lottery process described above. The lottery value is defined to be “65536” in total.

  First, the navigation mode transition lottery table will be described with reference to FIGS. FIG. 29 is a diagram illustrating an example of the navigation mode transition lottery table A of the gaming machine 1 according to the present embodiment. FIG. 30 is a diagram illustrating an example of the navigation mode transition lottery table B of the gaming machine 1 according to the present embodiment. FIG. 31 is a diagram showing an example of the navigation mode transition lottery table C of the gaming machine 1 in the present embodiment.

  The navigation mode transition lottery table is a table used when determining the destination navigation mode from the current navigation mode. In the navigation mode transition lottery table A, lottery values are defined according to the current navigation mode, the value of the small role / replay data pointer, and the like. In the navigation mode transition lottery table B, lottery values are defined according to the current navigation mode, the value of the bonus data pointer, and the like. In some cases, the same navigation mode as the current navigation mode is determined as the destination navigation mode (ie, the navigation mode does not shift).

  Next, the navigation game state transition standby number lottery table will be described with reference to FIG. FIG. 32 is a diagram showing an example of the navigation game state transition standby number lottery table of the gaming machine 1 in the present embodiment.

  The navigation game state transition standby number lottery table is a table used when determining the navigation game state transition standby number. In the navigation game state transition standby number table, lottery values are defined for each of the three patterns A, B, and C, as shown in the figure, and each pattern is properly used depending on the conditions for lottery.

  Next, the navigation game state 3 transition standby number lottery table will be described with reference to FIG. FIG. 33 is a diagram showing an example of the navigation game state 3 transition standby number lottery table of the gaming machine 1 in the present embodiment.

  The navigation gaming state 3 transition standby number lottery table is a table used when determining the navigation gaming state 3 transition standby number. In the navigation game state 3 transition standby number table, a lottery value is defined according to a value of a navigation game number counter, which will be described later.

  Next, with reference to FIGS. 34 to 37, the navigation game state 3 addition game number lottery table will be described. FIG. 34 is a diagram showing an example of the navigation game state 3 addition game number lottery table A of the gaming machine 1 in the present embodiment. FIG. 35 is a diagram showing an example of the navigation game state 3 addition game number random determination table B of the gaming machine 1 according to the present embodiment. FIG. 36 is a diagram illustrating an example of the navigation game state 3 addition game number random determination table C of the gaming machine 1 according to the present embodiment. FIG. 37 is a diagram illustrating an example of the navigation game state 3 addition game number random determination table D of the gaming machine 1 according to the present embodiment.

  The navigation game state 3 addition game number lottery table is a table used when determining the number of navigation game state 3 addition games. In the navigation game state 3 addition game number lottery tables A to C, lottery values are defined according to the current navigation mode, the value of the small role / replay pointer, the value of the bonus data pointer, and the like. In the navigation game state 3 addition game number lottery table D, the same lottery value is used regardless of the current navigation mode.

  Next, the navigation game state 3 addition lottery mode lottery table will be described with reference to FIGS. FIG. 38 is a diagram showing an example of the navigation game state 3 addition lottery mode lottery table A of the gaming machine 1 in the present embodiment. FIG. 39 is a diagram showing an example of the navigation game state 3 addition lottery mode lottery table B of the gaming machine 1 in the present embodiment. FIG. 40 is a diagram showing an example of the navigation game state 3 addition lottery mode lottery table C of the gaming machine 1 in the present embodiment. FIG. 41 is a diagram showing an example of the navigation game state 3 addition lottery mode lottery table D of the gaming machine 1 in the present embodiment.

  The navigation game state 3 addition lottery mode lottery table is a table used when determining the navigation game state 3 addition lottery mode. In the navigation game state 3 addition lottery mode lottery table A and the navigation game state 3 addition lottery mode lottery table D, lottery values are defined according to the current navigation mode. In the navigation game state 3 addition lottery mode lottery table B, lottery values are defined according to the current navigation mode, bonus data pointers, and the like. In the navigation game state 3 addition lottery mode lottery table C, lottery values are defined according to the current navigation mode and the small role / replay data pointer.

  Next, the navigation set number lottery table will be described with reference to FIG. FIG. 42 is a diagram showing an example of a navigation set number lottery table of the gaming machine 1 in the present embodiment.

  The navigation set number lottery table is a table used when determining the number of navigation sets. In the navigation set number lottery table, there are two lottery values that are used when BB3 is won (determined as an internal winning combination) and there is a game stop for production, and other cases. It is prescribed.

  Next, the navigation game state 3 navigation game number addition lottery table will be described with reference to FIG. FIG. 43 is a diagram illustrating an example of the navigation game state 3 navigation game number addition lottery table of the gaming machine 1 according to the present embodiment.

  The navigation game state 3 navigation game number addition lottery table is a table used when the navigation game state 3 navigation game number addition lottery table is performed. In the navigation game state 3 navigation game number addition lottery table, a lottery value is defined according to the navigation game state 3 addition lottery mode, the value of the small role / replay pointer, the value of the bonus data pointer, the game state, and the like. Yes.

  Next, the navigation game number special addition lottery table will be described with reference to FIG. FIG. 44 is a diagram showing an example of the navigation game number special addition lottery table of the gaming machine 1 in the present embodiment.

  The navigation game number special addition lottery table is a table used when determining the number of navigation games to be added in the navigation game number special addition lottery. In the navigation game number special addition lottery table, a lottery value is defined according to the value of the navigation game state 3 continuation counter, the type of BB determined as the internal winning combination, and the like.

  Next, a billy get challenge occurrence lottery table will be described with reference to FIG. FIG. 45 is a diagram showing an example of a billy get challenge occurrence lottery table of the gaming machine 1 in the present embodiment.

  The billy get challenge occurrence lottery table is a table used when the billy get challenge occurrence lottery is performed. In the billy get challenge occurrence lottery table, lottery values are defined according to the current navigation mode, the presence / absence of the game for production, and the on / off state of the billy get challenge success flag.

  Next, the billy get challenge control counter lottery table will be described with reference to FIG. FIG. 46 is a diagram showing an example of the billy get challenge control counter lottery table of the gaming machine 1 in the present embodiment.

  The billy get challenge control counter lottery table is a table used when the billy get challenge control counter lottery is performed. In the billy get challenge control counter lottery table, lottery values are defined in accordance with the presence / absence of stop of the game for production, the value of the small role / replay pointer, the value of the bonus data pointer, and the like.

  Next, the billy get challenge correct lottery table will be described with reference to FIG. FIG. 47 is a diagram illustrating an example of the billy get challenge correct lottery table of the gaming machine 1 according to the present embodiment.

  The billy get challenge correct lottery table is a table used when determining the correct answer (left, right, both) at the time of the billy get challenge. In the billy get challenge correct lottery table, lottery values are defined according to the situation when the billy get challenge is generated. Specifically, when the game is not in the RB game state, or when the game is in the RB game state and there is no stop for the effect, the right or left is determined with a probability of 50%. On the other hand, when there is an RB gaming state and there is an effect game stop, both (the correct answer on both the left and the right) are determined with a probability of “2048/65536 (= 3.125%)”.

  Next, with reference to FIG. 48, the lottery table when no billy get challenge is selected will be described. FIG. 48 is a diagram illustrating an example of a lottery table when no billy get challenge is selected for the gaming machine 1 according to the present embodiment.

  The no-bill-get-challenge lottery table is used to decide whether or not to win if the player chooses neither left nor right in the billy get challenge (ie, when no billy get challenge is selected). Table. In the lottery table when no billy get challenge is selected, a lottery value is defined according to the result of the billy get challenge correct lottery performed based on the billy get challenge correct lottery table.

  According to the lottery table when no billy get challenge is selected, even if the player selects neither left nor right, 50% if the result of the billy get challenge correct lottery is left or right. It is designed to win with a probability of. Also, if the result of the billy get challenge correct answer lottery is both, 100% probability is won.

[Control operation of main control circuit]
Next, the control operation of the main CPU 31 of the main control circuit 60 will be described with reference to the flowcharts shown in FIGS.

  First, with reference to FIG. 49, the reset interrupt process by the main CPU 31 of the main control circuit 60 will be described. FIG. 49 is a diagram showing a flowchart of reset interrupt processing by the main CPU 31 performed in the main control circuit 60 of the present embodiment. Further, the main CPU 31 generates a reset interrupt when power is turned on and a voltage is applied to the reset terminal, and the reset interrupt process stored in the main ROM 32 is sequentially performed based on the occurrence of the interrupt. Configured to do.

  First, the main CPU 31 clears the designated storage area (step S1). Specifically, the main CPU 31 clears the designated storage area of the main RAM 33 at the end of the previous game. More specifically, the main CPU 31 erases data in the writable area in the main RAM 33 used in the previous game, writes parameters necessary for the current game in the writable area in the main RAM 33, Specify the start address to the sequence program.

  Next, the main CPU 31 performs a bonus operation monitoring process (step S2).

  Next, the main CPU 31 performs medal acceptance / start check processing (step S3). In the medal acceptance / start check process, the insertion number counter is updated by checking the medal sensor 22S, the maximum BET switch 13S, and the like, and the input of the start switch 6S is checked. The main CPU 31 validates the winning line through the medal acceptance / start check process.

  Next, the main CPU 31 performs a process of extracting a random value and storing it in the random value storage area (step S4). Specifically, the main CPU 31 extracts a random value from the range of “0” to “65535” by the random number generator 36 and the sampling circuit 37 and stores the extracted random value in the random value storage area of the main RAM 33.

  Next, the main CPU 31 performs an internal lottery process (step S5). Specifically, the main CPU 31 refers to the internal lottery table determination table (see FIG. 11), the internal lottery table (see FIGS. 12 to 14), and the internal winning combination determination table (see FIGS. 16 and 17). To determine the internal winning role.

  Next, the main CPU 31 transmits start command data to the sub-control circuit 70 (step S6). The start command includes game state information, internal winning combination information (data pointer for small role / replay, bonus data pointer and internal winning combination storage area), carryover state information indicating whether or not a bonus carryover state, Information such as flags is included. The following command data is also transmitted to the sub control circuit 70 in the same manner.

  Next, the main CPU 31 determines whether or not the lock flag is on (step S7). When the main CPU 31 determines that the lock flag is on, the main CPU 31 turns off the lock flag and executes a lock effect (also referred to as effect game stop) for 5 seconds (step S8), and proceeds to the process of step S9. . The lock effect is an effect that delays the start of rotation of the reel 3. On the other hand, when the main CPU 31 determines that the lock flag is not on, the main CPU 31 proceeds to the processing of step S9 as it is.

  Next, the main CPU 31 requests the start of rotation of all reels (step S9). When the start of rotation of all reels is requested, rotation start processing and acceleration control processing of the reels 3L, 3C, and 3R are performed.

  Next, the main CPU 31 waits for a constant speed of reel rotation (step S10).

  Next, the main CPU 31 performs a reel stop control process (step S11). In the reel stop control process, the main CPU 31 stops the rotation of the reels 3L, 3C, 3R based on a stop signal transmitted from the stop switches 7LS, 7CS, 7RS by the stop operation of the player.

  Next, the main CPU 31 performs a display combination search process (step S12). In this display combination search process, the main CPU 31 determines the display combination and the number of payouts based on the combination of symbols displayed on the effective line as a result of stopping the rotation of all the reels 3L, 3C, 3R.

  Next, the main CPU 31 performs RT control processing (step S13).

  Next, the main CPU 31 transmits display command data (step S14). The display command includes information such as display combination information indicating a display combination and payout number information indicating a payout number.

  Next, the main CPU 31 performs medal payout processing (step S15). Specifically, in the payout mode, the main CPU 31 drives and controls the hopper 40 by the hopper drive circuit 41 based on the payout number, and pays out medals. In the credit mode, the main CPU 31 performs main control based on the payout number. The credit counter set in the RAM 33 is updated.

  Next, it is determined whether or not the bonus is being operated (step S16). Specifically, it is determined whether or not the BB1 gaming state to the BB4 gaming state or the SB gaming state. At this time, if the main CPU 31 determines that the bonus is being operated, it performs a bonus end check process (step S17), and proceeds to the process of step S18. On the other hand, when the main CPU 31 determines that the bonus operation is not being performed, or after finishing the processing of step S17, the main CPU 31 then performs a bonus operation check processing (step S18). The process proceeds to S1.

  As described above, the main CPU 31 executes the process from step S1 to step S18 as a process in one game (one game). When the process in step S18 is completed, the process in step S1 is executed to execute the process in the next game. Migrate to

  Next, the bonus operation monitoring process will be described with reference to FIG. FIG. 50 is a flowchart of the bonus operation monitoring process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the BB gaming state is set (step S31). At this time, when the main CPU 31 determines that it is in the BB gaming state, it proceeds to the processing of step S32. On the other hand, when determining that the main CPU 31 is not in the BB gaming state, the main CPU 31 ends the bonus operation monitoring process.

  When the main CPU 31 determines in the process of step S31 that it is in the BB gaming state, it then determines whether or not it is in the RB gaming state (step S32). At this time, when determining that the main CPU 31 is in the RB gaming state, the bonus operation monitoring process is terminated.

  On the other hand, when the main CPU 31 determines that it is not in the RB gaming state, the main CPU 31 performs RB operation processing according to the type of BB based on the bonus operation time table (see FIG. 19) (step S33), and performs bonus operation monitoring processing. Terminate. Specifically, the RB1 gaming state is activated in the BB1 gaming state to the BB3 gaming state, and the RB2 gaming state is activated in the BB4 gaming state.

  Next, with reference to FIGS. 51 and 52, the internal lottery process will be described. 51 and 52 are diagrams showing a flowchart of the internal lottery process performed by the main control circuit 60 of the present embodiment.

  First, the main CPU 31 refers to the internal lottery table determination table (see FIG. 11) and determines the type of the internal lottery table and the number of lotteries based on the game state flag (step S61). Next, the main CPU 31 acquires a random value from the random value storage area and sets it as a random number for determination (step S62). Next, the main CPU 31 sets “1” as the initial value of the winning number (step S63).

  Next, the main CPU 31 refers to the internal lottery table and acquires a lottery value based on the winning number (step S64). Next, the main CPU 31 subtracts the lottery value from the determination random number value, and sets the subtraction result as the determination random number value (step S65). Specifically, the main CPU 31 subtracts the lottery value acquired in the process of step S64 from the random number value for determination stored in the random number value storage area for determination, and updates the random number value storage area for determination with the subtraction result. .

  Next, the main CPU 31 determines whether or not a digit has been performed in the subtraction process of step S65, that is, whether or not the subtraction result has become a negative value (step S66). At this time, when the main CPU 31 determines that a digit has been made, the main CPU 31 obtains the small role / replay data pointer and the bonus data pointer based on the winning number (step S70), and proceeds to the processing of step S71.

  On the other hand, when the main CPU 31 determines that no digit has been placed, it then subtracts “1” from the number of lotteries and adds “1” to the winning number (step S67). Next, the main CPU 31 determines whether or not the number of lotteries is “0” (step S68).

  When determining that the number of lotteries is “0” in the process of step S68, the main CPU 31 determines the small role / replay data pointer and the bonus data pointer to be “0” (step S69). Transition to processing. On the other hand, when determining that the number of lotteries is not “0”, the main CPU 31 proceeds to the process of step S64. Thereafter, the main CPU 31 repeats the processing from step S64 to step S68 until the number of lotteries becomes “0” or a digit is made.

  After completing the processing of step S69 or step S70, the main CPU 31 refers to the small winning combination / replay internal winning combination determination table (see FIG. 17), and determines the internal winning combination based on the small winning combination / replay data pointer. A combination is acquired (step S71). Next, the main CPU 31 updates the internal winning combination storing area according to the internal winning combination storing area (step S72).

  Next, the main CPU 31 determines whether or not the carryover combination storage area is “00000000” (step S73). At this time, when the main CPU 31 determines that the carryover combination storage area is not “00000000”, the main CPU 31 proceeds to the process of step S80. On the other hand, when determining that the carryover combination storage area is “00000000”, the main CPU 31 refers to the bonus internal winning combination determination table (FIG. 16) and acquires the internal winning combination based on the bonus data pointer ( Step S74).

  Next, the main CPU 31 determines whether or not SB is an internal winning combination (step S75). At this time, when the main CPU 31 determines that the SB is an internal winning combination, the main CPU 31 updates the internal winning combination storing area according to the SB (step S76), and proceeds to the processing of step S80. On the other hand, when determining that SB is not an internal winning combination, the main CPU 31 determines whether or not BB is an internal winning combination (step S77).

  When the main CPU 31 determines in step S77 that BB is not an internal winning combination, the main CPU 31 proceeds to step S80. On the other hand, when determining that BB is an internal winning combination, the main CPU 31 updates the carryover combination storing area according to BB (step S78), turns on the RT4 gaming state flag (step S79), and performs the process of step S80. Migrate to

  When the main CPU 31 determines that the carryover combination storage area is not “00000000” in the process of step S73, and determines that BB is not the internal winning combination in the process of step S77, the process of steps S76 and S79. Then, the logical OR of the carryover combination storage area and the internal winning combination storage area 1 is taken, and the result is stored in the internal winning combination storage area 1 (step S80).

  Next, the main CPU 31 determines whether or not it is in the RB2 gaming state (step S81). When the main CPU 31 determines that it is not in the RB2 gaming state, it ends the internal lottery process. On the other hand, when determining that the main CPU 31 is in the RB2 gaming state, the main CPU 31 performs a lock lottery to win with a probability of 1/64 (step S82). Next, the main CPU 31 determines whether or not the result of the lock lottery is a win (step S83). If the main CPU 31 is a win, the main CPU 31 turns on the lock flag (step S84) and ends the internal lottery process. On the other hand, when the main CPU 31 determines that the result of the lock lottery is not winning, the internal lottery process is ended as it is.

  The main CPU 31 performs lottery of an internal winning combination by repeatedly executing the processes of steps S64 to S68 in the internal lottery process. Specifically, the main CPU 31 sequentially subtracts the lottery value from the extracted random number value, thereby obtaining the small role / replay data pointer and the bonus data pointer corresponding to the winning number when the digit is placed. The internal winning combination is determined based on the determined data pointers and the internal winning combination determination table.

  In the present embodiment, the lock lottery is performed with a probability of 1/64 in the RB2 gaming state, but the lock lottery is performed in the normal state (general gaming state, RT1 gaming state to RT3 gaming state). It is good. Further, the lock lottery has a high winning probability when a specific small combination (for example, a small combination with a data pointer for small combination replay of “18” to “22”) or a bonus combination (BB1 to BB4) is won internally. It is good also as performing lottery by setting a winning probability as follows.

  Next, the reel stop control process will be described with reference to FIG. FIG. 53 is a diagram showing a flowchart of the reel stop control process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 sets “3” in the stop button non-operation counter (step S101), and then acquires a stop table corresponding to the internal winning combination (step S102).

  Next, the main CPU 31 determines whether or not a valid stop button has been pressed (step S103). An effective stop button is a stop button that has not been stopped. At this time, if the main CPU 31 determines that a valid stop button has been pressed, the main CPU 31 proceeds to the processing of step S104. On the other hand, when the main CPU 31 determines that a valid stop button has not been pressed, the main CPU 31 executes the process of step S103 again. That is, the main CPU 31 repeats the process of step S103 until a stop operation corresponding to a valid stop button is detected.

  When the main CPU 31 determines in the process of step S103 that an effective stop button has been pressed, the main CPU 31 invalidates the operation of the corresponding stop button (step S104). Next, the stop table is reselected according to the operation stop button (stop order) (step S105).

  Next, the main CPU 31 sets “5” as the number of checks (step S106). Next, the main CPU 31 refers to the drawing priority table (see FIG. 20 and FIG. 21), and based on the internal winning combination, the symbol having the highest priority within the range of the number of checks from the symbol position corresponding to the symbol counter. The position is searched (step S107).

  Next, the main CPU 31 determines the number of sliding symbols based on the stop table, the symbol position corresponding to the symbol counter, and the search result, and sets the planned stop position (step S108). Next, the main CPU 31 transmits a reel stop command (step S109). The reel stop command includes information such as stop reel type information indicating which reel has stopped, stop start position information indicating the stop start position, and slip frame number information indicating the number of slide frames.

  Next, the main CPU 31 refers to the symbol arrangement table (see FIG. 3), acquires a symbol code based on the stop reel, the planned stop position, and the gaming state, and stores it in the symbol storage area (step S110).

  Finally, the main CPU 31 determines whether or not there is a stop button whose operation is valid (step S111). At this time, when the main CPU 31 determines that there is no stop button for which the operation is effective, the main CPU 31 ends the reel stop control process. On the other hand, when the main CPU 31 determines that there is a stop button whose operation is valid, the main CPU 31 proceeds to the process of step S103. Thereafter, the main CPU 31 repeats the processing from step S103 to step S111 until it is determined that there is no stop button for which the operation is valid.

  Next, the display combination search process will be described with reference to FIG. FIG. 54 is a diagram showing a flowchart of the display combination search process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 clears the display combination storing area (step S121).

  Next, the main CPU 31 designates the top address of the symbol storage area (step S122). Specifically, the main CPU 31 designates an address corresponding to the center line 8c as the head address when the gaming state is a gaming state other than the RB gaming state, and RB when the gaming state is the RB gaming state. The address corresponding to the middle special line 8f is designated as the head address.

  Next, the main CPU 31 designates the head address of the symbol combination table (see FIG. 18) (step S123). Specifically, the main CPU 31 designates an address corresponding to BB1 as the head address.

  Next, the main CPU 31 compares the symbol combination defined in the symbol combination table with the symbol combination stored in the symbol storage area (step S124).

  Next, as a result of the comparison in the process of step S124, the main CPU 31 determines whether or not the symbol combination specified in the symbol combination table matches the symbol combination stored in the symbol storage area ( Step S125). At this time, when the main CPU 31 determines that the symbol combination defined in the symbol combination table does not match the symbol combination stored in the symbol storage area, the main CPU 31 proceeds to the process of step S129, When it is determined that they match, data indicating the storage area type and the display combination is acquired from the symbol combination table (step S126).

  Next, the main CPU 31 stores the logical combination of the display combination storage area corresponding to the acquired storage area type and the data indicating the acquired display combination in the display combination storage area (step S127).

  Next, the main CPU 31 acquires the number of payouts from the symbol combination table and adds it to the payout number counter (step S128).

  When the main CPU 31 determines in the process of step S125 that the symbol combination specified in the symbol combination table does not match the symbol combination stored in the symbol storage area, or ends the process of step S128. Then, an address corresponding to the next combination in the symbol combination table is designated (step S129).

  Next, the main CPU 31 determines whether or not an end code is stored at the address designated in the process of step S129 (step S130). At this time, when the main CPU 31 determines that the end code is not stored, the main CPU 31 proceeds to the process of step S124. On the other hand, when determining that the end code is stored, the main CPU 31 then searches for all the effective lines, that is, whether or not the processes of steps S124 to S130 have been performed for all the effective lines. A determination is made (step S131).

  When the main CPU determines that all the effective lines have been searched in the process of step S131, the main CPU ends the display combination search process. On the other hand, when the main CPU determines that all the effective lines are not searched, the main CPU then designates an address corresponding to the next effective line in the symbol storage area (step S132), and the process proceeds to step S123.

  Next, RT control processing will be described with reference to FIG. FIG. 55 is a diagram showing a flowchart of the RT control process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not it is BB carryover (RT4 gaming state) (step S161). At this time, if the main CPU 31 determines that the BB is being carried over, it terminates the RT control process. On the other hand, when determining that the BB is not being carried over, the main CPU 31 determines whether or not the BB is being carried out (step S162). Specifically, it is determined whether any BB gaming state flag is on.

  When the main CPU 31 determines in step S162 that the BB is being performed, the main CPU 31 ends the RT control process. On the other hand, when determining that the BB is not in progress, the main CPU 31 refers to the RT transition table (see FIG. 15), and updates it when it is necessary to update the gaming state flag based on the display combination (step S163). ), The RT control process is terminated.

  Next, with reference to FIG. 56, the bonus end check process will be described. FIG. 56 is a diagram showing a flowchart of the bonus end check process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not BB is in progress (step S141). At this time, when the main CPU 31 determines that the BB is not in progress, the main CPU 31 turns off the SB gaming state flag (step S142) and ends the bonus end check process. On the other hand, when determining that the BB is in progress, the main CPU 31 determines whether or not the value of the bonus end number counter is “0” (step S143).

  When determining that the value of the bonus end number counter is “0”, the main CPU 31 performs a bonus end time process (step S144). Specifically, the BB gaming state flag and the RB gaming state flag that are on are turned off. Next, the main CPU 31 transmits a bonus end command (step S145), and ends the bonus end check process.

  On the other hand, when determining that the value of the bonus end number counter is not “0”, the main CPU 31 subtracts “1” from the value of the possible game number counter (step S146), and whether or not the display combination is a small combination Is determined (step S147). At this time, when the main CPU 31 determines that the display combination is not a small combination, the main CPU 31 proceeds to the process of step S149. On the other hand, when determining that the display combination is a small combination, the main CPU 31 subtracts “1” from the value of the winning possible number counter (step S148), and proceeds to the processing of step S149.

  Next, the main CPU 31 determines whether or not the value of the winning possible number counter or the value of the possible gaming number counter is “0” (step S149). At this time, when the main CPU 31 determines that neither the value of the winning possible number counter or the value of the possible gaming number counter is “0”, the main CPU 31 ends the bonus end check process. On the other hand, when the main CPU 31 determines that the value of the winning possible number counter or the value of the possible gaming number counter is “0”, the main CPU 31 then performs RB end time processing (step S150) and ends the bonus end check processing. . In the RB end process, a process such as turning off an RB gaming state flag that is turned on is performed.

  Next, the bonus operation check process will be described with reference to FIG. FIG. 57 is a diagram showing a flowchart of the bonus operation check process performed in the main control circuit 60 of the present embodiment.

  First, the main CPU 31 determines whether or not the display combination is BB (any one of BB1 to BB4) (step S171). At this time, when the main CPU 31 determines that the display combination is not BB, the main CPU 31 proceeds to the process of step S174. On the other hand, when the main CPU 31 determines that the display combination is BB, the main CPU 31 performs a bonus operation process (step S172). In this bonus operation time process, the bonus operation time table (FIG. 19) is referred to, the game state flag is turned on and a value is set in the bonus end number counter according to the game state to be operated. Next, the main CPU 31 turns off the RT4 gaming state flag, clears the carryover combination storage area (step S173), transmits a bonus start command (step S176), and ends the bonus operation check process. The bonus start command includes information indicating the type of bonus to be started.

  When the main CPU 31 determines in the process of step S171 that the display combination is not BB, the main CPU 31 then determines whether or not the display combination is SB (step S174). At this time, when the main CPU 31 determines that the display combination is not SB, the main CPU 31 proceeds to the process of step S177. On the other hand, when the main CPU 31 determines that the display combination is SB, it performs a bonus operation process (step S175). In the bonus operation time process, the bonus operation time table (FIG. 19) is referred to, and the SB game state flag is turned on. Next, the main CPU 31 transmits a bonus start command (step S176), and ends the bonus operation check process.

  When the main CPU 31 determines in the process of step S174 that the display combination is not SB, it next determines whether or not the display combination is replay (step S177). At this time, when determining that the display combination is not replay, the main CPU 31 ends the bonus operation check process. On the other hand, when determining that the display combination is replay, the main CPU 31 copies the value of the insertion number counter to the automatic insertion number counter (step S178), and ends the bonus operation check process. When a value is set in the automatic insertion number counter, in the process of step S3 in the next game, the number of medals corresponding to the value is automatically inserted (the player's medal is not reduced).

  Next, with reference to FIG. 58, an interrupt process controlled by the main CPU will be described. FIG. 58 is a diagram showing a flowchart of an interrupt process performed by the main CPU controlled by the main control circuit 60 of the present embodiment. The interrupt process under the control of the main CPU is an interrupt process that occurs every predetermined period (1.1173 milliseconds in this embodiment).

  First, the main CPU 31 interrupts the program being executed before calling the interrupt processing under the control of the main CPU, and saves the address indicating the interrupted position and the values of various registers in a predetermined area of the main RAM 33. (Step S181). This is because when the interrupt process under the control of the main CPU is completed, the address indicating the interrupted position of the saved program and the values of various registers are restored, and the program is continuously executed from the point of interruption. It is.

  Next, the main CPU 31 performs input port check processing (step S182). Specifically, the main CPU 31 checks a signal from each switch such as the maximum BET switch 13S.

  Next, the main CPU 31 performs a reel control process (step S183). Specifically, the main CPU 31 starts rotation of the reels 3L, 3C, and 3R and rotates them at a constant speed when there is a reel rotation start request in the reset interrupt process (see FIG. 49). Take control. Further, when the planned stop position is determined by determining the number of sliding frames in the reel stop control process (see FIG. 53), the main CPU 31 indicates the value of the symbol counter of the corresponding reel indicating the planned stop position. When the value becomes the same as the value, control is performed to stop the reel. For example, when the value indicating the planned stop position is “4”, the main CPU 31 performs control for stopping the corresponding reel when the value of the symbol counter becomes “4”.

  Next, the main CPU 31 performs a lamp drive control process (step S184). Next, the main CPU 31 refers to the value saved in the main RAM 33 in the process of step S181 and restores the register (step S185). When this process ends, the interrupt process under the control of the main CPU is ended, and the program interrupted by the occurrence of the interrupt process under the control of the main CPU is continuously executed.

[Operations related to sub-control circuit games]
Next, with reference to the flowcharts shown in FIGS. 59 to 79, the operation related to the game of the sub control circuit 70 will be described.

  First, the effect registration process will be described with reference to FIG. FIG. 59 is a diagram showing a flowchart of the effect registration process of the present embodiment.

  First, the sub CPU 71 sets a period of 4 ms for the effect registration process (step S310). Next, the sub CPU 71 takes out a message from the message queue (step S311). Next, the sub CPU 71 determines whether or not there is a message in the message queue (step S312). At this time, when the sub CPU 71 determines that there is no message in the message queue, the sub CPU 71 proceeds to the process of step S316. On the other hand, when the sub CPU 71 determines that there is a message in the message queue (step S314), the sub CPU 71 performs backup creation processing for creating backup data from the sub RAM 73-1 to the SRAM 73-2 (step S315).

  Next, the sub CPU 71 registers animation data (step S316). Specifically, the sub CPU 71 registers animation data based on the effect data registered in the effect content determination process. Thereby, an image is displayed on the liquid crystal display device 5. That is, the sub CPU 71 transmits an image display command to the GPU 74 based on the effect data determined in the effect content determination process.

  The GPU 74 selects appropriate image data from the image data expanded in the VRAM 75 based on the received image display command, determines the display position and size of the image data, and provides the image data in the VRAM 75. Is stored in one of the specified frame buffers. The GPU 74 performs a bank switching process for switching the display image data area and the write image data area in the frame buffer area every predetermined period (1/30 second). In the bank switching process, the GPU 74 outputs the image data written in the write image data area to the liquid crystal display device 5, replaces the display image data area with the write image data area, and sets the image data to be displayed next. Write.

  Next, the sub CPU 71 registers sound data (step S317). Specifically, the sub CPU 71 registers sound data based on the effect data registered in the effect content determination process. Thereby, a sound is output from the speakers 21L and 21R. Next, the sub CPU 71 registers LED data (step S318). Specifically, the sub CPU 71 registers LED data based on the effect data registered in the effect content determination process. As a result, the various LEDs 101 to 103 and 111 to 114 are turned on or off. When this process ends, the sub CPU 71 returns to the process of step S311.

  Next, the effect content determination process will be described with reference to FIG. FIG. 60 is a diagram showing a flowchart of effect content determination processing according to the present embodiment.

  First, the sub CPU 71 determines whether or not a start command has been received (step S351). At this time, when the sub CPU 71 determines that the start command has not been received, the sub CPU 71 proceeds to the process of step S354. On the other hand, when determining that the start command has been received, the sub CPU 71 performs a start command reception process (step S352), registers the start effect data (step S353), and ends the effect content determination process.

  Next, when the sub CPU 71 determines that a start command has not been received in the process of step S351, it then determines whether a reel stop command has been received (step S354). At this time, when the sub CPU 71 determines that the reel stop command has not been received, the sub CPU 71 proceeds to the process of step S357. On the other hand, when the sub CPU 71 determines that the reel stop command has been received, the sub CPU 71 performs a billy get challenge determination process (step S355), and registers the effect data at the time of stop according to the type of the operation stop button (step S355). S356), the effect content determination process is terminated.

  Next, when determining that the reel stop command has not been received in the process of step S354, the sub CPU 71 then determines whether or not a display command has been received (step S357). At this time, if the sub CPU 71 determines that the display command has not been received, the sub CPU 71 proceeds to the process of step S359. On the other hand, when determining that the display command has been received, the sub CPU 71 performs display command reception processing (step S358), and ends the effect content determination processing.

  Next, when the sub CPU 71 determines that a display command has not been received in the process of step S357, it then determines whether a BET command has been received (step S359). At this time, if the sub CPU 71 determines that the BET command has not been received, the sub CPU 71 proceeds to the process of step S361. On the other hand, when determining that the BET command has been received, the sub CPU 71 registers the effect data at the time of the BET according to the number of inserted sheets (step S360), and ends the effect content determination process.

  Next, when determining that the BET command has not been received in the process of step S359, the sub CPU 71 then determines whether or not a bonus start command has been received (step S361). At this time, if the sub CPU 71 determines that the bonus start command has not been received, the sub CPU 71 proceeds to the process of step S363. On the other hand, when determining that the bonus start command has been received, the sub CPU 71 registers the bonus start time effect data (step S362), and ends the effect content determination process.

  Next, when the sub CPU 71 determines in the process of step S361 that a bonus start command has not been received, the sub CPU 71 then determines whether or not a bonus end command has been received (step S363). At this time, when determining that the bonus end command has not been received, the sub CPU 71 ends the effect content determination process. On the other hand, when the sub CPU 71 determines that the bonus end command has been received, the sub CPU 71 performs a bonus end command reception process (step S364), registers bonus end time effect data (step S365), and ends the effect content determination process. Let

  Next, the start command reception process will be described with reference to FIGS. 61 and 62. FIG. FIGS. 61 and 62 are flowcharts showing the start command reception process according to the present embodiment.

  First, the sub CPU 71 determines whether or not it is in BB (BB gaming state 1 to BB gaming state 4) (step S381). At this time, if the sub CPU 71 determines that BB is in progress, it performs BB processing (step S382), and proceeds to the processing of step S400. On the other hand, when it is determined that the BB is not in progress, it is determined whether or not the BB carryover flag is on (step S383). The BB carryover flag is a flag that is turned on from the next game in which any of BB (BB1 to BB4) is internally won to the game in which the internally won BB is determined as a display combination. When the sub CPU 71 determines that the BB carryover flag is on, the sub CPU 71 proceeds to the process of step S400. When the sub CPU 71 determines that the BB carryover flag is not on, the sub CPU 71 then determines the number of navigation game state 3 addition games and lottery mode lottery. Processing is performed (step S384).

  Next, the sub CPU 71 refers to the navigation mode transition lottery table A (FIG. 29), and performs a navigation mode transition lottery based on the current navigation mode, data pointer, and the like (step S385).

The “navigation mode” includes a navigation mode 0 to a navigation mode 4. Navi means notifying the player of information that would be advantageous to the player. The period during which navigation is performed is referred to as AT (assist time), and the transition of the navigation mode from 0 to any one of 1 to 4 is referred to as AT winning (or ART winning).

  Next, the sub CPU 71 determines whether or not the game is a BB winning game (whether BB (BB1 to BB4) is won in the current game) (step S386). If it is not a BB winning game, the process proceeds to step S388. On the other hand, in the case of a BB winning game, referring to the navigation mode transition lottery table B (FIG. 30), the navigation mode transition lottery is based on the current navigation mode, bonus data pointer, presence / absence of the effect game stoppage. Is performed (step S387).

  Next, the sub CPU 71 determines whether or not the navigation mode has shifted from 0 to 1 as a result of the navigation mode transition lottery in the process of step S385 or the process of step S387 (step S388). At this time, if the navigation mode has not shifted from 0 to 1 to 4, the sub CPU 71 shifts to the process of step S392. On the other hand, if the navigation mode has shifted from 0 to 1-4, Time processing is performed (step S389), and it is determined whether the game is a BB winning game (step S390). If the sub CPU 71 is not a BB winning game, the sub CPU 71 proceeds to the process of step S400. On the other hand, in the case of a BB winning game, the navigation game state transition standby number lottery table (FIG. 32) is referred to, and the navigation game state transition standby number is determined and set in the navigation game state transition standby counter (step S391). ), The process proceeds to step S400.

  Here, the navigation game state includes a navigation game state 0 to a navigation game state 3, navigation is not performed in the navigation game state 0, and navigation is performed in the navigation game state 1 to navigation game state 3. Further, when the navigation mode shifts from 0 to 1 to 4, the navigation game state also shifts from 0 to 1 or 2. At this time, there is a case where the transition is made immediately, or there is a case where the transition is made after a predetermined number of games (navigation game state transition standby number) has elapsed.

  In the navigation game state 1 or the navigation game state 3, the value of the navigation game number counter is not subtracted, and in the navigation game state 2, the value of the navigation game number counter is subtracted. The number of remaining games in the navigation game states 1 to 3 is managed by the navigation game number counter and the navigation set number counter. Even when the navigation game number counter is changed from 1 to 0, the navigation set number counter is 1 or more. Then, 50 is set in the navigation game number counter.

  Returning to the flowchart, if the sub CPU 71 determines in step S392 that the navigation mode has not shifted from 0 to 1 to 4, then the navigation game state transition standby counter is 1 or more. Is discriminated (step S392). If the navigation game state transition standby counter is 1 or more, the sub CPU 71 performs a standby state navigation game state transition process (step S393), and proceeds to the process of step S400. On the other hand, if the navigation game state transition standby counter is not 1 or more, it is determined whether or not the navigation game state is 1 (step S394).

  In the case of the navigation game state 1, the sub CPU 71 performs a navigation game state transition process (step S395) during the navigation game state 1, and proceeds to the process of step S400. On the other hand, if it is not the navigation game state 1, it is then determined whether or not it is the navigation game state 2 (step S396). At this time, if the sub CPU 71 is in the navigation game state 2, the sub CPU 71 performs a navigation game state transition process (step S397) during the navigation game state 2 and proceeds to the process of step S400.

  On the other hand, if it is not the navigation game state 2, it is then determined whether or not it is the navigation game state 3 (step S398). At this time, in the case of the navigation game state 3, the sub CPU 71 performs a navigation game state transition process (step S399) during the navigation game state 3, and proceeds to the process of step S400. On the other hand, if it is not the navigation game state 3, the process proceeds to step S400.

  Next, the sub CPU 71 performs a billy get challenge lottery process (step S400). The billy get challenge is an event that is performed when a predetermined condition is satisfied. Specifically, the billy get challenge is executed when a billy get challenge production (an instruction to select left or right is displayed, for example, “select left or right” is displayed in the liquid crystal display area 23). In addition, until the player performs the third stop operation, the player holds his / her hand near the left selection panel 151L or the right selection panel 151R so as to be detected by the infrared sensors 120L and 120R (selection). Operation).

  At this time, when the correct answer (left, right, both) determined by the billy get challenge correct answer lottery performed in advance matches the right and left selected by the player (if both are correct, it is determined that they are the same) , Billy get challenge is successful, navigation mode will rise. Even if the player does not hold any hand, if the winning is determined by lottery when no billy get challenge is selected in advance, it is considered that the billy get challenge is successful.

  If the player holds his / her hand in a different direction from the correct answer, even if he / she wins a lottery when no billy get challenge is selected, the billy get challenge fails. In this embodiment, it is determined whether or not the selection operation has been performed before the third stop operation is performed. For example, the second stop operation is performed until the first stop operation is performed. It may be determined whether or not the selection operation has been performed until a predetermined time elapses until a predetermined time elapses.

  Furthermore, the determination as to whether or not the selection operation has been performed can be arbitrarily set, for example, after the start operation has been performed and the first stop operation has been performed. That is, the period for determining whether or not the selection operation has been performed can be an arbitrary period in one unit game (the period in which steps S1 to S18 are performed), or a plurality of units. An arbitrary period over the game (for example, from the start operation of a certain unit game to the third stop operation of the next unit game) can be used.

  Next, the sub CPU 71 determines whether or not the navigation game state is 1 to 3 and the pushing order is an internal winning combination (step S401). At this time, if the navigation game state is 1 to 3 and the pushing order is an internal winning combination, the sub CPU 71 performs navigation effect data (a navigation for establishing a role that is advantageous to the player). (Effect data to be performed) is registered (step S402), and the start command receiving process is terminated. In other cases, the start command reception process is terminated as it is.

  Next, with reference to FIG. 63, the processing during BB will be described. FIG. 63 is a diagram showing a flowchart of the BB processing in this embodiment.

  First, the sub CPU 71 determines whether or not the BB gaming state 4 is set (step S421). At this time, if the sub CPU 71 is in the BB4 gaming state, the sub CPU 71 performs lottery processing during BB4 (step S422), and ends the processing during BB. On the other hand, if not in the BB4 gaming state, the sub CPU 71 determines whether or not to change the navigation mode based on the data pointer, and updates the navigation mode according to the determination result (step S423). Specifically, if the small role / replay pointer is 28-31 (Don middle tier, per Don lower tempo, per Don upper tempo, per Don middle tempe), the navigation mode is increased by 1 (however, The navigation mode 4 is the upper limit), otherwise the navigation mode is left as it is.

  Although not shown, the sub CPU 71 registers don-matched effect data when the don symbols are aligned in the upper, middle, or lower stages. Further, in the process of step S423, the navigation mode may be increased by a plurality of stages when a specific condition is satisfied. The specific condition is, for example, that when 31 of 28 to 31 is determined as the small role / replay pointer, or when any of 28 to 31 is determined as the small role / replay pointer. For example, it is necessary to line up the line.

  Next, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table C (FIG. 36) and determines the number of navigation game state 3 addition games according to the current navigation mode and the small role / replay pointer data pointer. A lottery is performed (step S424). Next, the sub CPU 71 determines whether or not five or more games have been won by the lottery (step S425). At this time, if 5 or more games are not won (ie, 0 game), the sub CPU 71 ends the BB in-process. On the other hand, if five or more games are won, the sub CPU 71 then refers to the navigation game state 3 addition lottery mode lottery table C (FIG. 40) and responds to the current navigation mode and the small role / replay data pointer. Then, the navigation game state 3 addition lottery mode is lottery (step S426).

Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in the process of step S424 and the navigation game state 3 addition lottery mode determined in the process of step S426 with each other on the sub RAM 73-1. Is stored in the navigation game state 3 information storage area (step S427). The navigation game state 3 information storage area stores a maximum of 32 combinations of the number of navigation game state 3 addition games and the navigation game state 3 addition lottery mode. The stored information is processed by FIFO (First In, First Out). The number of navigation game state 3 addition games and the number of combinations of the navigation game state 3 addition lottery mode stored in the navigation game state 3 information storage area are displayed in the liquid crystal display area 23 so that the player can grasp them. . Next, the navigation game state 3 transition flag is turned on (step S428), and the processing during BB is ended. The navigation game state 3 transition flag is a flag indicating whether information is stored in the navigation game state 3 information storage area (ON when stored).

  Note that the number of navigation game state 3 addition games stored in the navigation game state 3 information storage area and the number of sets of the navigation game state 3 addition lottery mode may be notified only in the navigation 2 game state. Further, the number of groups stored in the navigation game state 3 information storage area may be notified as it is (that is, “5” if there are 5 groups), or the number of groups stored in the navigation game state 3 information storage area. It is good also as notifying some.

  For example, when the don-match effect data described later is registered, or when the billy get challenge success effect data described later is registered during the BB4 game state, the navigation game state 3 is always added to the navigation game state 3 information storage area. Since the number of games and the navigation game state 3 addition lottery mode are always stored, it is possible to display only the number of sets for which the effect data is registered.

  In other words, only the number of pairs for which a confirmed effect (for example, a don-matched effect or a billy get successful effect) that allows the player to recognize the acquisition of the right to move from the navigation game state 2 to the navigation game state 3 is notified. It is good as well. Further, when the number of rights to shift from the navigation game state 2 to the navigation game state 3 is 1 or more, it is preferable to notify that at least the number of rights is 1 or more.

  For example, in the case where only the number of pairs for which the above-described finalized effect has been performed is notified, the number of sets stored in the navigation game state 3 information storage area is “5”, and the finalized effect is once. If not, nothing will be notified. In such a case, at least the number of pairs stored in the navigation game state 3 information storage area is notified that it is “1” or more. Is preferred.

  Next, with reference to FIG. 64, the BB4 medium lottery process will be described. FIG. 64 is a diagram showing a flowchart of the BB4 lottery process according to the present embodiment.

  First, the sub CPU 71 refers to the billy get challenge occurrence lottery table (FIG. 45), sets the current navigation mode, presence / absence of production game stop (lock flag on / off in the main control circuit), and billy get challenge success flag. Accordingly, a lottery for generating a billy get challenge is performed (step S441). Next, the sub CPU 71 determines whether or not the lottery result is a win (step S442).

  If the sub CPU 71 is not the winner, the sub CPU 71 performs the lottery process during BB4. On the other hand, if it is a win, billy get challenge processing is performed (step S443), and then it is determined whether or not there is an effect game stop (the lock flag is on) (step S444). The sub CPU 71 performs lottery processing during BB4 when there is no stop for the game for performance. On the other hand, if there is a stop of the effect game, the sub CPU 71 registers display panel unit effect data (step S445) and performs lottery processing during BB4.

  Next, the billy get challenge process will be described with reference to FIG. FIG. 65 is a diagram showing a flowchart of the billy get challenge process of the present embodiment.

  First, the sub CPU 71 refers to the billy get challenge correct lottery table (FIG. 47), and performs a billy get challenge correct lottery according to the occurrence status of the billy get challenge and presence / absence of the game for the production (step S461). Next, the sub CPU 71 refers to the lottery table without billy get challenge selection (FIG. 48), and performs lottery without billy get challenge selection according to the result of the billy get challenge correct lottery (step S462).

  Next, the sub CPU 71 registers the billy get challenge effect described above (step S463), and ends the billy get challenge process. By registering the billy get challenge effect, the billy get challenge effect is executed immediately after the player presses the start lever 6.

  Next, with reference to FIG. 66, the number of navigation game state 3 addition games and lottery mode lottery processing will be described. FIG. 66 is a diagram showing a flowchart of the number of navigation game state 3 addition games and lottery mode lottery processing according to the present embodiment.

  First, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table A (FIG. 34), and adds the navigation game state 3 according to the current navigation mode, the small role / replay pointer, the bonus data pointer, and the like. The number of games is lottery (step S481). Next, the sub CPU 71 determines whether or not five games or more are won as the navigation game state 3 addition game number by this lottery (step S482).

  When the sub CPU 71 has not won more than 5 games, the sub CPU 71 proceeds to the processing of step S486. When the sub CPU 71 has won more than 5 games, the sub CPU 71 then refers to the navigation game state 3 addition lottery mode lottery table A (FIG. 38). Then, the navigation game state 3 addition lottery mode is lottery according to the current navigation mode (step S483).

  Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in the process of step S481 and the navigation game state 3 addition lottery mode determined in the process of step S483 with each other, so that the navigation game state 3 information Store in the storage area (step S484).

  Next, the sub CPU 71 turns on the navigation game state 3 transition flag (step S485), and proceeds to the process of step S486.

  Next, the sub CPU 71 determines whether or not the game is a BB winning game (step S486), and if it is not a BB winning game, the navigation game state 3 addition game number and lottery mode lottery processing ends. On the other hand, in the case of a BB winning game, the navigation state 3 addition game number lottery table B (FIG. 35) is referred to, and navigation is performed according to the current navigation mode, bonus data pointer, presence / absence of effect game stop. The game state 3 addition game number is lottery (step S487).

  Next, the sub CPU 71 determines whether or not five games or more are won as the number of navigation game state 3 addition games by this lottery (step S488). If the sub CPU 71 has not won more than 5 games, the navigation game state 3 added game number and lottery mode lottery processing is terminated. On the other hand, if five or more games are won, then, referring to the navigation game state 3 addition lottery mode lottery table B (FIG. 39), according to the current navigation mode, bonus data pointer, presence / absence of effect game stop Then, a lottery mode 3 addition lottery mode is lottery (step S489).

  Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in the process of step S487 and the navigation game state 3 addition lottery mode determined in the process of step S489 with each other, so that the navigation game state 3 information Store in the storage area (step S490). Next, the sub CPU 71 turns on the navigation game state 3 transition flag (step S491), and ends the navigation game state 3 addition game number and lottery mode lottery processing.

  Next, with reference to FIG. 67, the ART initial hitting process will be described. FIG. 67 is a diagram showing a flowchart of the ART initial hitting process according to the present embodiment.

  First, the sub CPU 71 refers to the navigation set number lottery table (FIG. 42) and determines the number of navigation sets (step S501). Next, the sub CPU 71 sets the number of navigation sets determined by lottery in the navigation set number counter (step S502), and sets 50 in the navigation game number counter (step S503). Next, the sub CPU 71 subtracts 1 from the navigation set number counter (step S504), and ends the ART initial hitting process.

  Next, with reference to FIG. 68, the navigation game state transition process during the standby state will be described. FIG. 68 is a diagram showing a flowchart of the waiting state navigation game state transition process according to the present embodiment.

  First, the sub CPU 71 determines whether or not the game is a BB winning game during digestion of the navigation game state transition standby counter (step S521). At this time, the sub CPU 71 clears the navigation game state transition standby counter when the BB winning game is being digested with the navigation game state transition standby counter (step S527), and shifts to the navigation game state 1 after the end of the BB. Is performed (step S528), and the waiting state navigation game state transition process is terminated.

  Although a process for shifting to the navigation game state 1 after the end of the BB is not described in detail, for example, a process for turning on the navigation game state 1 flag is performed. Although not shown, when the navigation game state 1 flag is on after the end of BB, the navigation game state 1 is shifted to. Hereinafter, in the flowchart, the same processing is performed in a portion described as “transition from next game to navigation game state 0 (or navigation game state 1, navigation game state 2, navigation game state 3)”. For example, when transitioning from the next game to the navigation game state 0, the navigation game state 0 flag is turned on in the process, and if the navigation game state 0 flag is on at the start of the next game, the navigation game state 0 is shifted. .

  On the other hand, if it is not the BB winning game being digested with the navigation game state transition standby counter, the sub CPU 71 then subtracts 1 from the navigation game state transition standby counter (step S522), and determines whether or not it has become 0 (step S522). Step S523). At this time, if it is not 0, the sub CPU 71 ends the navigation game state transition process during the standby state.

  On the other hand, if it becomes 0, it is determined whether or not it is in the RT3 gaming state (step S524). If it is not in the RT3 gaming state, a process for shifting from the next game to the navigation gaming state 1 is performed ( Step S525), the navigation game state transition process during the standby state is terminated. On the other hand, if it is in the RT3 gaming state, a process for shifting from the next game to the navigation gaming state 2 is performed (step S526), and the navigation gaming state transition process during the standby state is terminated.

  Next, the navigation game state transition process during the navigation game state 1 will be described with reference to FIG. FIG. 69 is a diagram showing a flowchart of the navigation game state transition process during the navigation game state 1 of the present embodiment.

  First, the sub CPU 71 determines whether or not the game is a BB winning game (step S541). If it is a BB winning game, the sub CPU 71 performs a process for shifting to the navigation game state 1 after the end of the BB (step S542), and ends the navigation game state transition process during the navigation game state 1.

  On the other hand, if the game is not a BB winning game, it is determined whether or not the game is an RT3 transition game (a game transitioned from another game state to the RT3 game state) (step S543). If it is RT3 transition game, the sub CPU 71 proceeds to the process of step S545. If it is not RT3 transition game, the sub CPU 71 determines whether or not a specific condition is satisfied without following the navigation (step S544). ).

The specific conditions are as follows: (i) When the SB winning in the general gaming state does not shift to the RT1 gaming state, (ii) The push order lip during the RT1 gaming state does not shift to the RT2 gaming state (Iii) in the RT1 gaming state or in the RT2 gaming state, when the transition is made to the general gaming state at the time of winning the push order bell, (iv) in the RT2 gaming state, when the transition to the RT1 gaming state is made in the SB winning state (v) This is satisfied when the transition to the RT3 gaming state is not made when the push order lip 2 is won in the RT2 gaming state.

  When the player does not follow the navigation and does not satisfy the specific condition, the sub CPU 71 ends the navigation game state transition process during the navigation game state 1, and the player satisfies the specific condition without following the navigation. In that case, the process proceeds to step S545.

  Next, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (step S545). The navigation game state 3 interruption flag is turned on when the BB is won in the navigation game state 3, and is cleared when the navigation game state 1 is shifted to the navigation game state 3 after the end of the BB.

  If the navigation game state 3 interruption flag is not on, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 2 (step S546), and ends the navigation game state transition process during the navigation game state 1 To do. On the other hand, if the navigation game state 3 interruption flag is ON, a process for shifting from the next game to the navigation game state 3 is performed (step S547), and the navigation game state transition process during the navigation game state 1 is terminated.

  Next, the navigation game state transition process during the navigation game state 2 will be described with reference to FIGS. 70 and 71. 70 and 71 are diagrams showing a flowchart of the navigation game state transition process during the navigation game state 2 of the present embodiment.

  First, the sub CPU 71 determines whether or not the game is a BB winning game (step S561). If the sub CPU 71 is a BB winning game, the sub CPU 71 performs a process for shifting to the navigation game state 1 after the end of the BB (step S562), and ends the navigation game state transition process during the navigation game state 1.

  On the other hand, if it is not the BB winning game, it is determined whether or not the BB is being carried over (step S563). If the sub CPU 71 is carrying over the BB, the navigation game state transition process during the navigation game state 1 ends. On the other hand, if the BB carryover is not in progress, it is determined whether or not the navigation game state 3 transition flag is on (step S564). If the navigation game state 3 is on, the navigation game state 3 transition process in the navigation game state 2 is performed. (Step S566), the navigation gaming state transition processing during the navigation gaming state 2 is terminated. On the other hand, if the navigation game state 3 transition flag is not on, it is then determined whether or not the navigation game state transition standby counter is 1 or more (step S565).

  If the navigation game state transition standby counter is 1 or more, the sub CPU 71 performs a navigation game state 3 transition process during the navigation game state 2 (step S566) and ends the navigation game state 2 navigation game state transition process. . On the other hand, when the navigation game state transition standby counter is not 1 or more, the navigation game number counter is decremented by 1 (step S567), and it is determined whether the navigation game number counter has become 0 (step S568).

  If the navigation game number counter is not 0, the sub CPU 71 ends the navigation game state transition process during the navigation game state 2. On the other hand, if the navigation game number counter reaches 0, it is then determined whether the navigation set number counter is 0 (step S569). If not, 50 is set in the navigation game number counter ( In step S570), 1 is subtracted from the navigation set number counter (step S571), and the navigation game state transition process in the navigation game state 2 is ended. On the other hand, when the navigation set number counter is 0, the navigation mode transition lottery table C (FIG. 41) is referred to, and the navigation mode transition lottery is performed (step S572).

  Next, the sub CPU 71 determines whether or not the transition destination navigation mode is determined to be 0 as a result of the navigation mode transition lottery (step S573). If the transition destination navigation mode is determined to be 0, the sub CPU 71 performs processing for shifting from the next game to the navigation game state 0 (step S578), and ends the navigation game state transition process during the navigation game state 2 To do.

  On the other hand, when a value other than 0 is determined as the destination navigation mode, the ART hitting process is performed (step S574). Next, the sub CPU 71 refers to the navigation game state transition standby number lottery table C (FIG. 32), lotteries the navigation game state transition standby number (step S575), and navigates the determined navigation game state transition standby number. It is set in the game state transition standby number counter (step S576).

  Next, the sub CPU 71 determines whether or not the navigation game state transition standby number counter is 0 (step S577). If the navigation game state transition standby number counter is not 0, the navigation game state 0 is started from the next game. (Step S578), and the navigation game state 2 middle game state transition process is terminated. On the other hand, if the navigation game state transition standby number counter is 0, a process for shifting from the next game to the navigation game state 2 is performed (step S579), and the navigation game state transition process during the navigation game state 2 is terminated. .

  Next, with reference to FIG. 72, the navigation game state 3 transition process in the navigation game state 2 will be described. FIG. 72 is a diagram showing a flowchart of the navigation game state 3 transition process during the navigation game state 2 of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 transition standby number counter is 0 (step S591). The navigation game state 3 transition standby number counter is a counter indicating the number of games until the navigation game state 2 shifts to the navigation game state 3. If the navigation game state 3 transition standby number counter is not 0, the sub CPU 71 decrements the navigation game state 3 transition standby number counter by 1 (step S597), and proceeds to the process of step S598. On the other hand, when the navigation game state 3 transition standby number counter is 0, it is then determined whether or not the navigation game state 3 transition flag is on when the navigation game state 2 is transitioned to (step S592).

  When the sub CPU 71 determines that the navigation game state 3 transition flag is not on when the navigation game state 2 is transitioned to, the sub CPU 71 refers to the navigation game state 3 transition standby number lottery table (FIG. 33) and determines the navigation game number counter. In accordance with the value of the game, etc., the navigation game state 3 transition standby number is lottery (step S593). Next, the sub CPU 71 sets the determined navigation gaming state 3 transition standby number in the navigation gaming state 3 transition standby number counter (step S594), and subtracts 1 from the navigation gaming state 3 transition standby number counter (step S597). The process proceeds to step S598.

  On the other hand, if the sub CPU 71 determines that the navigation game state 3 transition flag is on when the navigation game state 2 is switched to, then the sub CPU 71 was in the navigation game state 0 or 1 before the transition to the navigation game state 2 A determination is made (step S595). If the sub CPU 71 determines that the navigation game state is 0 or 1 before the transition to the navigation game state 2, the sub CPU 71 performs processing for shifting from the next game to the navigation game state 3 (step S599). 2. The middle navigation game state 3 transition process is terminated.

  On the other hand, if the sub CPU 71 determines that it was not the navigation game state 0 or 1 before the transition to the navigation game state 2, the sub CPU 71 sets 2 in the navigation game state 3 transition standby number counter (step S596). The state 3 transition standby number counter is decremented by 1 (step S597), and the process proceeds to step S598.

  In the process of step S598, the sub CPU 71 determines whether or not the navigation game state 3 transition standby number counter is 0 (step S598). When the sub CPU 71 determines that the navigation gaming state 3 transition standby number counter is not 0, the navigation gaming state 3 transition processing in the navigation gaming state 2 is terminated. On the other hand, when the sub CPU 71 determines that the navigation game state 3 transition standby number counter is 0, the sub CPU 71 performs processing for shifting from the next game to the navigation game state 3 (step S599), and the navigation game in the navigation game state 2 The state 3 transition process is terminated.

  Next, the navigation game state transition process during the navigation game state 3 will be described with reference to FIG. FIG. 73 is a diagram showing a flowchart of the navigation game state transition process during the navigation game state 3 of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 interruption flag is on (step S611). If the sub CPU 71 determines that the navigation game state 3 interruption flag is on, the number of navigation game state 3 addition games, the navigation game state 3 addition lottery mode, and the navigation game state saved in the process of step S621 described later. The continuation counter is returned (step S617), the navigation game state 3 transition flag is turned off (step S618), and the process proceeds to step S619. On the other hand, if the sub CPU 71 determines that the navigation game state 3 interruption flag is not on, then, the sub CPU 71 determines whether or not the game is a navigation game state 3 transition game (a game that has transitioned from another navigation game state to the navigation game state 3). Is determined (step S612).

  When the sub CPU 71 is not the navigation game state 3 transition game, the sub CPU 71 proceeds to the process of step S619. On the other hand, in the case of the navigation game state 3 transition game, the sub CPU 71 acquires information from the navigation game state 3 information storage area, and sets the number of navigation game state 3 addition games and the navigation game state 3 addition lottery mode ( Step S613).

  Next, the sub CPU 71 sets 1 in the navigation gaming state 3 continuation counter (step S614). The navigation game state 3 continuation counter is a counter that manages the number of continuous games in the navigation game state 3. Next, the sub CPU 71 determines whether or not the navigation game state 3 information storage area is emptied by acquiring information from the navigation game state 3 information storage area in the process of step S613 (the stored information is lost). Is determined (step S615).

  When the navigation game state 3 information storage area becomes empty, the sub CPU 71 turns off the navigation game state 3 transition flag (step S616), proceeds to the process of step S619, and displays the navigation game state 3 information storage area. If is not empty, the process proceeds to step S619.

  Next, the sub CPU 71 performs a navigation game number addition process (step S619). Next, the sub CPU 71 determines whether or not the game is a BB winning game (step S620). If it is a BB winning game, the sub CPU 71 saves the number of navigation game state 3 addition games, the navigation game state 3 addition lottery mode, and the navigation game state continuation counter (step S621), and sets the navigation game state 3 interruption flag. Turn on (step S622).

  Next, the sub CPU 71 performs processing for shifting to the navigation gaming state 1 after the end of BB (step S623), and ends the navigation gaming state transition processing during the navigation gaming state 1. On the other hand, if it is not a BB winning game, it is determined whether or not the result of the navigation game state 3 navigation game number addition lottery is non-winning (step S624). If the sub-CPU 71 is non-winning, the sub-CPU 71 performs processing for shifting from the next game to the navigation gaming state 2 (step S625), and ends the navigation gaming state transition processing during the navigation gaming state 1, while If there is, the navigation game state transition process in the navigation game state 1 is terminated as it is.

  Next, the navigation game number adding process will be described with reference to FIG. FIG. 74 is a diagram showing a flowchart of the number-of-navigation game addition processing of the present embodiment.

  First, the sub CPU 71 determines whether or not the navigation game state 3 is set (step S641). If the sub CPU 71 is not in the navigation game state 3, the sub CPU 71 ends the navigation game number addition process. On the other hand, in the case of the navigation game state 3, it is then determined whether or not the game is a BB winning game (step S642). If it is a BB winning game, the sub CPU 71 refers to the navigation game number special addition lottery table (FIG. 44) and performs a navigation game number special addition lottery according to the type of the winning BB (step S643). The determined number of navigation games is added to the navigation game number counter (step S644), and the navigation game number addition process is terminated.

  On the other hand, if it is not the BB winning game, the sub CPU 71 then determines whether or not it is the first game returned from the BB winning state in the navigation gaming state 3 (step S645). If it is the first game for return, the sub CPU 71 proceeds to the process of step S650. On the other hand, if it is not the first game returned, it is then determined whether or not the navigation game state 3 continuation counter is 1 or 2 (step S646), and if the navigation game state 3 continuation counter is 1 or 2, The process proceeds to step S650.

  On the other hand, when the navigation game state 3 continuation counter is not 1 or 2, the navigation game state 3 navigation game number addition lottery table (FIG. 43) is referred to, and the navigation game state 3 addition lottery mode, the small role / replay pointer data In accordance with the pointer, the bonus data pointer, etc., a navigation game state 3 navigation game number addition lottery is performed (step S647). Next, the sub CPU 71 determines whether or not the result of the navigation game state 3 navigation game number addition lottery is a win (step S648), and if it is a win, the process proceeds to step S650.

  On the other hand, in the case of non-winning, the navigation game state 3 addition lottery mode, the navigation game state 3 addition game number, and the navigation game state 3 continuation counter are cleared (step S649), and the navigation game number addition process is terminated.

  Next, the sub CPU 71 adds the navigation game state 3 added game number to the navigation game number counter in the process of step S650. (Step S650). Next, the sub CPU 71 determines whether or not the navigation game state 3 continuation counter is a specific value (step S651). The specific value is a value (5, 7, 10, 15, 20, 25, 30, 35, 40...) Defined in the navigation game number special addition lottery table (FIG. 44).

  When the sub CPU 71 determines that the navigation game state 3 continuation counter is not a specific value, the sub CPU 71 adds 1 to the navigation game state 3 continuation counter (step S654), and ends the navigation game number addition process. On the other hand, when the sub CPU 71 determines that the navigation game state 3 continuation counter has a specific value, the sub CPU 71 refers to the navigation game number special addition lottery table (FIG. 44), and according to the value of the navigation game state 3 continuation counter, A navigation game number special addition lottery is performed (step S652). Next, the sub CPU 71 adds the number of navigation games determined by the navigation game number special addition lottery to the navigation game number counter (step S653), adds 1 to the navigation game state 3 continuation counter (step S654), and determines the number of navigation games. The addition process is terminated.

  Next, the billy get challenge lottery process will be described with reference to FIG. FIG. 75 is a diagram showing a flowchart of the billy get challenge lottery process of the present embodiment.

  First, the sub CPU 71 determines whether or not the BB is in progress (step S671). If it is in the BB, the billy get challenge lottery process is terminated. On the other hand, if it is not in the BB, then whether or not the BB is being carried over. Is determined (step S672). If the BB carryover is in progress, the sub CPU 71 ends the billy get challenge lottery process. If not, the sub CPU 71 determines whether the navigation mode is 0 (step S673).

  When the navigation mode is not 0, the sub CPU 71 ends the billy get challenge lottery process. On the other hand, when the navigation mode is 0, the sub CPU 71 refers to the billy get challenge control counter lottery table (FIG. 46), A billy get challenge control counter lottery is performed in accordance with the combination / replay pointer, bonus data pointer, and presence / absence of the effect game stop (step S674).

  Next, the sub CPU 71 determines whether or not the result of the billy get challenge control counter lottery is a win (step S675). If it is a win, the sub CPU 71 adds 1 to the billy get challenge control counter (step S676). The process proceeds to step S677, and if it is not a win, the process proceeds to step S677. Next, the sub CPU 71 determines whether or not the billy get challenge control counter is 1 or more (step S677).

  If the billy get challenge control counter is not 1 or more, the sub CPU 71 ends the billy get challenge lottery process. If the billy get challenge control counter is 1 or more, the sub CPU 71 then determines whether the next game after the end of the specific liquid crystal effect. It is determined whether or not (step S678). The specific liquid crystal effect is a continuous effect over a plurality of games in the liquid crystal display area 23, an effect that expects a bonus or ART, and the like.

  When the sub CPU 71 determines that the game is not the next game after the end of the specific liquid crystal effect, the billy get challenge lottery process is ended. On the other hand, when it is determined that the game is the next game after the end of the specific liquid crystal effect, the billy get challenge process is performed (step S679), the billy get challenge control counter is decremented by 1 (step S680), and the billy get challenge lottery process is terminated. .

  Next, the billy get challenge determination process will be described with reference to FIG. In addition, FIG. 76 is a figure which shows the flowchart of the billy get challenge determination process of this Embodiment.

  First, the sub CPU 71 determines whether or not the billy get challenge effect has been registered in step S463 (FIG. 65) in the game (step S701). If the sub CPU 71 has not registered the billy get challenge effect, the sub CPU 71 ends the billy get challenge determination process. On the other hand, when the billy get challenge effect is registered, it is then determined whether or not it is the third stop time (step S702). If the sub CPU 71 is not in the third stop, the billy get challenge determination process is terminated.

  On the other hand, if it is the third stop time, it is determined whether or not the billy get challenge is successful (step S703). Specifically, the sub CPU 71 determines whether the player's selection operation has been performed by the infrared sensors 120L and 120R before the third stop, and when the selection operation is performed, the billy get challenge correct lottery ( It is determined whether the correct answer determined in step S461) in FIG.

  If they match, it is determined that the billy get challenge has succeeded, and if they do not match, it is determined that the billy get challenge has failed. If the selection operation has not been performed before the third stop, the sub CPU 71 determines that the result of the lottery when no billy get challenge is selected (step S462 in FIG. 65) is a win. If it is determined that the challenge is successful, and if it is not winning, it is determined that the billy get challenge has failed. Although not shown, in the case where the billy get challenge is successful, the sub CPU 71 registers billy get challenge success effect data indicating that the billy get challenge is successful, and notifies the player to that effect.

  When the sub CPU 71 determines that the billy get challenge is not successful (failure), the sub CPU 71 ends the billy get challenge determination process. On the other hand, if it is determined that the billy get challenge is successful, it is then determined whether or not BB4 is in progress (step S704). When the sub-CPU 71 is not in BB4, the navigation mode is increased by one step (step S705), and the navigation game state transition process (step S706) and the ART initial hit process (step S707) are performed to determine the billy get challenge. End the process.

  On the other hand, if it is during BB4, the sub CPU 71 turns on the billy get challenge success flag (step S708) and increases the navigation mode by one step (step S709). At this time, the sub CPU 71 determines whether or not the navigation mode has shifted from 0 to 1 (step S710). When the sub CPU 71 determines that the navigation mode has shifted from 0 to 1 to 4, it performs ART initial hit processing (step S711), and shifts to the processing of step S712, while the navigation mode is shifted from 0 to 1-4. If it is determined that the process has not shifted to step S712, the process proceeds to step S712.

  Next, the sub CPU 71 refers to the navigation game state 3 addition game number lottery table D (FIG. 37) and lots the navigation game state 3 addition game number (step S712). Next, the sub CPU 71 determines whether or not the lottery result is a win (a value other than 0 is determined as the number of games added in the navigation game state 3) (step S713). If the sub CPU 71 is not the winner, the billy get challenge determination process ends.

  On the other hand, in the case of winning, the navigation game state 3 addition lottery mode lottery table D (FIG. 41) is referred to, and the navigation game state 3 addition lottery mode lottery is determined according to the current navigation mode (step S714). Next, the sub CPU 71 associates the number of navigation game state 3 addition games won in step S712 with the navigation game state 3 addition lottery mode determined in step S714 on the sub RAM 73-1. The navigation game state 3 information is stored in the information storage area (step S715). Next, the sub CPU 71 turns on the navigation game state 3 transition flag (step S716) and ends the billy get challenge determination process.

  Next, the navigation game state transition process will be described with reference to FIG. FIG. 77 is a diagram showing a flowchart of the navigation game state transition process of the present embodiment.

  First, the sub CPU 71 determines whether or not it is in the RT3 gaming state (step S731). If the sub CPU 71 is in the RT3 gaming state, the sub CPU 71 performs processing for shifting from the next game to the navigation gaming state 2 (step S732), and ends the navigation gaming state transition processing. On the other hand, if the sub CPU 71 is not in the RT3 gaming state, the sub CPU 71 performs processing for shifting from the next game to the navigation gaming state 1 (step S733), and ends the navigation gaming state transition processing.

  Next, display command reception processing will be described with reference to FIG. FIG. 78 is a diagram showing a flowchart of processing at the time of display command reception according to the present embodiment.

  First, the sub CPU 71 determines whether or not the game is a BB winning game (step S751). If the display combination is BB winning game, the sub CPU 71 then determines whether or not the display combination is BB (internal winning BB) (step S752). If the display combination is BB, the display command On the other hand, if the display combination is not BB, the BB carryover flag is turned on (step S753), and the display command reception process ends.

  On the other hand, if it is not a BB winning game, the sub CPU 71 determines whether or not the BB carryover flag is on (step S754). If the BB carryover flag is not on, the sub CPU 71 terminates the display command reception process, and if the BB carryover flag is on, then the display combination is BB (BB being carried over). It is determined whether or not. (Step S755). At this time, if the display combination is not BB, the sub CPU 71 ends the display command reception process, and if the display combination is BB, the sub-CPU 71 turns off the BB carryover flag (step S756), and displays the display command. The process at the time of reception ends.

  Next, with reference to FIG. 79, a bonus end command reception process will be described. FIG. 79 is a diagram showing a flowchart of the bonus end command reception process according to the present embodiment.

  First, the sub CPU 71 determines whether or not it is at the end of the BB4 gaming state (step S771). If it is not at the end of the BB4 gaming state, the sub CPU 71 shifts to the processing of step S774. On the other hand, if it is at the end of the BB4 gaming state, it is then determined whether or not the billy get challenge success flag is on (step S772). At this time, if the billy get challenge success flag is not on, the sub CPU 71 proceeds to the process of step S774. On the other hand, if the billy get challenge success flag is on, the billy get challenge success flag is turned off (step S773), and the process proceeds to step S774.

  Next, the sub CPU 71 determines whether or not it is at the end of any BB gaming state (step S774). When the sub CPU 71 determines that it is not at the end of the BB gaming state, it ends the bonus end command reception process. On the other hand, when the sub CPU 71 determines that it is the end of the BB gaming state, it then determines whether the navigation mode is any one of 1 to 4 (step S775). If the navigation mode is not any of 1 to 4, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 0 (step S779), and ends the process at the time of receiving the bonus end command. On the other hand, when the navigation mode is any one of 1 to 4, the sub CPU 71 then determines whether or not it is a lottery transition in the BB winning game (step S776).

  If it is not a lottery transition in the BB winning game, the sub CPU 71 performs a process for shifting from the next game to the navigation game state 1 (step S780), and ends the process at the time of receiving the bonus end command. On the other hand, if it is a lottery transition in the BB winning game, the sub CPU 71 then determines whether the navigation mode transition lottery in the BB gaming state has been won (step S777). When the sub CPU 71 determines that the navigation mode transition lottery is won in the BB gaming state, the sub CPU 71 performs processing for shifting from the next game to the navigation gaming state 1 (step S780), and performs a bonus end command reception processing. finish.

  On the other hand, when determining that the navigation mode transition lottery in the BB gaming state has not been won, the sub CPU 71 refers to the navigation gaming state transition standby number lottery table B (FIG. 32) and waits for the navigation gaming state transition. The number is lottery and set in the navigation game state transition standby counter (step S778), and then a process for shifting from the next game to the navigation game state 0 is performed (step S779), and the process at the time of receiving the bonus end command is terminated. .

  The navigation mode transition lottery may be performed at the end of the BB gaming state. At this time, lottery may be performed according to the game content in the BB game state to be ended. For example, if JAC 1-7 (small role / replay pointers “25” to “31”) have never won during BB gaming states 1 to 3, the navigation mode is increased by 1 with a high probability. A lottery may be performed. In addition, when the billy get challenge in the BB gaming state is failed a specific number of times, lottery may be performed so that the navigation mode is increased by 1 with high probability.

  Next, with reference to FIG. 80, the display panel unit effect executed when the display panel unit effect data is registered in step S445 of the BB4 lottery process (FIG. 64) will be described.

  When the display panel unit effect data is registered, the sub CPU 71 changes the luminance of the LEDs 111 to 114 corresponding to the display panels 110Pa to 110Pd according to the time series shown in FIG. In this case, it appears to the player that the character is slowly approaching from the back at first, and then the front display panel 110Pa blinks at high speed with the light extinction period in between. Thereby, a player's expectation can be improved.

[Game machine management system]
Next, an error information history transmission system using the gaming machine 1 of the present embodiment will be described. The error information history transmission system is a system that stores various errors generated in the gaming machine 1 as error information, transmits the error information history to a remote server by using a mobile terminal, and analyzes the cause of the error. .

  As shown in FIG. 81, the error information history transmission system includes a gaming machine 1, a mobile communication terminal with a camera 400 (hereinafter referred to as “mobile terminal”) as a mobile terminal possessed by a staff member, and a data management server as a server. 500 and an analysis PC 600 as analysis means. In the example of FIG. 81, for convenience of explanation, one mobile terminal 400 is shown, but in reality, the data management server 500 can be accessed from many mobile terminals 400.

  For example, the data management server 500 manages not only error information but also information related to game records. The portable terminal 400 and the data management server 500 can transmit and receive data to and from each other via the network NW using, for example, TCP / IP as a communication protocol. The network NW is constructed by, for example, the Internet, a dedicated communication line (for example, a CATV (Community Antenna Television) line), a mobile communication network (including a base station), a gateway, and the like. Note that the gaming machine 1 is not connected to the network NW.

  Note that the portable terminal 400, the data management server 500, and the analysis PC 600 are each provided with a control unit, a storage unit, a display unit, a communication unit, and the like, although not particularly illustrated. Further, the data management server 500 and the analysis PC 600 are preferably installed in an area 700 separated from the installation location of the gaming machine 1 such as a manufacturer of the gaming machine 1 or a system management company.

  The sub CPU 71 of the gaming machine 1 displays the two-dimensional code 300 on the liquid crystal display area 23 so that the staff (portable terminal 400) accesses the data management server 500 when providing the service by the error information history transmission system. Specifically, as shown in FIG. 83, the clerk displays the error information history in the liquid crystal display area 23 and selects, for example, a predetermined item such as a COM error alarm (COM ERR ALM) 23b which is a communication error alarm. As a result, the two-dimensional code 300 is displayed.

  The control unit of the portable terminal 400 reads the displayed two-dimensional code 300 with the camera 401 of the portable terminal 400, analyzes the two-dimensional code 300 with the dedicated software of the portable terminal 400, for example, the domain in the code, the communication error log, etc. And the data management server 500 is accessed according to the domain included in the two-dimensional code 300, and the information included in the two-dimensional code 300 is transmitted as output transmission data.

  On the other hand, the control unit of the data management server 500 stores the communication error information included in the received transmission data in the storage unit.

  The control unit of the data management server 500 accumulates communication error information included in the output transmission data in an error information database DB (database) (not shown), and transmits the communication error information to the analysis PC 600. In addition, the control unit of the data management server 500 generates display data (for example, a web page) that allows the mobile terminal 400 to display the error content indicated by the received communication error information and the like. To reply (in the figure, one-dot chain line arrow). And the control part of the portable terminal 400 displays the screen 402 which shows the error content etc. on a display means based on the received display data. The clerk can confirm the error content from the screen 402.

  Further, the analysis PC 600 that has received the communication error information analyzes the cause of the communication error based on the communication error information and various information stored in the error information database DB. The cause of the communication error analyzed by the analysis PC 600 is that the game machine 1 manufacturer or system management company where the analysis PC 600 is installed improves the program or structure of the game machine 1 or installs the game machine 1. It will be used as appropriate, such as improved management in the halls.

  Next, the gaming machine 1 when the staff uses the error information history transmission service will be described. The sub CPU 71 of the gaming machine 1 employs two types of operation methods, a normal operation by a staff member and a simple operation, in order to display the error information history shown in FIG. 83 on the liquid crystal display device 5. When executing the normal operation, the clerk turns the door key 2 to the right to release the lock mechanism of the front door 1b, turns on the setting key to turn on the setting key switch 20S, and enters the liquid crystal display area 23. A menu screen shown in FIG. 82 is displayed.

  Then, when the clerk operates the operation key and selects the “error information history” item 23 a, the error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23. On the other hand, when executing a simple operation, the attendant resets the error by rotating the door key 2 counterclockwise when an error occurs or not playing, and holds the state for a predetermined time, for example, 5 seconds or more. As a result, the error information history screen shown in FIG. 83 is displayed in the liquid crystal display area 23.

  When the sub CPU 71 detects an operation of selecting the “error information history” item 23a using the selection button 24 and the determination button 25, the sub CPU 71 displays the error information history in the liquid crystal display area 23 as shown in FIG. . Further, when the sub CPU 71 detects an operation of selecting the “COM error alarm” item 23b by using the selection button 24 and the decision button 25, the sub CPU 71 generates transmission information based on the error information history, and FIG. As shown, the two-dimensional code 300 based on the transmission information is displayed on the right side of the “COM error alarm” item 23b.

  The sub CPU 71 does not display a COM error alarm when a communication error occurs once, and only when a communication error occurs again within 30 minutes after the first communication error occurs. Is displayed. For this reason, the sub CPU 71 includes a COM error timer for measuring an interval at which a communication error occurs. The COM error timer performs measurement based on the time measurement of the built-in RTC 70a or the time measurement by the function provided by the OS.

  In the present embodiment, the sub CPU 71 generates the two-dimensional code 300 only when a communication error occurs. For this reason, if a communication error occurs accidentally during, for example, a normal game, the data that is loaded as error information on the two-dimensional code 300 is communicated during normal processing as shown in FIG. 86 (a). An error occurs, and normal processing is executed again immediately after that. Here, the numerical value in FIG. 85 is the number of characters of data, 1-character data indicates the command type, and 2-character data indicates the parameter for the immediately preceding command.

  In addition, when a communication error has occurred due to the goto action and the setting has been changed in the gaming machine 1, the data placed as error information in the two-dimensional code 300 is a communication error as shown in FIG. 86 (b). The settings are changed immediately after the occurrence. Furthermore, when a communication error occurs and continuous transmission is performed by lever operation, the data that is placed as error information on the two-dimensional code 300 is the command type immediately after the occurrence of the communication error, as shown in FIG. 86 (c). A certain lever operation and a parameterized winning combination are continuous.

  In the communication log collection ring buffer area 73e-1 shown in FIG. 87 and the communication error storage area 73f-1 shown in FIG. 88, the command is made up of one character data and the parameter is made up of two character data.

  FIG. 89 shows that when the data in the sub-RAM 73-1 of the sub-control circuit 70 is destroyed, the sub-control circuit 70 has a thumb abnormality in the RAM data over almost the entire liquid crystal display area 23 of the gaming machine 1. An example of notifying that it cannot continue is shown. For example, when some or all of the data related to the command, effect data information, game state information, internal winning combination information, display combination information, various counters and various flags received from the main control circuit 60 are deleted, A notification that “RAM data abnormal game cannot be continued. Please change the setting” is given to the portion of the liquid crystal display area 23 of the gaming machine 1 excluding the symbol display areas 4L, 4C, 4R. By performing such notification, it can be expected to suppress goto action.

  Next, the operation of the error information history transmission system described above will be described with reference to the flowcharts shown in FIGS. First, the main board communication reception interrupt process in the sub control circuit 70 will be described with reference to FIG. FIG. 90 is a diagram showing a flowchart of main board communication reception interrupt processing in the sub-control circuit 70 of the present embodiment. The main board communication reception interrupt process program in the sub control circuit 70 is executed by the sub CPU 71 as an interrupt process when transmission data is transmitted from the main control circuit 60 to the sub control circuit 70.

  The sub CPU 71 acquires received data from the received data register of the I / O port interposed between the main CPU 31 (step S800). In addition, the sub CPU 71 acquires reception status data from the reception status register of the I / O port (step S801). Further, the sub CPU 71 registers the reception data and the reception status data related to the reception data in each queue buffer (step S802), and ends the main board communication reception interrupt process.

  The sub CPU 71 processes the received data of 1 byte by executing the main board communication reception interrupt process of steps S800 to S802 described above once. In the present embodiment, one command is composed of 8-byte data. Therefore, the sub CPU 71 completes processing of one command by executing serial data communication by processing steps S800 to S802 continuously eight times.

  Next, the main board communication process of the sub CPU 71 will be described with reference to FIG. FIG. 91 is a diagram showing a flowchart of the main board communication processing of the sub CPU 71 of the present embodiment.

  In response to the scheduling function of the OS, the sub CPU 71 sets a cycle so that the main board communication processing program of the sub CPU 71 is executed at a cycle of 2 ms (step S808). Thereby, this task is repeated at a cycle of 2 ms including the processing time. For this reason, the sub CPU 71 waits for a cycle of 2 ms (step S809), and waits for the remaining time of 2 ms when the flowchart is repeated.

  Note that the cycle of this task process is not limited to 2 ms, and may be executed between 2 ms and 4 ms. In addition, the main board communication processing program of the sub CPU 71 is not limited to one executed every predetermined time. For example, when a predetermined condition is satisfied regardless of the time interval, without setting the cycle and waiting for the cycle. It may be executed.

  Next, the sub CPU 71 acquires the reception data from the queue in which the reception data is registered in step S802 (step S810). The sub CPU 71 determines whether there is received data in the queue (step S811). If the sub CPU 71 determines that there is no received data in the queue, it acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines that there is received data in the queue, it determines whether a physical layer error has occurred in the received data (step S812). If the sub CPU 71 determines that no physical layer error has occurred in the received data, the sub CPU 71 checks and acquires the numerical range of the received command (step S813). In the present embodiment, the numerical range of the received command is 01H to 10H as shown in FIG. Then, the sub CPU 71 determines whether or not the numerical value of the received command is within an appropriate range (step S814).

  When the sub CPU 71 determines that the numerical value of the command is within the proper range, the BCC check process is performed on the received data (step S815). Here, since one command is composed of 8-byte data, the sub CPU 71 sequentially XORs the data of the first byte to the seventh byte of each command, and sets the result in advance as a correct result. The check process is performed by comparing with the 8th byte data.

  Then, the sub CPU 71 determines whether or not the result of the BCC check process is normal (step S816). When the sub CPU 71 determines that the result of the BCC check process is normal, the command type is extracted (step S817).

  Then, the sub CPU 71 determines whether or not the extracted command is a no-operation command (step S818). If the sub CPU 71 determines that the extracted command is a no-operation command, the sub CPU 71 acquires the received data from the queue again (step S810).

  If the sub CPU 71 determines that the extracted command is not a no-operation command, the sub CPU 71 executes a received data log saving process to be described later (step S819). Further, the sub CPU 71 executes a received command check process to be described later (step S820).

  Then, the sub CPU 71 determines whether or not the command received this time is different from the command received last time (immediately before) (step S821). If the sub CPU 71 determines that the command received this time is not different from the command received immediately before, that is, it is the same, it waits for a period of 2 ms (step S809) and acquires the received data from the queue again (step S809). S810).

  If the sub CPU 71 determines that the command received this time is different from the command received immediately before, the sub CPU 71 registers the command received this time in the message queue (step S822). Then, the sub CPU 71 performs a sum check on the sub control game data sum value area 73b-1 (step S823).

  Further, the sub CPU 71 determines whether or not the game data is normal as a result of the sum check (step S824). If the sub CPU 71 determines that the game data is normal, the sub CPU 71 waits for a period of 2 ms (step S809), and acquires the received data from the queue again (step S810).

  When the sub CPU 71 determines that the game data is abnormal, the error information registration unit 71d registers the occurrence of the data destruction error in the error information history storage area 73d-1 (step S825). Then, the sub CPU 71 waits for a period of 2 ms (step S809), and obtains received data from the queue again (step S810).

  The sub CPU 71 determines that a physical layer error has occurred in the received data in step S812, determines that the command is not within the proper range in step S814, or determines that the result of the BCC check process is normal in step S816. If not, it is determined that a communication error has occurred, and a COM error check process described later is executed (step S826). Then, the sub CPU 71 waits for a period of 2 ms (step S809), and obtains received data from the queue again (step S810).

  Next, the received data log saving process in step S819 will be described with reference to FIG. FIG. 92 is a diagram showing a flowchart of main board communication reception data log storage processing performed in the sub control circuit 70 of the present embodiment. The main board communication reception data log storage process is mainly executed by the reception data log storage means 71e of the sub CPU 71.

  When the main board communication received data log saving process is executed, the sub CPU 71 executes a main board communication received data log temporary area saving process described later (step S830). The main board communication reception data log temporary area saving process uses the communication log collection ring buffer area 73e-1 shown in FIG. 87, and saves all communication logs regardless of whether or not an error has occurred. ing.

  Subsequently, the sub CPU 71 executes main board communication error history data storage processing to be described later (step S831). The main board communication error history data storage process uses a communication error storage area shown in FIG. 88 and is a process for storing a related communication log when a communication error occurs. Thereafter, the sub CPU 71 ends the main board communication reception data log saving process.

  Next, with reference to FIG. 93, the main board communication received data log temporary area storing process in step S830 will be described. FIG. 93 is a diagram showing a flowchart of main board communication reception data log temporary area storage processing performed in the sub-control circuit 70 of the present embodiment.

  When the main board communication reception data log temporary area saving process is executed, the sub CPU 71 acquires the communication log data buffer index of the communication log collection ring buffer area 73e-1 (step S840). The number of buffers here is set as appropriate.

  Then, the sub CPU 71 calculates the communication log data buffer storage position of the communication log collection ring buffer area 73e-1 (step S841). Here, the sub CPU 71 calculates the storage position in the communication log collection ring buffer area 73e-1 from the value of the buffer index.

  Further, the sub CPU 71 stores the received data in the communication log collection ring buffer area 73e-1 (step S842). In the present embodiment, as shown in FIG. 87, a maximum of 256 sets of numerical values in which a command and a parameter corresponding to each command are consecutive are stored. Then, the sub CPU 71 updates the communication log data buffer index (step S843). Here, the sub CPU 71 adds one buffer index storing the received data.

  Then, the sub CPU 71 determines whether or not the value of the buffer index is an upper limit value (step S844). If the sub CPU 71 determines that the value of the buffer index is the upper limit value, the sub CPU 71 returns the communication log data buffer index to the first one (step S845), and causes this buffer to function as a ring buffer. Thereafter, the sub CPU 71 ends the main board communication reception data log temporary area saving process. If the sub CPU 71 determines that the value of the buffer index is not the upper limit value, the sub-CPU 71 ends the main board communication reception data log temporary area saving process as it is.

  Next, the main board communication error history data storage process in step S831 will be described with reference to FIG. FIG. 94 is a diagram showing a flowchart of main board communication error history data storage processing performed in the sub-control circuit 70 of the present embodiment.

  When the main board communication error history data storage process is executed, the sub CPU 71 acquires the storage buffer selection index of the communication error storage area 73f-1 (step S850). Then, the sub CPU 71 selects a communication error storage buffer based on the storage buffer selection index (step S851).

  Here, the sub CPU 71 determines whether or not a communication error (COM error) has occurred (step S852). If the sub CPU 71 determines that a COM error has occurred, the received data log storage unit 71e stores a communication log related to the communication error in the communication error storage area 73f-1 selected in step S851 (step S853). ). Then, the sub CPU 71 updates the selected buffer index (step S854). Thereafter, the sub CPU 71 ends the main board communication error history data storage process.

  If the sub CPU 71 determines that no COM error has occurred, the sub CPU 71 acquires the selected buffer index (step S855). Then, the sub CPU 71 determines whether or not reception data is being collected (step S856). If the sub CPU 71 determines that the received data is not being collected, the main CPU communication error history data storage process is terminated.

  If the sub CPU 71 determines that the received data is being collected, the sub CPU 71 determines whether or not the value of the buffer index is the upper limit value (step S857). In this embodiment, the value of the buffer index is 0 to 255, and the upper limit value is 255. When determining that the buffer index value is not the upper limit value, the sub CPU 71 stores the received data in the communication error storage buffer selected in step S851 (step S858). Then, the sub CPU 71 updates the selected buffer index (step S859). Thereafter, the sub CPU 71 ends the main board communication error history data storage process.

  If the sub CPU 71 determines that the buffer index value is the upper limit value, the sub CPU 71 obtains a storage buffer selection index (step S860). Then, the sub CPU 71 determines whether or not the value of the storage buffer selection index is an upper limit value (step S861). In the present embodiment, the upper limit value of the storage buffer selection index is 1024.

  When the sub CPU 71 determines that the value of the storage buffer selection index is not the upper limit value (step S861), the sub CPU 71 updates the storage buffer selection index (step S862). Here, the sub CPU 71 adds one storage buffer selection index. Thereafter, the sub CPU 71 ends the main board communication error history data storage process. When the sub CPU 71 determines that the value of the buffer selection index is the upper limit value (step S861), the main board communication error history data storage process is terminated.

  Next, the main board communication reception command check process in step S820 will be described with reference to FIG. FIG. 95 is a flowchart of the main board communication reception command check process performed by the sub control circuit 70 of the present embodiment.

  When the main board communication reception command check process is executed, the sub CPU 71 obtains reception data (step S870). Then, the sub CPU 71 sets a received command check table (step S871). Further, the sub CPU 71 acquires the previous (preceding time) received data (step S872).

  Then, the sub CPU 71 sets a command check counter (step S873). Further, the sub CPU 71 acquires confirmation data from the reception protocol confirmation data table (step S874). That is, here, the table of the received command and the previous received command shown in FIG. 85 is acquired.

Next, the sub CPU 71 checks the table of the received command and the previous received command acquired in step S874, and determines whether or not the procedure is a normal procedure performed in a normal game (step S875). For example, in the table shown in FIG. 85, when the reception command shown in 03H of Data is “game medal insertion”, if the previous reception command is a demo display, game medal insertion, payout end, bonus start or error, the procedure is Judge that the order is normal. If the sub CPU 71 determines that the received command is a command in the normal order, the sub-CPU 71 ends the main board communication received command check process.

If the sub CPU 71 determines that the received command is not a command in the normal order, for example, in the table shown in FIG. 85, the received command shown in Data 07H is “winning operation”.
In this case, if the previous reception command is not a reel stop but a winning operation, it is determined that the procedure is not performed in a normal game, and the reception command check table is updated (step S876). Then, the sub CPU 71 subtracts the command check counter (step S877).

  Further, the sub CPU 71 determines whether or not the command check has ended (step S878). Here, for example, the sub CPU 71 determines that the command check has been completed when the command check counter is equal to or less than a threshold value such as 0.

  If the sub CPU 71 determines that the command check has not ended, the sub CPU 71 obtains confirmation data from the reception protocol confirmation data table again (step S874). If the sub CPU 71 determines that the command check has ended, the error information registration unit 71d registers the occurrence of an abnormal procedure error (sequence error) in the error information history storage area 73d-1 (step S879). Thereafter, the sub CPU 71 ends the main board communication reception command check process.

  Next, the COM error check process in step S826 will be described with reference to FIG. FIG. 96 is a diagram showing a flowchart of the COM error check process performed in the sub control circuit 70 of the present embodiment.

  When the COM error check process is executed, the sub CPU 71 executes a received data log storage process (step S880). The procedure of this received data log saving process is as shown in the flowchart of the main board communication received data log saving process shown in FIG. In this case, it is determined in step S852 shown in FIG. 94 that a COM error has occurred, and the received data log storage unit 71e stores a communication log related to the communication error in the communication error storage area 73f-1 (step S853). ).

  Then, the sub CPU 71 determines whether or not the COM error timer is being counted (step S881). If the sub CPU 71 determines that the COM error timer is counting, it determines whether the COM error timer is within 30 minutes (step S882).

  When the sub CPU 71 determines that the COM error timer is within 30 minutes, the error information registration unit 71d registers the occurrence of a communication error (COM error) in the error information history storage area 73d-1 (step S883). Then, the sub CPU 71 sets the count stop of the COM error timer (step S884), and ends the COM error check process.

  If the sub CPU 71 determines that the COM error timer is not being counted, or if the COM error timer is determined not to be within 30 minutes, the sub CPU 71 sets the count start of the COM error timer (step S885), and the COM error End the check process.

  As described above, the gaming machine management system according to the present embodiment acquires the error information from the two-dimensional code 300 received by the server 500 and analyzes the analysis PC 600 that analyzes the cause of the error based on the error information. I have. Therefore, in the gaming machine 1 as in the prior art, it is not limited to simply specifying the content of the communication error, but the cause of the error can be analyzed and specified from the error information using the separately installed analysis PC 600. The cause of the obtained error can be used for the subsequent improvement of the gaming machine 1 or the like.

  Further, in the gaming machine 1 of the present embodiment, only when the occurrence of a communication error is detected by the sub CPU 71, the communication error information related to the communication error is converted into the two-dimensional code 300. Therefore, the two-dimensional code is more than necessary. Control can be simplified compared with the case of creating.

  Further, in the gaming machine 1 of the present embodiment, the error information history can be displayed on the liquid crystal display device 5 by operating the door key 2, so that the clerk displays the error information history without operating the setting key of the gaming machine 1. It becomes possible to confirm. For this reason, since the clerk can display the error information history of the gaming machine 1 even during business hours, the cause of the error can be more effectively promoted.

  Moreover, in the gaming machine 1 of the present embodiment, the attendant displays the error information history by rotating the door key 2 in the counterclockwise direction and holding the state where the error of the gaming machine 1 is reset for a certain period of time. It has become. For this reason, if it is a clerk who has the door key 2, the error information history can be displayed easily, and usually the clerk who has the door key 2 is more than the clerk who has the setting key, thereby improving convenience. be able to.

  Further, in the gaming machine 1 of the present embodiment, when the occurrence of a communication error is detected, the sub CPU 71 uses the sub RAM 73 as error information that indicates that a communication error has occurred, its occurrence time, and its release time. -1 is sequentially stored. Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when there is an information disclosure request by operating the door key 2. For this reason, it is possible to confirm the unauthorized release of the communication error notification in the gaming machine 1 and to confirm the occurrence time and the release time of the communication error notification later.

  Further, in the gaming machine 1 of the present embodiment, the sub CPU 71 detects that the procedure detecting means 71b detects a procedure that cannot occur in a normal game, that is, that the game has progressed in an abnormal procedure. The occurrence of an abnormal procedure and the procedure missed in the normal procedure are sequentially stored in the sub-RAM 73-1 as error information. Further, the sub CPU 71 creates an error information history from the stored error information, and causes the liquid crystal display device 5 to display the error information history when there is an information disclosure request by operating the door key 2.

  For example, FIG. 83 shows an example of the error information history in the liquid crystal display area 23. For example, no. In the error content “BLS123PE” shown in FIG. 7, the procedure of “L” and “S” indicating the start of rotation of the reel by the operation of the lever is usually followed by the procedure of “B” indicating insertion of a medal or the like, reel 1 The game ends after the procedure “1” indicating the stop of the reel 2, the procedure “2” indicating the stop of the reel 2, the procedure “3” indicating the stop of the reel 3, and the procedure “P” of the payment.

  However, the numeral “1” is circled to indicate that the procedure for stopping the reel 1 has been missed. Therefore, compared to the case where an abnormal procedure occurs as in the past, the procedure returns to the demo screen, the procedure that could not occur in normal games occurred, the number of steps that were missed, the number of occurrences, the presence or absence of continuous occurrence, etc. Since it can be confirmed, the occurrence of goto can be one of the judgment materials. In addition to enclosing a circle, the procedure that has been missed can be clearly expressed by distinguishing it by the color of the character itself, making the font different, or making the character line thicker.

  Further, in the gaming machine 1 according to the present embodiment, the sub CPU 71-1 uses the sub RAM 73-1 as error information that the data destruction has occurred when the data destruction of the sub RAM 73-1 is detected by the data destruction detection means 71c. Are sequentially stored (step S825). Further, the sub CPU 71 reads the error information history from the error information history storage area 73 d-1 and displays it on the liquid crystal display device 5 when there is an information disclosure request by operating the door key 2.

  For this reason, according to this gaming machine 1, it becomes possible to detect the data destruction of the sub RAM 73-1 during the game, and thus it is possible to suppress the occurrence of the goto by immediately informing the error against the data destruction. As the error notification, for example, as shown in FIG. 89, when the data in the sub RAM 73-1 of the sub control circuit 70 is destroyed, a fatal error is detected on almost the entire surface of the liquid crystal display area 23 of the gaming machine 1. This indicates that the game cannot be continued because of an abnormality in the RAM data. Thereby, the RAM destruction action by a goto action can be suppressed. Such notification is canceled by a setting change such as power-off.

  Further, in the gaming machine of the present embodiment described above, the case where the gaming machine 1 is a pachislot machine has been described. However, the gaming machine according to the present invention is not limited to this, and can be applied to, for example, a pachinko machine having a symbol variation display device as described later. Further, in the gaming machine of the present embodiment described above, the two-dimensional code 300 has been described as including only communication error history data. However, the gaming machine according to the present invention is not limited to this, and may include, for example, an error information history or a player's game record.

  As described above, the gaming machine according to the present embodiment can check the date and content of the occurrence of an error when a communication error occurs between the sub-control circuit and the scaler device. This is useful for managing machines and gaming machines.

[Sub CPU]
Next, the power-on process of the sub CPU 71 will be described with reference to FIG. FIG. 99 is a flowchart of the power-on process of the sub CPU 71.

  The power-on process of the sub CPU 71 is an initialization process in the OS. When the power of the sub CPU 71 is turned on, a sub CPU initial setting process is performed to initialize the CPU and internal devices and peripheral ICs. It is executed (step S910). Next, the sub CPU 71 executes mother task activation request processing, which will be described later with reference to FIG. 101, for various task activation requests (step S911). Then, the sub CPU 71 executes a sub RAM management process described later based on FIG.

  Further, a power interruption detection circuit is provided in the sub control circuit 70. (Not shown). When the power interruption detection circuit detects a voltage drop, for example, a voltage drop to 4.5 V, it outputs a power interruption detection signal. The sub CPU 71 executes the power supply interrupt process shown in FIG. 100 in response to an interrupt input from the external interrupt port (NMI).

  Unlike the main control, the sub CPU 71 does not calculate the sum value in the power interruption process. The calculation of the sum value by the sub CPU 71 is performed every time a valid command is received, when the effect mode is changed, or the like.

  The mother task request process shown in FIG. 101 is a process of requesting the OS to start a task necessary for the function of the gaming machine 1. First, the sub CPU 71 issues a main task activation request (step S1001). Next, as an activation request for a subtask, an accessory control task activation request is made (step S1002), a lamp control task activation request is made (step S1003), a sound control task activation request is made (step S1004), and a main board communication task activation is started. A request is made (step S1005), an animation task activation request is made (step S1006), an inter-subdevice communication control task activation request is made (step S1007), and then an RTC control task activation request is made (step S1008).

  When the main board communication task request is issued from the OS in response to the main board communication task activation request, the main board communication task is executed according to the flowchart shown in FIG. 91 as described above.

  The RTC control task is executed along the flow chat shown in FIG. First, the sub CPU 71 sets a period of 100 ms for OS time management (step S1011). Next, the sub CPU 71 reads the date / time from the external RTC 70c (step S1012), and sets the read date / time of the external RTC 70c as an initial value of the internal RTC 70a (step S1013).

  Next, the sub CPU 71 reads the status information from the external RTC 70c (step S1014), determines whether or not the status information has been read normally (step S1015). It is determined whether there is an abnormality (step S1016). If there is no power supply abnormality, it is determined whether there is an oscillation abnormality (step S1017). If there is no oscillation abnormality, a reset signal is detected. If the reset signal is not detected, the date / time is read from the external RTC 70c (step S1019).

When reading this date and time, the sub CPU 71 determines whether or not there is an abnormality in the date and time range (step S1020). For example, when the year, month, day, or time value exceeds two digits, it is determined that the date / time range is abnormal. When the sub CPU 71 determines that there is an abnormality in the date and time range, as shown in the table of FIG. 98B, the error code (RTC TIM) is set as the error time of the RTC and the error information history storage area 73d-1 in the sub RAM 73-1. (Step S1021).

On the other hand, if the sub CPU 71 determines in step S1015 that the status information cannot be normally read from the external RTC 70c, an error code (RTC) is stored in the error information history storage area 73d-1 as an RTC communication line abnormality. DSC) is registered (step S1021).

  If the sub CPU 71 determines in step S1016 that there is an abnormality in the power supply regarding the external RTC 70c, it registers an error code (RTC POWER) in the error information history storage area 73d-1 as the RTC voltage drop (step S1016). S1021).

  If the sub CPU 71 determines in step S1017 that there is an oscillation abnormality with respect to the external RTC 70c, it registers an error code (RTC CLK) in the error information history storage area 73d-1 as oscillation stop detection ( Step S1021).

  As described above, when registering an error code corresponding to the error type of the external RTC 70c as error information in step S1021, the sub CPU 71 initializes the external RTC 70c and sets the current date and time of the internal RTC 70a in the external RTC 70c. (Step S1022).

As described above, when the external RTC 70c is initialized and the current date / time of the built-in RTC 70a is set in the external RTC 70c, or when it is determined in step S1020 that there is no abnormality in the date / time range read from the external RTC 70c in step S1019. In step S1023, the sub CPU 71 determines whether or not the date and time setting of the external RTC 70c has been changed from the staff operation screen. The RTC 70c is set (step S1024).

  If the date / time data of the built-in RTC 70a is set in the external RTC 70c in step S1024, or if it is determined in step S1023 that there is no change in the date / time setting of the external RTC 70c, the sub CPU 71 waits for a cycle of 100 ms. Then, the status information is read again from the external RTC 70c (step S1014).

  Next, the management process of the sub control backup memory (SRAM) 73-2 will be described with reference to FIG. FIG. 103 shows a flowchart of the sub management process.

  First, the sub CPU 71 calculates the sum value of the backup data 1 area 73a-2 of the SRAM 73-2 to obtain a 4-byte backup data 1 sum value (step S1031). Next, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code of the backup data 1 area 73a-2 and the magic code of the program management data area 72f of the sub ROM 72 are the same. If the answer is YES, the backup data 1 area 73a-2 of the backup RAM 73-2 is copied to the game data area 73a-1 of the sub RAM 73-1 (step S1033).

  If the sub CPU 71 determines NO in step S1032, the sub CPU 71 calculates the sum value of the backup data 2 area 73c-2, which is the mirroring of the backup data 1 area 73a-2, and calculates the 4-byte backup data 2 sum value. Is obtained (step S1034).

  Subsequent to step S1034, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code in the backup data 2 area 73c-2 and the magic code in the program management data area 72f of the sub ROM 72 are the same. Determination is made (step S1035).

  If the determination in step S1035 is YES, the sub CPU 71 copies the backup data 2 area 73c-2 of the backup RAM 73-2 to the game data area 73a-1 of the sub RAM 73-1 (step S1036).

  If the determination in step S1035 is NO, the sub CPU 71 copies the game data initialization setting data area 72c in the sub ROM 72 to the game data area 73a-1 in the sub RAM 73-1 (step S1037).

When step S1036 or step S1037 is executed, the sub CPU 71 sets an error code (MEM ERR 1) as an error information history storage area 7 as a game data sum abnormality.
Registered to 3d-1 (step S1038). However, the screen as shown in FIG. 89 for notifying the RAM data abnormality is not displayed.

  After executing the process of step S1033 or the process of step S1038, the sub CPU 71 calculates a 4-byte sum value from the attendant backup data area 73e-2 and stores it in the attendant backup data sum value area 73g-2. (Step S1039).

  Next, the sub CPU 71 determines whether or not the stored sum value of the clerk backup data area 73g-2 is normal (step S1040). The data is copied to the clerk operation setting data area 73h-1 of the RAM 73-1 (step S1041).

  If the determination in step S1040 is NO, the sub CPU 71 copies the data in the clerk operation initial setting data area 72d in the sub ROM 72 to the clerk operation setting data area 73g-1 in the sub RAM 73-1 (step S1042).

After executing step S1042, the sub CPU 71 registers an error code (MEM ERR 2) in the error information history storage area 73d-1 as the clerk operation setting data sum abnormality (
Step S1043). Even for this RAM data abnormality, a screen for notifying abnormality as shown in FIG. 89 is not displayed.

  Next, after executing step S1041 or step S1043, the sub CPU 71 executes a backup creation process shown in FIG. 104 described later (step S1044).

  As described above, the sub CPU 71 determines whether the acquired sum value is normal and whether the magic code of the backup data 2 area 73c-2 and the magic code of the program management data area 72f of the sub ROM 72 are the same. However, if at least the sum value or the magic code is not the same, the sub CPU 71 copies the game data initialization setting data area 72c of the sub ROM 72 to the game data area 73a-1 of the sub RAM 73-1 (step S1035). Step S1037).

  Further, the sub CPU 71 determines whether or not the sum value of the clerk backup data area 73g-2 is normal (step S1040). If the sum is abnormal, the sub CPU 71 stores the data in the clerk operation initial setting data area 72d of the sub ROM 72. -1 is copied to the clerk operation setting data area 73g-1 (step S1042).

  As a result, it is possible to confirm whether or not the data in the sub RAM 73-1 is damaged when the power is turned on, and the initial value can be automatically set without using the damaged SRAM data.

  FIG. 104 is a flowchart of the backup creation process of the sub RAM management process shown in FIG. This process allows the correct value to be saved as a backup even if the data is corrupted.

  First, the sub CPU 71 creates a sum value of the game data area 73a-1, and stores the created sum value in the game data sum value area 73b-1 (step S1051). Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 1 area 73a-2, and stores the sum value stored in step S1051 in the backup data 1 sum value area 73b-2 (step S1052).

  Next, the sub CPU 71 copies the game data area 73a-1 to the backup data 2 area 73c-2 as mirroring of the backup data 1 area 73a-2, and uses the sum value stored in step S1051 as the backup data 2 sum value area. 73d-2 (step S1053).

  Next, the sub CPU 71 creates a sum value of the clerk operation setting data area 73g-1, and stores the created sum value in the clerk operation setting data sum value area 73h-1 (step S1054).

  Next, the sub CPU 71 copies the clerk operation setting data area 73g-1 to the clerk backup data area 73e-2, and saves the sum value stored in step S1054 as the clerk backup data sum value 73g-2 (step S1055). . Thereby, the backup creation process ends.

  Next, the inter-subdevice communication control task shown in FIG. 105 will be described. FIG. 105 is a diagram showing a flowchart of the inter-subdevice communication control task.

  First, the sub CPU 71 sets a period of 4 ms (step S1061). Subsequently, the sub CPU 71 collectively performs initial setting of the sub device serial port (step S1062).

  Next, the sub CPU 71 waits for a cycle of 4 ms (step S1063), and subsequently executes a sub device command reception process shown in FIG. 107 described later (step S1064).

  After executing the sub device command reception process in step S1064, the sub CPU 71 determines whether or not a command has been received (step S1065). If no command is received, the sub device communication disconnection shown in FIG. Processing is executed (step S1070).

  When the sub CPU 71 receives a command in step S1065, the sub CPU 71 executes a subdevice communication return process shown in FIG. 113 to be described later (step S1066). Thereafter, the sub device communication reception process shown in FIG. Is executed (step S1067).

  After executing the sub-device communication reception process in step S1067, the sub CPU 71 determines whether or not there is a command to be transmitted (step S1068), and if there is a transmission command, executes the sub-device command transmission process. (Step S1069).

  After executing the sub device command transmission process in step S1069, or determining that there is no transmission command in step S1068, or after executing the sub device communication disconnection process in step S1070, the sub CPU 71 proceeds to step S1063. The process returns to wait for a period of 4 ms, and the sub-device command reception process is executed again (step S1064).

  Next, the sub-device serial reception interrupt process shown in FIG. 106 will be described. FIG. 106 is a flowchart of the sub device serial reception interrupt process. The sub CPU 71 reads the reception status (step S1081), and determines whether there is an error in the physical layer (step S1082).

  If the sub CPU 71 determines in step S1082 that there is no error in the physical layer, it stores the received data in the communication log collection ring buffer area 73e-1 (step S1083). The size of the buffer for storing the received data is 512 bytes. The storage of the reception data ends the sub device serial reception interrupt process.

  If the sub CPU 71 determines that there is an error in the physical layer in step S1082, it stores the error code (SD COM) in the error information history storage area 73d-1 as a sub device physical layer abnormality (step S1084). Then, the sub-device serial reception interrupt process is terminated. Since the sub-device physical layer error is not as serious as the COM error, it is registered separately from the COM error.

  Next, sub-device command reception processing in the inter-sub-device communication control task shown in FIG. 105 will be described with reference to FIG. FIG. 107 is a flowchart of the sub device command reception process.

  First, the sub CPU 71 sets the reception buffer address in the communication log collection ring buffer area 73e-1, and turns off the STX reception flag (step S1091). Next, the sub CPU 71 attempts to acquire 1 byte of received data from the communication log collection ring buffer area 73e-1 (step S1092), and determines whether there is received data (step S1093).

  If the sub CPU 71 determines in step S1093 that there is no received data, the sub CPU 71 registers an error code (SD COM STX) in the error information history storage area 73d-1 (step S1105).

  In step S1093, when the sub CPU 71 determines that there is received data, the sub CPU 71 determines whether the received data is STX and the STX reception flag is off (step S1094). If the sub CPU 71 determines that the received data is STX and the STX reception flag is off in step S1094, the sub CPU 71 turns on the STX reception flag (step S1095), clears the command registration buffer (step S1096), and receives the buffer address. Is updated, 1 byte is added (step S1097), and 1 byte of received data is again obtained from the reception buffer (step S1092). The sub CPU 71 repeats this for the number of data.

  If the sub CPU 71 determines in step S1094 that the received data is STX and the STX reception flag is not OFF, the sub CPU 71 determines whether or not the reception data is ETX and the STX reception flag is ON (step S1098).

  If the sub CPU 71 determines in step S1098 that the received data is ETX and the STX reception flag is ON, the sub CPU 71 creates a sum value from the received data, and calculates the sum value of the received data stored in the reception buffer. Obtain (step S1099).

  Next, the sub CPU 71 determines whether or not the sum value of the received data is normal by comparing the created sum value with the stored sum value (step S1100). If it is determined, the sub-device command reception process is terminated. If the sub device error detection means 71h of the sub CPU 71 determines that the sum value of the received data is abnormal, the sub CPU 71 sets an error code in the error information history storage area 73d-1 as a sub device SUM abnormality. (SD COM SUM) is registered (step S1101).

  In step S1098, when the sub CPU 71 determines that the received data is ETX and the STX reception flag is not ON, the sub CPU 71 determines whether or not the reception data is ETX and the STX reception flag is OFF (step S1102).

  In step S1102, if the sub device error detection unit 71h of the sub CPU 71 determines that the received data is ETX and the STX reception flag is OFF, the sub CPU 71 stores an error in the error information history storage area 73d-1. The code (SD COM STX) is registered (step S1105), and the sub-device command reception process is terminated.

  In step S1102, if the sub CPU 71 determines that the received data is ETX and the STX reception flag is not OFF, the sub CPU 71 stores the received data in the command registration buffer (step S1103), updates the reception buffer address, and sets 1 Bytes are added (step S1104), and 1 byte of received data is obtained again from the reception buffer (step S1092). The sub CPU 71 repeats this for the number of data.

  Next, with reference to FIG. 108, the sub-device communication reception process in the inter-subdevice communication control task shown in FIG. 105 will be described. FIG. 108 is a diagram illustrating a flowchart of processing upon reception of sub-device communication.

  First, the sub CPU 71 obtains a device ID from the command “ADR” stored in the command registration buffer (step S1111), and determines whether or not the transmission destination of the device ID is the sub CPU 71 (step S1112). In step S1112, if the sub device error detection unit 71h of the sub CPU 71 determines that the transmission destination of the device ID is not the sub CPU 71, the sub CPU 71 sets an error in the sub device ID in the error information history storage area 73d-1. Then, an error code (SD COM DVC) is registered (step S1115). Accordingly, the sub CPU 71 ends the sub-device communication reception process.

  In step S1112, if the sub CPU 71 determines that the transmission destination of the device ID is the sub CPU 71, the sub CPU 71 further determines whether or not the transmission source of the device ID is the scaler control LSI of the scaler control board 77 ( Step S1113).

  If the sub CPU 71 determines in step S1113 that the device ID is transmitted from the scaler control LSI of the scaler control board 77, the sub CPU 71 executes a scaler control command reception process shown in FIG. 109 described later (step S1114). Then, the sub-device communication reception process is terminated.

  If the device error detection unit 71h of the sub CPU 71 determines in step S1113 that the transmission source of the device ID is not the scaler control LSI of the scaler control board 77, the sub CPU 71 determines that the error information history storage area 73d− 1, an error code (SD COM DVC) is registered as an abnormal sub-device ID (step S1115). Accordingly, the sub CPU 71 ends the sub-device communication reception process.

  Next, with reference to FIG. 97D, FIG. 97E, FIG. 97F, and FIG. 97D is a diagram showing a transmission / reception command data format, FIG. 97E is a diagram showing transmission / reception data contents, FIG. 97F is a diagram showing a sub-device communication data consistency check table, and FIG. 109 is a flowchart of processing at the time of receiving a scaler control command. FIG.

  First, the sub CPU 71 reads the scaler reception data consistency check table shown in FIG. 97F from the various program table areas 72e and sets it in the work area 73c-1 (step S1121). The sub CPU 71 passes the set table as an argument for the reception data determination process in the next step, thereby executing a sub device reception data determination process shown in FIG. 111 to be described later (step S1122).

  Next, the sub CPU 71 determines whether or not the reception data after the sub device reception data determination process is normal (step S1123). In step S1123, when the sub device error detection unit 71h determines that the received data is inconsistent, the sub CPU 71 returns error information as a return value, and the sub CPU 71 returns an error corresponding to the error information based on the returned error information. The code is registered (step S1124). The error code is shown in FIG. 98C. Thereby, the sub CPU 71 ends the process at the time of receiving the scaler control command.

  In step S1123, when the sub CPU 71 determines that there is no error code, the sub CPU 71 determines whether or not the CMD of the received data is “activation parameter request” (step S1125). In step S1125, when the sub CPU 71 determines that the CMD of the received data is “activation parameter request”, the sub CPU 71 sets a scaler activation parameter request confirmation command in the sub device transmission buffer (step S1126), and further the scaler. The setting phase is set to 1 (step S1127). Thereby, the sub CPU 71 ends the process at the time of receiving the scaler control command.

  In step S1125, when the sub CPU 71 determines that the CMD of the received data is not “activation parameter request”, the sub CPU 71 determines whether or not the CMD of the received data is “reception confirmation” (step S1128).

  In step S1128, when the sub CPU 71 determines that the CMD of the received data is “reception confirmation”, the sub CPU 71 executes a scaler control setting process shown in FIG. 110 described later (step S1129). After executing the scaler control setting process, the sub CPU 71 ends the scaler control command reception process.

  In step S1128, when the sub CPU 71 determines that the CMD of the reception data is not “reception confirmation”, the sub CPU 71 determines whether or not the CMD of the reception data is “reset notification” (step S1130).

  In step S1130, when the sub CPU 71 determines that the CMD of the received data is not “reset notification”, the sub CPU 71 ends the process at the time of receiving the scaler control command.

In step S1130, when the sub device error detection unit 71h of the sub CPU 71 determines that the CMD of the received data is “reset notification”, the sub CPU 71 determines that a reset has occurred in the error information history storage area 73d-1. , Error code (SCL RST
) Is registered (step S1131). Accordingly, the sub CPU 71 ends the sub-device communication reception process.

  Next, the scaler control setting process in the scaler control command reception process shown in FIG. 109 will be described with reference to FIG. FIG. 110 is a diagram illustrating a flowchart of the scaler control setting process.

  The sub CPU 71 determines whether or not the scaler setting phase is 1 (step S1141). In this step, when determining that the scaler setting phase is 1, the sub CPU 71 sets the luminance setting command data in the sub device transmission buffer and sets 2 in the scaler setting phase (step S1142). Thereby, the sub CPU 71 ends the scaler control setting process.

  In step S1141, when the sub CPU 71 determines that the scaler setting phase is not 1, the sub CPU 71 determines whether or not the scaler setting phase is 2 (step S1143).

  In step S1143, when the sub CPU 71 determines that the scaler setting phase is 2, the sub CPU 71 sets the contour setting command data in the sub device transmission buffer, and sets 3 in the scaler setting phase (step S1144).

  After executing the processing of step S1144, the sub CPU 71 determines whether or not the luminance setting value setting result is normal (step S1145). In step S1145, when the sub CPU 71 determines that the luminance setting value setting result is normal, the sub CPU 71 ends the scaler control setting process. In step S1145, when the sub device error detection unit 71h of the sub CPU 71 determines that the luminance setting value setting result is not normal, the sub CPU 71 sets an error code (SCL SET ERR1) as an error in luminance setting. Registration is made in the information history storage area 73d-1 (step S1146). Thereby, the sub CPU 71 ends the scaler control setting process.

  In step S1143, when the sub CPU 71 determines that the scaler setting phase is not 2, the sub CPU 71 determines whether or not the scaler setting phase is 3 (step S1147).

  In step S1147, if the sub CPU 71 determines that the scaler setting phase is 3, the sub CPU 71 sets the interpolation setting command data in the sub device transmission buffer, and sets 4 in the scaler setting phase (step S1148).

  After executing the processing of step S1148, the sub CPU 71 determines whether or not the setting result of the contour setting value is normal (step S1149). In step S1149, when the sub CPU 71 determines that the setting result of the contour setting value is normal, the sub CPU 71 ends the scaler control setting process. In step S1149, when the sub device error detection unit 71h of the sub CPU 71 determines that the setting result of the contour setting value is not normal, the sub CPU 71 sets an error code (SCL SET ERR2) as an error in the contour setting. Registration is made in the information history storage area 73d-1 (step S1150). Thereby, the sub CPU 71 ends the scaler control setting process.

  In step S1147, when the sub CPU 71 determines that the scaler setting phase is not 3, the sub CPU 71 sets a scaler setting completion command in the sub device transmission buffer, and clears the scaler setting phase to 0 (step S1151).

  When the process of step S1151 ends, the sub CPU 71 determines whether or not the interpolation setting value setting result is normal (step S1152). If the sub CPU 71 determines in step S1152 that the interpolation setting value setting result is normal, the sub CPU 71 ends the scaler control setting process. In step S1152, if the sub device error detection unit 71h of the sub CPU 71 determines that the setting result of the interpolation setting value is not normal, the sub CPU 71 sets an error code (SCL SET ERR3) as an error in the interpolation setting. Registration is made in the information history storage area 73d-1 (step S1153). Thereby, the sub CPU 71 ends the scaler control setting process.

  Next, the sub-device received data determination process in the scaler control command reception process shown in FIG. 109 will be described with reference to FIG. FIG. 111 is a diagram illustrating a flowchart of sub-device received data determination processing.

  The sub CPU 71 first obtains the size of the DATA part of the reception buffer. In this case, the sub CPU 71 passes the target position address of the sub device communication check table shown in FIG. 97F in the various program table areas 72e as an argument address. For the scaler, the table No. The position corresponds to 2.

  Based on this, the sub CPU 71 checks the presence and size of the received data (step S1161), and then determines whether the DATA size is 256 bytes or less (step S1162).

In step S1162, if the sub device error detection unit 71h of the sub CPU 71 determines that the DATA size is not less than 256 bytes, the sub CPU 71 determines that the data size is abnormal and stores an error in the error information history storage area 73d-1. A code (SCL COM SIZ) is registered (step S1163). Thus, the sub CPU 71 ends the sub device reception data determination process.

  In step S1162, when the sub device error detection unit 71h of the sub CPU 71 determines that the DATA size is 256 bytes or less, the sub CPU 71 determines whether there is a type registration in the sub device communication check table. (Step S1164).

  In step S1164, when the sub device error detection unit 71h of the sub CPU 71 determines that the type is not registered in the sub device communication check table, the sub CPU 71 determines that the command type is abnormal in the error information history storage area 73d-1. Register an error code (SCL COM TYP).

  If the sub CPU 71 determines that there is a type registration in the sub device communication check table in step S1164, the sub CPU 71 acquires a determination condition for the CMD type from the sub device communication check table (step S1165), and receives data. It is determined whether or not the type of CMD matches the determination condition (step S1166).

  If the sub CPU 71 determines in step S1166 that the type of CMD does not match the determination condition, the sub CPU 71 updates the check table, for example, updates the check table from the CMD of determination 1 to the CMD of determination 2 (step S1167). ). After updating the check table, the sub CPU 71 determines again whether there is a type registration in the sub device communication check table (step S1164).

  If the sub CPU 71 determines in step S1166 that the type of CMD matches the determination condition, the sub CPU 71 updates the check table and moves to DATA determination corresponding to CMD (step S1168). For example, in the case of determination 3 for the scaler, No. The check table is updated to the position of decision 3 in 2. Subsequently, the sub CPU 71 acquires a determination condition regarding the DATA size from the check table (step S1169).

  After execution of step S1169, the sub CPU 71 determines whether or not the DATA size of the received data matches the determination condition (step S1170). In step S1170, when the sub CPU 71 determines that the DATA size of the reception data matches the determination condition, the sub CPU 71 ends the sub device reception data determination processing.

In step S1170, if the sub device error detection unit 71h of the sub CPU 71 determines that the DATA size of the received data does not match the determination condition, the sub CPU 71 determines that the packet size is abnormal in the error information history storage area 73d-1. Register the error code (SCL COM PKT). Accordingly, the sub CPU 71 ends the sub device reception data determination process.

  Next, the sub-device communication disconnection process in the inter-sub-device communication control task shown in FIG. 105 will be described with reference to FIG. FIG. 112 is a diagram illustrating a flowchart of sub-device communication disconnection processing.

  First, since the inter-subdevice communication control task shown in FIG. 105 is executed at a cycle of 4 ms, the sub CPU 71 updates the scaler communication disconnection counter and adds 1 (step S1181) to the scaler communication disconnection counter. Is determined to be equal to or greater than 1250 (step S1182). This is because when the sub CPU 71 does not receive data from the scaler control board 77 for 5 seconds, it is determined that communication is disconnected, and 4 ms × 1250 = 5 s.

  Next, the sub CPU 71 determines whether or not the scaler communication disconnection flag is on (step S1183). If the sub CPU 71 determines in step S1183 that the scaler communication disconnection flag is on, the sub device communication disconnection process ends.

If the sub CPU 71 determines in step S1183 that the scaler communication disconnection flag is not on, the sub CPU 71 turns on the scaler communication disconnection flag (step S1184), and then stores the error in the error information history storage area 73d-1. An error code (SCL DSC) is registered as disconnection (step S1185). Thereby, the sub CPU 71 ends the sub device communication disconnection process.

  Note that in the inter-subdevice communication control task shown in FIG. 105, when this subdevice communication disconnection process ends, the task process flow returns to the subdevice command reception process (step S1064), and the task does not end. When the sub-device communication return process shown in FIG. 113 is executed and communication is resumed, the communication return is registered as an error history.

  For this reason, since the communication task is not completed even if an error occurs in the communication between the sub CPU 71 and the sub control board 77, the communication can be resumed. In addition, since communication resumption is registered in the error history, the date and time of communication interruption and communication resumption can be confirmed in the error history.

  Next, with reference to FIG. 113, sub-device communication return processing in the inter-device communication control task shown in FIG. 105 will be described. FIG. 113 is a flowchart of the sub device communication return process.

  First, the sub CPU 71 determines whether or not the received transmission source ID is the scaler control board 77 (step S1191). If it is determined that the received transmission source ID is not the scaler control board 77, the sub device communication return processing is terminated. .

  If the sub CPU 71 determines in step S1191 that the received transmission source ID is the scaler control board 77, the sub CPU 71 determines whether or not the scaler communication disconnection flag is on (step S1192).

If the sub device error detection unit 71h of the sub CPU 71 determines in step S1192 that the scaler communication disconnection flag is on, the sub CPU 71 sets an error code in the error information history storage area 73d-1 as a communication return. Register (SCL RSM).

  In step S1192, if the sub CPU 71 determines that the scaler communication disconnection flag is OFF or after executing step S1193, the sub CPU 71 turns off the scaler communication disconnection flag and clears the scaler communication disconnection counter to 0 (step S1192). S1194). Thereby, the sub CPU 71 ends the sub device communication return processing.

  Next, the control flow in the scaler control board will be described with reference to FIG. FIG. 114 is a flowchart of the scaler control main task.

  In the flowchart of the scaler control main task in FIG. 114, “U1” indicates that the scaler control LSI of the scaler control board 77 has a subdevice (the scaler control LSI of the scaler control board 77) performs transmission / reception with the sub CPU 71. The serial port U1 is provided. Further, “U2” indicates, for example, when a touch sensor or a camera is connected to the sub CPU 71 via the scaler control board 77 as another sub device, from the scaler control LSI of the scaler control board 77 to those other devices. This is a serial port U2 provided in the scaler control board 77 for allowing the received data to pass through.

  In addition, U1 and U2 acquire the reception data in units of 1 byte at the respective reception interrupts. The processing of the scaler control main task is almost the same as the sub device serial reception interrupt processing of the sub CPU 71 shown in FIG. 106, but no error registration processing is performed in the processing of the scaler control main task.

  In the scaler control main task of FIG. 114, the scaler control LSI of the scaler control board 77 first performs an initial setting process (step S1201). The scaler control LSI performs, for example, setting of a timer, serial port, etc. in the scaler control board 77, initialization of the work RAM, and initial setting of the resolution conversion LSI.

  Next, the scaler control LSI performs 10 ms cycle setting (step S1202). Thereby, the remaining time of the processing time so far is waited. For example, if the processing time so far is 1.5 ms, the standby time is 8.5 ms. However, the reception interrupt process operates even during standby.

  Next, the scaler control LSI executes a sub control reception process shown in FIG. 115 to be described later (step S1204).

  After the execution of step S1204, when a touch sensor or camera is connected as a sub device in addition to the scaler control board 77, the scaler control LSI executes a reception process with another device (step S1205).

  After execution of step S1205, the scaler control LSI determines whether or not there is transmission to the sub CPU 71 (step S1206), and if it is determined that there is transmission to the sub CPU 71, executes sub control transmission processing (step S1206). S1207).

  When it is determined in step S1206 that there is no transmission to the sub CPU 71, or after step S1207 is executed, the scaler control LSI determines whether there is transmission to another subdevice (step S1208). If the scaler control LSI determines in step S1208 that there is transmission to another subdevice, the scaler control LSI executes transmission processing to the other subdevice (step S1209). If the sub CPU 71 is the transmission destination in step S1209, the other sub devices perform through transmission. When no other subdevice is connected, no transmission / reception data is generated.

  After executing step S1209 or when it is determined in step S1208 that there is no transmission to another subdevice, the scaler control LSI executes an operation state determination process shown in FIG. 118 described later (step S1210). . After executing step S1210, the sub CPU 71 waits for the remaining time of the 10 ms period (step S1211), and performs the sub control reception process again (step S1204).

  Next, the sub-control reception process in the scaler control main task shown in FIG. 114 will be described with reference to FIG. FIG. 115 is a diagram showing a flowchart of the sub-control reception process.

  The scaler control LSI determines whether there is received data (step S1221). If it is determined that there is no received data, the sub-control reception process ends. If it is determined in step S1221 that there is received data, the scaler control LSI determines whether the destination ID of the received data is the scaler control LSI (step S1222).

  If the scaler control LSI determines in step S1222 that the destination ID of the received data is the scaler control LSI, the scaler control LSI determines whether the command CMD is a setting item (step S1223). As setting items related to the scaler control board 77, there are three items of backlight luminance setting, contour enhancement setting, and interpolation table setting, as shown in the table of FIG. 97E.

  If the scaler control LSI determines in step S1223 that the CMD is one of these three setting items, it performs resolution conversion LSI setting processing shown in FIG. 116 described later (step S1224). After executing this process, the scaler control LSI ends the sub-control reception process.

  In step S1223, when the scaler control LSI determines that the CMD is not one of those three setting items, it sets a reception confirmation command in the sub-control transmission buffer (step S1225), and performs sub-control reception processing. finish.

  If the scaler control LSI determines in step S1222 that the received data transmission destination ID is not the scaler control LSI, the scaler control LSI transmits the received data to the other subdevice transmission buffer in order to transmit the received data to the other subdevice. Data is copied (step S1226), and the sub-control reception process is terminated.

  Next, the resolution conversion LSI setting process in the sub-control reception process shown in FIG. 115 will be described with reference to FIG. FIG. 116 is a flowchart of resolution conversion LSI setting processing.

  The scaler control LSI first acquires setting items from the reception buffer and also acquires setting data from the reception buffer (step S1231). The setting item is one of three items of backlight luminance, contour enhancement, and scaler interpolation table setting.

  Next, the scaler control LSI sets the acquired setting data in the setting item of the resolution conversion LSI (step S1232).

  Next, the scaler control LSI reads the setting contents from the resolution conversion LSI (step S1233), and determines whether the read value is the same as the value set in step S1232 (step S1234).

  In step S1234, when the scaler control LSI determines that the set value and the read value are not the same, the resolution conversion LSI setting abnormality flag is turned on (step S1235), and the resolution conversion LSI setting process ends.

  If the scaler control LSI determines in step S1234 that the set value is the same as the read value, it sets a reception confirmation command with a setting item in the sub-control transmission buffer (step S1236). Thereafter, the scaler control LSI ends the resolution conversion LSI setting process.

  In this resolution conversion LSI setting process, when a parameter request is sent from the scaler control LSI to the sub CPU 71 and, for example, a command for outline enhancement setting is transmitted from the sub CPU 71 to the scaler control LSI, the scaler control LSI sends the sub CPU 71 to the sub CPU 71. Command receipt confirmation is sent.

  At this time, when the first parameter request is sent from the scaler control LSI to the sub CPU 71 and, for example, a command for outline enhancement setting is transmitted from the sub CPU 71 to the scaler control LSI, the scaler control LSI then sends the sub CPU 71 to the sub CPU 71. Before the reception confirmation of the contour emphasis setting command is transmitted, the scaler control LSI makes a second parameter request to the sub CPU 71. In response to this, for example, the backlight luminance setting command is sent from the sub CPU 71 to the scaler control LSI. At this time, when a command reception confirmation is transmitted from the scaler control LSI to the sub CPU 71, the sub CPU 71 confirms the reception of the “backlight luminance setting command”. Next, from the scaler control LSI to the sub C In U71, the acknowledgment for the "command backlight brightness setting" is transmitted, the sub-CPU71 has happen to ignore the acknowledgment due to misidentification of the.

  On the other hand, as shown in step S1236 above, a reception confirmation command with setting items is set in the sub-control transmission buffer. That is, instead of simply transmitting a reception confirmation from the scaler control LSI to the sub CPU 71, the setting items are added to the reception confirmation and transmitted.

  Therefore, according to the above configuration, the sub CPU 71 can correctly determine which setting change command is the reception confirmation command received from the scaler control LSI.

  Next, the sub-control transmission process in the scaler main control task shown in FIG. 114 will be described with reference to FIG. FIG. 117 is a flowchart of the sub control transmission process.

  The scaler control LSI updates the sub control transmission interval counter of the transmission data to the sub CPU 71 and adds 1 (step S1241).

  Next, the scaler control LSI determines whether the data transmission interval from the sub CPU 71 is 100 ms or more (step S1242). If the scaler control LSI determines in step S1242 that the data transmission interval from the sub CPU 71 is 100 ms or longer, the scaler control LSI determines whether there is transmission data in the transmission buffer (step S1243). On the other hand, when the scaler control LSI determines in step S1242 that the data transmission interval from the sub CPU 71 is less than 100 ms, the sub control transmission process is terminated.

  In step S1243, when the scaler control LSI determines that there is no transmission data in the transmission buffer, the scaler control LSI transmits a parameter request command to the sub CPU 71 at a cycle of 200 ms and determines whether the transmission interval is 200 ms or more (step). S1244).

  In step S1244, when the scaler control LSI determines that the transmission interval is 200 ms or longer, the scaler control LSI determines whether the activated flag is on (step S1245).

  On the other hand, if the scaler control LSI determines in step S1244 that the transmission interval is less than 200 ms, the sub-control transmission process ends.

  The activated flag is turned off by clearing the RAM in the initial setting process at a reset interrupt (power-on or counter reset).

  If the scaler control LSI determines in step S1245 that the activated flag is on, the scaler control LSI sets a parameter request command in the sub-control transmission buffer (step S1248).

  When the scaler control LSI determines in step S1245 that the activated flag is off, the activation parameter request command is set in the sub-control transmission buffer (step S1246), and then the activated flag is turned on. (Step S1247).

  After executing step S1247, after executing step S1248, or when the scaler control LSI determines that there is transmission data in the transmission buffer in step S1243, the scaler control LSI transmits the transmission data to the sub CPU 71 (step S1243). Next, the sub-control transmission interval counter is cleared to 0 (S1250). Thereby, the scaler control LSI ends the sub-control transmission process.

  Next, the operation state determination process in the scaler control main task shown in FIG. 114 will be described with reference to FIG. FIG. 118 is a diagram illustrating a flowchart of the operation state determination process.

  First, the scaler control LSI updates the determination interval counter and adds 1 (step S1261).

  Next, the scaler control LSI determines whether or not the determination interval is 500 ms or longer (step S1262). If the scaler control LSI determines in step S1262 that the determination interval is 500 ms or more, the determination interval counter is cleared to 0 (step S1263), and the data in the self-diagnosis area of the ROM is read into the register (step S1264). Subsequently, the data read into the register is written into the self-diagnosis area of the RAM (step S1265).

  Next, the scaler control LSI determines whether or not the value read into the register in step S1264 is the same as the value in the self-diagnosis area of the ROM (step S1266). In step S1266, when the scaler control LSI determines that the read value is the same as the value of the ROM self-diagnosis area, the value read into the register and the RAM self-diagnosis area value in step S1263. It is determined whether or not the value is the same (step S1267).

  If the scaler control LSI determines in step S1267 that the value read into the register in step S1264 is not the same as the value of the RAM self-diagnosis area, or in step S1266, the scaler control LSI registers in step S1264. If it is determined that the value read into the self-diagnostic area of the ROM is not the same, the reset notification (1) command is set in the sub-control transmission buffer (step S1268).

  On the other hand, when the scaler control LSI determines in step S1262 that the determination interval is less than 500 ms, or in step S1267, the value read by the scaler control LSI into the register in step S1264 and the value of the self-diagnosis area of the RAM Are determined to be the same, the scaler control LSI determines whether or not the resolution conversion LSI setting abnormality flag is on (step S1269).

  If the scaler control LSI determines in step S1269 that the resolution conversion LSI setting abnormality flag is off, the scaler control LSI clears the WDT counter register (step S1272). After the WDT is cleared, it automatically starts counting. After clearing the WDT counter register, the scaler control LSI ends the operation state determination process.

  If the scaler control LSI determines in step S1269 that the resolution conversion LSI setting abnormality flag is ON, it sets a reset notification (2) command in the sub-control transmission buffer (step S1270).

  The scaler control LSI transmits the transmission data to the sub CPU 71 after setting the reset notification (1) or the reset notification (2) in the sub control transmission buffer (after execution of step S1268 or step S1270) (step S1271). After a few seconds, the scaler control LSI and resolution conversion LSI are reset.

  As described above, when the scaler control LSI compares the ROM value and the register value at a constant interval of 500 ms and the values are different, the scaler control LSI and the resolution conversion LSI are reset. Thereby, when an error occurs, the scaler control board 77 can be self-recovered by resetting.

This reset is detected by the sub-device error detection means 71h and an error code (SCL RST) is registered as the occurrence of reset in the error information history storage area 73d-1, so that the date and time of error occurrence may be confirmed later. it can.

[Configuration of pachinko machines]
The present invention is not limited to a pachislot machine but can also be applied to a pachinko gaming machine. Hereinafter, the pachinko gaming machine will be described.

  First, an overview of the pachinko gaming machine 10 will be described with reference to FIGS. FIG. 119 is a perspective view showing an overview of a pachinko gaming machine 1010 according to another embodiment of the present invention. FIG. 120 is a front view showing an overview of a pachinko gaming machine 1010 according to the present embodiment. FIG. 121 is an exploded perspective view showing an overview of a pachinko gaming machine 1010 according to the present embodiment. FIG. 122 is a front view of the game board of the pachinko gaming machine 1010 according to the present embodiment.

  As shown in FIGS. 119 to 121, the pachinko gaming machine 1010 includes a glass door 1011, a wooden frame 1012, a base door 1013, a game board 1014, a dish unit 10, a liquid crystal display device 1032 for displaying an image, and a game ball. It comprises a launching device 1130 for launching, a dispensing unit 1500, a substrate unit 1600, and the like.

  The glass door 1011 described above is attached to the base door 1013 so that it can be opened and closed by a rotating shaft. An opening 1011a is formed in the center of the glass door 1011. A protective glass 1019 having transparency is disposed in the opening 1011a. The protective glass 1019 is disposed so as to face the front surface of the game board 1014 with the glass door 1011 closed.

  The dish unit 1020 is a unit body in which the upper dish 1021 and the lower dish 1022 are integrated, and is disposed below the glass door 1011 in the base door 1013. Further, the lower plate 1022 is positioned below the upper plate 1021. The upper plate 1021 and the lower plate 1022 are provided with payout ports 1021a and 1022a for renting out game balls and paying out game balls (prize balls). If predetermined payout conditions are met, The ball is discharged, and in particular, the upper plate 1021 stores a game ball for launching to a game area 15 described later.

  The launcher 1130 is disposed at the lower right portion of the base door 1013. The launching device 1130 includes a launching handle 1026 that can be operated by a player, and a panel body 1027 that fits in the lower right portion of the dish unit 1020. The firing handle 1026 is provided on the front side of the panel body 1027. A drive device for launching a game ball is provided on the back side of the panel body 1027.

  A plate unit 1021 and a launching device 1130 are disposed on the base door 1013, and the panel body 1027 is integrated with the lower right portion of the plate unit 1020. And the pachinko game can be advanced by operating the launch handle 1026 by the player.

  The game board 1014 described above is disposed in front of the base door 1013 so as to be positioned behind the protective glass 1019. Behind the game board 1014, a spacer 1031 and a liquid crystal display device 1032 are disposed. A payout unit 1500 and a substrate unit 1600 are disposed behind the base door 1013. A speaker 1046 is disposed below the lower plate 1022.

  The game board 1014 is entirely made of a plate-like resin (a member having permeability) having permeability. Examples of the transparent member include various materials such as acrylic resin, polycarbonate resin, and methacrylic resin. In addition, the game board 1014 has a game area 1015 on the front side thereof in which the launched game ball can roll down. This game area 1015 is surrounded by a guide rail 1030 (specifically, an outer rail 1030a shown in FIG. 122 described later), and is an area in which a game ball can roll. Further, a plurality of game nails 1018 are driven into the game area 1015 of the game board 1014. As described above, the game board 1014 is an example of a game board having a game area in which a game ball can roll.

  The liquid crystal display device 1032 is disposed behind the game board 1014 (on the back side). In other words, the liquid crystal display device 1032 is disposed behind the transparent member of the game board 1014. The liquid crystal display device 1032 has a display area 1032a that enables display of an image relating to a game. This display area 1032a is arranged so as to overlap all or part of the game board 1014 from the back side.

  In other words, the display area 1032a is arranged behind the game board 1014 so as to overlap at least all or part of the game area 1015 in the game board 1014. Specifically, the liquid crystal display device 1032 is disposed behind the game board 1014 so that the display area 1032a overlaps all or part of the game area 1015 and all or part of the game area outer area 1016. . In the display area 1032 a of the liquid crystal display device 1032, various images such as an identification symbol for presentation, a presentation image, and a decoration image for decoration are displayed.

  The spacer 1031 is arranged behind the game board 1014 (back side), and a game ball that rolls the game board 1014 between the back of the game board 1014 and the front (front side) of the liquid crystal display device 1032. This constitutes a space to be a flow path. In addition, an LED unit 1053 (see FIG. 122) is provided below the spacer 1031. The spacer 1031 is formed of a material having permeability. Note that although the spacer 1031 is formed using a material having permeability in this embodiment, the present invention is not limited to this, and for example, a part of the spacer 1031 may be formed using a material having transparency. Moreover, you may form with the material which does not have permeability | transmittance.

  The firing handle 1026 is rotatable, and a firing solenoid (not shown) as a driving device is provided on the back side of the firing handle 1026. Further, a touch sensor (not shown) is provided on the peripheral edge of the firing handle 1026. Inside the firing handle 1026 is provided a firing volume that changes the resistance value according to the amount of rotation of the firing handle 1026 and changes the power supplied to the firing solenoid (not shown).

  When the player touches a touch sensor (not shown), it is detected that the firing handle 1026 is gripped by the player. When the firing handle 1026 is gripped by the player and rotated clockwise, the resistance value of the firing volume (not shown) changes according to the rotation angle, and corresponds to the resistance value at this time. Electric power is supplied to a firing solenoid (not shown). As a result, the game balls stored in the upper plate 1021 are sequentially launched into the game area 1015 of the game board 1014, and the game is advanced. When a firing stop button (not shown) is pressed, the game ball is stopped firing even when the firing handle 1026 is held and rotated.

  On the lower left side of the game board 1014, members forming the general winning ports 1056a, 1056b, and 1056c are arranged, and a portion of the member facing the LED unit 1053 is transparent. Therefore, as shown in FIG. 122, the LED unit 1053 can be visually recognized from the lower left side of the game board 1014. The LED unit 1053 is provided with a special symbol display device, a normal symbol display device 1033, a first special symbol hold display LED 1034a, 1034b, a second special symbol hold display LED 1034c, 1034d, a normal symbol hold display LED 1050a, 1050b, and the like. .

  The special symbol display device is composed of 16 LEDs. These 16 LEDs are divided into two groups of 8 LEDs, and details will be described later, but one group performs variable display in response to a start winning at the first start port 1025. Yes, the other group performs variable display in response to a start winning at the second start port 1044. For convenience of the following description, one LED group is referred to as a first special symbol display device 1035a (see FIG. 123), and the other LED group is referred to as a second special symbol display device 1035b (see FIG. 123).

  The LEDs of the first and second special symbol display devices 1035a and 1035b perform variable display that repeatedly turns on and off in units of groups when a predetermined special symbol variable display start condition is satisfied. Then, the display pattern formed by turning on / off the eight LEDs is stopped and displayed as a special symbol (also referred to as an identification symbol). When the special symbol displayed in a stopped state is in a specific stop display mode, the gaming state shifts from a normal gaming state to a winning gaming state (special gaming state) that is advantageous to the player. In this winning game state, as will be described later, the shutter 1040 (see FIG. 122) is controlled to the open state, and the game ball can be received in the special winning opening 1039 (see FIG. 122).

  In other words, a game in which the big winning opening 1039 is opened is a winning game, and according to the embodiment, there are two types of winning games, a big hit game and a small hit game. In addition, it is a big hit that the special symbol becomes a stop display mode in which it shifts to the big hit gaming state, and a special symbol becomes a stop display mode in which the special symbol goes to the small hit gaming state.

  The difference between the big hit and the small hit will be described later. In the case of the big hit, there is a high possibility that a lot of balls will be obtained. On the other hand, when the lost symbol is stopped and displayed as a special symbol, the gaming state is maintained. As described above, a game in which a special symbol is variably displayed and then stopped and the game state is shifted or maintained according to the result is referred to as a “special symbol game”.

  Below the special symbol display device, a normal symbol display device 1033 is provided. The normal symbol display device 1033 includes two display lamps, and these display lamps are alternately lit and extinguished so that they are variably displayed as normal symbols. A game in which the normal symbol is variably displayed and then stopped and the open / closed state of the normal electric accessory 1048 (see FIG. 122) varies depending on the result is referred to as a “normal symbol game”.

  Below the normal symbol display device 1033, normal symbol hold display LEDs 1050a and 1050b are provided. The normal symbol hold display LEDs 1050a and 1050b display the number of executions of the fluctuation display of the normal symbol held by turning on, turning off, or blinking (so-called “hold number”, “hold number related to the normal symbol”). Specifically, when the execution of the normal symbol variation display is held for one time, the normal symbol hold display LED 1050a is turned on and the normal symbol hold display LED 1050b is turned off.

  When the execution of the normal symbol variation display is held twice, the normal symbol hold display LED 1050a is turned on and the normal symbol hold display LED 1050b is turned on. When the execution of the normal symbol fluctuation display is held three times, the normal symbol hold display LED 1050a blinks and the normal symbol hold display LED 1050b lights. When the execution of the normal symbol variation display is held four times, the normal symbol hold display LED 1050a blinks and the normal symbol hold display LED 1050b blinks.

  Below the normal symbol hold display LEDs 1050a and 1050b, first special symbol hold display LEDs 1034a and 1034b and second special symbol hold display LEDs 1034c and 1034d are provided. The first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d are displayed by the number of executions of so-called “hold number”, “special”. Display the number of reserved items "). The display mode of the number of reserved symbols related to the special symbols by the first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d is the same as the display mode of the number of held normal symbols by the normal symbol hold display LEDs 1050a and 1050b. is there.

  On the side of the normal symbol display device 1033, a hit notification LED or the like that is lit regardless of whether it is a big hit or a small hit is provided. According to this embodiment, since the number of rounds is constant, there is no LED for displaying the number of rounds. For this reason, on the display of the hit notification LED controlled by the main control circuit 1060, there is no discrimination on notification of big hit and small hit. In addition, as described later, the opening / closing pattern of the shutter 1040 when the hit occurs is selected from the same one for the large hit and the small hit, and the effect on the liquid crystal display device 1032 or the like controlled by the sub control circuit 1200 is also provided. Are the same. For this reason, the player cannot visually distinguish between big hits and small hits.

  Further, in the display area of the liquid crystal display device 1032 disposed on the rear side (back side) of the game board 1014, it is related to the special symbols displayed on the first special symbol display device 1035a and the second special symbol display device 1035b. An effect image is displayed.

  For example, during the variable display of the special symbols displayed on the first special symbol display device 1035a and the second special symbol display device 1035b, the display area 1032a of the liquid crystal display device 1032 is composed of numbers except in specific cases. Identification symbols (which are also identification information for effects), for example, numbers such as “1-8” are variably displayed. In addition, the special symbols that are variably displayed on the first special symbol display device 1035a (see FIG. 123) and the second special symbol display device 1035b (see FIG. 123) are stopped and displayed, and the display area 1032a of the liquid crystal display device 1032 is displayed. However, the identification symbol for production is stopped and displayed.

  In the first special symbol display device 1035a and the second special symbol display device 1035b, when the special symbol that has been changed or stopped is in a specific stop display mode, an effect image that allows the player to grasp that it is a win is displayed. The image is displayed in the display area 1032a of the liquid crystal display device 1032. Specifically, in either one of the first special symbol display device 1035a and the second special symbol display device 1035b, the special symbol is stopped and displayed in a specific display mode corresponding to, for example, a jackpot that can be obtained by many outgoing balls. In such a case, the combination of effect identification symbols displayed in the display area 1032a of the liquid crystal display device 1032 is stopped in a state where all the same symbols are arranged in a specific display mode (for example, a plurality of symbol rows). In addition, the effect image for the big hit is displayed in the display area 32 a of the liquid crystal display device 32. In the case of hits where it is difficult to obtain a ball (small hits, 15 hits, big hits, 16 hits, big hits), a display image of the liquid crystal display device 1032 is displayed on the display area of the liquid crystal display device 1032. It is not necessary to display in 1032a.

  As shown in FIG. 122, on the gaming board 1014 of the gaming machine 1010, there are two guide rails 1030 (1030a and 1030b), a stage 1055, a first starting port 1025, a second starting port 1044, a passing gate 1054, and a shutter 1040. Game members such as a grand prize opening 1039, general winning openings 1056a, 1056b, 1056c, 1056d, and an ordinary electric accessory 1048 are provided.

  A substantially inverted L-shaped stage 1055 is provided on the upper part of the game board 1014. A guide rail 1030 is provided so as to surround the game area 1015.

  The guide rail 1030 includes an outer rail 1030a that partitions (defines) the game area 1015, and an inner rail 1030b that is disposed inside the outer rail 1030a. The launched game ball is guided by a guide rail 1030 provided on the game board 1014 and moves to the upper part of the game board 1014. The plurality of game nails (not shown) and the game board 1014 described above are provided. Due to the collision with the stage 1055 and the like, the game flows down toward the lower side of the game board 1014 while changing its traveling direction. Specifically, a system that flows down the left side of the stage 1055 (so-called “left-handed”) and a firing handle 1026 are rotated to the right to the maximum, and a game ball is driven into the right side of the stage 1055 and flows down the right side of the stage 1055. There is a system (so-called right-handed).

  A first start port 1025 is provided below the stage 1055 and below the center of the game board 1014. A passage gate 1054 is provided at the upper right side of the stage 1055, and a second start port 1044 is provided below the passage gate 1054. The second starting port 1044 is provided with an ordinary electric accessory 1048. The ordinary electric accessory 1048 includes a tongue-like member 1048a that projects and retracts in the front-rear direction with respect to the plate surface of the game board 1014. When the tongue-like member 1048a protrudes, the game ball riding on the tongue-like member 1048a wins the second start port 1044, and when the tongue-like member 1048a is retracted, the game ball wins the second start port 1044. It is impossible.

  When the normal symbol is stopped and displayed with the predetermined symbol on the normal symbol display device 1033, the tongue-like member 1048a of the normal electric accessory 1048 is in the protruding state from the retracted state for a predetermined time, and is displayed at the second start port 1044. Game balls are easy to enter. Note that the ordinary electric accessory 1048 is not limited to the one that protrudes and retracts the tongue-like member 1048a, but may be one that opens and closes a pair of blade members (so-called electric tulips), for example.

  In addition, when a game ball is driven into the right side of the stage 1055, a game nail 1018 is driven into a path along which the game ball rolls from the right side of the stage 1055 to the first starting port 1025. The game ball cannot enter the first starting port 1025 from the right side of the stage 55.

  When the game ball passes through the passing gate 1054 during the normal symbol variation display, the display mode by the normal symbol hold display LEDs 1050a and 1050b is switched, and the passing gate is displayed until the normal symbol in the variation display is stopped and displayed. Execution (start) of the normal symbol variation display based on the passage of the game ball to 1054 is suspended. After that, when the normal symbol that has been variably displayed is stopped and displayed, the variably displayed normal symbol that has been suspended is started.

  When a specific symbol is stopped and displayed as a normal symbol on the normal symbol display device 1033, an effect image for allowing the player to grasp that the normal symbol lottery is won is displayed in the display area of the liquid crystal display device 1032. You may make it do.

  In addition, a shutter 1040 that opens and closes the special winning opening 1039 is disposed immediately below the first start opening 1025. An out port 1057 is formed at the lowermost part of the game area 1015 immediately below the shutter 1040. In the lower left portion of the game area 1015, general winning ports 1056a, 1056b, and 1056c are provided. Further, a general winning opening 1056d is provided at the lower right side of the game area 1015.

  In addition, a winning area is provided in the first starting port 1025 described above. This winning area is provided with a first start winning opening switch 1116 (see FIG. 123). A winning area is provided in the second starting opening 1044, and a second starting winning opening switch 1117 (see FIG. 123) is provided in the winning area. When a game medium such as a game ball is detected by the first start winning a prize opening switch 1116, the special symbol variation display by the first special symbol display device 1035a is started.

  In addition, when a game ball enters the first start opening 1025 during the variation display of the special symbol, the game ball enters the first start aperture 1025 until the special symbol during the variation display is stopped and displayed. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started. In the following description, the special symbol variably displayed on the first special symbol display device 1035a based on the game ball entering the first start port 1025 is referred to as a first special symbol.

  Further, when a game medium such as a game ball is detected by the second start winning a prize opening switch 1117, the special symbol variation display by the second special symbol display device 1035b is started. In addition, when a game ball enters the second start opening 1044 during the variation display of the special symbol, the game ball enters the second start opening 1044 until the special symbol during the variation display is stopped and displayed. Execution (start) of the special symbol variation display based on is suspended. Thereafter, when the special symbol that has been variably displayed is stopped and displayed, the variably displayed suspended special symbol is started.

  In the following description, the special symbol variably displayed on the second special symbol display device 1035b based on the game ball entering the second start port 1044 is referred to as a second special symbol.

  Here, the first special symbol display device 1035a and the second special symbol display device 1035b do not fluctuate at the same time. Further, in the present embodiment, the special symbol variation display is performed with priority given to the start winning at the second start port 1044. Thus, the first start port 1025 and the second start port 1044 are provided in the game area of the game board 1014 and are examples of start areas through which game balls can pass.

  Note that an upper limit is set for the number of times the execution of the special symbol variation display is suspended, and in this embodiment, the variation of the special symbol due to entering the first start port 1025 and the second start port 1044. The maximum number of display holds is 4 each. Specifically, when the special symbol game of the first special symbol is held four times, the information of the special symbol game corresponding to the changing first special symbol is stored in the main RAM 1070 (see FIG. 123). The information of the four special symbol games that are stored in the one special symbol start memory area (0) as the start memory and are held are the first special symbol start memory area (1) to the first special symbol start memory area (4 ) Is stored as the start memory.

  Similarly, for the special symbol game of the second special symbol, when the special symbol game of the second special symbol is held four times, the information of the special symbol game corresponding to the changing second special symbol is the main information. The information of the four special symbol games stored and stored in the second special symbol start storage area (0) of the RAM 70 (see FIG. 123) is held in the second special symbol start storage area (1) to the second special symbol start storage area (0). 2 is stored as a start memory in the special symbol start storage area (4). Therefore, a maximum of 8 holds is possible.

  In addition, as another condition (start of variable display of a predetermined special symbol), the special symbol is stopped and displayed. In other words, every time a predetermined special symbol variable display start condition is satisfied, the special symbol variable display is started.

  When the special symbol becomes a specific stop display mode in the first special symbol display device 1035a and the second special symbol display device 1035b and the gaming state is shifted to the big hit gaming state, the shutter 1040 can easily accept the gaming ball. It is driven to be in an open state. As a result, the special winning opening 1039 is in an open state (first state) in which a game ball can be easily received.

  On the other hand, the special winning opening 1039 provided on the back side (rear side) of the shutter 1040 has an area (not shown) having a count switch 1104 (see FIG. 123), and a predetermined number of game balls (for example, 7) or the shutter 1040 is driven to open until a predetermined time (for example, about 0.1 second or about 30 seconds) elapses. When a condition for winning a predetermined number of game balls at the grand prize opening 1039 or elapse of a predetermined time is satisfied in the open state, the shutter 1040 is driven so as to be in a closed state where it is difficult to accept the game balls. . As a result, the special winning opening 1039 is in a closed state in which it is difficult to accept a game ball (second state).

  Note that a game in which the special winning opening 1039 easily accepts a game ball for a certain period of time is referred to as a round game. Therefore, the shutter 1040 is opened during the round game and is closed between the round games. A round game is counted as the number of rounds such as “1” round, “2” round, and the like. For example, the first round game may be referred to as the first round and the second round as the second round. In this embodiment, there are cases where the shutter 1040 is opened and closed a plurality of times in one round, and the time during which the shutter 1040 is in the open state is set to a certain time.

  Subsequently, the shutter 1040 driven from the open state to the closed state (second state) is driven again to the open state. That is, when the round game is finished, it is possible to continue to the next round game. A game from the first round game until the end of the (final) round game that cannot continue to the next round game is called a special game or a big hit game. In this embodiment, all the big hits are 15 rounds.

  In the embodiment, when the special symbol is in a specific stop display mode in the first special symbol display device 1035a and the second special symbol display device 1035b and the gaming state is shifted to the small hit gaming state. The shutter 1040 is driven so that the special winning opening 1039 is in an open state in which it is easy to accept the game ball 15 times or 16 times. The small hit game is a game in which the big winning opening 1039 is opened 15 times or 16 times, and there is no concept of a round game like the big win. As described above, the special winning opening 1039 and the shutter 1040 are provided on the game board 1014 and are examples of variable members that can be changed between an open state in which a game ball can easily enter and a closed state in which it is difficult to enter the game ball. It is.

  In addition, when a game ball is won in the first starting port 1025, the second starting port 1044, the general winning ports 1056a to 1056d, and the big winning port 1039, the number set in advance according to the type of each winning port. Of the game balls are paid out to the upper plate 1021 or the lower plate 1022.

  Further, in the embodiment, after the big hit game is over, the winning probability of the normal symbol lottery becomes a high probability state, and the support by the ordinary electric accessory 1048 shifts to the short-time state where the reserved balls of the special symbol game are easily stored. There is. Here, in the short-time state, passing the game ball to the passing gate 1054 is a condition for executing the normal symbol lottery, so that the game proceeds while making a right strike.

  Further, when a big hit occurs in the right-handed state, it is possible to win the big winning opening 1039 by continuing the right-handed as it is. Further, when the support by the ordinary electric accessory 1048 cannot be received, the game is advanced while making a left strike.

  Also, as shown in FIG. 120, the production buttons 1080a, 1080b, and 1080c are provided on the front surface of the upper plate 1021, and these productions are performed during a mini-game such as an open game, a card turning, and a superb game. By depressing the button, the effect display content on the liquid crystal display device 1032 can be changed.

  In addition, in the said embodiment, although the liquid crystal display device was described as an example of an effect means, this invention is not limited to this. The production means may be a production means such as a plasma display, a rear projection display, a CRT display, a lamp, a speaker, or a movable accessory.

[Electric configuration of pachinko machines]
FIG. 123 is a block diagram illustrating a control circuit of the pachinko gaming machine 1010 in this embodiment.

  As shown in FIG. 123, the pachinko gaming machine 1010 mainly includes a main control circuit 1060 that controls a game and a sub-control circuit 1200 that controls an effect according to the progress of the game.

  The main control circuit 1060 includes a main CPU 1066, a main ROM 1068 (read only memory), and a main RAM 1070 (read / write memory).

  The main CPU 1066 is connected to a main ROM 1068, a main RAM 1070, and the like, and has a function of executing various processes according to a program stored in the main ROM 1068.

  The main ROM 1068 stores a program for controlling the operation of the pachinko gaming machine 1010 by the main CPU 1066, a program for causing the main CPU 1066 to execute main processing, and various tables.

  The main RAM 1070 has a function of storing various flags and variable values as a temporary storage area of the main CPU 1066. In this embodiment, the main RAM 1070 is used as a temporary storage area of the main CPU 1066. However, the present invention is not limited thereto, and any readable / writable storage medium may be used.

  The main control circuit 1060 includes an initial reset circuit 1064 that generates a reset signal when the power is turned on, an I / O port 1071, and a command output port 1072. The initial reset circuit 1064 is connected to the main CPU 1066. The I / O port 1071 is used to transmit input signals from various devices to the main CPU 1066 and output signals from the main CPU 1066 to various devices.

  The command output port 1072 transmits a command from the main CPU 1066 to the sub control circuit 1200. The main control circuit 1060 includes a backup capacitor 1074. The backup capacitor 1074 is used to hold various data stored in the main RAM 1070 by, for example, quickly supplying power to the main RAM 1070 at the time of power interruption.

  Various devices are connected to the main control circuit 1060.

  For example, as various devices that respond to signals from the main control circuit 1060, the main control circuit 1060 includes a first special symbol display device 1035a and a second special symbol display device 1035b that perform variable display of special symbols in a special symbol game. The first special symbol hold display LEDs 1034a and 1034b and the second special symbol hold display LEDs 1034c and 1034d for displaying the number of the special symbol variable display hold in the special symbol game, and the normal symbol as the identification symbol in the normal symbol game are variably displayed. Normal symbol display device 1033, normal symbol hold display LEDs 1050a and 1050b for displaying the number of hold of the variable symbol display in the normal symbol game, and the start-port solenoid that makes the tongue-like member 1048a of the normal electric accessory 1048 project or retract. 1118, shutter 1040 Is dynamic, special winning hole solenoid 1120 such that an open state or closed state winning opening 1039 is connected.

  Further, the main control circuit 1060 has an external terminal used to transmit data to a call device (not shown) having a function of calling a hall attendant and a function of displaying the number of hits, and a hall computer managing pachinko gaming machines throughout the hall. A plate 1310 is connected.

  The main control circuit 1060 also includes, for example, a count switch 1104 that supplies a predetermined detection signal to the main control circuit 1060 when a game ball passes through an area of the big prize opening 1039, and each general winning opening 1056. When a game ball passes through the general prize opening switches 1106, 1108, 1110, 1112 and the pass gate 1054, which supply a predetermined detection signal to the main control circuit 60 when the game passes, the predetermined detection signal is sent to the main control circuit 60. When the game ball wins the passing gate switch 1114 and the first start port 1025 supplied to 1060, the first start winning port switch 1116 and the second start port 1044 that supply a predetermined detection signal to the main control circuit 1060 are played. Second start winning port switch 1117 for supplying a predetermined detection signal to the main control circuit 1060 when the ball has won, Such as backup clear switch 1124 to clear depending on the administrator of the operation of the game arcade is connected to a backup data in such.

  The main control circuit 1060 is connected to a payout / firing control circuit 1126. Connected to the payout / launch control circuit 1126 are a payout device 1128 for paying out game balls, a launch device 1130 for launching game balls, and a card unit 1300. The card unit 1300 can be transmitted / received to / from a ball lending operation panel 1155 that outputs a signal requesting the card unit 1300 to lend a game ball to the card unit 1300 by an operation of the player.

  The payout / launch control circuit 1126 receives a prize ball control command supplied from the main control circuit 1060 and a lending ball control signal supplied from the card unit 1300, and transmits a predetermined signal to the payout device 1128. The payout device 1128 is caused to pay out the game ball. Further, the payout / firing control circuit 1126 supplies electric power to the firing solenoid according to the turning angle when the launching handle 1026 is gripped by the player and is turned clockwise. Control to fire the ball.

  Further, the sub control circuit 1200 is connected to the command output port 1072. The sub control circuit 1200 performs display control in the liquid crystal display device 1032, control related to sound generated from the speaker 1046, control of lamps including a decoration lamp, and the like in accordance with various commands supplied from the main control circuit 1060. . The sub control circuit 1200 has the same configuration as that of the sub control circuit 70 described in the above-mentioned pachislot machine, and can execute various processes. Furthermore, a sub device such as a scaler control board 77 may be connected to the sub control circuit 1200 in the same manner as the sub control circuit 70 of the pachislot machine.

  In this embodiment, a command is supplied from the main control circuit 1060 to the sub control circuit 1200 and a signal cannot be supplied from the sub control circuit 1200 to the main control circuit 1060. However, the configuration may be such that a signal can be transmitted from the sub control circuit 1200 to the main control circuit 1060.

  As described above, according to the pachinko gaming machine according to the present embodiment, the same effects as those of the pachislot gaming machine according to the above embodiment can be obtained.

DESCRIPTION OF SYMBOLS 1 Game machine 1a Case 1b Front door 2 Door key 3L, 3C, 3R Reel 4L, 4C, 4R Symbol display area (design display means)
5 Liquid crystal display device (display means)
6S start switch (start operation detection means)
7LS, 7CS, 7RS Stop switch (stop operation detection means)
23 Liquid crystal display area 31 Main CPU (internal winning combination determining means, command transmitting means)
39 Motor drive circuit (design variation means, stop control means)
49L, 49C, 49R Stepping motor (design variation means, stop control means)
50 Reel position detection circuit (design variation means, stop control means)
60, 1060 main control circuit (main control unit)
70, 1200 Sub control circuit (sub control unit)
71 Sub CPU (effect content determining means, effect control means, command receiving means, processing means)
71a Communication error detection means (error detection means)
71b Procedure detection means 71c Data destruction detection means 71d Error information registration means 71e Received data log storage means 71f Error information history display means 71g Two-dimensional code conversion means 71h Sub-device error detection means 72 Sub-ROM
72a OS area 72b Sub-control program area 72c Game data initialization setting data area 72d Personnel operation initialization data area 72e Various program table areas 72f Program management data area 72g Image data (still image / moving image)
72h Sound data 72i Actuator movable data 73-1 DRAM (storage unit)
73a-1 Sub-control game data area (game data storage area)
73b-1 Sub-control game data sum value area 73c-1 Work area 73d-1 Error information history storage area 73e-1 Communication log collection ring buffer area 73f-1 Communication error storage area (buffer)
73-2 SRAM
73a-2 Backup data 1 area 73b-2 Backup data 1 sum value 73c-2 Backup data 2 area 73d-2 Backup data 2 sum value 73e-2 Staff backup data area 73f-2 Error information history storage area 73g-2 Staff backup Data sum value 74 GPU
75 VRAM
76 Serial communication relay board 77 Scaler control board 300 Two-dimensional code 400 Mobile communication terminal with camera (mobile terminal)
500 Data management server (server)
600 PC for analysis (analysis means)

Claims (1)

A main control unit that executes processing relating to the progress of the game;
A display unit for displaying predetermined information;
A scaler control board capable of selecting the size of the original information of the predetermined information displayed on the display unit;
A sub-control unit that controls an effect according to the progress of the game based on a command output from the main control unit;
The sub-control unit, sub-device reception interrupt means for receiving transmission data from the scaler control board,
Sub-device error detection means for detecting a communication disconnection error different from the case where there is an abnormality in the received data from the scaler control board when there is no communication from the scaler control board for a predetermined time;
The communication disconnection error detected by the subdevice error detection unit is stored as communication disconnection error information, and after the subdevice error detection unit detects the communication disconnection error, the sub-control unit detects from the scaler control board. When receiving communication, an error storing that the communication has been received as communication return error information different from when there is no communication for a predetermined time from the scaler control board and when there is an abnormality in received data from the scaler control board A storage unit having an information history storage area,
The sub-device reception interrupt means discards the reception data without storing it when there is a physical layer error in the transmission data from the scaler control board,
The sub-device error detection means determines that there is no communication from the scaler control board even when the sub-device reception interrupt means discards the received data.
The sub device error detecting means detects the case where there is no communication from the scaler control board for a predetermined time as the communication disconnection error, and then stores the communication disconnection error information in the error information history storage area, and the sub control unit However, when it is determined whether or not there is a next communication from the scaler control board, and it is determined that the next communication has been received from the scaler control board, the communication return to the error information history storage area is performed. Error information history storage means for storing error information;
A gaming machine comprising: error information history display means for displaying the communication interruption error information and the communication return error information stored by the error information history storage means on the display unit.

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