JP5828256B2 - Data transfer control device, data transfer control method, and data transfer control system - Google Patents

Description

  The present invention relates to a data transfer control device, a data transfer control method, and a data transfer control system.

  In a computer system, a packet used for transferring data in a system generally includes a packet type field indicating a packet control type, a destination field indicating a destination, a requester field indicating a request source, and an address. Address field to indicate. Normally, all packets contain information on each field as a packet header. For example, even when a large amount of data is transferred in units of short packets such as DMA (Direct Memory Access), the same packet header is included in all packets. That is, the transfer of the packet header consumes a part of the throughput of the transfer path. For this reason, there is a problem that the transfer path cannot fully exhibit the data transfer capability.

  In the present application, data includes information to be processed such as characters, symbols, and numerical values, and control information for controlling information on each field, packet transfer, and the like.

  On the other hand, a method of increasing the packet length of the packet and reducing the overhead of header transfer is also conceivable. However, in the case of a computer system that shares the same transfer path for a plurality of data transfers, increasing the time during which a specific packet occupies the transfer path has a problem of deteriorating the latency performance of other packets. For this reason, it is often required to transfer a packet used for transferring data other than the control information as a packet having a relatively short packet length (for example, about 64 bytes).

  It is also conceivable to compress a part of the header or data to be transferred. As one compression technique, there is a technique for compressing data using a static or dynamic dictionary (for example, Patent Document 1). In the dictionary compression method described in Patent Document 1, when a character string to be transferred exists in the dictionary, a dictionary pointer (or index) is transmitted instead of the character string. In this case, if the size of the pointer is smaller than the size of the replaced character string, a compression effect can be obtained. When using a dynamic dictionary, when a new character string is transferred, the same new character string is added to the same position in the data compression side dictionary and the expansion side dictionary, and the dictionary is updated. (For example, paragraph 0013). Further, Patent Document 1 discloses a technique using sliding window compression as another dictionary compression method (for example, paragraph 0014). In sliding window compression, character strings are compared while moving a sliding window of a fixed size, and if they match, replacement with a dictionary pointer (or reference) is performed.

JP-T-2004-514366

  By the way, with the dictionary compression technique described in Patent Document 1, when the data to be compressed completely matches the data registered in the dictionary, the data can be replaced using the dictionary pointer. . Therefore, for example, when there are many types of target data, it is necessary to increase the number of data registrations in the dictionary in order to increase the probability that the data can be replaced using the dictionary pointer. However, when the size of the dictionary increases, the time required for comparison becomes longer when the input data to be compressed and the registered data are sequentially compared. Further, when comparing input data and registered data in parallel, the configuration of a comparator or the like increases.

  An object of the present invention is to provide a data transfer control device, a data transfer control method, and a data transfer control system that can solve the above-described problems.

The present invention has been made to solve the above-described problem. A data transfer control device according to an aspect of the present invention provides a plurality of predetermined pieces of entry registration information indicating compression target attributes for a plurality of sections. Storage means for storing each entry configured by the section; first comparing means for comparing, for each entry, whether the input information matches the entry registration information for each entry; Based on the comparison result of the second comparison means and the second comparison means , the result of adding the data lengths of the divisions that match in the comparison result by the first comparison means for each entry is compared between the entries. First information representing the selected entry and second information representing at least one of the classifications in which the entry registration information and the input information of the selected entry match. , And a compression means for compressing the input information by using the third information representing the input information corresponding to the segment that does not match in said entry registration information of the selected entries and the input information.

The present invention has been made in order to solve the above-described problem, and a data transfer control method according to an aspect of the present invention provides a plurality of predetermined pieces of entry registration information indicating attributes to be compressed for each of a plurality of sections. A first comparison step that compares, for each entry, whether the input information matches the entry registration information for each entry , with reference to storage means for storing each entry configured by the section; The comparison result of the second comparison step and the comparison result of the second comparison step are the results of adding, for each entry, the data lengths of the sections that match in the comparison result of the first comparison step. At least one of the first information representing the entry selected based on the entry registration information and the input information corresponding to the selected entry The input information is compressed using second information representing the classification and third information representing the input information corresponding to the classification that does not match the entry registration information and the input information of the selected entry. A compression step .

The present invention has been made to solve the above-described problem, and a data transfer control system according to an aspect of the present invention provides a plurality of predetermined pieces of entry registration information indicating attributes to be compressed for each of a plurality of sections. Storage means for storing each entry configured by the section; first comparing means for comparing, for each entry, whether the input information matches the entry registration information for each entry; Based on the comparison result of the second comparison means and the second comparison means , the result of adding the data lengths of the divisions that match in the comparison result by the first comparison means for each entry is compared between the entries. A first information representing the selected entry and a second information representing at least one of the classifications in which the entry registration information and the input information of the selected entry match. Compression means for compressing the input information using information and third information representing the input information corresponding to the classification that does not match the entry registration information and the input information of the selected entry, and the compression A transmission means for transmitting transfer information obtained by compressing the input information by the means; a reception means for receiving the transfer information transmitted by the transmission means; A second storage means for storing information classified into a plurality of entries, and the entry corresponding to the first information in the second storage means based on the transfer information received by the receiving means; and The information to be compressed is restored using the first partition information stored in the partition corresponding to the second information and the second partition information represented by the third information. And a data receiving unit and a source unit.

  According to the present invention, even if all of the input information to be compressed and all of the registered information for each entry do not match, a part of the information to be compressed and the storage means (that corresponds to the compression dictionary) If any of the entries in () match, it is possible to generate transfer information using the first information (that is, a pointer) representing the entry by the compression means. Therefore, the probability that data can be replaced using a pointer can be increased without increasing the number of entries in the storage means (that is, the number of registered data) as compared with the case where all matches are requested.

It is a block diagram which shows the structure of one embodiment of this invention. It is a figure which shows the structural example of the packet header of the normal packet and compression packet which are used by embodiment of FIG. It is a block diagram which shows the structural example of the compression dictionary table process part by the side of the transmission in embodiment of FIG. 3 is a flowchart illustrating an operation example of the packet generation logic of FIG. 1. 6 is a chart for explaining an operation example of a packet transmission side LSI in the embodiment of FIG. 1. It is a block diagram which shows the structural example of the compression dictionary table process part of the receiving side in embodiment of FIG. 3 is a chart for explaining an operation example of a packet receiving side LSI in the embodiment of FIG. 1; It is a schematic diagram for demonstrating the operation example of embodiment of FIG. FIG. 2 is a block diagram schematically showing the embodiment of FIG. 1 collectively for each main function.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a data transfer control device according to the present invention, and FIG. 2 is a configuration example of a normal packet header and a compressed packet header used in the embodiment of FIG. It is a schematic diagram shown. First, referring to FIG. 2, an uncompressed normal packet header (hereinafter referred to as a normal packet header) used in the embodiment of the present invention, and a packet header of a compressed packet (hereinafter referred to as a compressed packet header). An example of the format will be described. Of the packets transferred in this embodiment, a packet whose packet header is a normal packet header is a normal packet, a packet whose packet header is a compressed packet header is a compressed packet, and is restored from a normal packet or a compressed packet. The packet is called a restoration packet. Note that data that is the contents of the packet is stored behind the packet header. That is, the packet header is attribute information indicating an attribute of data that is the content of the packet.

  Referring to FIG. 2, the normal packet header 10000 shown in FIG. 2A includes a packet identifier field 10001, a packet type field 10002, a destination field 10003, a requester field 10004, an address field 10005, and other fields 10006. Has been. The address field 10005 includes an address upper field 10007, an address middle field 10008, and an address lower field 10009.

The packet identifier field 10001 is a 1-bit field that holds an identifier indicating whether or not the packet is a compressed packet. In the present embodiment, when the identifier “1” is stored in the packet identifier field 10001, this indicates a compressed packet. Further, when the identifier “0” is stored in the packet identifier field 10001, it indicates that the packet is a normal packet.
The packet type field 10002 is a field indicating the packet type.
The destination field 10003 is a field indicating the packet destination (link destination).
The requester field 10004 is a field indicating request source information.
The address field 10005 is a field indicating an address related to the transfer destination of the normal packet header 10000. That is, information indicating the transfer destination address of the normal packet is stored. The address field 10005 includes an address upper field 10007, an address middle field 10008, and an address lower field 10009. The upper address field 10007, the middle address field 10008, and the lower address field 10009 are fields obtained by dividing the address field 10005 by a predetermined number of bits, and are fields indicating upper, middle, and lower addresses of the predetermined number of bits. .
The other field 10006 is a field indicating other field information.

The compressed packet header 11000 shown in FIG. 2B includes a packet identifier field 11001, an entry number field 11002, a replacement information field 11003, and a mismatch field 11004.
The packet identifier field 11001 is a 1-bit field that holds an identifier indicating whether or not the packet is a compressed packet. In the present embodiment, when the identifier “1” is stored in the packet identifier field 10001, this indicates a compressed packet. Further, when the identifier “0” is stored in the packet identifier field 10001, it indicates that the packet is a normal packet.
The entry number field 11002 is a field indicating the position of the entry processing unit 31000 (i) in the compression dictionary table processing unit 20220. The compression dictionary table processing unit 20220 includes hardware resources that can be used as a plurality of entry processing units 31000 (i) allocated for each entry. Each entry processing unit 31000 (i) is assigned according to the usage status of each entry processing unit 31000 (i) in the hardware resource. The entry indicates a packet header unit registered in the compression dictionary table processing unit 20220.
The replacement information field 11003 is a field indicating a compressed field among the fields included in the packet header.
The mismatch field 11004 is a field that indicates an uncompressed field among the fields included in the packet header. Note that the information stored in the field that could not be compressed is added to the end of the packet as the uncompressed information.

Next, the configuration of an embodiment of the data transfer control device according to the present invention will be described with reference to FIG. Referring to FIG. 1, the data transfer control device according to an embodiment of the present invention is configured as a packet transmission unit 20200 in a packet transmission side LSI (Large Scale Integration) 20000.
The packet transmission side LSI 20000 is connected to the packet reception side LSI 21000 via a SerDes (Serializer / Deserializer) 22000 which is an interface between LSIs. Packet transfer between the packet transmission side LSI 20000 and the packet reception side LSI 21000 is serially transferred by the SerDes 22000.

The packet transmission side LSI 20000 includes a requester 20100, a packet transmission unit (data transfer control device) 20200, and a SerDes transmission unit 20300.
The requester 20100 executes a packet generation process for generating a normal packet. In the present embodiment, the requester 20100 divides transmission entity data to be transmitted to the packet receiving side LSI 21000 into a plurality of pieces. The requester 20100 writes each of the divided transmission entity data in a portion in which normal packet content data including a normal packet header 10000 is stored. Thereby, the requester 20100 generates a normal packet.

The packet transmission unit 20200 executes transmission processing for transmitting the normal packet generated by the requester 20100 to the receiving-side LSI 21000 and packet compression processing for compressing the packet header of the normal packet as necessary. The packet transmission unit 20200 outputs a compressed packet to the SerDes transmission unit 20300 when the packet compression process is executed, and a normal packet when the packet compression process is not executed.
The SerDes transmission unit 20300 converts the normal packet or the compressed packet output from the packet transmission unit 20200 into serial data, and transmits the serial data to the SerDes 22000.

On the other hand, the packet receiving side LSI 21000 includes a SerDes receiving unit 21100, a packet receiving unit 21200, and a target 21300.
The SerDes reception unit 21100 receives serial data from the packet transmission side LSI 20000 via the SerDes 22000 and packetizes it.
The packet receiving unit 21200 receives a packet via the SerDes 22000. When the received packet is a compressed packet, the packet receiving unit 21200 executes a restoration process for restoring the compressed packet and outputs the restored packet to the target 21300. Further, when the received packet is a normal packet, the packet reception unit 21200 outputs the normal packet as it is without executing the restoration process for restoring the packet.
The target 21300 receives the restoration packet or the normal packet output from the packet receiving unit 21200, and executes a predetermined process on the received packet.

The packet transmission unit 20200 in the packet transmission side LSI 20000 described above includes a normal packet holding register 20210, a compression dictionary table processing unit 20220, and a packet compression logic circuit 20230.
The normal packet holding register 20210 is a storage area that temporarily holds the normal packet received from the requester 20100 until the timing at which the normal packet is output to the SerDes transmission unit 20300.
The normal packet holding register 20210 compresses the information stored in each field of the normal packet header 10000 from the information stored in the normal packet input from the requester 20100 at the timing when a valid normal packet is held. The data is output to the dictionary table processing unit 20220 via the signal line 20241.
Similarly, the normal packet holding register 20210 outputs information stored in the normal packet input from the requester 20100 to the packet compression logic circuit 20230 at the timing when a valid normal packet is held. In other words, the normal packet holding register 20210 stores information stored in all fields of the normal packet (that is, information stored in all fields of the normal packet header 10000 and the normal packet header 10000 included in the normal packet). The information stored in all fields) is output to the packet compression logic circuit 20230 through the signal line 20242.

  The compression dictionary table processing unit 20220 includes a plurality of logic circuits, registers, and the like. Based on information stored in a packet header that passes, a compression target field used for compression processing by the packet compression logic circuit 20230 is stored. Judge whether it is registered or not. The compression dictionary table processing unit 20220 is registered in a register containing dictionary data to be referred to when a field to be compressed is searched. That is, the compression dictionary table processing unit 20220 has a table that functions as a dictionary for searching for a feed to be compressed. When the compression dictionary table processing unit 20220 obtains a feed to be compressed by a search, the compression dictionary table processing unit 20220 determines to compress the feed. On the other hand, when the feed that is the compression target cannot be detected by the search, the compression dictionary table processing unit 20220 determines not to execute the compression process.

  The compression dictionary table processing unit 20220 has a function of outputting an entry number indicating an entry to be used when it is determined to compress and replacement information indicating which field in the entry is used during compression. doing. The table functioning as a compression dictionary included in the compression dictionary table processing unit 20220 stores a plurality of sets of data expected to be stored in the normal packet header 10000 in a form that can be compared, selected, and rewritten in units of fields. . Each set of data in the table corresponds to one normal packet header 10000. The storage position of each set of data is indicated by a predetermined one entry number. In the present embodiment, each set of data in the table is a circuit block called an entry having one set of registers (or a certain range of storage areas) for storing one set of data corresponding to one normal packet header 10000. Is remembered.

  The packet compression logic circuit 20230 has a function for determining whether or not to compress based on the entry number and replacement information output from the compression dictionary table processing unit 20220, and generates a compressed packet header when it is determined to compress. At the same time, it has a function of replacing the generated compressed packet header with the normal packet header 10000 in the normal packet to synthesize the compressed packet. Also, the packet compression logic circuit 20230 outputs information representing the result of determination as to whether or not to compress to the compression dictionary table processing unit 20220 using the signal line 20245 as compression information. The packet compression logic circuit 20230 has a function of outputting the generated compressed packet or the normal packet that has not been compressed to the SerDes transmission unit 20300.

  Now, a detailed configuration example of the compression dictionary table processing unit 20220 in the packet transmission side LSI 20000 will be described with reference to FIG. FIG. 3 shows only the storage area of the normal packet holding register 20210 that holds the normal packet header 10000. In FIG. 3, the normal packet holding register 20210 includes a packet identifier field 10001, a packet type field 10002, a destination field 10003, a requester field 10004, an address high-order field 10007, an address that constitute the normal packet header 10000 shown in FIG. It has a plurality of registers (storage areas) 20211 to 20214, 20217 to 20219, and 20216 that temporarily hold data stored in the middle field 10008, the address lower field 10009, and the other fields 10006. .

  The compression dictionary table processing unit 20220 shown in FIG. 3 includes a plurality of entry processing units 31000 (i), a bit width comparison logic circuit 32000, a match information selection circuit 33000, a counter control circuit 34000, and a registration destination selection circuit 35000. And have. Each entry processing unit 31000 (i) has the same configuration. Each entry processing unit 31000 (i) is assigned an entry number (i) which is unique identification information (or position information).

  The compression dictionary table processing unit 20220 assigns an entry number (i) to each piece of information stored in the passing normal packet header 10000, and includes hardware resources including a comparator and a register used as the entry processing unit 31000 (i). Is assigned the functional configuration of the entry processing unit 31000 (i). That is, the compression dictionary table processing unit 20220 determines whether or not the entry processing unit 31000 (i) corresponding to the information stored in the normal packet header 10000 input from the call packet holding register 20210 is assigned. When the corresponding entry processing unit 31000 (i) is not assigned, the compression dictionary table processing unit 20220 applies the entry processing unit 31000 (for the hardware resource not functioning as the entry processing unit 31000 (i). i) Assign. The processing performed by the compression dictionary table processing unit 20220 is hereinafter referred to as compression dictionary table processing unit registration processing.

  If the entry processing unit 31000 (i) corresponding to the information stored in the passing normal packet header 10000 is registered, the compression dictionary table processing unit 20220 is registered in the entry processing unit 31000 (i). On the basis of the collation result between the stored information and the information stored in the normal packet header 10000, a part of the information in the normal packet header 10000 is compressed. Hereinafter, the processing performed by the compression dictionary table processing unit 20220 is referred to as compression processing.

  The entry processing unit 31000 (i) includes a Valid register 31100, a registration packet information register 31200, a coincidence counter 31300, seven comparators 31401 to 1407, a bit width adder 31500, and a bundling circuit 31600. Yes. The entry processing unit 31000 (i) is a processing unit that is assigned to hardware resources including a comparator and a register for each entry number (i) registered by the compression dictionary table processing unit registration process.

  The Valid register 31100 stores 1-bit data indicating validity / invalidity of each entry processing unit 31000 (i). The Valid register 31100 stores, for example, data corresponding to the entry processing unit 31000 (i) registered after information registered in the hardware resource used as the entry processing unit 31000 (i) is initialized. In the state before being stored, information “0” indicating invalidity is stored. The valid register 31100 is assigned an entry processing unit 31000 (i) corresponding to the passed normal packet header 10000, and information stored in the normal packet header 10000 is registered (stored) in the registered packet information register 31200. In this state, information “1” indicating that it is valid is stored.

The registration packet information register 31200 stores entry registration information indicating attributes to be compressed for each of a plurality of fields (sections). For example, the registration packet information register 31200 is a register (or a register) that holds entry registration information stored in each field excluding the packet identifier field 10001 in the feed included in the normal packet header 10000 so that it can be read and written in units of fields. Storage area) 31201 to 1207.
Each register 31201 to 1207 indicates packet type information indicating the packet type, destination information indicating the destination, and request source information, which are data of each field 10002 to 10004, 10007 to 10009 and 10006 of the normal packet header 10000. Requester information, address high-order information indicating a high-order address, address medium-level information indicating a middle-order address, address low-order information indicating a low-order address, and other information indicating other field information are held. In each of the registers 31201 to 3207, the data held in the registers 20211 to 20214, 20217 to 20219, and 20216 of the normal packet holding register 20210 in the compression dictionary table processing unit registration process is fetched when a predetermined condition is satisfied. , Retained.

The coincidence counter 31300 is a counter that holds the number of times packet compression has been performed using entry registration information.
The match counter 31300 stores “0” in the initial state. The match counter 31300 stores information “1”, “2”,... Incremented by one when packet compression is performed using entry registration information.

The comparators 31401 to 1407 are information stored in each register of the normal packet holding register 20210 (hereinafter referred to as input information) and information (entry registration information) stored in each register 31201 to 31206 of the registered packet information register 31200. ) For each corresponding field, and a comparator that determines whether or not the input information of the normal packet holding register 20210 matches the entry registration information of the registered packet information register 31200 in at least one field. is there.
The comparators 31401 to 1407 compare the input information stored in the corresponding field included in the normal packet holding register 20210 with the entry registration information stored in the corresponding field included in the registration packet information register 31200, 1-bit data representing the presence or absence of a match is output for each field. For example, when the input information of the normal packet holding register 20210 matches the entry registration information of the registered packet information register 31200, the comparators 31401 to 1407 output “1”. On the other hand, if the input information of the normal packet holding register 20210 and the entry registration information of the registered packet information register 31200 do not match, the comparators 31401 to 1407 output “0”.

Bundled wire circuit 31600 is a result of bundling the outputs of all comparators 31401-31407, as the comparison result of the entry processing section 31000 (i) (as matching information _{G i} in this case), entry processing unit 31000 of the (i) Output outside. In this case, bundled wire circuit 31600 outputs matching information _{G i} of 7 bits are bundled output of seven comparators 31401-31407. The output representing the comparison result of each of the comparators 31401 to 1407 is also input to the bit width adder 31500.

The bit width adder 31500 adds the bit width values of the matched fields based on the outputs of the respective comparators 31401 to 1407, and performs entry processing as the matching bit width information H _i of each entry processing unit 31000 (i). Output outside the unit 31000 (i). For example, it is assumed that the bit width of the packet type field 10002 of the normal packet header 10000 is 7 bits and the bit width of the destination field 10003 is 5 bits. Also, the input information stored in the packet type register 20212 matches the entry registration information stored in the packet type register 31201, and the input information stored in the destination register 20213 matches the destination register 31202. Assume that the stored entry registration information matches. Furthermore, it is assumed that the input information stored in the register of the other field and the entry registration information do not match. In this case, the output (match bit width information H _i ) of the bit width adder 31500 is a match bit width “12” obtained by adding the bit width “7” of the packet type field and the bit width “5” of the destination field. It becomes. Further, the bit width adder 31500 is, when the state in which not match in any of the comparators 31401 to 31407 was not detected, and outputs "0" as the matching bit width information _{H i.}

The bit width comparison logic circuit 32000 is a composite circuit of various logic circuits such as a comparator, a selector, and a counter. The bit width comparison logic circuit 32000 compares the matching bit width information H _{i of} each entry output from each entry processing unit 31000 (i), and based on the comparison result, the entry processing unit 31000 (maximum matching bit width). The entry number (i) indicating i) is output.
However, when there are a plurality of entry processing units 31000 (i) having the matching bit width information H _i having the same maximum value, the bit width comparison logic circuit 32000 selects, for example, the entry number (i) having the smallest number. Output. Alternatively, the bit width comparison logic circuit 32000 outputs the entry number (i) having the largest value of the coincidence counter 31300 among the entry processing units 31000 (i) having the coincidence bit width information H _i having the same maximum value. You may make it do. Also, the bit width comparison logic circuit 32000, when a value having a bit width equal to or larger than the value corresponding to the bit width of at least one field is not input from any entry processing unit 31000 (i), that is, each entry processing If no matching state is detected in any of the comparators 31401 to 1407 of the section 31000 (i), the entry number (eg, 0 or negative) indicating that there is no valid entry number (i). (Hereinafter referred to as an invalid entry number). The entry number output from the bit width comparison logic circuit 32000 is an entry number when a packet held in the normal packet holding register 20210 is converted into a compressed packet header 11000 (see FIG. 2) (ie, compressed). The value is stored in the number field 11002.

Matching information selection circuit 33000 is based on the type of the matching information _{G i} output from the beam line circuit 31600, entry number output from the bit width compare logic 32000 (i) for each entry processing unit 31000 (i) Then, the output (match information G _i ) of the bundling circuit 31600 of the entry processing unit 31000 (i) designated by the entry number (i) is selected and output as replacement information S _i . The replacement information S _i output from the match information selection circuit 33000 is used when a packet held in the normal packet holding register 20210 is converted into a compressed packet header 11000 (see FIG. 2) (that is, when compressed). This value is stored in the replacement information field 11003. When the invalid entry number is output from the bit width comparison logic circuit 32000, the coincidence information selection circuit 33000 outputs replacement information S _i with all bits set to 0 (that is, a value indicating that no replacement is performed). .

  Further, the counter control circuit 34000 uses the entry number (i) output from the bit width comparison logic circuit 32000 and the compression information input from the packet compression logic circuit 20230 to use the packet using the entry number (i). When compression is performed, the match counter 31300 of the entry processing unit 31000 (i) designated by the entry number (i) (that is, determined as the entry having the largest match bit width) is selected and selected. The value of the coincidence counter 31300 is incremented by 1.

The registration destination selection circuit 35000 is a circuit that controls updating of the value in the registration packet information register 31200 of each entry processing unit 31000 (i) 0. The registration destination selection circuit 35000 receives the value of the Valid register 31100 and the count value of the match counter 31300 in each entry processing unit 31000 (i), and the compression information output from the packet compression logic circuit 20230.
When the registration destination selection circuit 35000 first detects that compression processing has not been performed based on the compression information input from the packet compression logic circuit 20230, the registration destination selection circuit 35000 matches the value of the Valid register 31100 and the count value of the coincidence counter 31300. Based on the above, one entry processing unit 31000 (i) is selected. Here, the case where the compression processing is not performed in the packet compression logic circuit 20230 means that the packet compression logic circuit 20230 does not generate a compressed packet header and outputs a normal packet. In this case, when a normal packet is received on the receiving side, the entry registration information update process of the compression dictionary table processing unit 21220 on the receiving side is performed. Therefore, the compression dictionary table processing unit 20220 on the transmission side also updates the entry registration information. Update process needs to be implemented.

If there is an entry processing unit 31000 (i) in which the value of the Valid register 31100 is invalid (if there is an entry processing unit 31000 (i) for which data is not yet registered), the entry processing is invalid. One of the units 31000 (i) is selected by the registration destination selection circuit 35000.
When there are a plurality of invalid entry processing units 31000 (i), for example, the entry processing unit 31000 (i) having the lowest entry number (i) is selected by the registration destination selection circuit 35000. On the other hand, when there is no entry processing unit 31000 (i) whose value of the Valid register 31100 is invalid, one of the entry processing units 31000 (i) having the smallest count value of the match counter 31300 is selected by the registration destination selection circuit 35000. Is done.

When there are a plurality of entry processing units 31000 (i) having the smallest count value, for example, the entry processing unit 31000 (i) having the smallest entry number (i) is selected by the registration destination selection circuit 35000. Then, the registration destination selection circuit 35000 then stores in the registration packet information register 31200 of the entry processing unit 31000 (i) selected based on the value of the Valid register 31100 and the count value of the match counter 31300, to the normal packet holding register 20210. Register retained data. That is, the data held in the registers 20212 to 20214, 20217 to 20219, and 20216 of the normal packet holding register 20210 is stored in the registers 31201 to 1207 of the registered packet information register 31200.
Also, the registration destination selection circuit 35000 sets the value of the Valid register 31100 of the entry processing unit 31000 (i) selected based on the value of the Valid register 31100 and the count value of the match counter 31300 to be valid and Clear the count value to zero.

  In this way, when the packet compression logic circuit 20230 does not perform compression processing, the normal packet header 10000 that does not at least partially match the information in the compression dictionary table processing unit 20220 is stored in the normal packet holding register 20210. When it passes, it is taken into the invalid entry or the entry processing unit 31000 (i) of the compression dictionary table processing unit having the smallest count value. That is, when the compression processing is not performed in the packet compression logic circuit 20230, the information of the normal packet header 10000 to be passed is not registered in the compression dictionary table processing unit 20220, so that the compression dictionary table processing unit 20220 passes the normal Information of the packet header 10000 is registered as entry registration information in the registration packet information register 31200 for each corresponding field.

  Next, the operation of the packet compression logic circuit 20230 of the packet transmission side LSI shown in FIG. 1 will be described with reference to FIG. 4 and FIG. FIG. 4 is a flowchart showing an example of the flow of processing by the packet compression logic circuit 20230. FIG. 5 is a chart for explaining an operation example. In the chart of FIG. 5, information corresponding to seven types of operation examples of case numbers 1 to 7 is shown.

  In the example of FIG. 5, the field length of the normal packet header 10000 is 64 bits. The field length of the packet identifier field 10001 is 1 bit. The field length of the packet type field 10002 is 7 bits. The field length of the destination field 10003 is 5 bits. The field length of the requester field 10004 is 5 bits. The field length of the upper address field 10007 is 22 bits. The field length of the middle address field 10008 is 9 bits. The field length of the address lower field 10009 is 8 bits. The field length of the other field 10006 is 7 bits.

  The bit length of the entry number (i) is 8 bits. In this case, for example, the entry number (0) can be used as an invalid entry number, and i = 1 to 255 can be used as a valid entry number (i).

Each bit of the replacement information S _i is set to “1” when the comparison results of the comparators 31401 to 1407 in FIG. 3 match and “0” when they do not match. For example, in case number 1, all 7 bits of the replacement information S _i are “1”. In this case, all the comparison results in the seven comparators 31401 to 1407 in FIG. 3 are in agreement.

Now, assuming that the normal packet holding register 20210 receives a packet from the requester 20100, the packet compression logic circuit 20230 first receives the replacement information S received from the compression dictionary table processing unit 20220 using the signal line 20244. _i set to the effect it is possible to carry out the replacement, ie whether (in the above example 1) a value indicating that it is possible to perform the replacement on one of bit replacement information S _i is set Is determined (step S11 in FIG. 4). When the packet compression logic circuit 20230 determines that the replacement information S _i is set (in the case of “yes” in step S11), the packet compression logic circuit 20230 calculates the number of bits of the compressed packet head based on the value of each bit of the replacement information S _i. Calculate (step S12).

For example, as in case number 1 in FIG. 5, when all the 7 bits constituting the replacement information S _i are 1, that is, in the entry processing unit 31000 (i) of any entry number (i) When a match is detected by the comparators 31401 to 1407, the data of each field held in the registered packet information register 31200 of the entry processing unit 31000 (i) and the corresponding data held in the normal packet holding register 20210 All the data in each field match. In this case, the total number of coincidence bits is 63 bits (that is, a value obtained by subtracting 1 bit of the packet identifier field 10001 from 64 bits of the normal packet header 10000). In this case, since the mismatch field 11004 is 0 bits, the compressed packet header 11000 has a total of 16 bits including a 1-bit packet identifier field 11001, an 8-bit entry number field 11002, and a 7-bit replacement information field 11003. Will be composed. Incidentally, in this case, the packet receiving side LSI 21000 uses only the information of the entry number (i) stored in the entry number field 11002 in the compressed packet header 11000 (that is, without the replacement information S _i ) before the normal packet before compression. The same data as the header 10000 can be restored.

Further, for example, as in case number 2 in FIG. 5, the five bits constituting the replacement information S _i are 1, and the two bits corresponding to the address lower field 10009 and the other fields 10006 are 0. Suppose.
In this case, in the entry processing unit 31000 (i) of any entry number (i), a match is detected by the five comparators 31401 to 1405, and a mismatch is detected by the two comparators 31406 to 31407. That is, in this case, the data of each field held in the registered packet information register 31200 of the entry processing unit 31000 (i) is compared with the data of each corresponding field held in the normal packet holding register 20210 as follows. become that way. That is, the data held in the registers 31201 to 1205 excluding the data held in the register 31206 that holds the address lower information indicating the lower address and the register 31207 that holds the other information indicating other field information. Matched.

  In this case, the total number of matching bits is 48 bits (that is, from the bit width of 64 bits of the normal packet header 10000 to 1 bit of the packet identifier field 10001, 8 bits of the address lower field 10009, and 7 bits of the other field 10006). Reduced value). In this case, in the compressed packet header 11000, 8-bit data in the address lower field 10009 and 7-bit data in the other field 10006 are stored in the mismatch field 11004. That is, the total number of bits in the mismatch field 11004 is 15 bits. Therefore, the compressed packet header 11000 is composed of a total of 31 bits including a 1-bit packet identifier field 11001, an 8-bit entry number field 11002, a 7-bit replacement information field 11003, and a 15-bit other field 10006. Will be.

Similarly, in the examples of case numbers 3, 4, 5, 6, and 7 in FIG. 5, the total number of bits of the compressed packet header 11000 is 24, 46, 51, 56, and 63 bits.
Here, the case number 3 is a register 31205 that holds address middle information indicating a middle address, a register 31206 that holds address lower information indicating a lower address, and a register that holds other information indicating other field information. This corresponds to an example in which the data held in 31207 does not match.
Case number 4 corresponds to an example in which the data held in the register 31204 holding the address high-order information indicating the high-order address does not match, in addition to the registers 31205 to 31207 that do not match the case number 3.
Case number 5 corresponds to an example in which the data held in the register 31203 holding the requester information indicating the information of the request source is inconsistent in addition to the registers 31204 to 31207 that are not matched in the case number 4. .
Case number 6 corresponds to an example in which the data held in the register 31202 that holds the destination information indicating the destination is inconsistent in addition to the registers 31203 to 31207 that are not matched in the case number 5.
Case number 7 corresponds to an example in which the data held in the register 31201 holding the packet type information indicating the packet type is inconsistent in addition to the registers 31202 to 31207 that are not matched in the case number 6.

  Next, the packet compression logic circuit 20230 compares the number of bits of the compressed packet header, that is, the compressed packet header, with the number of bits of the non-compressed packet header, that is, the normal packet header 10000 (step S14). For example, in the example shown in FIG. 5, the packet compression logic circuit 20230 compares the number of bits of the compressed packet header obtained in step S13 with the number of bits of the normal packet header 10000 of 64 bits.

As a result of the comparison in step S13, if the number of bits in the compressed packet header, ie, the compressed packet header, is smaller than the number of bits in the non-compressed packet header, ie, the normal packet header 10000 (in the case of “yes” in step S14), The packet compression logic circuit 20230 generates a compressed packet header 11000 based on the entry number (i), the replacement information S _i, and the normal packet header 10000 (step S15). In step S15, compressed information indicating that the packet header 11000 has been generated is output.

As described above, in the example of case number 1 in FIG. 5, the number of bits of the compressed packet header 11000 is 16 bits. Therefore, in step S14, the number of bits of the compressed packet header is greater than the number of bits of 64 bits of the normal packet header 10000. If it is less, it is determined by the packet compression logic 20230 (“yes” in step S14).
Therefore, in step S15, the packet compression logic circuit 20230 generates a compressed packet header. In this case, as described above, the 16-bit compressed packet header 11000 including the 1-bit packet identifier field 11001, the 8-bit entry number field 11002, and the 7-bit replacement information field 11003 is the packet compression logic circuit 20230. Generated by.

In the example of case number 2 in FIG. 5, since the number of bits of the compressed packet header 11000 is 31 bits, it is determined in step S14 that the number of bits of the compressed packet header is less than the number of bits of the normal packet header 10000. (“Yes” in step S14). Therefore, in step S15, the packet compression logic circuit 20230 generates a compressed packet header.
In this case, as described above, a compressed packet of 31 bits in total consisting of a 1-bit packet identifier field 11001, an 8-bit entry number field 11002, a 7-bit replacement information field 11003, and another 15-bit field 10006. A header 11000 is generated by the packet compression logic 20230.

On the other hand, for example, in the case of case number 5 in FIG. 5, the number of bits of the compressed packet header 11000 is 67 bits. Therefore, in step S14, the number of bits of the compressed packet header is not less than 64 bits of the normal packet header 10000. Is determined by the packet compression logic circuit 20230 (“no” in step S14).
In this case, the packet compression logic circuit 20230 outputs the normal packet received from the normal packet holding register 20210 to the SerDes transmission unit 20300 (step S17). Similarly, when the determination result in step S11 is no, a normal packet is output from step S17.

  When the packet compression logic circuit 20230 generates the compressed packet header in step S15, the pad generation logic 20230 replaces the normal packet header 10000 of the normal packet received from the normal packet holding register 20210 with the compressed packet header generated in step S15. The compressed packet is generated and output to the SerDes transmission unit 20300 (step S16).

For example, in the case of case number 1 in FIG. 5, the 64-bit normal packet header 10000 is replaced by the packet compression logic circuit 20230 with a 16-bit compressed packet header.
In this case, a reduction effect of 48 bits from 64 bits to 16 bits can be obtained. In the example of case number 2 in FIG. 5, the 64-bit normal packet header 10000 is replaced by the packet compression logic circuit 20230 with a 31-bit compressed packet header. In this case, a reduction effect of 33 bits from 64 bits to 31 bits can be obtained.
Similarly, in the case of case number 3 and case number 4 in FIG. 5, a reduction effect of 24 bits and 2 bits can be obtained, respectively. On the other hand, in the examples of case numbers 5 to 7, there is no reduction effect and the packet header is not compressed.

As described above, the packet compression logic circuit 20230 receives the normal packet header 10000 received from the normal packet holding register 20210 based on the entry number (i) received from the compression dictionary table processing unit 20220 and the information of the replacement information S _i. When there is a compression effect, a compressed packet is generated by replacing the compressed packet header.
On the other hand, the packet compression logic circuit 20230 does not perform replacement if the replacement information S _i received from the compression dictionary table processing unit 20220 has a bit width larger than that of a normal packet when replaced by the replacement information S _i. The packet is transferred as it is.

The details of the chart shown in FIG. 5 will be described as follows. That is, the chart shown in FIG. 5 shows an example of the operation of the packet compression logic circuit 20230 of the packet transmission side LSI 20000.
In the diagram of FIG. 5, a case of replacement information S _i the packet compression logic circuit 20230 receives from the compression dictionary table processing section 20220 (not all cases), the bit width of the compressed packet to be generated at that time, and the compressed packet generation Indicates the presence or absence.
Note that the bit width of each field is a temporarily set value and may increase or decrease depending on the control method of the computer system.
In this embodiment, the packet identifier field is 1 bit wide (0 is a normal packet, 1 is a compressed packet), the packet type field is 7 bits, the destination field is 5 bits, the requester field is 5 bits, and the address field is 39 bits. The match comparison range of the address field is divided into upper 22 bits, middle 9 bits, and lower 8 bits.
In addition, other fields are calculated as 7 bits. Respect compressed packet includes a packet identifier field 1 bit, the entry number information 8 bits, the replacement information S _i the 7bit, mismatch field is variable number of mismatches field, by the width. In this case, a 16-bit width is required even for a compressed packet having no mismatch field. The bit width of the normal packet header is 64 bits.

Further, the case number 1 in the diagram of FIG. 5 will be described as an example. In case 1, since the replacement information S _i received from the compression dictionary table processing unit 20220 through the signal line 20244 is a result indicating that a match is detected in all the comparison target fields, the match bit is 63 bits.
When a compressed packet is generated, there is no mismatch field, so the bit width of the compressed packet is only 16 bits, and there is a 48-bit reduction effect.
In this case, the packet compression logic circuit 20230 determines that there is an effect and performs a replacement operation. The same applies to cases 2 to 4, but since the mismatched information is added to the mismatch field, the effect is reduced accordingly, but the bit width can be reduced compared to the normal packet, so replacement with a compressed packet is performed. . Regarding cases 5 to 7, when a compressed packet is generated, the compressed packet is larger than the normal packet, so that the replacement with the compressed packet is not performed.

  On the other hand, the packet receiving unit 21200 shown in FIG. 1 includes a compressed packet holding register 21210, a compressed dictionary table processing unit 21220, and a packet restoration logic 21230. The compressed packet holding register 21210 temporarily holds the compressed packet received from the SerDes receiving unit 21100 or the packet header of the normal packet until the timing at which the packet header is output to the target 21300. The compression dictionary table processing unit 21220 holds header information of a preceding packet that is data of restoration information. The packet restoration logic 21230 restores the packet header to the information before compression, or uses the packet header as it is to generate a normal packet and transmits it to the target 21300.

A detailed configuration example of the compression dictionary table processing unit 21220 in the packet receiving side LSI 21000 is shown in FIG. In FIG. 6, in the compressed packet holding register 21210, a part holding the compressed packet header is shown as a register 21210A, and a part holding the normal packet header 10000 is shown as a register 21210B.
That is, in FIG. 6, registers (or storage areas) 21211B to 21218B have a packet identifier field 10001, a packet type field 10002, a destination field 10003, and a requester field 10004 that constitute the normal packet header 10000 shown in FIG. , Data in the upper address field 10007, middle address field 10008, lower address field 10009, and other fields 10006 are held.
The registers (or storage areas) 21211A to 21214A include a packet identifier field 11001, an entry number field 11002, a replacement information field 11003, and a mismatch field 11004 that constitute the compressed packet header 11000 shown in FIG. Data is retained.

  The compression dictionary table processing unit 21220 shown in FIG. 3 has a plurality of entry processing units 41000 (i), a counter control circuit 44000, a registration destination selection circuit 45000, and a packet information selection circuit 46000. Each entry processing unit 41000 (i) has the same configuration, but each entry processing unit 41000 (i) is assigned a different entry number (i) which is unique identification information (or position information).

The entry processing unit 41000 (i) includes a Valid register 41100 and a packet information register 41200. The Valid register 41100 has a configuration corresponding to the Valid register 31100 shown in FIG. 3, and stores 1-bit data indicating validity / invalidity of the entry.
The Valid register 41100 is set to be invalid in a state before data is stored after initialization, for example, and valid in a state where the normal packet header 10000 is stored in the packet information register 41200.
The packet information register 41200 has a configuration corresponding to the registered packet information register 31200 shown in FIG. 3, and is a register that holds each field information of the normal packet header 10000 so that it can be read and written in units of fields.
The coincidence counter 41300 has a configuration corresponding to the coincidence counter 31300 shown in FIG. 3, and the number of coincidence with the subsequent packet (that is, the number of times that the data held in the packet information register 41200 is used when restoring the packet header). Is a counter that holds
The match counter 41300 is cleared to 0 in the initial state, and the entry number (i) held in the register 21212A in the compressed packet holding register 21210 matches the entry number (i) of the entry processing unit 41000 (i). In this case, the counter counts up by one.

The packet information register 41200 corresponds to the registered packet information register 31200 shown in FIG. 3, and includes registers (or storage areas) 41201 to 41207.
Each register 41201 to 41207 indicates packet type information indicating the packet type, destination information indicating the destination, and request source information, which is data of each field 10002 to 10004, 10007 to 10009 and 10006 of the normal packet header 10000. Requester information, address high-order information indicating a high-order address, address medium-level information indicating a middle-order address, address low-order information indicating a low-order address, and other information indicating other field information are held.
The data held in the registers 20211B to 20214B, 20217B to 20219B, and 20216B of the compressed packet holding register 21210 are fetched and held in the registers 41201 to 41207, respectively. That is, when a normal packet (not a compressed packet) passes through the compressed packet holding register 21210, one entry processing unit 41000 (i) is selected by the registration destination selection circuit 45000 from among a plurality of entry processing units 41000 (i). Then, data is taken into the selected entry processing unit 41000 (i).

  The counter control circuit 44000 has a configuration corresponding to the counter control circuit 34000 shown in FIG. 3, and indicates that the packet identifier field held in the register 21211A in the compressed packet holding register 21210 is in a compressed state. If there is, the entry processing unit 41000 (i) matching the entry number (i) held in the register 21212A is selected, and the value of the selected match counter 41300 is incremented by one.

Further, the registration destination selection circuit 45000 has a configuration corresponding to the registration destination selection circuit 35000 shown in FIG. 3, and is a circuit that controls updating of the value in the packet information register 41200 in each entry processing unit 41000 (i) 0. It is.
The registration destination selection circuit 45000 includes a value (packet identifier field) held in the registers 21211B and 21211A in the compressed packet holding register 21210, a value of the Valid register 41100 in each entry processing unit 41000 (i), and a match counter. A count value of 41300 is input.

When the packet identifier field held in the register 21211B in the compressed packet holding register 21210 indicates that the packet identifier field is not in a compressed state (that is, the normal packet header 10000), the registration destination selection circuit 45000 One entry processing unit 41000 (i) 0 is selected on the basis of the value of and the count value of the coincidence counter 41300.
The conditions used in this selection are the same as those used in the registration destination selection circuit 35000 shown in FIG. That is, when there is an entry processing unit 41000 (i) whose value in the Valid register 41100 is invalid, one of the entry processing units 41000 (i) whose value is invalid is selected by the registration destination selection circuit 45000.
If there are a plurality of invalid entry processing units 41000 (i), for example, the entry processing unit 41000 (i) having the lowest entry number (i) is selected by the registration destination selection circuit 45000.
On the other hand, if there is no entry processing unit 41000 (i) whose value of the Valid register 41100 is invalid, one of the entry processing units 41000 (i) having the smallest count value of the match counter 41300 is selected by the registration destination selection circuit 45000. Is done.
When there are a plurality of entry processing units 41000 (i) having the smallest count value, for example, the entry processing unit 41000 (i) having the smallest entry number (i) is selected by the registration destination selection circuit 45000.

Then, the registration destination selection circuit 45000 holds the packet information register 41200 of the entry processing unit 41000 (i) selected based on the value of the Valid register 41100 and the count value of the match counter 41300, and holds it in the register 21210B of the compressed packet holding register 21210. Registered data. That is, the data held in the respective registers 20212B to 20214B, 20217B to 20219B, and 20216B of the compressed packet holding register 21210 (that is, information of the normal packet header) is stored in the respective registers 41201 to 41207 of the packet information register 41200.
In addition, the registration destination selection circuit 45000 sets the value of the Valid register 41100 of the entry processing unit 41000 (i) selected based on the value of the Valid register 41100 and the count value of the match counter 41300 to be valid, Clear the count value to zero.

  In this way, a normal packet header that does not match the information in the compression dictionary table processing unit 21220 is an invalid entry or a compression dictionary table having a minimum count value when it passes through the compressed packet holding register 21210. The data is taken into the entry processing unit 41000 (i) of the processing unit.

  As described above, the selection conditions of the entry processing unit 41000 (i) by the registration destination selection circuit 45000 are the same as the selection conditions of the entry processing unit 31000 (i) by the registration destination selection circuit 35000 shown in FIG. Is set. Therefore, the data stored in each of the registers 31100 and 31200 and the match counter 31300 of each entry processing unit 31000 (i) in the compression dictionary table processing unit 20220 and each entry processing unit 41000 ( The data stored in the registers 41100 and 41200 and the coincidence counter 41300 in i) coincide with each other.

  That is, the packet information holding control of the compression dictionary table processing unit 20220 is the same as the control in the compression dictionary table processing unit 20220 of the packet transmission side LSI 20000. For this reason, although there is a time difference, the information in the compression dictionary table processing unit 21220 in the packet receiving side LSI 21000 indicates that the normal packet is normally stored in the packet transmitting side LSI 20000 at the timing when the normal packet passes through the compressed packet holding register 21210. It matches the information in the compression dictionary table processing unit 20220 of the packet transmission side LSI 20000 at the time of passing through the packet holding register 20210. Therefore, the information held by the entry designated by the packet in the compression dictionary table processing unit 20220 of the packet transmission side LSI 20000 at the timing when the packet transmission side LSI 20000 outputs the compressed packet from the SerDes transmission unit 20300 Since the entry specified by the packet in the compression dictionary table processing unit 21220 of the packet receiving side LSI 21000 at the timing of passing through the compressed packet holding register 21210 of the packet receiving side LSI 21000 matches the information held by the packet, the receiving side compression dictionary Packets can be restored using information in the table processing unit 21220.

Further, the packet information selection circuit 46000 has a value (that is, packet identifier) held in the registers 21211B and 21211A in the compressed packet holding register 21210 and a value (that is, entry number (i)) held in the register 21212A. And packet information output to the packet restoration logic 21230 is generated based on the value held in the register 21213A (that is, the replacement information S _i ). The packet information is configured to include field data to be replaced, and is generated only when the compressed packet header is held in the compressed packet holding register 21210. That is, it is generated only when the values (that is, packet identifiers) held in the registers 21211B and 21211A indicate that they are compressed packets. When the packet is a compressed packet, the packet information selection circuit 46000 stores the packet information register 41200 of the entry processing unit 41000 (i) indicated by the value held in the register 21212A (that is, the entry number (i)) in the register 21213A. Data stored in one or more of the registers 41201 to 41207 that hold the value of the field indicated by the held value (that is, the replacement information S _i ) is output as packet information.

Next, the operation of the packet restoration logic 21230 of the packet receiving side LSI 20000 will be described with reference to FIG. FIG. 7 is a chart for explaining an operation example of the packet restoration logic 21230 for the example of the normal packet header 10000 and the five examples of the compressed packet header. In Figure 7, the packet recovery logic 21230 is a case of replacement information S _i received from compressed packet holding register 21210 (not all cases) shows the fields of a reference source Resilient Packet generating at that time. In these examples, the packet identifier field is 0 for a normal packet and 1 for a compressed packet. Note that X indicates that the value is invalid. The replacement information S _i indicates that each field is replaced with data in the compression dictionary table processing unit 21220 by 1 for each bit, and is not replaced by 0. In the “packet generation” column of the chart of FIG. 7, each field of the generated packet header is generated using any of the fields in the normal or compressed packet header or the data in the compression dictionary table processing unit 21220. It shows. “As is” indicates that the value of the field in the packet header received by the packet receiving side LSI 20000 is used as it is. “Table” indicates that the data in the corresponding entry processing unit 41000 (i) is used in the compression dictionary table processing unit 21220. The “mismatch field” indicates that the value of the mismatch field in the compressed packet header received by the packet receiving side LSI 20000 is used.

The packet restoration logic 21230 displays the packet information received from the compression dictionary table processing unit 21220 using the signal line 21243, the replacement information S _i input from the compressed packet holding register 21210 using the signal line 21242, and the mismatch field of the compressed packet. Originally, the normal packet is restored.

First, case number 1 in FIG. 7 will be described as an example. Case 1 indicates that the packet identifier field of the compressed packet holding register 21210 is 0, that is, a normal packet. For this reason, the packet restoration logic 21230 does not perform a packet restoration operation. On the other hand, for the case numbers 2 to 6, since the packet identifier field of the compressed packet holding register 21210 is 1, that is, a compressed packet, the packet recovery logic 21230 performs a packet recovery operation. At this time, a field corresponding to a bit whose replacement information S _i is “1” input from the compressed packet holding register 21210 using the signal line 21242 is output from the compression dictionary table processing unit 21220 using the signal line 21243. The information of each field is generated with reference to the packet information. For the field corresponding to the bit for which the replacement information S _i is “0”, field information is generated by referring to the information of the mismatch field input using the signal line 21242, and the original packet is merged. Restore to information.

  In the following, referring to FIG. 1 and FIG. 8, DMA transfer that performs a plurality of packet transfers for a continuous address space is taken as an example, and operations for registration in the compression dictionary and compression and decompression of packet headers in subsequent packets are performed. explain. FIG. 8 shows a specific example of information processed in the following operation example. Also, it is assumed that no data is registered in the compression dictionary table processing units 20220 and 21220.

[Register to compression dictionary]
The requester 20100 transmits the first packet of the DMA transfer to the memory of the target 21300. The first packet is output from the requester 20100 to the packet transmission unit 20200 and taken into the normal packet holding register 20210 in the packet transmission unit 20200. The normal packet holding register 20210 outputs the packet header information to the compression dictionary table processing unit 20220 on the transmission side through the signal line 20241. Hereinafter, a case where the packet header P1 of FIG. 8A is output to the compression dictionary table processing unit 20220 will be described as an example. The packet header P1 in FIG. 8A is configured by storing data D1 to D8 in the fields 10001 to 10004, 10007 to 10009, and 10006, respectively. However, D1 is 0 indicating that the packet head is not compressed.

The compression dictionary table processing unit 20220 on the transmission side refers to the signal line 20241, and the packet header to be compressed matches a valid entry in the compression dictionary table processing unit 20220 on the transmission side, or some information is It is determined whether or not there is a matching entry (here, there is no matching entry because it is the first packet). In this case, as a result of the determination in the compression dictionary table processing unit 20220 on the transmission side, there is no entry match, so the compression dictionary table processing unit 20220 on the transmission side does not match (replacement) as the replacement information S _i (signal line 20244). The result of information S _i = all 0) is output to the packet compression logic circuit 20230. Since the replacement information S _i = all 0, the packet compression logic circuit 20230 outputs information indicating that compression processing is not performed as the compression information (signal line 20245). Therefore, the compression dictionary table processing unit 20220 on the transmission side compares the match counter counter value of each entry processing unit 31000 (i) in the table, and the entry with the smallest number of matches or the invalid entry is All the information of the packet header P1 from the packet holding register 20210 is fetched and thereafter held as a valid entry. Here, as shown in FIG. 8B, each field except the packet identifier field 10001 of the packet header P1 is stored in each register 31201 to 1207 of the registered packet information register 31200 in the entry processing unit 31000 (i) with the entry number “1”. The data D2 to D8 are fetched.

The packet compression logic circuit 20230 that has received a result of no match (all 0) as the replacement information S _i (signal line 20244) from the compression dictionary table processing unit 20220 on the transmission side does not perform the compression operation and retains the normal packet. The normal packet received using the signal line 20242 from the register 20210 is transferred to the SerDes transmission unit 20300 as it is. Here, the packet header of the normal packet transferred to the SerDes transmission unit 20300 is the same as the normal packet header P1 of FIG.

  A packet that has passed through SerDes 22000 and received by the SerDes receiving unit 21100 of the packet receiving side LSI 21000 is taken into the compressed packet holding register 21210 of the packet receiving unit 21200 in the form of an uncompressed packet (packet identification = 0). The compressed packet holding register 21210 outputs the received packet header information to the receiving-side compressed dictionary table processing unit 21220 via a signal line 21241. The receiving-side compressed dictionary table processing unit 21220 receives the received packet header information. Similarly to the table processing unit 20220, it is determined whether or not there is an entry that matches a valid entry in the compression dictionary table processing unit 21220 on the receiving side or a part of the information matches (in this case, transmission). Like the side, there is no matching entry).

  As a result of the determination by the compression dictionary table processing unit 21220 on the reception side, there is no match between the entries. Therefore, the compression dictionary table processing unit 21220 on the reception side counts the match counter 41300 included in each entry processing unit 41000 (i) in the table. The values are compared, and all the packet header information from the compressed packet holding register 21210 is fetched into the entry with the smallest number of matches or an invalid entry, and thereafter held as a valid entry. Since the logic for determining the registered entry is the same in the compression dictionary table processing unit 20220 on the transmission side and the compression dictionary table processing unit 21220 on the reception side, one packet shown in this example is stored in two compression dictionaries. The number of the entry registered in is the same. That is, as shown in FIG. 8C, the data of each field excluding the packet identifier field 10001 of the packet header P1 is stored in each register 41201 to 41207 of the packet information register 41200 in the entry processing unit 41000 (i) of the entry number 1. D2 to D8 are taken in.

  The compressed packet holding register 21210 outputs the packet information to the receiving side compression dictionary table processing unit 21220 and simultaneously outputs the packet information to the packet restoration logic 21230 through the signal line 21242. The packet restoration logic 21230 that has received this does not perform the packet restoration operation, and outputs the information of the packet as it is to the target 21300. Here, the packet header of the packet output to the target 21300 is the same as the normal packet header P1 of FIG.

  For the transfer of the first packet in the DMA transfer, since the compression operation is not performed, there is no effect of improving the throughput, and the operation is merely updating the information in the compression dictionary table processing unit.

[Packet compression and decompression]
The requester 20100 transmits the second packet of the DMA transfer to the memory of the target 21300. The packet header difference from the first packet is only the lower part of the address, and all others are the same. FIG. 8D shows a normal packet header P2 as the second packet. In the normal packet header P2, the value of the address lower field 10009 is changed from D7 to D7-2.

The requester 20100 outputs the second DMA packet to the packet transmission unit 20200 and is taken into the normal packet holding register 20210 in the packet transmission unit 20200. The normal packet holding register 20210 outputs the packet header information to the compression dictionary table processing unit 20220 on the transmission side through the signal line 20241. The transmission-side compression dictionary table processing unit 20220 refers to the signal 20241 to check whether there is an entry that matches a valid entry in the transmission-side compression dictionary table processing unit 20220 or that matches some information. Determine whether or not. The compression dictionary table processing unit 20220 on the transmission side detects that the entry information registered in the first DMA packet matches information other than the lower address, and sends the entry number (signal line) to the packet compression logic circuit 20230. 20243) and replacement information S _i (signal line 20244). In addition, when compression information indicating that compression has been performed is input from the packet compression logic circuit 20230, the compression dictionary table processing unit 20220 on the transmission side adds 1 to the match counter 31300 of the matched entry, and compression transfer is performed. Record the number of times In this example, the replacement information S _i is “1111101” in binary. However, each bit of the replacement information S _i indicates that 0 is not replaced and 1 is replaced. Further, each bit of the replacement information S _i has the most significant bit corresponding to the packet type field 10002, and in order of lower order, the destination field 10003, the requester field 10004, the upper address field 10007, the middle address field 10008, the address It corresponds to the lower field 10009 and other fields 10006. That is, the replacement information S _i “1111101” indicates that the address lower field 10009 is not replaced and the other fields are replaced.

Valid replacement information _{S i} packet compression logic receives (i.e. one bit replacement information _S i which is a 1) (signal line 20244) 20230 is a packet identifier as 1 (compressed packet), the sender The entry number information received from the compression dictionary table processing unit 20220 and the replacement information S _i in the entry number field and the replacement information field are subordinate to the address received from the normal packet holding register 2021 through the signal line 20242, respectively. A compressed packet in which the field is applied to the mismatch field is generated and transferred to the SerDes transmission unit 20300. FIG. 8E shows a compressed packet header P3 of the compressed packet transferred to the SerDes transmission unit 20300 here. The packet identifier field 11001 of the compressed packet header P3 is “1”, the entry number field 11002 is entry number = “0000001”, the replacement information field 11003 is replacement information S _i “1111101”, and the mismatch field 11004 is the address of the normal packet header P2 The value of the lower field is “D7-2”.

  The compressed packet received by the SerDes receiving unit 21100 of the packet receiving side LSI 21000 through the SerDes 22000 is taken into the compressed packet holding register 21210 of the packet receiving unit 21200 in the form of a compressed packet (packet identification = 1). The compressed packet holding register 21210 outputs the packet header information to the receiving side compression dictionary table processing unit 21220 via the signal line 21241. Upon receiving this, the compression dictionary table processing unit 21220 on the receiving side reads the information registered in the entry when receiving the previous DMA transfer packet from the information in the entry number field 11002 of the compressed packet header, and restores the packet as packet information. Output to logic 21230. At the same time, the match counter 41300 of the entry is incremented by 1 to match the information in the compression dictionary table processing unit 20220 on the transmission side.

The compressed packet holding register 21210 outputs the packet header information to the compression dictionary table processing unit 21220 on the receiving side, and simultaneously outputs the packet information to the packet decompression logic 21230 through the signal line 21242. Receiving this, the packet restoration logic 21230 restores the packet based on the replacement information S _i . That is, in this example, in the replacement information S _i , the fields other than the lower address are information that matches the compression dictionary table processing unit 21220, so the information other than the lower address is output from the compression dictionary table processing unit 21220 on the receiving side. The packet is restored by referring to the mismatched field information from the compressed packet holding register 21210 for the lower address field. FIGS. 8E and 8F show the relationship between the packet header P3 of the restored packet restored here and the data reference source of each field. The data D7-2 in the address lower field 11009 is restored based on the mismatch field 11004 in the compressed packet header P3. The other fields are restored based on the data in the corresponding fields of the packet information register 41200 of the entry processing unit 41000 (i) with the entry number = 1 of the compression dictionary table processing unit 21220 on the receiving side.

  Then, the packet restoration logic 21230 that restored the packet header outputs the restored packet header to the target 21300.

  According to the present embodiment, even if all of the input information to be compressed does not match all of the entry registration information for each entry, any of the entry processing units 31000 (i) can input the input to be compressed. If a part of the information matches the information in any field of the entry registration information in the compression dictionary table processing unit, the information compressed by the packet compression logic circuit 20230 using the entry number (i) representing the entry Can be generated. That is, it is possible to increase the probability that data can be replaced using the entry number (that is, the pointer of the compression dictionary) without increasing the number of entries in the compression dictionary (that is, the number of registered data).

  In the above-described embodiment, the compression target is the packet header portion. However, the present invention is not limited to this, and the present invention can also be applied to data such as predetermined control information other than the packet header. .

  The features of the present invention can be understood as follows. The present invention relates to a computer system for transferring data between LSIs and transferring control information by using a packet, a function of transferring a packet header or the like having a high appearance frequency by compressing it by a packet sending control unit, and a packet The receiving section is provided with a function of restoring the compressed packet, whereby the throughput of the transfer path can be improved without losing necessary information.

  In addition, the present invention provides a compression dictionary table processing unit that has a plurality of entries and can store packet header information and the like in the packet transmission unit and the packet reception unit, and passes from the packet transmission unit to the packet reception unit. The information in each compression dictionary is controlled to be in the same state in synchronization with the packet to be transmitted. In the packet transmission unit, information such as the address of the packet to be transferred to the packet reception unit is indexed by the compression dictionary table processing unit, and when it is determined that the packet is compressible, the header information of the packet is The amount of information such as packet headers can be reduced by replacing the pointers in the compression dictionary in the compression dictionary (information shorter than the header information, etc.), and throughput can be improved by reducing the bandwidth of packet headers etc. in the transfer path. Is possible. Further, the packet receiving unit restores the header information from the pointer in the compression dictionary, so that it can operate as before without losing the information.

  For the embodiment of the present invention, for example, it is possible to appropriately make changes such as dividing, integrating, or multiplexing blocks in the packet transmission unit 20200 and the packet reception unit 21200. is there. In the above embodiment, for the registration destination selection circuit 35000 and the registration destination selection circuit 45000, the registration destination entry number (i) is selected based on the value of the Valid register or the count value of the match counter. It is also possible to determine the registration destination using other methods, such as recording past usage records using a memory or the like and determining the entry of the registration destination based thereon. In addition, the data transfer control device of the present invention can be regarded not only as the packet transmission unit 20200 but also as the packet transmission side LSI 20000, or can be combined with the packet reception side LSI 21000 as a transmission / reception system. . The packet transmission unit 20200 and the like can be configured using a CPU (central processing unit) and a program executed by the CPU, and the program is recorded and distributed on a communication line or a computer-readable recording medium. It is possible.

  The correspondence between the configuration of the embodiment and the matters described in the claims is as follows. The “storage means” in the claims corresponds to the compression dictionary table processing unit 20220 and the registered packet information register 31200. The “compression target information” usually corresponds to a packet header. “Entry” corresponds to the entry processing unit 31000 (i), and “Partition” corresponds to the fields 10002 to 10009 and the registers 31201 to 1207. The “first comparison unit” corresponds to the compression dictionary table processing unit 20220 and the comparators 31401 to 1407. The “second comparison unit” corresponds to the compression dictionary table processing unit 20220 and the bit width comparison logic circuit 32000. The “first information” corresponds to the entry number field 11002, the “second information” corresponds to the replacement information field 11003, and the “third information” corresponds to the mismatch field 11004. “Counter” corresponds to the coincidence counter 31300. “Valid information storage means” corresponds to the Valid register 31100.

  The “transmission means” corresponds to the SerDes transmission unit 20300. “Receiving means” corresponds to the SerDes receiving unit 21100. The “first storage unit” corresponds to the compression dictionary table 20220 and the registered packet information register 31200. The “second storage unit” corresponds to the compression dictionary table processing unit 20220 and the packet information register 41200. The “restoring means” corresponds to the packet restoration logic 21230. The “first division information” corresponds to data stored in the registers 41201 to 41200. “Second division information” corresponds to the data stored in the mismatch field 11004.

  Moreover, when the structure of the said embodiment is summarized for every main function and shown typically, it can represent as shown in FIG. In addition, the same code | symbol is attached | subjected to the thing corresponding to the structure of the said embodiment. That is, the data transfer control device 10 of the present invention uses the storage means 1 for storing information divided into a plurality of entries for each entry, the information 20 to be compressed, and the information stored in the storage means 1 as entries. The first comparison means 2 for comparing each and every section, the second comparison means 3 for comparing the comparison results by the first comparison means 2 between a plurality of entries, and the comparison results by the second comparison means 3 First information representing one entry selected based on the second information, second information representing one or more sections that match the compression target information 20 in the selected entry, and the entry selected in the compression target information 20 And compression means 4 for generating transfer information using third information representing information corresponding to zero or more sections that did not match the information stored in.

Further, the packet transmission side LSI 20000 and the packet reception side LSI 21000 according to the present embodiment have a computer system therein. The process of operation is stored in a computer-readable recording medium in the form of a program, and the above-described processing is performed by the computer system reading and executing this program. The “computer system” herein includes a CPU, various memories, an OS, and hardware such as peripheral devices.
Further, the “computer system” includes a homepage providing environment (or display environment) if a WWW system is used.

“Computer-readable recording medium” means a flexible disk, a magneto-optical disk, a ROM, a writable non-volatile memory such as a flash memory, a portable medium such as a CD-ROM, and a storage such as a hard disk built in a computer system. Refers to the device.
Further, the “computer-readable recording medium” means a volatile memory (for example, DRAM (for example, DRAM) inside a computer system that becomes a server or a client when a program is transmitted via a network such as the Internet or a communication line such as a telephone line. Dynamic Random Access Memory)) may also be included which hold a program for a certain period of time.

Further, the program may be transmitted from a computer system storing the program in a storage device or the like to another computer system via a transmission medium or by a transmission wave in the transmission medium. Here, the “transmission medium” for transmitting the program refers to a medium having a function of transmitting information, such as a network (communication network) such as the Internet or a communication line (communication line) such as a telephone line.
The program may be for realizing a part of the functions described above. Furthermore, what can implement | achieve the function mentioned above in combination with the program already recorded on the computer system, and what is called a difference file (difference program) may be sufficient.

20000 packet transmission side LSI
20100 Requester 20200 Packet transmission unit 20210 Normal packet holding register 20220 Compression dictionary table processing unit 20230 SerDes transmission unit 20230 Packet generation logic 21000 Packet receiving side LSI
21100 SerDes receiving unit 21200 Packet receiving unit 21210 Compressed packet holding register 21220 Compression dictionary table processing unit 21230 Packet recovery logic 11001 Packet identifier field 11002 Entry number field 11003 Replacement information field 11004 Mismatch field

Claims (7)

Storage means for storing entry registration information indicating attributes to be compressed for each of a plurality of sections for each entry configured by a plurality of the predetermined sections;
First comparing means for comparing, for each entry, whether the input information matches the entry registration information for each entry;
A second comparing means for comparing the results obtained by adding the data lengths of the sections that match in the comparison result by the first comparing means for each entry;
The first information representing the entry selected based on the comparison result by the second comparing means, and the first information representing at least one section in which the entry registration information and the input information of the selected entry match. Compression means for compressing the input information using the information of 2 and the third information representing the input information corresponding to the classification that does not match the entry registration information and the input information of the selected entry A data transfer control device comprising: The storage means has a plurality of counting means for each entry for performing a counting operation according to a comparison result by the first comparison means or a comparison result by the second storage means,
As a result of comparison by the first comparison means, if the input information does not match at least one of the pieces of information in each entry registration information, the storage means responds to the count value of the counting means. The data transfer control device according to claim 1 , wherein the input information is stored in one of the entries selected in the above. The storage means has a plurality of counting means for each entry according to the comparison result by the first comparison means or the comparison result by the second storage means for each entry, and information indicating valid or invalid A plurality of effective information storage means for storing each entry,
As a result of the comparison by the first comparison means, if the input information does not match at least one of the information for each of the entries in each entry registration information, the storage means valid information data transfer control device according to claim 1 or 2 as the entry registration information of one of the entries selected according to the stored contents and to store the input information in the storage means. Wherein the plurality of sections, to any one of claims 1 to 3, wherein a plurality of indicator is included corresponding to a plurality of portions obtained by dividing the address of the destination of the input information The data transfer control device described. In the compression means, any of the four preceding claims 1, wherein the transfer information is the transfer information using the third information from the first is smaller than the input information is generated 2. A data transfer control device according to item 1. Referring to a storage unit that stores entry registration information indicating attributes to be compressed for each of a plurality of sections for each entry configured by a plurality of predetermined sections , input information and the entries for each entry A first comparison step for comparing, for each section, whether registration information matches ,
A second comparison step for comparing the results of adding, for each entry, the data lengths of the sections that match in the comparison result obtained by the first comparison step;
A selection step of selecting one of the entries based on the comparison result obtained by the second comparison step;
First information representing the entry selected in the selection step, and second information representing at least one of the sections in which the entry registration information and the input information of the entry selected in the selection step match. And a compression step of compressing the input information using the entry registration information of the entry selected in the selection step and the third information representing the input information corresponding to the classification that does not match the input information When,
A data transfer control method comprising: Storage means for storing entry registration information indicating attributes to be compressed for each of a plurality of sections for each entry configured by a plurality of the predetermined sections;
First comparing means for comparing, for each entry, whether the input information matches the entry registration information for each entry;
A second comparing means for comparing the results obtained by adding the data lengths of the sections that match in the comparison result by the first comparing means for each entry;
The first information representing the entry selected based on the comparison result by the second comparing means, and the first information representing at least one section in which the entry registration information and the input information of the selected entry match. Compression means for compressing the input information using the information of 2 and the third information representing the input information corresponding to the classification that does not match the entry registration information of the selected entry and the input information; Transmitting means for transmitting transfer information obtained by compressing the input information by a compression means;
A data transmission unit having
Receiving means for receiving the transfer information transmitted by the transmitting means;
Second storage means for storing a plurality of entries of information divided into a plurality for each entry;
Based on the transfer information received by the receiving means, the first section stored in the section corresponding to the second information and the entry corresponding to the first information in the second storage means A decompression unit that decompresses the information to be compressed using the information and the second segment information represented by the third information;
A data receiver having
A data transfer control system comprising:

Images