JP5820567B2 - Analysis system and semiconductor device - Google Patents

Description

  The present application relates to an analysis system for a semiconductor device such as an LSI and the semiconductor device.

  Conventionally, in the development of a system including an LSI, an operation analysis is performed by monitoring a program counter, a flag register, a memory area, and the like via an ICE (In-Circuit Emulator) from the viewpoint of software development. From the viewpoint of hardware development, signal changes are analyzed by monitoring the main signals on the board with a logic analyzer, oscilloscope, or the like.

  In this connection, a configuration for improving the efficiency of debugging has been proposed. For example, a configuration is known in which time information is stored in a memory in addition to the contents of an event every time an event occurs.

JP-A-6-139116 JP 2004-86447 A

  However, with the recent high integration, most of the necessary functions are mounted on a single LSI. As a result, the main signals are gathered inside the chip, making it impossible to monitor signals with a logic analyzer or the like. Oops. On the other hand, it is conceivable to provide dedicated terminals for the number of signals to be monitored and output main signals to the outside of the chip, but there are problems such as cost.

  When the time information at the time of event occurrence is stored in the memory area inside the chip, the number of digits of the counter increases according to the time detection accuracy, and the memory area required for storing the time information increases. Therefore, it is difficult to improve time detection accuracy.

  An object of the present application is to provide an analysis system and a semiconductor device capable of easily confirming a transition of a signal inside a semiconductor device such as an LSI.

  In the semiconductor device analysis system disclosed in the present application, an internal signal to be analyzed is input inside the semiconductor device, and when a transition of the internal signal is detected, it is converted into a predetermined code and output. An encoding circuit for outputting a notification signal for informing a transition of an internal signal, an internal memory for storing the code output from the encoding circuit inside the semiconductor device, and the code outside the semiconductor device A timing circuit for timing the transition timing of the internal signal, and an external memory for storing time information measured by the timing circuit outside the semiconductor device. Prepare.

  According to the disclosed semiconductor device analysis system and semiconductor device, transition of internal signals can be easily confirmed, and debugging efficiency can be improved.

It is a block diagram which shows an example of embodiment. It is a block diagram which shows the specific example of an encoder circuit. It is a timing chart which shows the operation example of an edge detection part. It is a timing chart which shows the example of internal operation at the time of debugging. It is a figure which shows an example of each data at the time of event detection, and its storage state. It is a figure which shows the example of a display of the PC screen which reproduced the transition of a signal.

  FIG. 1 is a block diagram illustrating an example of an embodiment of the overall configuration of the analysis system. The microcontroller 10 includes an encoder circuit 11. Event signals 1 to 5 output from the functional blocks F1 to F5 are input to the encoder circuit 11. When the encoder circuit 11 detects a transition of the event signals 1 to 5, the encoder circuit 11 outputs an event number and an event trigger.

  With reference to FIG. 2, the generation of an event number and an event trigger in the encoder circuit 11 will be described. FIG. 2 is a block diagram showing a specific example of the encoder circuit 11. The encoder circuit 11 includes edge detection units E1 to E5, an encoding unit 51, and an OR gate 52. Event signals 1 to 5 are input to the edge detectors E1 to E5, respectively. The edge detection units E <b> 1 to E <b> 5 detect rising edges and falling edges for the event signals 1 to 5 and output detection results to the encoding unit 51 and the OR gate 52.

  With reference to FIG. 3, the edge detection in the edge detection parts E1-E5 is demonstrated. FIG. 3 is a timing chart showing an operation example of the edge detectors E1 to E5. The edge detection unit generates a delay signal B obtained by adding a delay to the input event signal A, and further generates a delayed inverted signal XB obtained by inverting the logic of the delayed signal B. Then, the edge detection unit uses the AND signal A (XB) obtained by ANDing the event signal A and the delayed inversion signal XB as a detection result of the rise of the event signal A. Further, the edge detection unit uses the NOR signal X (A + XB) obtained by taking the negative logical sum of the event signal A and the delayed inverted signal XB as the detection result of the fall of the event signal A.

  With reference to FIG. 2 again, the description of the encoder circuit 11 is continued. The encoding unit 51 converts the detection results output from the edge detection units E1 to E5 into encoded values corresponding to the rising and falling edges of the event signals 1 to 5, respectively, and outputs them as event numbers. The OR gate 52 outputs a logical sum of detection results output from the edge detection units E1 to E5 as an event trigger.

  Returning to FIG. 1, the overall configuration of the analysis system will be described. The event number output from the encoder circuit 11 is stored in a memory area 12 which is a FIFO (First In, First Out) memory. The event trigger output from the encoder circuit 11 is input to the external measurement circuit 20 via the external terminal of the microcontroller 10. The external measurement circuit 20 measures the time when the event trigger is input and stores the time information in order to grasp the transition timing of the event signals 1 to 5 which are internal signals of the microcontroller 10. The external measurement circuit 20 exchanges control signals with the debug unit 14 in order to analyze the movement of the CPU 13, and is an ICE function that enables the program counter, flag register, memory area, and the like to be monitored on the host PC 30. Can be configured as a part.

  The operation and effect of the analysis system having the above configuration will be described. FIG. 4 is a timing chart showing an example of the internal operation of the microcontroller 10 during debugging. When the event signal 1 rises from the L level to the H level, the edge detection unit E1 of the encoder circuit 11 detects the rise as described above. Based on the detection result, the encoding unit 51 of the encoder circuit 11 outputs “01h”, which is a code associated with the rising edge of the event signal 1, as an event number. An event trigger is output from the OR gate 52 of the encoder circuit 11. Similarly, the corresponding event number and event trigger are output according to the transition of each event signal 1-5.

  As described above, the event number is stored in the memory area 12 which is a FIFO memory. The event trigger is input to the external measurement circuit 20, and time information indicating the transition timing of the event signals 1 to 5 is stored. FIG. 5 is a diagram showing an example of each data at the time of event detection and its storage state corresponding to the operation example of FIG. As shown in FIG. 5, event numbers are stored in the memory area 12 which is a FIFO memory in the order of output. The external measurement circuit 20 stores the measurement result of the time when the event trigger is input as time information indicating the transition timing of the event signals 1 to 5.

  After a series of operations to be debugged are completed, each data stored in the memory area 12 and the external measurement circuit 20 is taken into the host PC 30. The host PC 30 reproduces the signal waveform based on the acquired data. FIG. 6 is a diagram illustrating a screen display example of the host PC 30 that reproduces the transition of the event signals 1 to 5 based on the data of FIG. The host PC 30 extracts the event number from the memory area 12 that is a FIFO memory, and sequentially associates it with the time information of the external measurement circuit 20. As a result, the host PC 30 reproduces a detailed signal waveform in the same manner as a monitor by a logic analyzer or the like. Also, as shown in FIG. 6, the address bus and data bus information may be reproduced by existing functions of a general ICE and displayed side by side with transitions of event signals 1 to 5.

  As described above in detail, according to the above-described embodiment, it is grasped which signal has transitioned according to the event number, and has grasped when the transition has occurred according to the time information based on the event trigger. Thereby, the transition of the signal inside the LSI can be easily confirmed, and the debugging efficiency can be improved. In the embodiment, as shown in FIG. 5, data saved inside the chip is distinguished from data saved outside the chip. Event numbers with a small data amount (bit length) are stored in the memory area 12 inside the chip. This eliminates the need to provide a dedicated terminal for outputting to the outside of the chip according to the number of signals to be analyzed. On the other hand, time information at the time of occurrence of an event with a large amount of data (bit length) is stored in the external measurement circuit 20 outside the chip. This eliminates the need to provide a memory area for storing time information inside the microcontroller 10. The microcontroller 10 only needs to output an event trigger to the outside of the chip, and the time detection accuracy can be easily improved depending on the external measurement circuit 20. According to the embodiment, the scale of the dedicated debug circuit can be minimized, and the cost increase can be suppressed.

  Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

  For example, the memory area 12 is not limited to a FIFO memory. Any configuration may be used as long as the event number stored in the memory area 12 and the time information stored in the external measurement circuit 20 can be associated with each other by determining the storage order in advance. The time information measured by the external measurement circuit 20 may be saved in the host PC 30.

  In addition, in the case where edges overlap between the event signals 1 to 5, for example, it may be determined in advance which signal has priority.

  The microcontroller 10 is an example of a semiconductor device. Each of the event signals 1 to 5 is an example of an internal signal. The event number is an example of a code. An event trigger is an example of a notification signal. The encoder circuit 11 is an example of an encoding circuit. The memory area 12 is an example of an internal memory. The external measuring circuit 20 is an example of a time measuring circuit and an external memory. The edge detection units E1 to E5 are examples of edge detection units. The encoding unit 51 is an example of an encoding unit. The OR gate 52 is an example of a logical operation unit.

10 Microcontroller 11 Encoder circuit 12 Memory area 13 CPU
14 Debug unit 20 External measurement circuit 30 Host PC
51 Encoding Unit 52 OR Gate E1 to E5 Edge Detection Unit F1 to F5 Functional Block

Claims (7)

A semiconductor device analysis system,
A code for inputting an internal signal to be analyzed in the semiconductor device, converting the internal signal into a predetermined code upon detection of a transition of the internal signal, and outputting a notification signal for informing the transition of the internal signal Circuit and
Inside the semiconductor device, an internal memory for storing the code output from the encoding circuit;
Outside the semiconductor device , based on the time information that the notification signal output from the encoding circuit is input, a timing circuit that measures the transition timing of the internal signal,
Outside the semiconductor device, an external memory for storing time information timed by the timekeeping circuit;
An analysis system comprising: The encoding circuit includes:
An edge detector for detecting rising and falling for each of the internal signals;
An encoding unit that outputs the code associated with each rising and falling of the internal signal based on a detection result of the edge detection unit;
The analysis system according to claim 1, further comprising: The encoding circuit includes:
A logical operation unit that performs a logical operation based on the detection result of the edge detection unit;
The analysis system according to claim 2, wherein a logical sum of detection results of the edge detection unit is output as the notification signal. The edge detector
Generating a delayed inverted signal having a delay and inverted logic with respect to the internal signal;
The logical product of the internal signal and the delayed inverted signal is a detection result of the rising edge of the internal signal,
The analysis system according to claim 2 or 3, wherein a negative logical sum of the internal signal and the delayed inverted signal is used as a detection result of the falling edge of the internal signal. The analysis system according to claim 1, wherein the code and the time information are stored in the internal memory and the external memory, respectively, so that they can be associated with each other. The analysis system according to claim 5, wherein the internal memory is a FIFO memory that stores the codes in the order of output from the encoding circuit. An encoding circuit that converts and outputs a predetermined code when detecting a transition of an internal signal to be analyzed;
An internal memory for storing the code output from the encoding circuit;
With
In response to detection of the transition of the internal signal, a notification signal for notifying the transition of the internal signal is output to the outside, and the transition timing of the internal signal based on time information when the notification signal is input is transmitted to the outside. A semiconductor device.

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