JP5817511B2 - Periodic disturbance suppression control device - Google Patents

Description

  The present invention relates to suppression of periodic disturbances by a periodic disturbance observer with a learning function, and more particularly to periodic disturbance suppression control having a limiter processing function that operates when a control amount reaches the upper limit of the device rated capacity.

  The present inventor first expresses the transfer characteristic of the control system as a complex number by system identification. This complex number and DFT (Discrete Fourier Transform) calculation, a periodic disturbance observer, and further, a periodic disturbance (by a system identification result learning function) For example, the control which suppresses a harmonic current) was proposed. This proposed control is characterized by the following points.

  The transfer characteristic from the output command value to the point where the actual output is detected is expressed by a complex number, focusing on the specific frequency.

  The complex reciprocals Qa and Qb (hereinafter referred to as coefficients Qa and Qb) are used as control parameters as inverse functions of transfer characteristics.

  A state in which the periodic disturbance is suppressed by the periodic disturbance observer is developed on the complex plane, and the coefficients Qa and Qb are automatically corrected from the locus.

  Control instability due to fluctuations in the control system transfer function such as sudden load changes can be prevented, and periodic disturbances can be suppressed following the fluctuations. Furthermore, even if the initial values of the coefficients Qa and Qb are not appropriate, the coefficients Qa and Qb can be set to appropriate values by correction while suppressing periodic disturbance, so that no trial operation is required.

  For example, if it is a use of the active filter for electric power, since a harmonic current can be considered as a periodic disturbance, the effect shown below is acquired.

  The coefficients Qa and Qb are inverse functions of transfer characteristics from the output current command value to the actually output current.

  Even when there is a resonance point in the load or the system, the optimum coefficients Qa and Qb are automatically searched for and the harmonic current is suppressed, so that conventional filter adjustment is not necessary. In addition, it is possible to prevent control instability due to changes in system conditions such as load fluctuations, and to suppress harmonic currents following the changes. Furthermore, even if the initial values of the coefficients Qa and Qb are not appropriate, they can be made appropriate by correction, so that there is no need for trial operation.

JP 2009-106131 A Japanese Patent Laid-Open No. 2001-16867

  Actually, the amount of control that can be output from the periodic disturbance suppression control device to the controlled object is finite. Therefore, the control amount is determined by the device rated capacity, and when the upper limit value of the device rated capacity is reached, the control amount is limited by the limiter operation of the periodic disturbance suppression control device, and therefore it is necessary to perform a limiter process.

  At this time, the periodic disturbance suppression command value href of the controlled variable is not the value obtained by the periodic disturbance observer, but changes with the upper limit value of the device rated capacity by the limiter operation. Therefore, during the limiter operation, the same coefficients Qa and Qb as before are used. Even if correction (learning function processing) is performed, the obtained coefficients Qa and Qb contain many errors.

  If the control is continued using the coefficients Qa and Qb containing a large amount of such errors, the effect of suppressing the periodic disturbance is lowered, and conversely, the periodic disturbance is increased. Further, when the control amount does not change at the upper limit value of the device rated capacity due to the limiter operation, the locus of suppression of periodic disturbance also becomes the upper limit value of the device rated capacity, and the coefficients Qa and Qb cannot be corrected. Even if the transfer characteristic fluctuates, it can no longer follow.

  FIG. 21 is a diagram illustrating an example when the phase correction of the coefficients Qa and Qb is not correctly performed by the limiter operation. In FIG. 21, a circle is drawn with the initial value of the periodic disturbance as the center and the device rated capacity operation as the radius. The magnitude of the control amount (periodic disturbance suppression command value href) that can be output from the periodic disturbance suppression control device is limited to the upper limit value of the device rated capacity. As a result, the periodic disturbance suppression command value href can move only inside the circle.

  Now, let us consider a state in which the phase error of the coefficients Qa and Qb is θ and the periodic disturbance is about to change further in contact with the upper limit value of the device rated capacity. The trajectory of the periodic disturbance suppression command value href when it is assumed that there is no limiter operation is indicated by a broken line. At this time, the angle between the origin and the locus based on the current value is θ. However, in reality, a locus indicated by a solid line is drawn by the limiter operation. Here, if the angle between the origin and the locus (with limiter) based on the current value is obtained, θL is obtained, which is a value different from the actual phase error θ.

  When the periodic disturbance suppression control device is applied to a power active filter, the phenomenon of FIG. 21 becomes the following problem.

  When the device rated capacity is small relative to the speed of the periodic disturbance suppression locus, the periodic disturbance suppression command value of the active filter may exceed the device rated capacity before the coefficients Qa and Qb are corrected. Some loads output periodic disturbances exceeding the rated capacity of the active filter. In this case, the limiter inside the active filter operates and correction of the coefficients Qa and Qb (learning function processing) is not performed correctly. Therefore, there arises a problem that the periodic disturbance suppressing effect is lowered, and conversely, the periodic disturbance is enlarged.

  As described above, in the periodic disturbance suppression control device with a learning function, when the periodic disturbance suppression command value exceeds the upper limit value of the limiter, it is an issue to appropriately correct the coefficients Qa and Qb. .

  The present invention has been devised in view of the conventional problems, and one aspect thereof is a periodic disturbance detection unit that outputs a periodic disturbance to be suppressed as a periodic disturbance detection value of a DC value, and a control system. A signal obtained by multiplying the periodic disturbance detection value by an integrator using a coefficient defined as an inverse function of the transfer function from the periodic disturbance suppression command value determined based on the transfer characteristic of the input signal to the input signal detection value; The periodic disturbance observer for estimating the periodic disturbance by taking the difference between the periodic disturbance suppression command value and the signal obtained by adding only the detection delay, the periodic disturbance estimated value estimated by the periodic disturbance observer, and the disturbance An adder that calculates the periodic disturbance suppression command value by taking a deviation between the disturbance disturbance command value and the periodic disturbance detection value and a change amount between the periodic disturbance detection value of the previous cycle, Periodic disturbance detection one cycle before The phase correction amount command value of the coefficient is calculated based on the phase difference between the coefficient and the variation amount, and the amplitude correction amount command of the coefficient is calculated based on the amplitude difference between the periodic disturbance detection value one cycle before and the variation amount. A coefficient correction amount calculation unit that calculates a value, a phase correction amount command value calculated by the coefficient correction amount calculation unit, a coefficient correction unit that corrects the phase and amplitude of the coefficient based on the amplitude correction amount command value, and periodicity When the disturbance suppression command value reaches the upper limit value of the limiter, a periodic disturbance observer and a limiter countermeasure unit that stops the coefficient correction amount calculation unit are provided.

Further, as another aspect, from a periodic disturbance detection unit that outputs a periodic disturbance to be suppressed as a periodic disturbance detection value of a DC value, and a periodic disturbance suppression command value determined based on a transfer characteristic of a control system A signal obtained by multiplying the periodic disturbance detection value by an integrator using a coefficient defined as an inverse function of the transfer function up to the input signal detection value, a signal obtained by adding only a detection delay to the periodic disturbance suppression command value, and By taking the difference between the periodic disturbance observer for estimating the periodic disturbance, the periodic disturbance estimated value estimated by the periodic disturbance observer, and the disturbance command value for suppressing the disturbance, the periodic disturbance is taken. An adder that calculates a suppression command value, and a change amount between the periodic disturbance detection value and the periodic disturbance detection value one cycle before are obtained, and a position between the periodic disturbance detection value one cycle before and the change amount is calculated. of the coefficient based on the phase difference Calculating a phase correction amount command value, and the coefficient correction amount calculation unit for calculating an amplitude correction amount command value of the coefficient based on the amplitude difference between the preceding cycle of the periodic disturbance detection value and the change amount, the coefficient correction When the phase correction amount command value calculated by the amount calculation unit and the amplitude correction amount command value respectively correct the phase and amplitude of the coefficient, and the periodic disturbance suppression command value exceeds the upper limit value of the limiter, A limiter that compares the amplitude of the current periodic disturbance detection value with the amplitude of the periodic disturbance detection value of the previous cycle while changing the phases of the coefficients Qa and Qb, and changes the phase correction amount command value based on the comparison result. And a countermeasure circuit, and when the periodic disturbance suppression command value exceeds the upper limit value of the limiter, the coefficient correction amount calculation unit is stopped.

  Further, based on the phase error estimated value of the periodic disturbance detection value immediately after the start of the limiter operation and the periodic disturbance detection value after a lapse of a certain time after the start of the limiter operation, the coefficients Qa and Qb are first calculated in the limit countermeasure circuit. An initial phase error determination unit that determines a code to be changed may be provided.

  Further, a coefficient phase conversion unit that changes the phases of the coefficients Qa and Qb when the phase difference between the start of the limiter operation in the periodic disturbance detection value and the current periodic disturbance detection value exceeds a threshold value may be provided. good.

  According to the present invention, in the periodic disturbance suppression control device with a learning function, it is possible to appropriately correct the coefficients Qa and Qb when the periodic disturbance suppression command value exceeds the upper limit value of the limiter.

It is a figure which shows the control structure which added the limiter countermeasure function to the general periodic disturbance suppression control apparatus with a learning function. It is a block diagram which shows the open loop of the periodic disturbance observer at the time of coefficient Qa, Qb measurement. It is a block diagram which shows the periodic disturbance suppression control apparatus of Embodiment 1. FIG. In this invention, it is explanatory drawing which shows a mode that the periodic disturbance changes when control is validated in the optimal state. In this invention, when a phase shift is 60 degree | times, it is explanatory drawing which shows a mode that a periodic disturbance changes. In this invention, it is explanatory drawing which shows a mode that a periodic disturbance changes, when an amplitude shift is 2.5 times and a phase shift is 10 degree | times. It is a flowchart which shows the coefficient correction amount operation | movement in this invention. 3 is a flowchart showing the operation of the first embodiment. It is a block diagram which shows the periodic disturbance suppression control apparatus of Embodiment 2. FIG. 10 is an explanatory diagram showing a locus of periodic disturbance suppression in the second embodiment. 10 is a flowchart illustrating the operation of the second embodiment. It is a block diagram which shows the periodic disturbance suppression control apparatus in Embodiment 3. It is explanatory drawing which shows the locus | trajectory of periodic disturbance suppression in Embodiment 3, and a phase error estimation operation | movement. 10 is a flowchart showing the operation of the third embodiment. It is explanatory drawing which shows the operation | movement of the periodic disturbance compensation by the periodic disturbance observer which made the learning function invalid. It is explanatory drawing which shows the angle of the convergence point of the periodic disturbance compensation by the periodic disturbance observer which invalidated the learning function. It is explanatory drawing which shows the case where the control method of Embodiment 3 does not operate | move correctly. It is a block diagram which shows the periodic disturbance suppression control apparatus in Embodiment 4. It is explanatory drawing which shows a mode that periodic disturbance is suppressed by Embodiment 4. FIG. 10 is a flowchart showing the operation of the fourth embodiment. It is a figure which shows an example in case phase correction is not correctly performed by a limiter operation | movement.

  FIG. 1 shows a control configuration in which a limiter countermeasure function is added to a general periodic disturbance suppression control apparatus with a learning function. Based on FIG. 1, the basic structure of the periodic disturbance suppression control apparatus with a learning function in this invention is demonstrated.

  First, an input signal detection value hdet on which a periodic disturbance to be removed is superimposed is input from the actual system. Further, the phase n is input from the actual system. This phase n is, for example, an output result of a PLL that receives a system voltage as input in the case of a grid-connected power converter, and is an output of a rotary encoder in the case of a motor.

  In accordance with the frequency of the periodic disturbance to be removed, the gain block 601 multiplies the phase by n, and calls the trigonometric function corresponding to the phase multiplied by n by the sin and cos blocks 602a and 602b. Multipliers 603a and 603b take the product of the obtained trigonometric function and the input signal detection value hdet to calculate the periodic disturbance detection value. Next, the frequency components to be suppressed (outputs of the multipliers 603a and 603b) are converted into direct current by the LPFs 605a and 605b. Here, the sine wave is used as a reference, the in-phase component of the detected sine wave of the n-th periodic disturbance detection value is the real axis component detection value hndret, and the 90 deg advance component is the imaginary axis component detection value hndetim.

  The obtained real axis component detection value hndetre and imaginary axis component detection value hndetim are input to the periodic disturbance observer 613. The configuration of the periodic disturbance observer 613 is shown below.

  Multipliers 606a to 606d and adders 607a and 607b are provided with hndetre as a real part and hndetim as an imaginary part, and a product of complex numbers Qa + jQb (coefficients Qa and Qb) is obtained. As a result, a signal that passes through the real system and cancels the transfer characteristics of the real system is obtained, and includes a signal that includes the periodic disturbance of the real system and the detection delay.

A signal including a periodic disturbance of this real system and a detection delay (a signal obtained by multiplying Qa + jQb), and a signal obtained by performing LPF processing in the LPFs 609a and 609b on the output of the periodic disturbance observer 613 and adding only the detection delay Is calculated by the adders 608a and 608b. The periodic disturbance estimated value is calculated by this calculation. That is, the estimated disturbance value is obtained by taking a deviation between two signals.
(1) The periodic disturbance suppression command values hnrefre and hnrefim pass through the real system and are multiplied by the products of the coefficients Qa and Qb to cancel the transfer characteristic of the real system. (2) The periodic disturbance suppression command values hnrefre and hnrefim are Only the LPFs 609a and 609b are applied without passing through the actual system.

  The above (1) is a signal on which a disturbance on the actual system is superimposed, and the above (2) is a signal that does not include a disturbance, only LPFs 609a and 609b are applied to the periodic disturbance suppression command values hnrefre and hnrefim. By taking the difference between these two signals by the adders 608a and 608b, the estimated disturbance value can be obtained.

  Then, adders 610a and 610b take the deviation between the estimated disturbance value and the disturbance command value. The disturbance command value is set to 0 in order to suppress the disturbance to “0”.

  By this calculation, the real axis component hnrefre and imaginary axis component hnrefim of the periodic disturbance suppression command value for suppressing the periodic disturbance are obtained. The real axis component hnrefre and imaginary axis component hnrefim of the periodic disturbance suppression command value are subjected to LPF processing by LPFs 609a and 609b, and compared with the outputs of the adders 608a and 608b, and used for calculation of disturbance estimated values.

  The values obtained by the adders 610a and 610b (the real axis component hnrefre and the imaginary axis component hnretim of the periodic disturbance suppression command value) are subjected to limiter processing by the limiter countermeasure unit 620.

  In order to return the real axis component hnrefre and imaginary axis component hnrefim of the periodic disturbance suppression command value to the AC signal, the multipliers 611a and 611b multiply the trigonometric functions (sine wave and cosine wave), respectively, and the multipliers 611a and 611b. Are added by an adder 612 to calculate a periodic disturbance suppression command value href. This periodic disturbance suppression command value href is added to a current command value or the like for an active filter, for example.

  In order to realize the control by the periodic disturbance observer 613, it is necessary to obtain the coefficients Qa and Qb in advance. There are various methods for measuring the coefficients Qa and Qb, such as obtaining a ratio of input and output power spectral densities by inputting a Gaussian noise signal. Here, the simplest method will be described.

  First, the d-axis is defined as the real part and the q-axis is defined as the imaginary part. As a result, the amplitude change and phase change, which are transfer characteristics, are expressed in complex numbers. In FIG. 2, the real axis component hndetre and the imaginary axis component hndetim of the nth-order periodic disturbance detection value are set to hdetd and hdetq, and the periodic disturbance suppression command value hnrefre is set to hdref1.

  Next, the periodic disturbance suppression control device of FIG. 1 is changed to an open loop as shown in FIG. Set d-axis q-axis periodic disturbance command value of n-order periodic disturbance to zero (d-axis and q-axis periodic disturbance suppression command input to integrators 611a and 611b by setting switch SW3 downward) Both the values are set to zero), and the periodic disturbance suppression control device is operated, and the n-th order periodic disturbance detection values of the input signal detection values hdet on the d-axis and q-axis at that time are set to hddd0 and hdetq0, respectively. After measuring the n-th order periodic disturbance detection values hddd0, hdetq0, all the switches SW1 to SW3 in FIG. 2 are switched to the upper side, the d-axis periodic disturbance suppression command value is changed to hdref1, and the d-axis q-axis periodic disturbance is changed. The n-th order periodic disturbances hddd1 and hdtq1 of the detection value hdet are measured. From the above measurement, the transfer characteristic Pa + jPb from the periodic disturbance suppression command value href to the input signal detection value hdet can be expressed by the following equation (1).

  Pa represents an output of the same phase with respect to the input command value, and Pb represents an output of 90 deg phase advance with respect to the input command value. The inverse characteristic Qa + jQb is an inverse number of the transfer characteristic Pa + jPb as shown in the following equation (2).

  When the n-th order periodic disturbance detection value of the periodic disturbance detection value hdt is hddd, hdetq, the transfer characteristic can be canceled by the calculation of the following equation (3).

  Next, the coefficient correction amount calculation unit 100 and the coefficient correction unit 200 that perform the learning function of the coefficients Qa and Qb will be described.

  First, in the coefficient correction amount calculation unit 100, the average processing units 101a and 101b extract DC components based on the periodic disturbance detection values output from the multipliers 603a and 603b. In the average processing units 101a and 101b, the input signal is integrated in one period of the fundamental wave, and the result is output. Here, one period of the fundamental wave is 50 Hz or 60 Hz in the grid-connected power converter, and is a time required for one rotation in the motor.

The Z ^-1 calculator (for example, buffer) 103a, 103b, 104, 105 outputs a periodic disturbance detection value one cycle before the periodic disturbance detection value.

In the subtraction units 102a and 102b, the current periodic disturbance detection value output from the average processing units 101a and 101b and the periodic disturbance detection value one cycle before output from the Z ⁻¹ calculators 103a and 103b are calculated. Calculate the difference. The outputs of the subtracters 102a and 102b are the amount of change between the period before and the current period of the periodic disturbance detection value, and the outputs of the Z- ¹ calculators 104 and 105 are the period disturbance detection values one period before. is there. The amount of change in the detected periodic disturbance value and the detected periodic disturbance value one period before are converted into polar coordinates by the polar coordinate converters 106 and 107, respectively.

  The adder 108 obtains a phase error estimate value of the periodic disturbance vector by using the output of the polar coordinate conversion unit 106 as a positive input, the output of the polar coordinate conversion 107 as a negative input, and π as a positive input. This phase error estimated value is subjected to moving average processing by the moving average processing unit 109.

  The moving average processing unit 109 includes a terminal that outputs a variation in the estimated phase error value. That is, the absolute value of the variation in the phase error estimated value is obtained by the ABS 110, and it is determined by the comparator 111 whether or not the result is less than θth. When the absolute value of the variation in the phase error estimated value is less than θth, A one-level signal is output to the switch 112.

  The switch 112 outputs 0 when the input signal from the comparator 111 is 0 level, and outputs the calculation result of the moving average processing unit 109 when the input signal from the comparator 111 is 1 level.

  A switch 113 is further provided at the subsequent stage of the switch 112, and the switch 113 is switched by the comparator 121 and the AND element 122. That is, the estimation result of the phase error detection value is output only when the amplitude of the periodic disturbance detection value exceeds Ath, and 0 is output when the amplitude of the periodic disturbance detection value is equal to or less than Ath. The output of the switch 113 becomes the phase correction amount command value Qpc.

  On the amplitude side, the gain unit 114 divides the output of the polar coordinate converter 106 (the amplitude of the detected value change amount during one period) by the fundamental frequency Tf. The result is divided by the divider 115 by the periodic disturbance detection value one cycle before (the output of the polar coordinate conversion unit 107). It is theoretically known that the value thus obtained is a / T, where a is the amplitude error and T is the LPF time constant in the periodic disturbance observer 613.

  Comparators 116 and 117 compare the output of divider 115 with k1 / T and 1 / k2T (gains k1 and k2 are real numbers greater than 1). Comparator 116 outputs a 1-level signal if the output of divider 115 is greater than k1 / T, and comparator 117 outputs a 1-level signal if the output of divider 115 is less than 1 / k2T.

  The outputs of the comparators 116 and 117 are output to the switches 118 and 119, respectively. The switch 118 outputs 1 if the signal from the comparator 117 is a 0 level signal, and the signal from the comparator 117 is 1 level. If it is a signal, k2 is output. On the other hand, the switch 119 outputs the output signal of the switch 118 when the signal from the comparator 116 is 0 level, and outputs 1 / k1 when the signal from the comparator 116 is 1 level. That is, the switch 119 outputs 1 / k1 if the division result of the divider 115 is larger than k1 / T, outputs 1 if it is 1 / k2T or more and k1 / T or less, and is smaller than 1 / k2T. Outputs k2.

  A switch 120 is further provided in the subsequent stage, and the output of the switch 119 is output as the amplitude correction command value Qac only when the amplitude of the periodic disturbance detection value exceeds Ath. On the other hand, when the amplitude of the periodic disturbance detection value is Ath or less, 1 is output from the switch 120 as the amplitude correction command value Qac.

The coefficient correction unit 200 subtracts the difference between the phase correction amount command value Qpc of the coefficient calculated by the coefficient correction amount calculation unit 100 and the phase correction amount command value of the previous cycle output from the Z ⁻¹ calculator 202b. Calculated at 204. The output of the subtracter 204 is added to the initial value Qpi of the coefficient (phase) in the adder 205.

Further, a limiter process is performed on the coefficient amplitude correction amount command value Qac calculated by the coefficient correction amount calculation unit 100 using the upper limit value and the lower limit value set based on the device rated capacity by the limiter 207, and Z ^{−. One} calculator 202a outputs an amplitude correction amount command value one cycle before. The multiplier 201 multiplies the amplitude correction amount command value Qac of the coefficient calculated by the coefficient correction amount calculation unit 100 by the amplitude correction amount command value of the previous cycle stored in the Z ⁻¹ calculator 202a. The multiplier 203 multiplies the output of the multiplier 201 by the coefficient (amplitude) initial value Qai.

  The outputs of the multiplier 203 and the adder 205 are input to the polar coordinate conversion unit 206, and are converted into polar coordinates by the polar coordinate conversion unit 206 to update the coefficients Qa and Qb. The coefficients Qa and Qb are multiplied by the real axis component detection value hndetre and the imaginary axis component detection value hndetim of the periodic disturbance suppression command value by multipliers 606a to 606d and input to adders 607a and 607b.

  Next, the limiter countermeasure unit 620 will be described.

  The limiter countermeasure unit 620 is provided after the adders 610a and 610b, and includes a limiter 621, multipliers 622a and 622b, a hold block 623, an adder 624, and a timer 625.

  The limiter 621 is set with an upper limit value of the device rated capacity. When the input signal exceeds the upper limit value, the limiter 621 reduces the input signal to the upper limit value and outputs it. The limiter 621 has an output terminal for outputting a signal indicating an operating state (a signal that becomes 1 level when the output signal is reduced to the upper limit value of the device rated capacity), and the output terminal includes a hold block. 623. Once the 1-level signal is input, the hold block 623 continues to output the 1-level signal until a reset command is input.

  The output of the hold block 623 is input to the timer 625, and a reset command is output from the timer 625 to the hold block 623 after a certain time has elapsed since the 1-level signal was input to the timer 625.

  The adder 624 takes the output of the hold block 623 as a negative input and 1 as a positive input, and outputs the result to the multipliers 622a and 622b. The multipliers 622a and 622b multiply the outputs of the limiter 621 and the adder 624 to obtain the real axis component hnrefre and imaginary axis component hnrefim of the periodic disturbance suppression command value. That is, the multipliers 622a and 622b output 0 while the hold block 623 outputs a 1-level signal, and output the limiter 621 as it is while the hold block 623 outputs a 0-level signal. Output.

  The output of the hold block 623 is inverted in level and input to the AND element 122, and the AND element 122 is connected to the switches 113 and 120 on the output side of the coefficient correction amount calculation unit 100. That is, while the 1-level signal is output from the hold block 623, 1 is output from the switch 120 as the amplitude correction amount command value Qac, and 0 from the switch 113 is output as the phase correction amount command value Qpc.

[Embodiment 1]
FIG. 3 is a configuration diagram illustrating the periodic disturbance suppression control device according to the first embodiment. In the first embodiment, the basic configuration is applied to an active filter. Since the first embodiment is specialized for an active filter, it differs from the first embodiment in the following points.

  An input signal detection value input to the periodic disturbance suppression control device is Iout + Iload, and the periodic disturbance detection values are Ihd and Ihq. In addition, the real axis component and the imaginary axis component of the periodic disturbance suppression command value are Idn and Iqn, and the periodic disturbance suppression command value is Ihdef and Iqref.

  Since the input signal detection value Iout + Iload is three-phase, the input signal detection value Iout + Iload is converted into a DC component using the dq converter 615. Further, the dq conversion unit 616 performs dq reverse conversion when converting the real axis component Idn and the imaginary axis component Iqn of the periodic disturbance suppression command value to AC. Further, since the real system that inputs the periodic disturbance suppression command values Ihdref and Ihqref is an ACR configured on the dq coordinates, the obtained periodic disturbance suppression command values Ihdref and Ihqref are dq converted by the dq conversion unit 617 with a fundamental wave. .

  Further, in order to extract the DC component effectively, the LPFs 605a, 605b, 609a, and 609b are used in combination with the average processing units 604a, 604b, 614a, and 614b to remove disturbances such as noise. In the first embodiment, the dq conversion unit 618 and the average processing units 604a and 604b constitute a DFT (Discrete Fourier Transform) calculation unit (periodic disturbance detection unit) 618.

  Further, the divider 115 with a large CPU load is removed from the coefficient correction amount calculation unit 100. Here, the changed part of the coefficient correction amount calculation unit 100 will be described.

  The signals subjected to the polar coordinate conversion by the polar coordinate conversion units 106 and 107 are compared in the adders 124 and 125 and the determination units 128 and 129, respectively.

  That is, the adder 124 compares the amplitudes of the periodic disturbance vectors with the output of the polar coordinate conversion unit 106 as a positive input and the output of the polar coordinate conversion unit 107 multiplied by 0.9 by the multiplier 126 as a negative input. .

  The adder 125 compares the amplitudes of the periodic disturbance vectors with the output of the polar coordinate conversion unit 106 as a positive input and the output of the polar coordinate conversion unit 107 multiplied by 0.2 by the multiplier 127 as a negative input. .

  Then, the determination unit 128 determines whether or not the output of the adder 125 is less than zero (whether or not the amplitude change amount exceeds 20%). If the output is less than zero, the amplitude correction amount changeover switch 118 is set to 2. Switch to double side.

  In addition, it is determined in the determiner 129 whether or not the output of the adder 124 exceeds zero, and if it exceeds zero, the amplitude correction amount changeover switch 119 is switched to the 0.5 times side.

In addition, even when the periodic disturbance detection values Ihd and Ihq are determined to be within 0.5% of the ratings by the determination unit 121, the phase correction amount changeover switch 113 is switched to the zero side, and the switch 120 is switched to the 1 side. Correction and amplitude correction are not performed. This is due to the following two reasons.
・ If it is within 0.5% of the rating, suppression of periodic disturbances operates normally, and the coefficients Qa and Qb are also considered appropriate. ・ If the amplitude is small, the accuracy of polar coordinate conversion decreases. Is the same as the basic configuration shown in FIG.

  Next, the operation of the periodic disturbance observer 613 will be described.

  FIG. 4 shows how the periodic disturbance detection values Ihd and Ihq by the DFT calculation unit 618 of the input signal detection value Iout + Iload change when the control is enabled under the optimum conditions of the coefficients Qa and Qb. The input signal detection value Iout + Iload before starting control is d-axis, q-axis periodic disturbance detection value is Ihd0, Ihq0, d-axis is n cycles after control start, q-axis periodic disturbance detection value is Ihdn, Ihqn, complex Plotted on a plane. If the coefficients Qa and Qb are optimal, as shown in FIG. 4, the locus of the detected periodic disturbance detection values Ihd and Ihq linearly goes to the origin, and the periodic disturbance is suppressed.

  Next, FIG. 5 shows how the periodic disturbance detection values Ihd and Ihq change when the amplitudes of the coefficients Qa and Qb are optimum, but the phase is shifted by +60 deg from the optimum value. In FIG. 5, the vector (Ihd1-Ihd0, Ihq1-Ihq0) indicating the compensation amount by the control is shifted by a certain angle with respect to the line segment between the origin and (Ihq0, Ihq0), and the curve trace is drawn and converged over time. To do. This angle corresponds to the phase error estimated value φ of the coefficients Qa and Qb, and is +60 deg in this example. Therefore, the phase error estimated value φ of the coefficients Qa and Qb can be obtained by detecting the angle during the compensation operation.

In order to calculate the phase error estimated value φ, the following vectors are required.
-Periodic disturbance detection value one cycle before (Ihd0, Ihq0) (output of polar coordinate converter 107)
The amount of change in the periodic disturbance detection value between the previous cycle and the current time (Ihd1-Ihd0, Ihq1-Ihq0) (output of the polar coordinate conversion unit 106)
The phase error estimated value φ can be obtained by the following equation.

  Where arg is a symbol representing the angle of deviation of the complex plane.

  The above is a case where it is assumed that changes in the periodic disturbance detection values Ihd and Ihq corresponding to the vectors (Ihd1-Ihd0, Ihq1-Ihq0) are due to the compensation operation. However, in practice, disturbances such as changes in the periodic disturbance detection values Ihd and Ihq due to load fluctuations are also included. It is necessary to remove the influence of this disturbance.

  As a method for removing the disturbance, the moving average unit 109 first takes a moving average for the detected phase error estimated value (φ). Next, the comparator 111 confirms the variation in the phase error estimated value (φ). If the variation is large, it is considered that the error due to the disturbance is included in the estimated phase error value (φ), and the phase correction amount changeover switch S112 is switched to zero and the phase correction is not performed. This is one of the conditions. In FIG. 3, the variation is within θth.

  FIG. 6 shows how the periodic disturbance detection values Ihd and Ihq change when the phases of the coefficients Qa and Qb are shifted by −10 deg from the optimum value and the amplitude is set to 2.5 times the optimum value. In FIG. 6, the amplitude of the vector (Ihd1-Ihd0, Ihq1-Ihq0) indicating the compensation amount by the control is longer than the amplitude of (Ihd0, Ihq0), and overshoot occurs in the compensation operation. By detecting that the compensation amount exceeds the detection value in this way, it is possible to detect that the amplitudes of the coefficients Qa and Qb are excessive. Similarly, when the compensation amount is extremely small with respect to the detected value, it means that the amplitudes of the coefficients Qa and Qb are insufficient.

  The manner in which the periodic disturbance detection value changes is changed by the first-order lag filters (LPFs 605a and 605b) or the filters of the average processing units 604a and 604b. In FIG. 6, average processing and first-order lag filters (LPFs 605a and 605b) having a time constant of 20 ms are used. Therefore, if the coefficients Qa and Qb are appropriate, the convergence operation is close to the characteristics of the first-order lag filter as shown in FIG. With a time constant of 20 ms, the amplitude of (Ihd1-Ihd0, Ihq1-Ihq0) is about 60% with respect to (Ihd0, Ihq0). The same applies to the case where the phases of the coefficients Qa and Qb are shifted.

  Therefore, in FIG. 3, when the amplitude of (Ihd1-Ihd0, Ihq1-Ihq0) exceeds 90% with respect to (Ihd0, Ihq0), the comparator 129 determines that the amplitude is excessive, and the amplitude correction amount changeover switch 119 is switched to the 0.5 side, and the amplitude is multiplied by 0.5. Similarly, if it is less than 20%, the comparator 128 determines that the amplitude is insufficient, and switches the amplitude correction amount changeover switch 118 to the 2 side to double the amplitude. Thereby, the amplitude can be brought close to an appropriate value.

  The correction operation so far is shown in the flowchart of FIG.

  Step S41: The periodic disturbance detection values Ihd and Ihq are detected by the DFT calculation unit 618.

  Step S42: The compensation amount is detected by the polar coordinate converters 106 and 107.

  Step S43: The comparator 121 determines whether or not the periodic disturbances Ihd0 and Ihq0 are 0.5% or more of the device rated capacity.

  Step S44: If the decision result in the step S43 is NO, the switch 120 is switched to 1 side and 1 is set to the amplitude correction amount command value Qac.

  Step S45: When the determination result in Step S43 is YES, the comparator 129 determines whether the amplitude of (Ihd1-Ihd0, Ihq1-Ihq0) exceeds 90% with respect to (Ihd0, Ihq0). .

  Step S46: If the decision result in the step S45 is YES, the switch 119 is switched to the 0.5 side and 0.5 is set to the amplitude correction amount command value Qac.

  Step S47: When the determination result in Step S45 is NO, the comparator 128 determines whether the amplitude of (Ihd1-Ihd0, Ihq1-Ihq0) is less than 20% with respect to (Ihd0, Ihq0). If the determination result is NO, step S44 is executed.

  Step S48: If the decision result in the step S47 is YES, the switch 118 is switched to the 2 side and 2 is set to the amplitude correction amount command value Qac.

  Step S49: The phase error estimated value (φ) is measured by the addition operation by the adder 108.

  Step S50: The moving average of the phase error estimated value φ is calculated by the moving average unit 109.

  Step S51: The ABS 110 calculates the absolute value of the variation of the phase error estimated value (φ).

  Step S52: The comparator 111 determines whether or not the variation of the phase error estimated value (φ) is within θth.

  Step S53: If the determination result in step S52 is YES, the comparator 121 determines whether the periodic disturbance is 0.5% or more of the rating.

  Step S54: If the decision result in the step S53 is YES, the switch 112 is switched to the side opposite to zero (the moving average unit 109 side), and the phase error estimated value φ is set to the phase correction amount command value Qpc.

  Step S55: If the determination results in steps S52 and S53 are NO, the switches 112 and 113 are switched to zero to set the phase correction amount command value Qpc to zero.

  The correction operation can be changed according to the purpose. For example, when it is desired to suppress the occurrence of overshoot, there is a method of setting an amplitude increase condition to detect an amplitude shortage in all fixed periods and further reducing the amplitude increase amount to 1.5 times.

  Also, when it is necessary to increase the accuracy of the amplitudes of the coefficients Qa and Qb, for example, to increase the response of periodic disturbance suppression, the conditions for over / under amplitude are set loosely such as 80% or more and less than 50%. This can be realized by setting the amplitude adjustment amount as small as 1.1 times or 0.9 times.

  The above is a case where the filter of the DFT calculation unit 618 is combined with 50 Hz average processing and LPF. If the filter is different, the periodic disturbance suppression operation also changes. For example, when 50 Hz moving average is selected for the filter, the amplitudes of (Ihd1-Ihd0, Ihq1-Ihq0) and (Ihd0, Ihq0) match if the coefficients Qa and Qb are appropriate. Therefore, if the amplitude of (Ihd1-Ihd0, Ihq1-Ihq0) exceeds 120% with respect to (Ihd0, Ihq0), it is determined that the amplitude is excessive, and if the amplitude is 0.5 times or less than 50%, the amplitude is regarded as insufficient. It is necessary to change the amplitude correction condition such as 2 times.

  By applying the above correction function, even if the initial value Qai of the amplitude and the initial value Qpi of the phase are inappropriate values including large errors, the coefficients Qa and Qb are automatically corrected to realize stable periodic disturbance suppression. .

  In the unlikely event that the phase shift is π / 2 or more, the periodic disturbance after the start of control will increase the periodic disturbance, but at this time as well, the coefficient is obtained by detecting the phase error estimated value φ during the compensation operation. The phase shift between Qa and Qb can be corrected, and the operation switches to the periodic disturbance suppression operation. Therefore, in any state, the periodic disturbance is finally suppressed, so that the trial run can be omitted.

It is assumed that the correction functions for the coefficients Qa and Qb are operated once during one period of the fundamental wave. The reason is shown below.
・ Because average processing is used for DFT calculation, it takes time for one period of the fundamental wave to update the detection value. ・ A certain amount of time is required to obtain the amount of change in the periodic disturbance detection values Ihd and Ihq.・ Polar coordinate transformation used to estimate coefficients Qa and Qb is computationally expensive and reduces the computational burden by increasing the interval. However, if you want to shorten the time to suppress periodic disturbances or reduce the computational burden further. For example, the correction interval can be changed according to the purpose.

  Next, the limiter countermeasure unit 620 will be described.

  First, the limiter 621 monitors whether or not the absolute values of the periodic disturbance suppression command values Idn and Iqn exceed the set upper limit values, and if so, decreases the periodic disturbance suppression command values Idn and Iqn. If the upper limit value is not exceeded, the added limiter countermeasure circuit 620 does not operate, and thus the operation is exactly the same as the conventional one. The limiter countermeasure unit 620 is the same as the basic configuration (FIG. 1).

  If the limiter 621 operates even for a moment, 1 is continuously output from the hold block 623, so that zero is input to the multipliers 622a and 622b at the subsequent stage of the limiter 621, and the periodic disturbance suppression command values Idn and Iqn become zero. The periodic disturbance suppression command values Idn and Iqn are also input to the averaging units 614a and 614b and LPFs 609a and 609b inside the periodic disturbance observer 613, so that the LPFs 609a and 609b take zero over a time equivalent to a time constant. Reset.

  The output of the hold block 623 is also input to the AND element 122 of the coefficient correction amount calculation unit 100. Since the signal from the hold block 623 is inverted by the AND element 122, the output of the AND element 122 becomes zero when the limiter 621 operates, and the outputs of the switches 120 and 113 are fixed at Qac = 1 and Qpc = 0. . Thereby, after the operation of the limiter 621, the correction function of the coefficients Qa and Qb is stopped for a certain time.

  If a certain time elapses after the operation of the limiter 621, the hold block 623 is reset by a reset command of the timer 625. After this, the periodic disturbance observer 613 and the coefficient Qa, Qb correction function (coefficient correction amount calculation unit 100) resume operation. Immediately after the restart, since the values of the periodic disturbance suppression command values Idn and Iqn are zero, there is a time margin until the periodic disturbance suppression command values Idn and Iqn reach the upper limit value of the limiter 621 again.

  If the coefficients Qa and Qb can be corrected in the meantime, the periodic disturbance can be suppressed. Even if the correction of the coefficients Qa and Qb is not successful and the limiter 621 is applied again, the correction of the coefficients Qa and Qb can be retried by repeating the above operation.

  FIG. 8 is a flowchart showing processing steps in the first embodiment. The processing in the first embodiment will be described based on the flowchart of FIG.

  S11: It is determined whether the output of the hold block 623 is 1 (that is, whether the coefficient correction function is invalid). Normally, at the start of processing, the correction function for the coefficients Qa and Qb is effective, and the process proceeds to S12.

  S 12: The limiter 621 determines whether the periodic disturbance suppression command values Idn and Iqn exceed the upper limit value of the limiter 621. If the upper limit value of the limiter 621 is not exceeded, nothing is done, the process is terminated, and the process is started from S11. At this time, since the correction functions for the coefficients Qa and Qb remain valid, the operation is the same as in the conventional control. If the upper limit value of the periodic disturbance suppression command value Idn, Iqn limiter 621 is exceeded, the process proceeds to S13.

  S13: The correction function of the coefficients Qa and Qb is disabled by the AND element 122 and the switches 113 and 120.

  S14: The periodic disturbance suppression command values Idn and Iqn are fixed to 0 by the multipliers 622a and 622b, and the periodic disturbance observer 613 is stopped.

  S15: The hold block 623 outputs a 1-level signal to the timer 625 and starts the timer 625.

  Also, the process is started from S11, and when the correction function of the coefficients Qa and Qb is invalid, the process proceeds to S16.

  S16, S17: If a fixed time (time set in the timer 625) has elapsed since the correction function of the coefficients Qa, Qb is disabled, the process proceeds to S17, and the AND element 122 and the switches 113, 120 cause the coefficients Qa, The Qb correction function is reactivated.

  S18: The operation of the periodic disturbance observer 613 is restarted by canceling zero fixation of the periodic disturbance suppression command values Idn and Iqn by the multipliers 622a and 622b.

  Note that if the fixed time has not elapsed since the coefficient correction function was disabled in S16, the process is terminated, and the process is started from S11.

  In the first embodiment, it is assumed that the periodic disturbance is small and it is known that the periodic disturbance can be sufficiently suppressed with the periodic disturbance suppression command values Idn and Iqn within the upper limit value of the limiter 621.

  When the periodic disturbance suppression command values Idn and Iqn exceed the device rated capacity, the periodic disturbance suppression command values Idn and Iqn reach the limiter 621 and become zero even if the coefficients Qa and Qb are correct. End up.

  As described above, according to the first embodiment, in the periodic disturbance suppression control apparatus, when the periodic disturbance suppression command values Idn and Iqn exceed the upper limit value of the limiter 621, a learning function (coefficient correction) is temporarily performed. The quantity calculation unit 100) and the periodic disturbance observer 613 are stopped, and the periodic disturbance suppression command values Idn and Iqn are reduced to zero, thereby prompting recorrection of the coefficients Qa and Qb and without being affected by the limiter 621. Qa and Qb can be estimated with high accuracy.

  In addition, since the number of blocks to be added to the conventional configuration is small and the load on the CPU or the like is small, the implementation is easy.

[Embodiment 2]
FIG. 9 is a configuration diagram showing the periodic disturbance suppression control apparatus according to the second embodiment, which is applied to an active filter. The second embodiment is different from the first embodiment in the following points.

  A limiter 621 is provided after the adders 610a and 610b for adding the disturbance command value 0. The limiter 621 uses the periodic disturbance suppression current command values Idn and Iqn as the output signals, and signals indicating the operation state (the input signal is the limiter 621). And an output terminal that outputs a signal that is larger than the upper limit value and becomes one level when the output signal is reduced to the upper limit value.

Further, a limiter countermeasure circuit 300 is provided, and an operation state output terminal of the limiter 621 is connected to the timer 301 of the limiter countermeasure circuit 300. The timer 301 outputs the elapsed time after the 1-level signal is input to the Z ⁻¹ calculators 302a to 302d. For example, the Z ⁻¹ calculators 302a and 302b store the periodic disturbance detection values Ihd and Ihq at the time when the output of the timer 301 is 1 m [sec] (m is an integer equal to or greater than zero). The Z ⁻¹ calculators 302 c and 302 d store the outputs of the Z ⁻¹ calculators 302 a and 302 b when the output of the timer 301 is 1 m [sec]. In the subsequent stage of each of the Z ^-1 calculators 302a to 302d, multipliers 303a to 303d for finding the squares of the stored periodic disturbance detection values Ihd and Ihq, and Ihd ² and Ihq ² squared by the multipliers 303a to 303d, respectively. Adders 304a and 304b to be added are installed.

  A subtracter 305 and a comparator 306 are provided at the subsequent stage of the adders 304a and 304b, and the magnitudes of the two absolute values obtained previously (outputs of the adders 304a and 304b) are compared. That is, the output of 304b is subtracted from the output of the adder 304a by the subtractor 305, whether or not the output of the subtractor 305 is larger than 0 is compared by the comparator 306, and the output of the subtracter 304 is smaller than 0. When it is large, a 1-level signal is output, and when it is 0 or less, a 0-level signal is output.

  A switch 307 is provided at the subsequent stage of the comparator 306. The switch 307 outputs -0.5 when the output of the comparator 306 is 1 level, and outputs 1 when the output is 0 level.

An output signal of the switch 307 is multiplied by an output signal of a Z ^-1 calculator 309 described later by a multiplier 308 and output to the switch 310. The switch 310 outputs the output signal of the multiplier 308 when the limiter 621 is operating, outputs π / 6 when the limiter 621 is not operating, and sets the Z ⁻¹ calculator 309 at the subsequent stage to π. Reset to / 6.

The output of the switch 310 is output to the Z ⁻¹ calculator 309, and the Z ⁻¹ calculator 309 stores the output of the switch 310 and outputs it to the switch 311 and the lower limit setting unit 312. A lower limit value is set in the lower limit setting unit 312, a limiter process is performed on the absolute value in the output of the Z ⁻¹ calculator 309, and the result is output to the multiplier 308.

The switch 311 outputs the output of the Z ⁻¹ calculator 309 when the limiter 621 is operating, and outputs zero when the limiter 621 is not operating. The output of the switch 311 is input to the adder 123. The other input of the adder 123 is a signal that has been used as the conventional phase correction amount command value Qpc. The conventional phase correction amount command value and the newly added phase correction value are added to obtain a new phase correction amount command value Qpc.

  The operation signal of the switch 120 in the previous stage of the amplitude correction amount command value Qac and the switch 113 that has output the phase correction command value Qpc in the conventional configuration is an output signal of the AND element 122 and is switched down during the operation of the limiter 621. That is, the switch 120 outputs 1 as the amplitude correction amount command value Qac, and the switch 113 outputs 0 to the adder 123.

  The operation when the periodic disturbance suppression control apparatus according to the second embodiment is applied to an active filter will be described below.

  When the limiter 621 provided in the periodic disturbance observer 613 is not operating, the switch 311 outputs 0, and the switches 120 and 113 are the amplitude correction amount command values Qac and phase correction amount command values of the conventional coefficients Qa and Qb. Qpc is output. For this reason, it becomes the same operation | movement as before.

When the limiter 621 operates, the timer 301 is started, and when the timer 301 reaches 1 m [sec] (m is an integer equal to or greater than zero), the Z ⁻¹ calculators 302a to 302d store the periodic disturbance detection values (Ihd, Ihq). . For example, after the limiter 621 operates and 1 [sec] has elapsed, the two Z ⁻¹ calculators 302a and 302b hold the current values, and the two Z ⁻¹ calculators 302c and 302d Holds the value.

The subsequent stage multipliers 303a to 303d and the adders 304a and 304b obtain the squares of the absolute values of the periodic disturbance detection values Ihd and Ihq. When combined with the subtractor 305 and the comparator 306, the switch 307 It becomes the operation like this.
The absolute values of the periodic disturbance detection values Ihd and Ihq before 1 [sec] and after 1 [sec] are compared. If the absolute values of the periodic disturbance detection values Ihd and Ihq after 1 [sec] are large, −0 .5 is output.
The absolute values of the periodic disturbance detection values Ihd and Ihq before 1 [sec] and after 1 [sec] are compared, and 1 when the absolute value of the periodic disturbance detection values Ihd and Ihq before 1 [sec] is large. Is output.

The switch 310 switches to the lower side when the limiter 621 is not operating, resets the Z ⁻¹ calculator 309 to π / 6, and switches to the multiplier 308 side when the limiter 621 is operating. The product of the ^-1 calculator 309 and the switch 307 is output.

As described above, the limiter countermeasure circuit 300 added in the second embodiment operates as follows.
When the limiter 621 starts operating, the periodic disturbance detection values Ihd and Ihq at that time are stored, π / 6 is output as the phase correction amount command value Qpc, and the phases of the coefficients Qa and Qb are changed by π / 6.
When 1 [sec] has elapsed after the phase change, the periodic disturbance detection values Ihd and Ihq are stored again and compared with the amplitude of the periodic disturbance detection values Ihd and Ihq one [sec] before by the comparator 306. .
As a result of comparison, if the amplitudes of the periodic disturbance detection values Ihd and Ihq after 1 sec are smaller, π / 6 is output as the phase correction amount command value Qpc, and the phases of the coefficients Qa and Qb are changed. Further, π / 6 is changed.
As a result of comparison, when the amplitudes of the periodic disturbance detection values Ihd and Ihq after 1 [sec] have elapsed, −π / 12 is output as the phase correction amount command value Qpc, and the phases of the coefficients Qa and Qb Is changed by −π / 12.
By repeating the above, the sign of the phase correction amount Qpc is inverted and the magnitude is halved each time the amplitude of the periodic disturbance detection values Ihd and Ihq after 1 [sec] elapses.
However, a lower limit is set by the lower limit setting unit 312 to the absolute value of the phase correction amount Qpc.

  With the above operation, the phases of the coefficients Qa and Qb that minimize the amplitude of the periodic disturbance detection values Ihd and Ihq are searched.

  FIG. 10 shows a trajectory in which the periodic disturbance detection values Ihd and Ihq are suppressed in the configuration in which the periodic disturbance suppression control apparatus according to the second embodiment is applied to an active filter. The periodic disturbance detection values are developed on a plane with the horizontal axis being Ihd and the vertical axis being Ihq.

  The point O indicates the initial values of the periodic disturbance detection values Ihd and Ihq before the active filter operation, and the broken-line circle is centered on the initial value O of the periodic disturbance detection values Ihd and Ihq and the device rated capacity is the radius. Therefore, when this active filter is operated, the periodic disturbance detection values Ihd and Ihq can be changed in the region inside the broken-line circle.

  Now, the active filter is operated with the phase error of the coefficients Qa and Qb being π / 2. Then, the locus advances by shifting the phase by π / 2 with respect to the origin, but if the conventional coefficient Qa, Qb correction function does not operate due to reasons such as the locus being too fast, the upper limit of the limiter 621 at point A. Multiplies to the value and stops almost without moving.

Here, the coordinates of the point A (periodic disturbance of each axis) are stored in the Z ⁻¹ calculators 302a and 302b, and the phase is corrected by π / 6. As a result, the phase errors of the coefficients Qa and Qb become π / 3, and the periodic disturbance detection values Ihd and Ihq move to the point B.

  After a sufficient time has elapsed (here, 1 [sec]), the coordinates of point B are stored, and the distance between origin-point A and the distance between origin-point B are compared. This time, since the distance between the origin and the point B is shorter, it is determined that there is an effect of phase correction, and the phase is further corrected by π / 6 and moved to the point C.

  By repeating this, the periodic disturbance detection values Ihd and Ihq move to the point E. At this time, since the distance between the origin and the point E is larger than the distance between the origin and the point D, it is determined that there is no effect of the phase correction, and the phase correction amount is −π / 12. As a result, the periodic disturbance detection values Ihd and Ihq start to advance in the opposite direction.

  By repeating the above, the periodic disturbance detection values Ihd and Ihq finally converge to the point D closest to the origin while oscillating. Although the vibration remains until the end, the phase correction amount command value Qpc of the coefficients Qa and Qb decreases, so the amplitude of the vibration becomes very small.

  Further, if the system condition fluctuates, the phase correction is performed again based on the above operation. Furthermore, when the load becomes light and the periodic disturbance detection values Ihd and Ihq become small, the limiter 621 does not operate and the conventional correction function is switched.

  In FIG. 10, if the phase errors of the coefficients Qa and Qb are negative amounts, the periodic disturbance detection values Ihd and Ihq go to the fourth quadrant (downward). At this time, since the first phase correction is directed to increase the error, the periodic disturbance detection values Ihd and Ihq are conversely increased. However, after 1 [sec], correction is performed in the reverse direction, so that the periodic disturbance detection values Ihd and Ihq finally converge to the point D closest to the origin.

  FIG. 11 is a flowchart showing the processing steps of the second embodiment.

  S21: If the periodic disturbance suppression command values Idn and Iqn have reached the upper limit value of the limiter 621, the process proceeds to S22. If the upper limit value of the limiter 621 has not been reached, the process proceeds to S33.

  S22: Start the timer 301 or continue the operation of the timer 301 if the timer 301 has already started.

  S23: If the timer 301 = 0 and the timer 301 is operating (immediately after the start of the timer 301 operation), the process proceeds to S24. If the timer 301 = 0 and the timer 301 is not operating, the process proceeds to S27.

S24: The periodic disturbance detection values Ihd and Ihq of the timer 301 = 0 (immediately after the limiter 621 operates) are stored by the Z ⁻¹ calculators 302a and 302b.

  S25: The phase correction amount is set to π / 6 by the switch 310.

  S26: The adder 123 adds the phase correction value to the phase correction amount command value Qpc.

S27, S28: Z ^-1 calculator 302a, by 302b, each time the timer 301 detects the 1 [sec] elapses, Z ^-1 calculator 302a, periodic disturbance detection value at the present time by 302b Ihd, amplitude Ihq And the amplitudes of the periodic disturbance detection values Ihd and Ihq before 1 [sec] are stored by the Z ⁻¹ calculators 302c and 302d.

  S29: The comparator 306 compares the current periodic disturbance detection values Ihd and Ihq with the amplitude of the periodic disturbance detection values Ihd and Ihq one [sec] before.

  S30: If the amplitude of the periodic disturbance detection values Ihd and Ihq at the present time is larger than the amplitude of the periodic disturbance detection values Ihd and Ihq before 1 [sec] by the comparator 306, the process proceeds to S31, and the current period If the amplitude of the detected disturbances Ihd and Ihq is smaller than the amplitude of the periodic disturbance detected values Ihd and Ihq before 1 [sec], the phase correction amount is left as it is, and the process proceeds to S26, and the phase correction amount π / 6 is set as the phase. Add to the correction amount command value Qpc.

  S31: The phase correction amount is multiplied by -0.5 by the switch 307.

  S32: The limiter 312 performs limiter processing on the phase correction amount.

  S33: When the output command values Idn and Iqn have not reached the upper limit value of the limiter 621, the timer 301 is stopped and reset.

  As described above, according to the second embodiment, when the periodic disturbance suppression command values Idn and Iqn exceed the upper limit value of the limiter 621, the coefficient Qa is confirmed while checking the amplitudes of the periodic disturbance detection values Ihd and Ihq. , Qb are corrected to find the optimum values of the phases of the coefficients Qa, Qb, and the periodic disturbance can be minimized by the periodic disturbance suppression command values Ihdref, Ihqref within the range of the limiter 621.

  Further, unlike the first embodiment, since the periodic disturbance suppression command values Idn and Iqn are not lowered to zero, it is not necessary to interrupt the suppression of the periodic disturbance, and the correction of the coefficients Qa and Qb and the compensation of the periodic disturbance are performed simultaneously. Can be done.

  Furthermore, in the first embodiment, when the periodic disturbance is large and the periodic disturbance suppression command values Idn and Iqn within the range of the limiter 621 cannot be compensated, the limiter 621 operates and sets the periodic disturbance suppression command values Idn and Iqn. Although the pulling-down operation is repeated, this unnecessary operation can be eliminated in the second embodiment.

[Embodiment 3]
FIG. 12 is a configuration diagram showing the periodic disturbance suppression control apparatus according to the third embodiment, which is applied to an active filter. The difference from the second embodiment is that an initial phase error determination unit 400 is provided.

In the third embodiment, the Z ^-1 calculators 302a to 302d of the limiter countermeasure circuit 300 added in the second embodiment operate in 1m + 1 [sec] (m is an integer equal to or greater than zero) after the timer 301 is started. It shall be.

Initial phase error judging unit 400, downstream of the timer 301, the periodical disturbance detection value Ihd, the Z ^-1 calculator 401a~401d for storing IHQ 4 one with, the Z ^-1 calculator 401a~401d limiter 621 It operates after 0 [sec] and 1 [sec] after the operation. Z ^-1 calculator 401a, 401b, the limiter 621 operates 1 [sec] after the elapse periodic disturbance detection value Ihd, stores IHQ, Z ^-1 calculator 401c, 401d limiter 621 operates Periodic disturbance detection values Ihd and Ihq after 0 [sec] are stored.

The adders 402a and 402b are installed in the subsequent stage of the Z ⁻¹ arithmetic units 401a to 401d, and the amount of change in the periodic disturbance detection values Ihd and Ihq between 0 [sec] immediately after the limiter 621 operation and 1 [sec] after it is operated. To detect.

  The polar coordinate conversion unit 403a performs polar coordinate conversion on the periodic disturbance detection values Ihd and Ihq after 1 [sec] after the operation of the limiter 621, and the polar coordinate conversion unit 403b converts the periodic disturbance detection values Ihd and Ihq between 1 [sec]. Convert the amount of change to polar coordinates.

  Similar to the conventional phase error estimation method for the coefficients Qa and Qb, the adder 404 calculates the phase error estimation values for the coefficients Qa and Qb from the polar coordinate conversion result. The comparator 405 compares the phase error estimation result with zero. The comparison result is output to the switch 406. If the phase error estimated value is greater than 0, π / 6 is output, and if the phase error estimated value is 0 or less, −π / 6 is output. The output of the switch 406 is input to the switch 310.

  The operation of the periodic disturbance suppressing device according to Embodiment 3 will be described below.

  The periodic disturbance observer 613 does not stop the operation immediately after the output periodic disturbance command values Idn and Iqn reach the upper limit value of the limiter 621, and moves slightly closer to the origin along the upper limit value of the limiter 621. . This operation does not depend on the errors of the coefficients Qa and Qb.

  The added initial phase error determination unit 400 uses this operation to determine the sign of the first phase correction amount after the periodic disturbance suppression command values Idn and Iqn reach the upper limit value of the limiter 621.

  FIG. 13 shows a state of a locus in which the periodic disturbance detection values Ihd and Ihq are suppressed in the configuration in which the periodic disturbance suppression control apparatus according to the third embodiment is applied to an active filter. The periodic disturbance detection values are developed on a plane with the horizontal axis being Ihd and the vertical axis being Ihq.

  The point O indicates the initial values of the periodic disturbance detection values Ihd and Ihq before the active filter operation, and the broken-line circles center on the initial values of the periodic disturbance detection values Ihd and Ihq and the device rated capacity is the radius. Therefore, when this active filter is operated, the periodic disturbance detection values Ihd and Ihq can be changed in the region inside the broken-line circle.

First, in FIG. 13, let us consider from the locus how the periodic disturbance detection values Ihd and Ihq are compensated when the phase errors of the coefficients Qa and Qb are θ _1A . As shown in FIG. 13, the phase error is represented by the angle between the origin and the locus point 1A of the periodic disturbance detection values Ihd and Ihq, taking the initial point O as a reference.

When the limiter 621 operates and the locus reaches a broken-line circle, the periodic disturbance detection values Ihd and Ihq move slightly closer to the origin as shown in FIG. 13, and then stop at the point 1A. At this time, if the phase error is obtained from the angle between the origin and the point 1B using the point 1A as a reference in the same manner as described above, θ _1B is obtained. Compared to θ _1A , the size is different, but the direction is clockwise as indicated by the arrow, so the signs are equal. Therefore, the angle θ _{1B at} which the limiter 621 operates is detected, and the sign thereof is used as the sign of the first phase correction amount.

On the other hand, in FIG. 13, it is considered from the locus how the periodic disturbance detection values Ihd and Ihq are compensated when the phase errors of the coefficients Qa and Qb are smaller than before and θ _2A .

At this time, when the phase error after the limiter 621 is operated is obtained, it becomes θ _2B , and the sign is different from θ _2A . Therefore, when the phase error between the coefficients Qa and Qb is small, the initial phase correction amount is reversed. However, since the subsequent operation is the same as that of the second embodiment, the phase correction amount is corrected in the correct direction after 1 [sec] has elapsed.

  FIG. 14 is a flowchart showing the processing steps of the third embodiment.

  S21 to S24: Almost the same as in the second embodiment. The difference from the second embodiment is that the periodic disturbance is stored immediately after the limiter 621 is operated (S24), and the phase correction of the coefficients Qa and Qb (S25). ) Is not performed.

  S40: If timer 301 = 1 [sec], the process proceeds to S41, and if timer 301 = 1 [sec], the process proceeds to S27.

S41: The periodic disturbance detection values Ihd and Ihq after 1 [sec] after the operation of the limiter 621 are stored in the Z ⁻¹ arithmetic units 401a and 401b, and the Z ⁻¹ arithmetic units 401c and 401d immediately after the operation of the limiter 621 (0 [Sec]) periodic disturbance detection values Ihd and Ihq are stored.

  S42: The phase between the periodic disturbance detection values Ihd and Ihq after 1 [sec] after the operation of the limiter 621 and the periodic disturbance detection values Ihd and Ihq immediately after the operation of the limiter 621 (0 [sec]) by the adder 404. Estimate the error.

  S43: The comparator 405 determines the sign of the phase error. If it is greater than 0, the process proceeds to S44, and if it is 0 or less, the process proceeds to S45.

  S44: The phase correction amount is set to π / 6 by the switch 406.

  S45: The phase correction amount is set to −π / 6 by the switch 406.

  S26: The adder 123 adds the phase correction amount to the phase correction amount command value Qpc.

  S27 to S32: Except for the timer 301 = 1m + 1 [sec] in S27, the operation is exactly the same as that of S27 to S32 of the second embodiment. If the output command value is not applied to the limiter 621 in S21, the process proceeds to S33, and the timer 301 is stopped and reset.

  In the third embodiment, the capacity that can be used by the active filter function is small due to the addition of another function in addition to the active filter function to the device such as the power conversion device, and the periodic disturbance suppression operation starts. It is assumed that the periodic disturbance suppression command values Idn and Iqn immediately reach the upper limit value of the limiter 621 and the conventional correction function of the coefficients Qa and Qb is difficult to operate.

  Conversely, when the active filter function alone has a large capacity and the coefficients Qa and Qb can be corrected almost certainly before the periodic disturbance suppression command values Idn and Iqn reach the upper limit value of the limiter 621, this is added in the third embodiment. The direction of the inequality sign of the comparator 405 in the initial phase error determination unit 400 is set in reverse. As a result, the initial phase correction amount after the operation of the limiter 621 can be matched when the phase error of the coefficients Qa and Qb is small, and it is possible to prevent the periodic disturbance from expanding and to quickly suppress it.

  Operation of the periodic disturbance suppression control apparatus described above “The periodic disturbance suppression command values Idn and Iqn reach the upper limit value of the limiter 621 and do not stop immediately, but slightly approach the origin along the limiter 621. It will be proved based on FIG.

In the periodic disturbance suppression control apparatus in which the automatic correction function of the coefficients Qa and Qb is disabled, the operation shown in FIG. In FIG. 15, the initial values of the periodic disturbance detection values Ihd and Ihq are taken as a reference, and the x axis is taken. (Initial phase error θ, periodic disturbance detection values Ihd, Ihq initial amplitude L, limiter 621 upper limit value r, L> r)
When a circular limiter is used as the limiter 621, if the direction of the vector in which the trajectory of the periodic disturbance detection values Ihd and Ihq is about to coincide with the normal direction of the circular limiter, the limiter 621 stops moving and stops. This is the convergence point. That is, as shown in FIG. 16, the angle formed by the line connecting the origin and the convergence point and the normal passing through the convergence point is θ. At this time, the angle between the origin and the convergence point when the center of the circular limiter is used as shown in FIG.

   Consider the initial phase error θ as 0 <θ <180 deg and the convergence point as 0 <α <180 deg. For simplification, it is considered that the trajectories of the periodic disturbance detection values Ihd and Ihq are almost straight until reaching the upper limit value of the limiter 621.

  The coordinates of the convergence point are (L-r cos α, r sin α). Therefore, when θ is represented by α, the following equation (5) is obtained.

Since L> r, the denominator of the tan ⁻¹ term is positive, and the numerator is also positive with 0 <α <180 deg. Therefore, the tan ⁻¹ term is positive.

  Therefore, θ> α is established. This indicates that the convergence point is always on the origin side with respect to the point that proceeds in the direction of θ as the initial phase error and first contacts the upper limit value of the limiter 621.

When the initial phase error θ is 0>θ> 180 deg and the convergence point is 0>α> −180 deg, the tan ⁻¹ term becomes negative, and θ <α. Also in this case, the convergence point is always on the origin side rather than the point that first contacts the upper limit value of the limiter 621.

  As described above, according to the third embodiment, in addition to the effects of the second embodiment, the following effects can be obtained.

  It is possible to estimate the sign of the initial value of the phase correction amount in the coefficients Qa and Qb.

  Further, when the limiter 621 operates in a state where the errors of the coefficients Qa and Qb are large and the periodic disturbance detection values Ihd and Ihq are expanded, the coefficients Qa and Qb are corrected so as to surely suppress the periodic disturbance. Can do.

  On the other hand, when the errors of the coefficients Qa and Qb are small, the correction of the first coefficients Qa and Qb is reversed, but since the errors of the original coefficients Qa and Qb are small, in most cases the periodic disturbance suppression control device No worse than before.

  Further, when the upper limit value of the limiter 621 is set high, the conventional correction function operates before the operation of the limiter 621, and the errors of the coefficients Qa and Qb are reduced. Therefore, the sign of the initial value is reversed. Thus, it is possible to shorten the time until suppression of periodic disturbance.

[Embodiment 4]
The problems of the second and third embodiments will be described. Although the periodic disturbance detection values Ihd and Ihq are smaller than the rated capacity of the device, the correction of the coefficients Qa and Qb does not operate correctly because the pulsation of the periodic disturbance detection values Ihd and Ihq is very large. Suppose that the periodic disturbance suppression command values Idn and Iqn of the device reach the upper limit value of the limiter 621.

  At this time, depending on the initial phase errors of the coefficients Qa and Qb, as shown in FIG. 17, the periodic disturbance detection values Ihd and Ihq may not converge to a specific point. In the example of FIG. 17, the periodic disturbance vector always has a component that tends to move counterclockwise along the upper limit value of the limiter 621. Therefore, the periodic disturbance detection values Ihd and Ihq continue to move counterclockwise along the upper limit value of the limiter 621. In the second and third embodiments, it is assumed that the periodic disturbance detection values Ihd and Ihq always converge to a certain point, so the example of FIG. 17 cannot be handled.

  FIG. 18 is a configuration diagram showing the periodic disturbance suppression control apparatus according to the fourth embodiment, which is applied to an active filter. The difference from the third embodiment is that a coefficient phase changing unit 500 is provided.

  The coefficient phase changing unit 500 detects the phase of the periodic disturbance on the complex plane from the periodic disturbance detection values Ihd and Ihq using the polar coordinate conversion unit 501. The hold block 502 of the periodic disturbance determination unit 520 inputs the operation signal of the limiter 621 as a reset signal through the NOT element 514, and holds the output value of the polar coordinate conversion unit 501 during the operation of the limiter 621, thereby limiting the limiter 621. The phase of the periodic disturbance immediately after the start of the operation (output of the polar coordinate conversion unit 501) is continuously output. In the adder 503, π is added to the output signal of the hold block 502, and the difference between the output of the adder 503 and the phase on the complex plane of the current periodic disturbance detection values Ihd and Ihq output from the polar coordinate converter 501. Is taken by the adder 504. The ABS block 505 takes the absolute value of the output of the adder 504, and the comparator 506 determines whether the output of the ABS block 505 is less than θr.

  As described above, the periodic disturbance phase determination unit 520 detects whether the periodic disturbance detection values Ihd and Ihq have made a half turn around the origin on the complex plane from the start of the operation of the limiter 621 to the present. To do.

Further, the phase of the periodic disturbance detection values Ihd and Ihq of the previous cycle is stored by the Z ⁻¹ calculator 507, and the subtractor 508 calculates Z ⁻¹ from the phase of the current periodic disturbance detection values Ihd and Ihq. The output of the unit 507 is subtracted. The output of the subtracter 508 indicates the rotational speed of the periodic disturbance detection values Ihd and Ihq centered on the origin. The output of the subtracter 508 is filtered by the LPF 509 and exceeds zero by the comparator 510. It is determined whether or not. As described above, it is determined whether the rotation direction of the periodic disturbance detection values Ihd and Ihq centered on the origin on the complex plane is counterclockwise or clockwise with respect to the origin.

  The output of the comparator 510 is input to the switch 511. The switch 511 outputs + 2π / 3 if the periodic disturbance detection values Ihd and Ihq are counterclockwise, and outputs −2π / 3 if it is clockwise. Next, the output of the switch 511 is input to the switch 512, and the switch 512 is switched by the output signal of the comparator 506. That is, the switch 512 outputs the input from the switch 511 as it is if the movement of the periodic disturbance detection values Ihd and Ihq has reached a half turn since the start of the limiter 621, and outputs zero if it has not reached the half turn. To do. The output of the switch 512 is added to the output of the switch 311 (limiter countermeasure circuit 300) by an adder 513.

  The fourth embodiment is a method in which the coefficient phase changing unit 500 is added to the second and third embodiments to solve the above problems (FIG. 17).

  As a feature of the operation in question, the periodic disturbance detection values Ihd and Ihq continue to draw a circle along the upper limit value of the limiter 621. Therefore, a function for detecting this operation and changing the phase of the coefficients Qa and Qb greatly is added.

  First, when the limiter 621 is stopped, the hold block 502 outputs the same value as the input. Therefore, the output of the subtraction unit 504 is π. Since θr is set to a value close to zero, the output of the subtractor 504 exceeds θr, and the switch 512 outputs zero. Therefore, the coefficient phase changing unit 500 is in a stopped state.

  On the other hand, when the limiter 621 operates, the hold block 502 holds the phase of the periodic disturbance detection values Ihd and Ihq immediately after that. When the periodic disturbance detection values Ihd and Ihq start to move along the upper limit value of the limiter 621 and the phase immediately after the start of the limiter 621 operation is π, that is, more than half a circle with respect to the origin, the switch 512 is switched upward.

  Further, the phases of the periodic disturbance detection values Ihd and Ihq are differentiated and converted into a signal corresponding to the angular velocity by performing LPF processing by the LPF 509. If this is positive (that is, the rotation direction is counterclockwise), 2π / 3 is output, and if it is negative (that is, the rotation direction is clockwise), −2π / 3 is output. Since the rotation direction of the periodic disturbance detection values Ihd and Ihq is determined by the sign of the phase error, the phases of the coefficients Qa and Qb are corrected in an appropriate direction by looking at the rotation direction.

  FIG. 19 shows how the periodic disturbance is suppressed by the fourth embodiment. In FIG. 19, it is assumed that the periodic disturbance detection values Ihd and Ihq are smaller than the device rated capacity and the initial phase error is 3π / 4.

  The periodic disturbance detection values Ihd and Ihq move in an increasing direction from the initial value, the correction function of the coefficients Qa and Qb does not operate for some reason, moves to the point A, and the limiter 621 operates. Thereafter, it starts to move counterclockwise along the upper limit value of the limiter 621. However, since it is detected by the periodic disturbance phase determination unit 520 at the point B that it has made a half turn with respect to the origin, the phases of the coefficients Qa and Qb are subtracted by 2π / 3. As a result, since the phase errors of the coefficients Qa and Qb are reduced to π / 12, the periodic disturbance detection values Ihd and Ihq move toward the origin and are suppressed to zero.

  Here, the reason why the correction amounts of the coefficients Qa and Qb are set to ± 2π / 3 will be described. The coefficient phase changing unit 500 according to the fourth embodiment takes three types of the phases of the coefficients Qa and Qb: “no change”, “+ 2π / 3 correction added”, and “−2π / 3 correction added”. Can do. As a result, the phase error of the coefficients Qa and Qb can be suppressed to within π / 3 regardless of the magnitude of the initial phase error. With this phase error, the periodic disturbance detection values Ihd and Ihq can be suppressed by the periodic disturbance suppression control device alone.

  It is assumed that the initial phase change unit 500 added in the fourth embodiment is operated simultaneously with the limiter countermeasure circuit 300 and the initial phase error determination unit 400 of the second and third embodiments. This is because if the initial phase error is too large, the periodic disturbance detection values Ihd and Ihq may converge to a specific point even when the periodic disturbance detection values Ihd and Ihq are smaller than the rated capacity of the device. It is necessary to change the phases of the coefficients Qa and Qb appropriately to obtain the state shown in FIG. This can be realized by the second or third embodiment.

  The condition that the periodic disturbance detection values Ihd and Ihq exceed the origin by more than half a circle is limited to the case where the periodic disturbance detection values Ihd and Ihq are smaller than the device rated capacity as shown in FIG. On the other hand, when the periodic disturbance detection values Ihd and Ihq are larger than the rated capacity of the apparatus, the phase in which the periodic disturbance detection values Ihd and Ihq change is limited to less than half a circle as seen from the origin, as shown in FIG. . In addition, when the periodic disturbance detection values Ihd and Ihq are larger than the device rated capacity, the second and third embodiments operate normally.

  Due to the above characteristics, the coefficient phase changing unit 500 does not operate under the conditions where the second and third embodiments are effective. Further, the coefficient phase changing unit 500 added in the fourth embodiment alone can be compensated for by the second and third embodiments. Thus, these functions do not compete with each other.

  FIG. 20 is a flowchart showing the processing steps of the fourth embodiment, which is assumed to be processed following the end of the flowcharts shown in FIGS. 11 and 14 (S26).

  S60: Periodic disturbance detection values Ihd and Ihq are detected by the polar coordinate conversion unit 501.

S61: The phase difference between the periodic disturbance detection values Ihd and Ihq is detected by the Z- ¹ calculator 507 and the adder 508.

  S62: The LPF 509 performs LPF processing on the phase difference and detects the rotational direction of the periodic disturbance detection values Ihd and Ihq.

  S63: The limiter 621 determines whether or not the periodic disturbance suppression command values Idn and Iqn have reached the upper limit value of the limiter 621. If reached, the process proceeds to S64, and if not, the process proceeds to S65.

  S64: The hold block 502 holds and outputs the signal input from the polar coordinate converter 501 because the reset signal input via the NOT element 514 is at 0 level.

  S65: Since the reset signal input via the NOT element 514 is 1 level, the hold block 502 updates and outputs the signal input from the polar coordinate converter 501.

  S66: The comparator 506 determines whether or not the difference between the phase of the hold block 502 and the current periodic disturbance detection values Ihd and Ihq is within π ± θr. If it is within π ± θr, the process proceeds to S67. If not within π ± θr, the process proceeds to S68.

  S67: The phase correction amount is set to 0 through S512, and the adder 513 adds the phase correction amount to the phase correction amount of the limit countermeasure circuit 300.

  S68: The comparator 510 determines whether or not the phase rotation direction (rotation direction of S62) is 0. If the rotation direction is greater than 0, the process proceeds to S69. If the rotation direction is 0 or less, the process proceeds to S70. Transition.

  S69: The phase correction amount is set to 2π / 3 by the switch 511, and is added to the phase correction amount of the limiter countermeasure circuit 300 by the adder 513.

  S70: The phase correction amount is set to −2π / 3 by the switch 511, and is added to the phase correction amount of the limiter countermeasure circuit 300 by the adder 513.

  That is, when the limiter 621 operates, the periodic disturbance detection values Ihd and Ihq at that time are stored, and when the periodic disturbance detection values Ihd and Ihq make a half turn with respect to the origin, the periodic disturbance detection values Ihd and Ihq are rotated in the rotational direction. The phases of the coefficients Qa and Qb are corrected with a corresponding code.

  Next, it is proved that when the periodic disturbance detection values Ihd and Ihq are smaller than the rated capacity of the apparatus, the periodic disturbance detection values Ihd and Ihq may not converge to a specific point depending on the initial phase error.

The above equation (5) holds even when L <r. When the equation (5) is differentiated, the following equation (6) is obtained, and becomes zero when α = cos ⁻¹ (L / r).

  Α that satisfies this condition does not exist when L> r, but exists when L <r. At this time, the above expression (5) becomes the following expression (7) and is minimized.

Therefore, there is no convergence point α where 0 ≦ θ <cos ⁻¹ (L / r) + π / 2.

  As described above, according to the fourth embodiment, the following effects can be obtained in addition to the effects of the second and third embodiments.

  When the periodic disturbance detection values Ihd and Ihq are smaller than the upper limit value of the limiter 621 and the phase error of the coefficients Qa and Qb is large to some extent, the periodic disturbance detection values Ihd and Ihq do not have a specific convergence point and change steadily. It falls into the phenomenon that keeps doing. Although it was impossible to cope with the second and third embodiments, the periodic disturbance detection values Ihd and Ihq can be suppressed in the fourth embodiment.

  The correction of the coefficients Qa and Qb does not operate due to the pulsation of the periodic disturbance detection values Ihd and Ihq, superposition of excessive noise, or the like, or malfunctions and falls into positive feedback, so that the periodic disturbance suppression command values Idn and Iqn become limiters 621. Even when the upper limit is increased, the phase of the coefficients Qa and Qb can be reliably corrected to escape the positive feedback, and the periodic disturbance detection values Ihd and Ihq can be suppressed.

  Moreover, since it does not compete with Embodiments 2 and 3, the effects of Embodiments 2 and 3 can be obtained as they are.

  Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

  The first to fourth embodiments described above can be applied not only to the three-phase active filter device but also to various periodic disturbance suppression control devices with a learning function. Moreover, the periodic disturbance over a plurality of frequencies can be suppressed by arranging a plurality of the above periodic disturbance suppression control devices in parallel.

  In the second and third embodiments, the initial value of the phase correction amount is π / 6 and the interval for detecting the periodic disturbance is 1 [sec]. However, this numerical value is an example, and different values may be set. Good.

DESCRIPTION OF SYMBOLS 100 ... Coefficient correction amount calculation part 200 ... Coefficient correction part 300 ... Limiter countermeasure circuit 400 ... Initial phase error determination part 500 ... Coefficient phase conversion part 613 ... Periodic disturbance observer 618 ... DFT (discrete Fourier transform) calculation part (periodic disturbance detection) Part)
620 ... Limiter countermeasure unit 621 ... Limiter

Claims (4)

A periodic disturbance detection unit that outputs the periodic disturbance to be suppressed as a periodic disturbance detection value of a DC value;
A signal obtained by multiplying the periodic disturbance detection value by an integrator using a coefficient defined as an inverse function of the transfer function from the periodic disturbance suppression command value to the input signal detection value determined based on the transfer characteristic of the control system And a periodic disturbance observer that estimates the periodic disturbance by taking the difference between the periodic disturbance suppression command value and the signal obtained by adding only the detection delay,
A periodic disturbance estimated value estimated by the periodic disturbance observer, a disturbance command value for suppressing the disturbance, and an adder for calculating a periodic disturbance suppressing command value by taking a deviation between these values,
A change amount between the periodic disturbance detection value and the periodic disturbance detection value one cycle before is obtained, and a phase correction amount of the coefficient based on a phase difference between the periodic disturbance detection value one cycle before and the change amount A coefficient correction amount calculation unit that calculates a command value and calculates an amplitude correction amount command value of the coefficient based on a difference in amplitude between the periodic disturbance detection value of the previous cycle and the change amount;
A coefficient correction unit that corrects the phase and amplitude of the coefficient respectively by the phase correction amount command value and the amplitude correction amount command value calculated by the coefficient correction amount calculation unit;
A periodic disturbance suppression control device comprising a periodic disturbance observer and a limiter countermeasure unit that stops a coefficient correction amount calculation unit when the periodic disturbance suppression command value reaches an upper limit value of the limiter. A periodic disturbance detection unit that outputs the periodic disturbance to be suppressed as a periodic disturbance detection value of a DC value;
A signal obtained by multiplying the periodic disturbance detection value by an integrator using a coefficient defined as an inverse function of the transfer function from the periodic disturbance suppression command value to the input signal detection value determined based on the transfer characteristic of the control system And a signal obtained by adding only a detection delay to the periodic disturbance suppression command value, and by taking a difference between them, a periodic disturbance observer for estimating the periodic disturbance,
A periodic disturbance estimated value estimated by the periodic disturbance observer, a disturbance command value for suppressing the disturbance, and an adder for calculating a periodic disturbance suppressing command value by taking a deviation between these values,
A change amount between the detected periodic disturbance value and the detected periodic disturbance value one cycle before is obtained, and a phase correction amount command for the coefficient is obtained based on the phase difference between the detected periodic disturbance value one cycle before and the changed amount. calculating a value, and the coefficient correction amount calculation unit for calculating an amplitude correction amount command value of the coefficient based on the amplitude difference between the periodic disturbance detection value of one period before and the amount of change,
A coefficient correction unit that corrects the phase and amplitude of the coefficient respectively by the phase correction amount command value and the amplitude correction amount command value calculated by the coefficient correction amount calculation unit;
When the periodic disturbance suppression command value exceeds the upper limit value of the limiter, the amplitude of the periodic disturbance detection value at the present time is compared with the amplitude of the periodic disturbance detection value of the previous cycle while changing the phases of the coefficients Qa and Qb. And a limiter countermeasure circuit that changes the phase correction amount command value based on the comparison result,
A periodic disturbance suppression control device that stops a coefficient correction amount calculation unit when a periodic disturbance suppression command value exceeds an upper limit value of a limiter.   Based on the phase error estimated value of the periodic disturbance detection value immediately after the start of the limiter operation and the periodic disturbance detection value after a lapse of a certain time after the start of the limiter operation, the coefficients Qa and Qb are first changed in the limit countermeasure circuit. The periodic disturbance suppression control device according to claim 2, further comprising an initial phase error determination unit that determines a code.   A coefficient phase conversion unit is provided that changes the phase of the coefficients Qa and Qb when the phase difference between the periodic disturbance detection value immediately after the start of the limiter operation in the periodic disturbance detection value and the current periodic disturbance detection value exceeds a threshold value. The periodic disturbance suppression control device according to claim 2 or 3.

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