JP5802400B2 - Resin sheet for sealing, semiconductor device using the same, and method for manufacturing the semiconductor device - Google Patents
Resin sheet for sealing, semiconductor device using the same, and method for manufacturing the semiconductor device Download PDFInfo
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- JP5802400B2 JP5802400B2 JP2011028470A JP2011028470A JP5802400B2 JP 5802400 B2 JP5802400 B2 JP 5802400B2 JP 2011028470 A JP2011028470 A JP 2011028470A JP 2011028470 A JP2011028470 A JP 2011028470A JP 5802400 B2 JP5802400 B2 JP 5802400B2
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- 239000004065 semiconductor Substances 0.000 title claims description 109
- 229920005989 resin Polymers 0.000 title claims description 91
- 239000011347 resin Substances 0.000 title claims description 91
- 238000007789 sealing Methods 0.000 title claims description 91
- 238000000034 method Methods 0.000 title description 29
- 238000004519 manufacturing process Methods 0.000 title description 9
- 239000011256 inorganic filler Substances 0.000 claims description 51
- 229910003475 inorganic filler Inorganic materials 0.000 claims description 51
- 239000003822 epoxy resin Substances 0.000 claims description 35
- 229920000647 polyepoxide Polymers 0.000 claims description 35
- 239000000155 melt Substances 0.000 claims description 26
- 229920001971 elastomer Polymers 0.000 claims description 23
- 239000000806 elastomer Substances 0.000 claims description 23
- 239000000203 mixture Substances 0.000 claims description 18
- 239000005011 phenolic resin Substances 0.000 claims description 14
- 238000003475 lamination Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- NLHHRLWOUZZQLW-UHFFFAOYSA-N Acrylonitrile Chemical compound C=CC#N NLHHRLWOUZZQLW-UHFFFAOYSA-N 0.000 claims description 4
- JIGUQPWFLRLWPJ-UHFFFAOYSA-N Ethyl acrylate Chemical compound CCOC(=O)C=C JIGUQPWFLRLWPJ-UHFFFAOYSA-N 0.000 claims description 4
- CQEYYJKEWSMYFG-UHFFFAOYSA-N butyl acrylate Chemical compound CCCCOC(=O)C=C CQEYYJKEWSMYFG-UHFFFAOYSA-N 0.000 claims description 4
- 229920001577 copolymer Polymers 0.000 claims description 4
- PNJWIWWMYCMZRO-UHFFFAOYSA-N pent‐4‐en‐2‐one Natural products CC(=O)CC=C PNJWIWWMYCMZRO-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 11
- 239000011342 resin composition Substances 0.000 description 11
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 9
- 229920006267 polyester film Polymers 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 239000002966 varnish Substances 0.000 description 6
- 238000005304 joining Methods 0.000 description 5
- UFWIBTONFRDIAS-UHFFFAOYSA-N Naphthalene Chemical compound C1=CC=CC2=CC=CC=C21 UFWIBTONFRDIAS-UHFFFAOYSA-N 0.000 description 4
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 238000009434 installation Methods 0.000 description 4
- 238000010030 laminating Methods 0.000 description 4
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 3
- XEKOWRVHYACXOJ-UHFFFAOYSA-N Ethyl acetate Chemical compound CCOC(C)=O XEKOWRVHYACXOJ-UHFFFAOYSA-N 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 125000003700 epoxy group Chemical group 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 125000003710 aryl alkyl group Chemical group 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- JHIVVAPYMSGYDF-UHFFFAOYSA-N cyclohexanone Chemical compound O=C1CCCCC1 JHIVVAPYMSGYDF-UHFFFAOYSA-N 0.000 description 2
- -1 for example Substances 0.000 description 2
- 239000005350 fused silica glass Substances 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 229920003986 novolac Polymers 0.000 description 2
- FDPIMTJIUBPUKL-UHFFFAOYSA-N pentan-3-one Chemical compound CCC(=O)CC FDPIMTJIUBPUKL-UHFFFAOYSA-N 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- RIOQSEWOXXDEQQ-UHFFFAOYSA-N triphenylphosphine Chemical compound C1=CC=CC=C1P(C=1C=CC=CC=1)C1=CC=CC=C1 RIOQSEWOXXDEQQ-UHFFFAOYSA-N 0.000 description 2
- RYHBNJHYFVUHQT-UHFFFAOYSA-N 1,4-Dioxane Chemical compound C1COCCO1 RYHBNJHYFVUHQT-UHFFFAOYSA-N 0.000 description 1
- RNFJDJUURJAICM-UHFFFAOYSA-N 2,2,4,4,6,6-hexaphenoxy-1,3,5-triaza-2$l^{5},4$l^{5},6$l^{5}-triphosphacyclohexa-1,3,5-triene Chemical compound N=1P(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP(OC=2C=CC=CC=2)(OC=2C=CC=CC=2)=NP=1(OC=1C=CC=CC=1)OC1=CC=CC=C1 RNFJDJUURJAICM-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000006229 carbon black Substances 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 229910002026 crystalline silica Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000003063 flame retardant Substances 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000000049 pigment Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000454 talc Substances 0.000 description 1
- 229910052623 talc Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
- H01L23/295—Organic, e.g. plastic containing a filler
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29075—Plural core members
- H01L2224/2908—Plural core members being stacked
- H01L2224/29082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Sealing Material Composition (AREA)
- Wire Bonding (AREA)
Description
本発明は、接続用電極部を有する半導体素子を、マザーボード等の配線回路基板上に実装する際に用いられる封止用樹脂シート、およびそれを用いた実装体である半導体装置、並びにその半導体装置の製法に関するものである。 The present invention relates to a sealing resin sheet used when a semiconductor element having a connection electrode portion is mounted on a printed circuit board such as a mother board, a semiconductor device which is a mounting body using the same, and the semiconductor device Is related to the manufacturing method.
半導体パッケージ分野、特に携帯機器向け等の高密度実装が要求される半導体パッケージ分野では、一般的に、小型・薄型化が可能な実装方法であるフリップチップ実装が採用されている。フリップチップ実装は、半導体素子（チップ）の端子と、配線回路基板の端子とを向かい合わせて接続する実装方式であり、半導体素子・配線回路基板間の熱膨張率差による熱応力により接続不良が発生しやすい。そのため、フリップチップ実装では、通常、半導体素子と配線回路基板との間に、無機質充填剤を含有した熱硬化性樹脂を封入し、これにより補強することによって、半導体素子・配線回路基板間の端子接続部に集中する応力を分散させ、接続信頼性を向上させている。 In the semiconductor package field, particularly in the semiconductor package field where high-density mounting is required, such as for portable devices, flip chip mounting, which is a mounting method capable of being reduced in size and thickness, is generally employed. Flip chip mounting is a mounting method in which the terminal of a semiconductor element (chip) and the terminal of a printed circuit board are connected to face each other. Connection failure is caused by thermal stress due to a difference in thermal expansion coefficient between the semiconductor element and the printed circuit board. Likely to happen. Therefore, in flip-chip mounting, a terminal between a semiconductor element and a printed circuit board is usually encapsulated by reinforcing a thermosetting resin containing an inorganic filler between the semiconductor element and the printed circuit board. The stress concentrated on the connecting part is dispersed to improve the connection reliability.
上記熱硬化性樹脂を半導体素子と配線回路基板との間に充填する方法として、現在主に用いられている方法は、半導体素子を配線回路基板にボンディングした後、液状のアンダーフィルを、半導体素子と配線回路基板との間に注入する方法である。しかしながら、この方法では、近年の半導体パッケージの低背化、端子ピンの多数化に伴う狭ギャップのために、上記注入する際にボイドが発生しやすいといった問題がある。そこで、このような問題を解決する方法として、近年、半導体素子と配線回路基板との間に、無機質充填剤を含有する封止用樹脂シートを挟み込み、これを加熱溶融させて封止樹脂層を形成するとともに、半導体素子・配線回路基板の端子間を加圧により圧着接合するといった樹脂封止方法が提案されている（例えば、特許文献１参照）。 As a method for filling the thermosetting resin between the semiconductor element and the printed circuit board, the method mainly used at present is that after bonding the semiconductor element to the printed circuit board, a liquid underfill is applied to the semiconductor element. And a wiring circuit board. However, this method has a problem in that voids are likely to occur during the above-described injection due to the recent reduction in the height of semiconductor packages and the narrow gap associated with the increase in the number of terminal pins. Therefore, as a method for solving such a problem, in recent years, a sealing resin sheet containing an inorganic filler is sandwiched between a semiconductor element and a printed circuit board, and this is heated and melted to form a sealing resin layer. A resin sealing method has been proposed in which, while being formed, the terminals of the semiconductor element and the printed circuit board are pressure-bonded and bonded by pressure (for example, see Patent Document 1).
しかしながら、上記のように封止用樹脂シートを用いて樹脂封止する手法では、半導体素子と配線回路基板との間に封止用樹脂シートを挟み込む際に、半導体素子と配線回路基板の端子間に、封止用樹脂シート中の無機質充填剤が噛みこむことにより、導通特性が低下し、結果、接続信頼性を低下させるおそれがある。 However, in the method of resin sealing using the sealing resin sheet as described above, when the sealing resin sheet is sandwiched between the semiconductor element and the printed circuit board, the gap between the terminals of the semiconductor element and the printed circuit board is determined. In addition, when the inorganic filler in the sealing resin sheet is bitten, the conduction characteristics are lowered, and as a result, the connection reliability may be lowered.
このような問題を解決する方法として、特許第３９９９８４０号において、本出願人は、封止用樹脂シートを、無機質充填剤含有層と無機質充填剤不含層との積層体とし、これを用いて樹脂封止したときに、半導体素子・配線回路基板間の端子接続部が無機質充填剤不含層のところに位置するように工夫して、半導体素子と配線回路基板の端子間での無機質充填剤の噛みこみを抑制する手法を、既に提案している。しかしながら、このように、半導体素子と配線回路基板の端子間に、確実に無機質充填剤がない状態をつくり、接合信頼性を向上させることは、実際には難しい。そのため、上記特許発明においても、未だ改善の余地がある。 As a method for solving such a problem, in Japanese Patent No. 3999840, the applicant of the present invention uses a sealing resin sheet as a laminate of an inorganic filler-containing layer and an inorganic filler-free layer. Inorganic filler between the terminals of the semiconductor element and the printed circuit board so that the terminal connection between the semiconductor element and the printed circuit board is located at the inorganic filler-free layer when the resin is sealed. A method for suppressing the biting of the lip has already been proposed. However, it is actually difficult to improve the bonding reliability by reliably creating a state where there is no inorganic filler between the terminals of the semiconductor element and the printed circuit board. Therefore, there is still room for improvement in the above-mentioned patented invention.
本発明は、このような事情に鑑みなされたもので、半導体素子・配線回路基板間の熱膨張率差による接続不良を改善するとともに、半導体素子・配線回路基板の端子間での無機質充填剤の噛みこみを、より確実に抑え、接続信頼性を向上させた、封止用樹脂シートおよびそれを用いた半導体装置、並びにその半導体装置の製法の提供をその目的とする。 The present invention has been made in view of such circumstances, and improves the connection failure due to the difference in thermal expansion coefficient between the semiconductor element and the printed circuit board, and the inorganic filler between the terminals of the semiconductor element and the printed circuit board. It is an object of the present invention to provide a sealing resin sheet, a semiconductor device using the same, and a method for manufacturing the semiconductor device, in which biting is more reliably suppressed and connection reliability is improved.
上記の問題を解決するために、本発明は、半導体素子に設けられた接続用電極部と、配線回路基板に設けられた接続用端子とを対向させた状態で上記配線回路基板上に半導体素子が搭載されてなる半導体装置を対象とし、その配線回路基板と半導体素子との間の空隙を樹脂封止するために用いられる封止用樹脂シートであって、上記封止用樹脂シートが、（α）無機質充填剤を含有するエポキシ樹脂組成物層と、（β）無機質充填剤を含有しないエポキシ樹脂組成物層との二層構造からなり、上記（α）層が、エポキシ樹脂とフェノール樹脂とエラストマー成分と無機質充填剤を含有し、エラストマー成分量を１重量％以上２０重量％未満とするエポキシ樹脂組成物からなり、上記（β）層が、エポキシ樹脂とフェノール樹脂とエラストマー成分を含有し、エラストマー成分量を２０重量％以上５０重量％未満とするエポキシ樹脂組成物からなり、かつ上記（α）層および（β）層が下記の特性（ｘ）〜（ｚ）を備えている封止用樹脂シートを第１の要旨とする。
（ｘ）６０〜１２５℃から選ばれるラミネート温度における溶融粘度が、上記（α）層が１．０×１０2〜２．０×１０4Ｐａ・ｓであり、上記（β）層が１．０×１０3〜２．０×１０5Ｐａ・ｓである。
（ｙ）上記（β）層の溶融粘度と（α）層の溶融粘度の差〔（β）層−（α）層〕が、１．５×１０4Ｐａ・ｓ以上である。
（ｚ）上記封止用樹脂シートの（β）層の厚みが、上記接続用電極部の高さ（ｈ）を基準として、１／３ｈ〜４／５ｈである。
In order to solve the above problem, the present invention provides a semiconductor element on a wiring circuit board in a state where a connection electrode provided on the semiconductor element and a connection terminal provided on the wiring circuit board face each other. Is a resin sheet for sealing used for resin-sealing a gap between the wiring circuit board and the semiconductor element, wherein the sealing resin sheet is ( It consists of a two-layer structure of (α) an epoxy resin composition layer containing an inorganic filler and (β) an epoxy resin composition layer not containing an inorganic filler, and the (α) layer comprises an epoxy resin and a phenol resin. An epoxy resin composition containing an elastomer component and an inorganic filler and having an elastomer component content of 1 wt% or more and less than 20 wt%. The (β) layer comprises an epoxy resin, a phenol resin, and an elastomer component. Containing the elastomer component amounts an epoxy resin composition is less than 20 wt% to 50 wt%, and the (alpha) layer and (beta) layer is provided with the following properties (x) ~ (z) The sealing resin sheet is a first gist.
(X) The melt viscosity at a lamination temperature selected from 60 to 125 ° C. is that the (α) layer is 1.0 × 10 2 to 2.0 × 10 4 Pa · s, and the (β) layer is 1. It is 0 * 10 < 3 > -2.0 * 10 < 5 > Pa * s.
(Y) The difference between the melt viscosity of the (β) layer and the melt viscosity of the (α) layer [(β) layer− (α) layer] is 1.5 × 10 4 Pa · s or more.
(Z) The thickness of the (β) layer of the sealing resin sheet is 1 / 3h to 4 / 5h on the basis of the height (h) of the connecting electrode portion.
また、本発明は、半導体素子に設けられた接続用電極部と、配線回路基板に設けられた接続用端子を対向させた状態で上記配線回路基板上に半導体素子が搭載されてなる半導体装置であって、上記配線回路基板と半導体素子との間の空隙が、上記第１の要旨の封止用樹脂シートからなる、無機質充填剤含有層と無機質充填剤不含層の二層構造からなる封止樹脂層によって、上記無機質充填剤含有層が半導体素子側に位置するよう樹脂封止されている半導体装置を第２の要旨とする。 The present invention also relates to a semiconductor device in which a semiconductor element is mounted on the wiring circuit board in a state in which a connection electrode provided on the semiconductor element and a connection terminal provided on the wiring circuit board face each other. And the gap between the printed circuit board and the semiconductor element is a sealing layer composed of a two-layer structure of an inorganic filler-containing layer and an inorganic filler-free layer made of the sealing resin sheet of the first aspect. A semiconductor device in which the inorganic filler-containing layer is resin-sealed so that the inorganic filler-containing layer is located on the semiconductor element side by a stopping resin layer is a second gist.
また、本発明は、剥離シートの片面に、上記第１の要旨の封止用樹脂シートの（β）層が直接積層されるよう、上記封止用樹脂シートが積層されてなる剥離シート付封止用樹脂シートを準備する工程と、接続用電極部が設けられた半導体素子面に、上記剥離シート付封止用樹脂シートを貼付し加圧して、接続用電極部が設けられた半導体素子に剥離シート付封止用樹脂シートを貼り合わせる工程と、上記剥離シートを剥離した後、接続用端子が設けられた配線回路基板に、上記半導体素子に設けられた接続用電極部と配線回路基板に設けられた接続用端子とを対向させるよう、上記配線回路基板上に、封止用樹脂シート付半導体素子を載置し、加圧する工程と、上記封止用樹脂シートを加熱硬化することにより、上記配線回路基板と半導体素子との間の空隙を樹脂封止する工程とを備えた半導体装置の製法を第３の要旨とする。 Further, the present invention provides a sealing with release sheet, wherein the sealing resin sheet is laminated so that the (β) layer of the sealing resin sheet according to the first aspect is directly laminated on one side of the release sheet. A step of preparing a resin sheet for fastening, and a semiconductor element surface provided with a connecting electrode portion, and affixing and pressing the sealing resin sheet with a release sheet to the semiconductor element provided with a connecting electrode portion A process of bonding a sealing resin sheet with a release sheet, and after peeling off the release sheet, a wiring circuit board provided with connection terminals, a connection electrode portion provided in the semiconductor element, and a wiring circuit board By placing and pressurizing the semiconductor element with a sealing resin sheet on the wired circuit board so as to oppose the connecting terminal provided, and by heating and curing the sealing resin sheet, Wiring circuit board and semiconductor element The method of a semiconductor device having a step of resin-sealing a gap between the the third aspect.
すなわち、本発明者らは、前記課題を解決するため鋭意研究を重ねた。その過程で、先の特許第３９９９８４０号に係る特許発明を基礎とし、より確実に、無機質充填剤の噛みこみによる接続信頼性の低下が生じないよう、本発明者らは封止用樹脂シートの改良を重ねた。そして、本発明者らは、封止用樹脂シートを、無機質充填剤含有層と無機質充填剤不含層との二層構造のエポキシ樹脂組成物シートにするとともに、その各層の融解粘度（ラミネート温度における溶融粘度）と厚みの関係に着目し、各種実験を重ねた結果、これらを本発明に規定する特定範囲内に設定したところ、良好な結果が得られることを突き止めた。すなわち、本発明者らは、このように各層の融解粘度や厚みが設定された封止用樹脂シートの、無機質充填剤含有層側を、接続用電極部（バンプ）が設けられた半導体素子面に貼付し加圧して、半導体素子に封止用樹脂シートを貼り合わせ、バンプ先端部が無機質充填剤含有層を貫通し無機質充填剤不含層内に位置するようにし、端子接合時に確実にバンプ先端部付近に無機質充填剤がない状態をつくり、この状態で、上記封止用樹脂シートの無機質充填剤不含層側を、接続用端子が設けられた配線回路基板に貼り合わせた。そして、特許第３９９９８４０号に係る特許発明と同様、上記封止用樹脂シートの加熱溶融、および半導体素子・配線回路基板間の圧着接合により、樹脂封止を行ったところ、半導体素子の接続用電極部と、配線回路基板の接続用端子との間での無機質充填剤の噛みこみをより確実に抑えることができ、その結果、接続信頼性が向上するとともに、半導体素子・配線回路基板間の熱膨張率差による接続不良も改善されるようになることを見いだし、本発明に到達した。 That is, the present inventors have intensively studied to solve the above problems. In the process, the inventors of the sealing resin sheet are based on the patent invention according to the previous patent No. 3999840, and more reliably, the connection reliability is not lowered due to the biting of the inorganic filler. Repeated improvements. Then, the present inventors made the resin sheet for sealing into an epoxy resin composition sheet having a two-layer structure of an inorganic filler-containing layer and an inorganic filler-free layer, and the melt viscosity (laminating temperature of each layer). As a result of repeating various experiments focusing on the relationship between the melt viscosity) and the thickness, it was found that when these were set within a specific range defined in the present invention, good results were obtained. That is, the present inventors provide a semiconductor element surface provided with connecting electrode portions (bumps) on the inorganic filler-containing layer side of the sealing resin sheet in which the melt viscosity and thickness of each layer are set as described above. Affixed to the semiconductor element and affixed with the sealing resin sheet on the semiconductor element, and the bump tip is located in the inorganic filler-free layer through the inorganic filler-containing layer, so that the bump can be reliably bonded at the time of terminal bonding. A state in which no inorganic filler was present in the vicinity of the tip portion was created, and in this state, the inorganic filler-free layer side of the sealing resin sheet was bonded to a printed circuit board provided with connection terminals. And, similar to the patent invention relating to Japanese Patent No. 3999840, when the resin sealing was carried out by heating and melting the sealing resin sheet and pressure bonding between the semiconductor element and the wiring circuit board, the connection electrode for the semiconductor element was obtained. Ingredients and the connection terminal of the printed circuit board can be more reliably suppressed, and as a result, the connection reliability is improved and the heat between the semiconductor element and the printed circuit board is improved. It has been found that poor connection due to the difference in expansion coefficient is improved, and the present invention has been achieved.
以上のように、本発明の封止用樹脂シートは、無機質充填剤含有層と無機質充填剤不含層との二層構造のエポキシ樹脂組成物シートであり、その各層の融解粘度（６０〜１２５℃から選ばれるラミネート温度における溶融粘度）が特定の範囲内であり、両層の融解粘度差が特定の範囲内であるとともに、無機質充填剤不含層の厚みが特定の範囲内である。そして、本発明では、上記封止用樹脂シートを、配線回路基板と半導体素子との間で、所定の配置で介在させ、上記封止用樹脂シートの加熱溶融、および半導体素子・配線回路基板間の圧着接合により、樹脂封止を行うことから、半導体素子の接続用電極部と、配線回路基板の接続用端子との間での無機質充填剤の噛みこみをより確実に抑えることができ、その結果、接続信頼性が向上するとともに、半導体素子・配線回路基板間の熱膨張率差による接続不良も改善されるようになる。したがって、半導体素子と配線回路基板間の導通特性の低下が抑制されて、信頼性の高い半導体装置が得られるようになる。 As described above, the sealing resin sheet of the present invention is an epoxy resin composition sheet having a two-layer structure of an inorganic filler-containing layer and an inorganic filler-free layer, and the melt viscosity (60 to 125 of each layer). The melt viscosity at a laminating temperature selected from ° C. is within a specific range, the difference in melt viscosity between the two layers is within a specific range, and the thickness of the inorganic filler-free layer is within a specific range. In the present invention, the sealing resin sheet is interposed between the wiring circuit board and the semiconductor element in a predetermined arrangement, and the sealing resin sheet is heated and melted, and between the semiconductor element and the wiring circuit board. Since the resin sealing is performed by the crimp bonding, the biting of the inorganic filler between the connection electrode portion of the semiconductor element and the connection terminal of the printed circuit board can be more reliably suppressed, As a result, connection reliability is improved and connection failure due to a difference in thermal expansion coefficient between the semiconductor element and the printed circuit board is also improved. Therefore, a decrease in conduction characteristics between the semiconductor element and the printed circuit board is suppressed, and a highly reliable semiconductor device can be obtained.
つぎに、本発明の実施の形態について詳しく説明する。 Next, embodiments of the present invention will be described in detail.
本発明の封止用樹脂シートは、先に述べたように、半導体素子に設けられた接続用電極部と、配線回路基板に設けられた接続用端子とを対向させた状態で上記配線回路基板上に半導体素子が搭載されてなる半導体装置を対象とし、その配線回路基板と半導体素子との間の空隙を樹脂封止するために用いられるシートである。そして、図１に示すように、本発明の封止用樹脂シート１は、（α）無機質充填剤を含有するエポキシ樹脂組成物層（無機質充填剤含有層３）と、（β）無機質充填剤を含有しないエポキシ樹脂組成物層（無機質充填剤不含層２）との二層構造からなり、上記（α）層が、エポキシ樹脂とフェノール樹脂とエラストマー成分と無機質充填剤を含有し、エラストマー成分量を１重量％以上２０重量％未満とするエポキシ樹脂組成物からなり、上記（β）層が、エポキシ樹脂とフェノール樹脂とエラストマー成分を含有し、エラストマー成分量を２０重量％以上５０重量％未満とするエポキシ樹脂組成物からなり、かつ上記（α）層および（β）層が下記の特性（ｘ）〜（ｚ）を備えていることを最大の特徴とするものである。なお、下記の特性（ｘ）における溶融粘度は、一般的なレオメーターを用いて測定すればよいが、例えば、回転型粘度計（ＨＡＫＫＥ社製、レオストレスＲＳ１）を用い、ギャップ１００μｍ、回転コーン直径２０ｍｍ、回転速度１０ｓ-1という条件で測定することにより導き出すことができる。
（ｘ）６０〜１２５℃から選ばれるラミネート温度における溶融粘度が、上記（α）層が１．０×１０2〜２．０×１０4Ｐａ・ｓであり、上記（β）層が１．０×１０3〜２．０×１０5Ｐａ・ｓである。
（ｙ）上記（β）層の溶融粘度と（α）層の溶融粘度の差〔（β）層−（α）層〕が、１．５×１０4Ｐａ・ｓ以上である。
（ｚ）上記封止用樹脂シートの（β）層の厚みが、上記接続用電極部の高さ（ｈ）を基準として、１／３ｈ〜４／５ｈである。
As described above, the sealing resin sheet of the present invention is the wiring circuit board in a state where the connection electrode portion provided in the semiconductor element and the connection terminal provided in the wiring circuit board face each other. This is a sheet used for resin-sealing a gap between a printed circuit board and a semiconductor element, intended for a semiconductor device on which a semiconductor element is mounted. As shown in FIG. 1, the
(X) The melt viscosity at a lamination temperature selected from 60 to 125 ° C. is that the (α) layer is 1.0 × 10 2 to 2.0 × 10 4 Pa · s, and the (β) layer is 1. It is 0 * 10 < 3 > -2.0 * 10 < 5 > Pa * s.
(Y) The difference between the melt viscosity of the (β) layer and the melt viscosity of the (α) layer [(β) layer− (α) layer] is 1.5 × 10 4 Pa · s or more.
(Z) The thickness of the (β) layer of the sealing resin sheet is 1 / 3h to 4 / 5h on the basis of the height (h) of the connecting electrode portion.
上記封止用樹脂シートの使用に際し、半導体素子・配線回路基板の端子間での無機質充填剤の噛みこみを、より確実に抑え、接続信頼性を向上させる観点から、上記特性（ｘ）における、（α）層の溶融粘度は、好ましくは、５．０×１０2〜１．０×１０3Ｐａ・ｓの範囲であり、（β）層の溶融粘度は、好ましくは、１．０×１０4〜２．０×１０5Ｐａ・ｓの範囲である。 In the use of the sealing resin sheet, from the viewpoint of more reliably suppressing the biting of the inorganic filler between the terminals of the semiconductor element / wiring circuit board and improving the connection reliability, in the characteristic (x), The melt viscosity of the (α) layer is preferably in the range of 5.0 × 10 2 to 1.0 × 10 3 Pa · s, and the melt viscosity of the (β) layer is preferably 1.0 × 10. 4 is in the range of ~2.0 × 10 5 Pa · s.
また、上記と同様の観点から、上記特性（ｙ）における、（β）層の溶融粘度と（α）層の溶融粘度の差〔（β）層−（α）層〕は、好ましくは、１．５×１０4〜２．０×１０5Ｐａ・ｓの範囲である。 From the same viewpoint as described above, the difference between the melt viscosity of the (β) layer and the melt viscosity of the (α) layer ((β) layer− (α) layer) in the property (y) is preferably 1 The range is from 5 × 10 4 to 2.0 × 10 5 Pa · s.
また、上記と同様の観点から、上記特性（ｚ）における、（β）層の厚みは、好ましくは、半導体素子に設けられた接続用電極部の高さ（ｈ）を基準として、１／２ｈ〜２／３ｈの範囲である。 Further, from the same viewpoint as described above, the thickness of the (β) layer in the characteristic (z) is preferably ½ h based on the height (h) of the connection electrode portion provided in the semiconductor element. It is in the range of ~ 2 / 3h.
さらに、本発明の封止用樹脂シートにおいては、上記と同様の観点から、その（α）層の厚みが、上記接続用電極部の高さ（ｈ）を基準として、１／２ｈ〜２／３ｈであることが好ましい。 Furthermore, in the sealing resin sheet of the present invention, from the same viewpoint as described above, the thickness of the (α) layer is 1/2 h to 2/2 based on the height (h) of the connection electrode portion. 3 h is preferable.
なお、上記接続用電極部の高さ（ｈ）は、通常、１０〜２００μｍの範囲である。したがって、この値に従い、上記（α）層および（β）層の厚みは決定する。 The height (h) of the connection electrode part is usually in the range of 10 to 200 μm. Therefore, according to this value, the thickness of the (α) layer and (β) layer is determined.
上記（α）層の形成材料としては、先に述べたように、エポキシ樹脂とフェノール樹脂とエラストマー成分と無機質充填剤を含有するエポキシ樹脂組成物が用いられ、上記（β）層の形成材料としては、エポキシ樹脂とフェノール樹脂とエラストマー成分を含有するエポキシ樹脂組成物が用いられる。また、各層の形成材料には、必要に応じて、硬化促進剤、難燃剤、カーボンブラックをはじめとする顔料等、他の添加剤を適宜配合することができる。 The material for the formation of the (alpha) layer, as previously described, the epoxy resin composition is used which contains an epoxy resin and the phenol resin and the elastomer component and inorganic filler, as a material of the (beta) layer an epoxy resin composition containing the error epoxy resin and the phenol resin and the elastomer component is used. In addition, other additives such as a curing accelerator, a flame retardant, and a pigment such as carbon black can be appropriately blended with the material for forming each layer as necessary.
上記エポキシ樹脂としては、具体的には、ナフタレン型エポキシ樹脂、トリスフェノールメタン型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂等が用いられる。また、上記フェノール樹脂としては、具体的には、アラルキル型フェノール樹脂、フェノールノボラック樹脂等が用いられる。また、エラストマー成分としては、具体的には、アクリル酸エチルとアクリル酸ブチルとアクリロニトリルの共重合ポリマー等が用いられる。上記無機質充填剤としては、具体的には、石英ガラス、タルク、シリカ（溶融シリカや結晶性シリカ等）、アルミナ、窒化アルミニウム、窒化珪素等の粉末等が用いられる。 Specifically, naphthalene type epoxy resin, trisphenol methane type epoxy resin, bisphenol A type epoxy resin or the like is used as the epoxy resin. As the phenol resin, specifically, an aralkyl type phenol resin, a phenol novolac resin, or the like is used. As the elastomer component, specifically, a copolymer of ethyl acrylate, butyl acrylate, and acrylonitrile is used. Specific examples of the inorganic filler include quartz glass, talc, silica (fused silica, crystalline silica, etc.), powder of alumina, aluminum nitride, silicon nitride, and the like.
そして、前記特性（ｘ）に示すように、（α）層および（β）層の溶融粘度を調整する方法としては、例えば、各層の形成材料中のエラストマー量、無機質充填剤量によって調整する方法があげられるが、熱応力信頼性のための低熱線膨張化の観点から、本発明ではエラストマー量で調整される。そして、本発明では、前記特性（ｘ）を満足させるために、（α）層の形成材料中のエラストマー量を１重量％以上２０重量％未満とし、（β）層の形成材料中のエラストマー量を２０重量％以上５０重量％未満とすることが、粘度調整の容易化の観点から求められる。 And as shown in the said characteristic (x), as a method of adjusting the melt viscosity of (α) layer and (β) layer, for example, a method of adjusting by the amount of elastomer and the amount of inorganic filler in the forming material of each layer From the viewpoint of low thermal linear expansion for thermal stress reliability, the amount of elastomer is adjusted in the present invention . In the present invention, in order to satisfy the above characteristic (x), the amount of the elastomer in the (α) layer forming material is 1 wt% or more and less than 20 wt%, and the amount of the elastomer in the (β) layer forming material is 20 wt% or more and less than 50 wt% is required from the viewpoint of facilitating viscosity adjustment.
本発明の封止用樹脂シートは、例えば、以下のようにして製造することができる。 The sealing resin sheet of the present invention can be produced, for example, as follows.
すなわち、まず、（α）層および（β）層の材料である樹脂組成物を、それぞれ、その各配合成分が均一に分散混合されるまで混合し、調製する。そして、上記調製された樹脂組成物を、シート状に形成する。この形成方法としては、例えば、上記調製された樹脂組成物を押出成形してシート状に形成する方法や、上記調製された樹脂組成物を有機溶剤等に溶解または分散してワニスを調製し、このワニスを、ポリエステル等の基材上に塗工し乾燥させることにより樹脂組成物シートを得る方法等があげられる。なかでも、均一な厚みのシートを簡便に得ることができるという観点から、ワニスの塗工による形成方法が好ましい。なお、上記のように形成された樹脂組成物シートの表面には、必要に応じ、樹脂組成物シートの表面を保護するためにポリエステルフィルム等の剥離シートを貼り合わせ、封止時に剥離するようにしてもよい。また、上記のポリエステル等の基材を、この剥離シートとしてもよい。 That is, first, the resin compositions that are the materials of the (α) layer and the (β) layer are mixed and prepared until the respective blending components are uniformly dispersed and mixed. Then, the prepared resin composition is formed into a sheet shape. As this formation method, for example, a method of forming the resin composition prepared above by extrusion molding into a sheet form, or preparing a varnish by dissolving or dispersing the prepared resin composition in an organic solvent or the like, A method of obtaining a resin composition sheet by coating the varnish on a substrate such as polyester and drying the varnish is exemplified. Among these, from the viewpoint that a sheet having a uniform thickness can be easily obtained, a forming method by varnish coating is preferable. In addition, on the surface of the resin composition sheet formed as described above, if necessary, a release sheet such as a polyester film is bonded to protect the surface of the resin composition sheet, and is peeled off at the time of sealing. May be. Moreover, it is good also considering base materials, such as said polyester, as this peeling sheet.
上記ワニスを調製する際に用いる有機溶剤としては、例えば、メチルエチルケトン、アセトン、シクロヘキサノン、ジオキサン、ジエチルケトン、トルエン、酢酸エチル等を用いることができる。これらは単独でもしくは二種以上併せて用いられる。また、通常、ワニスの固形分濃度が３０〜６０重量％の範囲となるように有機溶剤を用いることが好ましい。 As an organic solvent used when preparing the varnish, for example, methyl ethyl ketone, acetone, cyclohexanone, dioxane, diethyl ketone, toluene, ethyl acetate and the like can be used. These may be used alone or in combination of two or more. Moreover, it is usually preferable to use an organic solvent so that the solid content concentration of the varnish is in the range of 30 to 60% by weight.
このようにして得られた、（α）層および（β）層に相当するシート状エポキシ樹脂組成物を積層して、本発明の封止用樹脂シートとする。 The sheet-like epoxy resin composition corresponding to the (α) layer and the (β) layer thus obtained is laminated to obtain the sealing resin sheet of the present invention.
本発明の半導体装置は、上記封止用樹脂シートを用いて、例えば、次のようにして製造することができる。すなわち、まず、剥離シートの片面に、上記封止用樹脂シートの（β）層が直接積層されるよう、上記封止用樹脂シートが積層されてなる剥離シート付封止用樹脂シートを準備する。つぎに、接続用電極部が設けられた半導体素子面に、上記剥離シート付封止用樹脂シートを貼付し加圧して、接続用電極部が設けられた半導体素子に剥離シート付封止用樹脂シートを貼り合わせる。続いて、上記剥離シートを剥離した後、接続用端子が設けられた配線回路基板に、上記半導体素子に設けられた接続用電極部と配線回路基板に設けられた接続用端子とを対向させるよう、上記配線回路基板上に、封止用樹脂シート付半導体素子を載置し、加圧する。そして、上記封止用樹脂シートを加熱硬化することにより、上記配線回路基板と半導体素子との間の空隙を樹脂封止する。 The semiconductor device of the present invention can be manufactured using the sealing resin sheet as follows, for example. That is, first, a sealing resin sheet with a release sheet is prepared by laminating the sealing resin sheet so that the (β) layer of the sealing resin sheet is directly laminated on one side of the release sheet. . Next, the sealing resin sheet with a release sheet is applied to the semiconductor element surface provided with the connection electrode part and pressed, and the sealing resin with release sheet is applied to the semiconductor element provided with the connection electrode part. Paste the sheets together. Subsequently, after peeling off the release sheet, the connection electrode portion provided on the semiconductor element and the connection terminal provided on the wiring circuit substrate are opposed to the wiring circuit substrate on which the connection terminal is provided. The semiconductor element with a sealing resin sheet is placed on the printed circuit board and pressed. And the space | gap between the said wiring circuit board and a semiconductor element is resin-sealed by heat-hardening the said resin sheet for sealing.
このようにして得られた本発明の半導体装置は、半導体素子に設けられた接続用電極部と、配線回路基板に設けられた接続用端子を対向させた状態で上記配線回路基板上に半導体素子が搭載されてなる半導体装置であって、上記配線回路基板と半導体素子との間の空隙が、上記封止用樹脂シートからなる、無機質充填剤含有層と無機質充填剤不含層の二層構造からなる封止樹脂層によって、上記無機質充填剤含有層が半導体素子側に位置するよう樹脂封止されている。 The semiconductor device of the present invention thus obtained has a semiconductor element on the wiring circuit board in a state where the connection electrode provided on the semiconductor element and the connection terminal provided on the wiring circuit board are opposed to each other. A two-layer structure of an inorganic filler-containing layer and an inorganic filler-free layer, wherein the gap between the wiring circuit board and the semiconductor element is made of the sealing resin sheet. The sealing resin layer made of is sealed with resin so that the inorganic filler-containing layer is located on the semiconductor element side.
先に述べた本発明の半導体装置の製造工程は、具体的には、図２〜図６に示す工程順序で行われる。 Specifically, the above-described manufacturing process of the semiconductor device of the present invention is performed in the process sequence shown in FIGS.
すなわち、まず、図２に示すように、上記封止用樹脂シート１の、無機質充填剤含有層３〔（α）層〕の表面を、ステージ上に載置した半導体素子５の接続用電極部４設置面に対し、ロールラミネーター（ロール９）を用いて貼り合わせる。この貼り合わせ時のステージ温度が、本発明に規定するラミネート温度であり、無機質充填剤含有層３〔（α）層〕と無機質充填剤不含層２〔（β）層〕とが特定の粘度範囲を示す、６０〜１２５℃から選ばれる任意の温度である。なお、無機質充填剤含有層３〔（α）層〕の表面に剥離シート（ポリエステルフィルム等）がある場合は、剥離してから貼り合わせる。また、半導体素子５の接続用電極部４の先端部が無機質充填剤含有層３を貫通して無機質充填剤不含層２に位置するよう、ラミネート圧力は０．１〜１ＭＰａが好ましい。
That is, first, as shown in FIG. 2, the electrode part for connection of the
上記のようにして貼り合わせ、封止用樹脂シート１の裁断を行うと、図３に示すような状態となる。なお、上記封止用樹脂シート１の裁断は、上記貼り合わせ前に行うようにしてもよく、さらに、後記のように半導体素子５がウエハの場合におけるダイシング工程の際に同時に行うようにしてもよい。続いて、上記のようにして貼り合わせた封止用樹脂シート１の、無機質充填剤不含層２側の剥離シート１０（ポリエステルフィルム等）を剥離し、これにより露呈した無機質充填剤不含層２の表面を、図４に示すように、配線回路基板７上の、接続用端子６設置面に貼り合わせる。次いで、フリップチップボンダー（パナソニック社製）等の装置を用いて、所定の圧力および熱を加え、図５に示すように、上記半導体素子５の接続用電極部４と、配線回路基板７の接続用端子６との接合を行う。接合条件としては、ボンディング圧力（接続用電極部１個あたりの荷重）が０．０１９６〜０．９８Ｎ／ｂｕｍｐ（０．００２〜０．１ｋｇｆ／ｂｕｍｐ）、接合温度が２６０〜２９０℃、接合時間が２〜２０秒であることが好ましい。これにより、上記封止用樹脂シート１は溶融し、その後熱硬化して樹脂封止が行われ、図６に示すように、樹脂硬化体８となる。このようにして、半導体素子５と配線回路基板７を接合し、半導体装置を得る。
When the bonding and the sealing
なお、半導体素子５がウエハの場合は、バックグラインド工程、ダイシング工程が、図３に示す工程と図４に示す工程との間に追加される。すなわち、ウエハに対するバックグラインド処理およびダイシング処理が行われた後、無機質充填剤不含層２側の剥離シート１０を剥離する。
When the
つぎに、実施例について比較例と併せて説明する。ただし、本発明は、これら実施例に限定されるものではない。 Next, examples will be described together with comparative examples. However, the present invention is not limited to these examples.
まず、封止用樹脂シートの形成材料として、下記に示すエポキシ樹脂、フェノール樹脂、エラストマー、硬化促進剤および無機質充填剤を準備した。 First, the following epoxy resin, phenol resin, elastomer, curing accelerator, and inorganic filler were prepared as forming materials for the sealing resin sheet.
〔エポキシ樹脂Ａ〕
エポキシ基当量が１４２ｇ／ｅｑのナフタレン型エポキシ樹脂（製品名：ＨＰ４０３２Ｄ（ＤＩＣ））
[Epoxy resin A]
Naphthalene type epoxy resin having an epoxy group equivalent of 142 g / eq (product name: HP4032D (DIC))
〔エポキシ樹脂Ｂ〕
エポキシ基当量が１６９ｇ／ｅｑのトリスフェノールメタン型エポキシ樹脂（製品名：ＥＰＰＮ５０１ＨＹ（日本化薬社製））
[Epoxy resin B]
Trisphenolmethane type epoxy resin having an epoxy group equivalent of 169 g / eq (product name: EPPN501HY (manufactured by Nippon Kayaku Co., Ltd.))
〔エポキシ樹脂Ｃ〕
エポキシ基当量が１８５ｇ／ｅｑのビスフェノールＡ型エポキシ樹脂（製品名：ＹＬ−９８０（ジャパンエポキシレジン社製））
[Epoxy resin C]
Bisphenol A type epoxy resin having an epoxy group equivalent of 185 g / eq (product name: YL-980 (manufactured by Japan Epoxy Resin))
〔フェノール樹脂Ａ〕
水酸基当量１７５ｇ／ｅｑのアラルキル型フェノール樹脂（製品名：ＭＥＨＣ−７８００Ｓ（明和化成社製））
[Phenolic resin A]
Aralkyl type phenol resin having a hydroxyl group equivalent of 175 g / eq (product name: MEHC-7800S (manufactured by Meiwa Kasei Co., Ltd.))
〔フェノール樹脂Ｂ〕
水酸基当量１０５ｇ／ｅｑのフェノールノボラック樹脂（製品名：ＣＳ−１８０（群栄化学社製））
[Phenolic resin B]
Phenol novolac resin having a hydroxyl group equivalent of 105 g / eq (product name: CS-180 (manufactured by Gunei Chemical Co., Ltd.))
〔エラストマーＡ〕
重量平均分子量４５００００のアクリル酸エチルとアクリル酸ブチルとアクリロニトリルの共重合ポリマー（ガラス転移温度：−１５℃）
[Elastomer A]
Copolymer of ethyl acrylate, butyl acrylate and acrylonitrile having a weight average molecular weight of 450,000 (glass transition temperature: −15 ° C.)
〔エラストマーＢ〕
重量平均分子量４５００００のアクリル酸エチルとアクリル酸ブチルとアクリロニトリルの共重合ポリマー（ガラス転移温度：１５℃）
[Elastomer B]
Copolymer of ethyl acrylate, butyl acrylate and acrylonitrile having a weight average molecular weight of 450,000 (glass transition temperature: 15 ° C.)
〔硬化促進剤〕
トリフェニルホスフィン（製品名：ＴＰＰ−Ｋ（北興化学社製））
[Curing accelerator]
Triphenylphosphine (Product name: TPP-K (Hokuko Chemical Co., Ltd.))
〔無機質充填剤〕
平均粒径０．５μｍの球状溶融シリカ（製品名：ＳＥ−２０５０（アドマテックス社製））
[Inorganic filler]
Spherical fused silica with an average particle size of 0.5 μm (Product name: SE-2050 (manufactured by Admatechs))
〔熱硬化性樹脂組成物シートの作製〕
上記各材料を、下記の表１に示す割合（表１において、組成１〜１１に示される各材料の割合）で配合し、これにメチルエチルケトンを加えて混合溶解し、この混合溶液を、離型処理したポリエステルフィルム上に塗布した。次に、上記混合溶液を塗布したポリエステルフィルムを１１０℃で乾燥させ、メチルエチルケトンを除去した。これにより、上記ポリエステルフィルム上に、組成１〜１１のいずれかからなり、所望の厚みを有する熱硬化性樹脂組成物シートを作製した。なお、下記の表１に示すように、組成１〜５からなるシートは、無機質充填剤含有層（α層）を構成するものであり、組成６〜１１からなるシートは、無機質充填剤不含層（β層）を構成するものである。
[Preparation of thermosetting resin composition sheet]
The above materials are blended in the proportions shown in the following Table 1 (the proportions of the materials shown in Tables 1 to 11 in Table 1), and methyl ethyl ketone is added and mixed and dissolved therein. It was applied on the treated polyester film. Next, the polyester film coated with the mixed solution was dried at 110 ° C. to remove methyl ethyl ketone. Thereby, the thermosetting resin composition sheet which consists of either of the compositions 1-11 and has desired thickness was produced on the said polyester film. In addition, as shown in Table 1 below, the sheet composed of
〔実施例１〜９、比較例１〜１０〕
上記作製の熱硬化性樹脂組成物シートを、ポリエステルフィルムをつけたまま、後記の表２および表３に示すα層およびβ層の組み合わせ（各層の厚みは、表２および表３に示す。）で、その樹脂組成物シート面同士を貼り合わせ、二層構造の封止用樹脂シートを作製した。
[Examples 1-9, Comparative Examples 1-10]
Combinations of α layer and β layer shown in Table 2 and Table 3 below (with the thickness of each layer shown in Table 2 and Table 3) with the polyester film attached to the thermosetting resin composition sheet prepared above. Then, the resin composition sheet surfaces were bonded together to produce a sealing resin sheet having a two-layer structure.
このようにして作製した封止用樹脂シートの、α層側のポリエステルフィルム（剥離シート）を剥離し、これにより露呈したα層の表面を、ステージ上に載置した半導体素子のバンプ（接続用電極部）設置面に接するようにし、ロールラミネーター（ロール速度：０．１ｍ／分、ロール圧力：０．５ＭＰａ、製品名：ＤＲ３０００II（日東精機社製））を用いて貼り合わせた（図２参照）。なお、上記貼り合わせに用いた封止用樹脂シートは、半導体素子と同寸法に裁断されている。また、貼り合わせ時のステージ温度（ラミネート温度）は、表２および表３に示す通りである。また、そのラミネート温度におけるα層およびβ層の溶融粘度は、回転型粘度計（ＨＡＫＫＥ社製、レオストレスＲＳ１）を用い、測定温度１３０℃、ギャップ１００μｍ、回転コーン直径２０ｍｍ、回転速度１０ｓ-1という条件で測定した。この測定結果も、後記の表２および表３に併せて示した。また、半導体素子のバンプは、半田バンプであり、そのバンプの高さは６０μｍである。 The α layer side polyester film (release sheet) of the sealing resin sheet thus produced is peeled off, and the surface of the exposed α layer is then bumped on the semiconductor element placed on the stage (for connection) The electrode part was brought into contact with the installation surface and bonded using a roll laminator (roll speed: 0.1 m / min, roll pressure: 0.5 MPa, product name: DR3000II (manufactured by Nitto Seiki Co., Ltd.)) (see FIG. 2). ). In addition, the sealing resin sheet used for the bonding is cut to the same dimensions as the semiconductor element. Moreover, the stage temperature (laminate temperature) at the time of bonding is as shown in Table 2 and Table 3. The melt viscosity of the α layer and the β layer at the lamination temperature was measured using a rotational viscometer (manufactured by HAKKE, Rheo Stress RS1) at a measurement temperature of 130 ° C., a gap of 100 μm, a rotational cone diameter of 20 mm, and a rotational speed of 10 s −1. It measured on condition of. The measurement results are also shown in Tables 2 and 3 below. The bumps of the semiconductor element are solder bumps, and the bump height is 60 μm.
続いて、上記のようにして貼り合わせた封止用樹脂シートのβ層側のポリエステルフィルム（図３参照）を剥離し、これにより露呈したβ層の表面を、配線回路基板上の、接続用端子設置面に貼り合わせた(図４参照)。次いで、パナソニック社製のフリップチップボンダー（ボンディング圧力：０．０２９Ｎ/ｂｕｍｐ（０．００３ｋｇｆ/ｂｕｍｐ）、接合温度：２８０℃×１０秒、ステージ温度：１４０℃）を用いて、半導体素子のバンプと、配線回路基板の接続用端子との接合を行い（図５参照）、樹脂封止を行うことにより、半導体装置（図６参照）を得た。 Subsequently, the β layer side polyester film (see FIG. 3) of the sealing resin sheet bonded as described above is peeled off, and the exposed β layer surface is connected to the printed circuit board on the wiring circuit board. Affixed to the terminal installation surface (see FIG. 4). Next, using a flip chip bonder manufactured by Panasonic (bonding pressure: 0.029 N / bump (0.003 kgf / bump), bonding temperature: 280 ° C. × 10 seconds, stage temperature: 140 ° C.) The semiconductor device (see FIG. 6) was obtained by performing bonding with the connection terminal of the printed circuit board (see FIG. 5) and resin sealing.
このようにして行われた半導体装置の製造過程において、下記の基準に従い、本発明の基準を充分に満足し得るものであったか否かを評価した。その結果を、後記の表２および表３に併せて示した。 In the manufacturing process of the semiconductor device thus performed, it was evaluated whether or not the criteria of the present invention could be sufficiently satisfied according to the following criteria. The results are also shown in Table 2 and Table 3 below.
〔「貼り合わせ」評価〕
半導体素子に封止用樹脂シートを貼り合わせた後、その断面を、顕微鏡（キーエンス社製のデジタルマイクロスコープＶＨＸ−５００）を用いて１０００倍に拡大して観察した。その結果、バンプ先端に無機質充填剤がない場合を○、完全にβ層にバンプが理没している場合を◎、バンプ先端に無機質充填剤層が確認された場合を×と評価した。
["Bonding" evaluation]
After the sealing resin sheet was bonded to the semiconductor element, the cross section thereof was observed with a microscope (Digital Microscope VHX-500 manufactured by Keyence Corporation) magnified 1000 times. As a result, the case where there was no inorganic filler at the bump tip was evaluated as ◯, the case where the bump was completely buried in the β layer was evaluated as ◎, and the case where the inorganic filler layer was confirmed at the bump tip was evaluated as ×.
〔「接合」評価〕
半導体素子と配線回路基板とを接合した後、その断面を、顕微鏡（キーエンス社製デジタルマイクロスコープＶＨＸ−５００）を用いて１０００倍に拡大して観察した。その結果、半導体素子のバンプと、配線回路基板の接続用端子との接合部に無機質充填剤がない場合を○、上記接合部に無機質充填剤層が確認された場合を×と評価した。
[Evaluation of “joining”]
After joining the semiconductor element and the printed circuit board, the cross section was observed by magnifying it 1000 times using a microscope (Keyence Corporation digital microscope VHX-500). As a result, the case where there was no inorganic filler at the joint between the bump of the semiconductor element and the connection terminal of the printed circuit board was evaluated as ◯, and the case where the inorganic filler layer was confirmed at the joint was evaluated as x.
上記表の結果より、実施例では、封止用樹脂シートのα層（無機質充填剤含有層）とβ層（無機質充填剤不含層）とが、本発明の規定（α層の溶融粘度が１．０×１０2〜２．０×１０4Ｐａ・ｓであり、β層の溶融粘度が１．０×１０3〜２．０×１０5Ｐａ・ｓであり、両層の粘度差が１．５×１０4Ｐａ・ｓ以上であり、β層の厚みが２０〜４８μｍ（バンプ高さの１／３〜４／５）である。）を満たしていることから、上記の「貼り合わせ」および「接合」評価において良好な結果が得られ、無機質充填剤の噛みこみによる半導体素子・配線回路基板間での接続信頼性の低下を防止することができていることがわかる。 From the results of the above table, in the examples, the α layer (inorganic filler-containing layer) and the β layer (inorganic filler-free layer) of the sealing resin sheet are defined in the present invention (the melt viscosity of the α layer is 1.0 × 10 2 to 2.0 × 10 4 Pa · s, the melt viscosity of the β layer is 1.0 × 10 3 to 2.0 × 10 5 Pa · s, and the viscosity difference between the two layers is Since it is 1.5 × 10 4 Pa · s or more and the thickness of the β layer satisfies 20 to 48 μm (1/3 to 4/5 of the bump height), the “bonding” is performed. It can be seen that good results were obtained in the evaluation of “joining” and “joining”, and it was possible to prevent a decrease in connection reliability between the semiconductor element and the printed circuit board due to the inclusion of the inorganic filler.
これに対し、比較例では、実施例と同様、α層（無機質充填剤含有層）とβ層（無機質充填剤不含層）とからなる封止用樹脂シートを用いて半導体封止を行っているが、そのα層、β層の一方あるいは双方が、上記の、本発明の規定を満たしていないことから、「貼り合わせ」および「接合」評価に劣る結果となった。 On the other hand, in the comparative example, as in the example, semiconductor sealing was performed using a sealing resin sheet composed of an α layer (inorganic filler-containing layer) and a β layer (inorganic filler-free layer). However, one or both of the α layer and β layer do not satisfy the above-mentioned provisions of the present invention, resulting in inferior “bonding” and “joining” evaluations.
１ 封止用樹脂シート
２ 無機質充填剤不含層
３ 無機質充填剤含有層
DESCRIPTION OF
Claims (6)
（ｘ）６０〜１２５℃から選ばれるラミネート温度における溶融粘度が、上記（α）層が１．０×１０2〜２．０×１０4Ｐａ・ｓであり、上記（β）層が１．０×１０3〜２．０×１０5Ｐａ・ｓである。
（ｙ）上記（β）層の溶融粘度と（α）層の溶融粘度の差〔（β）層−（α）層〕が、１．５×１０4Ｐａ・ｓ以上である。
（ｚ）上記封止用樹脂シートの（β）層の厚みが、上記接続用電極部の高さ（ｈ）を基準として、１／３ｈ〜４／５ｈである。 A wiring for a semiconductor device in which a semiconductor element is mounted on the wiring circuit board in a state in which a connection electrode provided on the semiconductor element and a connection terminal provided on the wiring circuit board are opposed to each other. An epoxy resin composition layer that is used for resin-sealing a gap between a circuit board and a semiconductor element, wherein the sealing resin sheet contains (α) an inorganic filler. And (β) an epoxy resin composition layer that does not contain an inorganic filler, wherein the (α) layer contains an epoxy resin, a phenol resin, an elastomer component, and an inorganic filler, and the amount of the elastomer component The (β) layer contains an epoxy resin, a phenol resin, and an elastomer component, and the amount of the elastomer component is 20 layers. % To 50 an epoxy resin composition is less than wt%, and the (alpha) layer and (beta) layer is a resin for sealing, characterized in that it comprises the following properties (x) ~ (z) Sheet.
(X) The melt viscosity at a lamination temperature selected from 60 to 125 ° C. is that the (α) layer is 1.0 × 10 2 to 2.0 × 10 4 Pa · s, and the (β) layer is 1. It is 0 * 10 < 3 > -2.0 * 10 < 5 > Pa * s.
(Y) The difference between the melt viscosity of the (β) layer and the melt viscosity of the (α) layer [(β) layer− (α) layer] is 1.5 × 10 4 Pa · s or more.
(Z) The thickness of the (β) layer of the sealing resin sheet is 1 / 3h to 4 / 5h on the basis of the height (h) of the connecting electrode portion.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011028470A JP5802400B2 (en) | 2011-02-14 | 2011-02-14 | Resin sheet for sealing, semiconductor device using the same, and method for manufacturing the semiconductor device |
| US13/364,592 US20120205820A1 (en) | 2011-02-14 | 2012-02-02 | Encapsulating resin sheet and semiconductor device using the same, and manufacturing method for the semiconductor device |
| KR1020120013651A KR20120093085A (en) | 2011-02-14 | 2012-02-10 | Resin sheet for sealing, semiconductor apparatus using the same, and method for manufacturing the semiconductor apparatus |
| TW101104692A TW201243967A (en) | 2011-02-14 | 2012-02-14 | Encapsulating resin sheet and semiconductor device using the same, and manufacturing method for the semiconductor device |
| CN2012100331715A CN102683297A (en) | 2011-02-14 | 2012-02-14 | Encapsulating resin sheet and semiconductor device using same, and manufacturing method for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2011028470A JP5802400B2 (en) | 2011-02-14 | 2011-02-14 | Resin sheet for sealing, semiconductor device using the same, and method for manufacturing the semiconductor device |
Publications (2)
| Publication Number | Publication Date |
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| JP2012169414A JP2012169414A (en) | 2012-09-06 |
| JP5802400B2 true JP5802400B2 (en) | 2015-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| JP2011028470A Expired - Fee Related JP5802400B2 (en) | 2011-02-14 | 2011-02-14 | Resin sheet for sealing, semiconductor device using the same, and method for manufacturing the semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20120205820A1 (en) |
| JP (1) | JP5802400B2 (en) |
| KR (1) | KR20120093085A (en) |
| CN (1) | CN102683297A (en) |
| TW (1) | TW201243967A (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| JP5830250B2 (en) * | 2011-02-15 | 2015-12-09 | 日東電工株式会社 | Manufacturing method of semiconductor device |
| US9330993B2 (en) * | 2012-12-20 | 2016-05-03 | Intel Corporation | Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby |
| JP6222941B2 (en) * | 2013-02-21 | 2017-11-01 | 日東電工株式会社 | Underfill sheet, back-grinding tape-integrated underfill sheet, dicing tape-integrated underfill sheet, and semiconductor device manufacturing method |
| JP6066856B2 (en) * | 2013-08-01 | 2017-01-25 | 日東電工株式会社 | Semiconductor device manufacturing method and sealing sheet |
| US20150371916A1 (en) * | 2014-06-23 | 2015-12-24 | Rohm And Haas Electronic Materials Llc | Pre-applied underfill |
| JP6379051B2 (en) * | 2015-01-23 | 2018-08-22 | 日東電工株式会社 | Hollow electronic device sealing sheet |
| CN107210235B (en) | 2015-03-27 | 2020-04-14 | 惠普发展公司，有限责任合伙企业 | Circuit package |
| JP6933463B2 (en) * | 2016-12-28 | 2021-09-08 | 日東電工株式会社 | Resin sheet |
| JPWO2021010208A1 (en) * | 2019-07-12 | 2021-01-21 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2848357B2 (en) * | 1996-10-02 | 1999-01-20 | 日本電気株式会社 | Semiconductor device mounting method and its mounting structure |
| WO1998028788A1 (en) * | 1996-12-24 | 1998-07-02 | Nitto Denko Corporation | Manufacture of semiconductor device |
| JP3999840B2 (en) * | 1997-04-16 | 2007-10-31 | 日東電工株式会社 | Resin sheet for sealing |
| JPH1154662A (en) * | 1997-08-01 | 1999-02-26 | Nec Corp | Flip-chip resin-sealed structure and resin-sealing method |
| JP3119230B2 (en) * | 1998-03-03 | 2000-12-18 | 日本電気株式会社 | Resin film and method for connecting electronic components using the same |
| JP3325000B2 (en) * | 1999-05-28 | 2002-09-17 | ソニーケミカル株式会社 | Semiconductor element mounting method |
| WO2001028769A1 (en) * | 1999-10-15 | 2001-04-26 | 3M Innovative Properties Company | Conformable multilayer films |
| JP4438973B2 (en) * | 2000-05-23 | 2010-03-24 | アムコア テクノロジー，インコーポレイテッド | Sheet-shaped resin composition and method for manufacturing semiconductor device using the same |
| JP2002151551A (en) * | 2000-11-10 | 2002-05-24 | Hitachi Ltd | Flip-chip mounting structure, semiconductor device therewith and mounting method |
| US6794751B2 (en) * | 2001-06-29 | 2004-09-21 | Intel Corporation | Multi-purpose planarizing/back-grind/pre-underfill arrangements for bumped wafers and dies |
| JP3718190B2 (en) * | 2002-07-31 | 2005-11-16 | 富士通株式会社 | Method for forming surface mount structure and surface mount structure |
| JP4170839B2 (en) * | 2003-07-11 | 2008-10-22 | 日東電工株式会社 | Laminated sheet |
| MY138566A (en) * | 2004-03-15 | 2009-06-30 | Hitachi Chemical Co Ltd | Dicing/die bonding sheet |
| CN101714513B (en) * | 2004-04-20 | 2012-05-30 | 日立化成工业株式会社 | Method for producing the semiconductor device |
| JP5569126B2 (en) * | 2009-05-29 | 2014-08-13 | 日立化成株式会社 | Adhesive composition, adhesive sheet, and method for manufacturing semiconductor device |
| CA2782339C (en) * | 2009-12-01 | 2018-05-22 | Kuraray Co., Ltd. | Multilayered structure and method for producing the same |
| WO2011149299A2 (en) * | 2010-05-28 | 2011-12-01 | (주)Lg화학 | Melt-processed molded resin article |
| TW201220977A (en) * | 2010-07-01 | 2012-05-16 | Sumitomo Bakelite Co | Preppreg, circuit board, and semiconductor device |
| KR101351617B1 (en) * | 2010-12-23 | 2014-01-15 | 제일모직주식회사 | Anisotropic conductive film |
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2011
- 2011-02-14 JP JP2011028470A patent/JP5802400B2/en not_active Expired - Fee Related
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2012
- 2012-02-02 US US13/364,592 patent/US20120205820A1/en not_active Abandoned
- 2012-02-10 KR KR1020120013651A patent/KR20120093085A/en not_active Application Discontinuation
- 2012-02-14 TW TW101104692A patent/TW201243967A/en unknown
- 2012-02-14 CN CN2012100331715A patent/CN102683297A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20120205820A1 (en) | 2012-08-16 |
| KR20120093085A (en) | 2012-08-22 |
| JP2012169414A (en) | 2012-09-06 |
| CN102683297A (en) | 2012-09-19 |
| TW201243967A (en) | 2012-11-01 |
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