JP5789912B2 - Frequency detector - Google Patents

Description

  The present invention relates to a frequency detection device used in a semiconductor integrated circuit.

  Conventionally, as a frequency analyzer, a modulation unit that chirp-modulates a signal output from a signal source, a digital distributed delay circuit unit that expands the modulated signal as a digital signal, and distributes and outputs with a different delay amount for each frequency And a frequency detector that detects the frequency of the output signal based on the delay amount of each signal (for example, see Patent Document 1).

JP 2001-242201

  However, such a frequency analysis apparatus has a problem that it is difficult to integrate it into a semiconductor substrate because a surface acoustic wave element is used in a modulation unit that chirp-modulates a signal.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a frequency detection device that can be easily integrated on a semiconductor substrate.

A frequency detection device according to the present invention is a frequency detection device integrated on a semiconductor substrate, and includes a delay control voltage source that supplies a control voltage, and a delay element that changes a delay amount based on the control voltage. A ring oscillator that changes a delay amount based on a control voltage of the delay control voltage source, a PLL circuit that keeps the output of the control voltage of the delay control voltage source constant, and an input signal as a rectangular wave signal A signal conversion means for converting, and a plurality of delay units having different delay amounts each including a delay element having the same delay characteristics as the delay element of the ring oscillator with respect to the control voltage on the semiconductor substrate , A signal delay means for delaying the rectangular wave signal based on the control voltage, and a phase of the rectangular wave signal and a plurality of delayed rectangular wave signals delayed by the signal delay means. A phase comparison means for comparing each phase; a voltage conversion means for converting the comparison result of the phase comparison means into a DC voltage; a comparison means for comparing the DC voltage with a predetermined voltage; and the comparison Frequency detection means for detecting the frequency of the input signal based on a combination of comparison results by means and characteristics of a preset voltage and frequency.

  According to the present invention, the input signal is converted into a rectangular wave signal and then delayed based on the control voltage output from the PLL circuit, and the phase difference between the rectangular wave signal and the delayed rectangular wave signal obtained by delaying the rectangular wave signal is changed to a DC voltage. By converting and detecting the frequency of the input signal based on the preset voltage and frequency characteristics, a frequency detection device that can be easily integrated on a semiconductor substrate without using a surface acoustic wave device can be obtained.

It is a figure which shows the structure of the frequency detection apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows operation | movement of the phase comparator of FIG. It is a figure which shows the output voltage-frequency characteristic of LPF described in FIG. It is a figure which shows the structure of the frequency detection apparatus which concerns on Embodiment 2 of this invention. It is a figure which shows the output voltage-frequency characteristic of each LPF described in FIG. It is a figure which shows the relationship between each comparator output and frequency in the frequency detection apparatus of FIG. It is a figure which shows the structure of the frequency detection apparatus which concerns on Embodiment 3 of this invention. It is a figure which shows the output voltage-frequency characteristic of each LPF described in FIG. It is a figure which shows the relationship between each comparator output in the frequency detection apparatus of FIG. 7, and the operation code for detecting a frequency .

Embodiment 1 FIG.
A frequency detection apparatus 1 according to Embodiment 1 for carrying out the present invention will be described with reference to FIGS. In FIG. 1, a frequency detection apparatus 1 amplifies a limiter amplifier 5 that converts a signal input from a signal input terminal 4 on a semiconductor substrate 2 into a rectangular wave signal, that is, a signal converting means, and a rectangular wave signal branched into two. Buffer amplifiers 6a and 6b, a delay element unit 7 that delays a rectangular wave signal from the buffer amplifier 6a according to the control voltage, that is, a signal delay unit, a delayed rectangular wave signal from the delay element unit 7 and a buffer amplifier 6b A phase comparator 8 constituted by an XOR logic gate for comparing the phase differences of the rectangular wave signals, that is, phase comparison means, and a low-pass filter 9 (hereinafter referred to as LPF 9) for smoothing the phase difference pulse obtained as a result of the phase comparison into a DC voltage. Voltage conversion means, AD converter 10 for converting a DC voltage into a digital signal, and preset voltage and frequency characteristic data Based on it includes a voltage frequency converter 11 or frequency detection means for detecting a frequency corresponding to the voltage value digitized, and an output terminal 12 for outputting the detected frequency to the outside of the semiconductor substrate 2.

  The control voltage is feedback-controlled so that the output becomes constant by the PLL circuit 3 including the external reference signal source 14, the phase comparator 15, and the loop filter 16, and the control voltage input terminal 18 provided on the semiconductor substrate 2 is connected to the control voltage. To the delay element section 7. Further, in the middle of the feedback path of the PLL circuit 3, an N-stage ring oscillator 19 whose delay amount is changed by its own control voltage as with the delay element unit 7, a regulator that stably supplies the output of the loop filter 16, etc. The delay control voltage source 17 is provided.

  The delay element unit 7 and the ring oscillator 19 are configured by a delay element 70a having the same delay characteristic with respect to the control voltage. The delay element unit 7 has a plurality of delay elements 70a connected in series so that the delay amount becomes Td, and the ring oscillator 19 has the same delay characteristics as the (N-1) delay elements 70a and outputs an inverter. One delay element 70b connected in a ring shape. The delay element 70b only needs to be able to oscillate the ring oscillator 19, and any number of delay elements 70b may be used as long as it is an odd number. In this case, the total number of delay elements 70a and 70b is adjusted to be N.

Next, the operation will be described.
The signal input from the input terminal 4 is converted into a rectangular wave signal having the same cycle Tsig as the input signal by the limiter amplifier 5, branched into two, and then amplified by the buffer amplifiers 6a and 6b. The rectangular wave signal amplified by the buffer amplifier 6a is delayed by the delay amount Td by the delay element unit 7, and transmitted to the phase comparator 8 as a delayed rectangular wave signal.
On the other hand, the rectangular wave signal amplified by the buffer amplifier 6b is directly transmitted to the phase comparator 8, and the phase comparator 8 compares the phase difference between these two signals and outputs a rectangular phase difference pulse signal.

  Here, assuming that a rectangular wave signal is included for a maximum of n periods (where n is a positive integer) in the period of the delay amount Td, the remaining time ΔTd can be expressed by the following equation.

When this ΔTd is shorter than a half cycle of the rectangular wave input signal, that is, 0 ≦ ΔTd <Tsig / 2, a phase difference pulse signal having a pulse width ΔTd is output twice during a period of Tsig as shown in FIG. Is done.
On the other hand, when ΔTd is longer than a half cycle of the rectangular wave input signal, that is, when Tsig / 2 ≦ ΔTd <Tsig, as shown in FIG. 2B, a phase difference pulse signal having a pulse width (Tsig−ΔTd). Are output twice during the period of Tsig.

  The phase difference pulse signal output from the phase comparator 8 is smoothed to a DC voltage by the LPF 9 as shown by a one-dot chain line in FIG. When the DC voltage smoothed by the LPF 9 is normalized by setting the maximum output voltage of the phase difference pulse signal output from the phase comparator 8 to 1, Equation 2 is obtained when 0 ≦ ΔTd <Tsig / 2, and Tsig / 2 ≦ ΔTd. In the case of <Tsig, it can be represented by each equation of Formula 3. Note that Fsig (= 1 / Tsig) is the frequency of the rectangular wave input signal.

  FIG. 3 is a graph of the above two formulas. Since the frequency Fsig and the DC voltage are in a proportional relationship, the frequency Fsig is unique depending on the value of the DC voltage as long as nFd / 2 ≦ Fsig <[(n + 1) / 2] Fd (where Fd = 1 / Td). It is decided.

  The signal smoothed to a DC voltage by the LPF 9 is converted to a digital signal by the AD converter 10 and input to the voltage frequency converter 11. The voltage frequency converter 11 detects the frequency corresponding to the digitized voltage value as the frequency of the input signal based on the preset voltage and frequency characteristic data, and outputs it to the outside of the semiconductor substrate 2 via the output terminal 12. . However, the detectable range is limited to the frequency range nFd / 2 ≦ Fsig <[(n + 1) / 2] Fd preset in the AD converter 10.

Here, the operation of the control voltage applied to the delay element unit 7 will be described.
As described above, the control voltage is feedback controlled by the PLL circuit 3. The phase comparator 15 provided in the PLL circuit 3 compares the phase of the frequency fref signal input from the external reference signal source 14 with the frequency f signal oscillated by the ring oscillator 19 and outputs a phase difference pulse. . The phase difference pulse is smoothed to a DC voltage by the loop filter 16 and applied as a control voltage to the ring oscillator 19 and the delay element unit 7 provided on the semiconductor substrate 2 via the control voltage input terminal 18.

  The delay amounts of the delay elements 70a and 70b constituting the ring oscillator 19 change according to the control voltage, and the signal oscillated by the ring oscillator 19 whose delay amount has changed is input to the phase comparator 15 again. The PLL circuit 3 locks when the phase difference between the signal of the external reference signal source 14 and the signal fed back to the phase comparator 15 becomes constant, and outputs it as a fixed voltage to the semiconductor substrate 2 via the delay control voltage source 17. Is done.

  When the PLL circuit 3 is locked, the delay amount of the delay element 70a is also fixed, so that the output timing of the phase difference pulse is fixed, and the value of the DC voltage smoothed by the LPF 9 becomes constant. Thereby, the voltage value input to the voltage frequency converter 11 is stabilized, and the frequency Fsig of the input signal can be detected.

  According to this embodiment, the frequency detection device 1 configures the delay element unit 7 and the ring oscillator 19 using the delay elements 70a and 70b having the same delay characteristic with respect to the control voltage, so that the input signal Since the value of the DC voltage obtained from the phase difference pulse is constant, the frequency can be detected from the proportional characteristic of voltage and frequency, and a frequency detection device that can be easily integrated on the semiconductor substrate 2 can be obtained.

Embodiment 2. FIG.
A frequency detection apparatus 1A according to the present embodiment will be described with reference to FIGS. In FIG. 4, the frequency detection device 1 </ b> A includes a limiter amplifier 5 that converts a signal input from the signal input terminal 4 onto the semiconductor substrate 2 into a rectangular wave signal, that is, a signal conversion unit, as in the first embodiment. Buffer amplifiers 6a and 6b for amplifying the branched rectangular wave signal, delay element units 7a to 7c for delaying the rectangular wave signal from the buffer amplifier 6a with different delay amounts according to the control voltage, that is, signal delay means, and delay Phase comparison was performed with phase comparators 8a to 8c, ie, phase comparison means, each composed of an XOR logic gate for comparing the phase difference between each of the delayed rectangular wave signals from the element units 7a to 7c and the rectangular wave signal from the buffer amplifier 6b. LPFs 9a to 9c for smoothing the resulting phase difference pulses to DC voltages, that is, voltage conversion means, and outputs of LPFs 9a to 9c are external Comparators 20a to 20c that compare whether the voltage is higher than the voltage of the reference voltage source 21 applied from the above, that is, comparison means, combinations of comparison results of the comparators 20a to 20c, preset voltage and frequency A voltage frequency converter 11a that detects the frequency of the input signal based on the characteristic data, that is, a frequency detection means, and an output terminal 12 that outputs the detected frequency to the outside of the semiconductor substrate 2 are provided.

  The control voltage is feedback-controlled so that the output becomes constant by the PLL circuit 3 including the external reference signal source 14, the phase comparator 15, and the loop filter 16, and the control voltage input terminal 18 provided on the semiconductor substrate 2 is connected to the control voltage. To the delay element portions 7a to 7c. Further, in the middle of the feedback path of the PLL circuit 3, the output of the N-stage ring oscillator 19 whose delay amount is changed by its own control voltage and the loop filter 16 as well as the delay element units 7a to 7c are stably supplied. A delay control voltage source 17 such as a regulator is provided.

  The delay element units 7a to 7c and the ring oscillator 19 are configured by a delay element 70a having the same delay characteristic with respect to the control voltage. Each of the delay element units 7a to 7c includes one or a plurality of delay elements 70a connected in series so that the delay amount is 1 / 2Td, Td, 2Td and a power of 2, and the ring oscillator 19 includes (N -1) One delay element 70a and one delay element 70b having the same delay characteristic and outputting an inverter are connected in a ring shape. The delay element 70b only needs to be able to oscillate the ring oscillator 19, and any number of delay elements 70b may be used as long as it is an odd number. In this case, the total number of delay elements 70a and 70b is adjusted to be N. Further, the delay amount of the delay element units 7a to 7c is not limited to a power of 2, and may be a power of 2 or more integers.

Next, the operation will be described.
The signal input from the input terminal 4 is converted into a rectangular wave signal having the same cycle Tsig as the input signal by the limiter amplifier 5, branched into two, and then amplified by the buffer amplifiers 6a and 6b. The rectangular wave signal amplified by the buffer amplifier 6a is further branched into three, and delayed by delay amounts 1 / 2Td, Td, and 2Td, respectively, by the delay element units 7a to 7c. 8c.

  On the other hand, the rectangular wave signal amplified by the buffer amplifier 6b is directly transmitted to the phase comparators 8a to 8c. The phase comparators 8a to 8c each output the phase difference between the input delayed rectangular wave signal and rectangular wave signal as a rectangular phase difference pulse signal, and these phase difference pulse signals are smoothed to DC voltages by the LPFs 9a to 9c, respectively. It becomes.

  When the DC voltages output from the LPFs 9a to 9c are normalized in the same manner as in the first embodiment, voltage-frequency characteristics as shown in FIG. 5 are obtained. Assuming that the voltage of the reference voltage source 21 applied from the outside is ½ of the standardized voltage as indicated by the broken line in the figure, the comparators 20a to 20c respectively compare the DC voltage of the LPFs 9a to 9c with the voltage of the reference voltage source 21. And output as a binary value of High / Low.

  The comparison results of the comparators 20a to 20c are transmitted to the voltage frequency converter 11a as a 3-bit signal having the output of the comparator 20a as the most significant. In the voltage frequency converter 11a, voltage and frequency characteristic data corresponding to the 3-bit signal from each of the comparators 20a to 20c is set in advance, the frequency is detected according to the value of the input 3-bit signal, and the output terminal 12 is connected. To the outside of the semiconductor substrate 2.

In FIG. 6, for example, when the output of the 3-bit signal is LLL, the frequency is in the range of 0 to Fd / 8, and therefore 0 corresponding to the minimum value in this range is output as the frequency of the input signal. Similarly, if the output of the 3-bit signal is LLH, Fd / 8 corresponding to the minimum value in the range of Fd / 8 to 2Fd / 8 is output. In this way, the frequency in the range of 0 to Fd can be detected as an 8-stage digital signal.
Although the minimum value in each range is output as the frequency of the input signal here, it is only necessary to divide each stage equally, and the maximum value, intermediate value, etc. may be output.

  Since the operation of the control voltage applied to the delay element units 7a to 7c is the same as that of the first embodiment, the description is omitted. However, when the PLL circuit 3 that outputs the control voltage is locked, the delay amount of the delay element 70a is also increased. Since it is fixed, the output timing of the phase difference pulses output from the phase comparators 8a to 8c is fixed, and the DC voltage smoothed by the LPFs 9a to 9c is constant. Thereby, the comparators 20a to 20c stably output binary values, and the voltage frequency converter 11a can detect the frequency Fsig of the input signal.

According to this embodiment, the frequency detection device 1A includes the delay element units 7a to 7c and the ring oscillator 19 using the delay elements 70a and 70b having the same delay characteristic with respect to the control voltage, thereby enabling the input. Since the value of the DC voltage obtained from the phase difference pulse of the signal is constant, the frequency can be detected from the proportional characteristic of voltage and frequency, and a frequency detection device that can be easily integrated on the semiconductor substrate 2 can be obtained. .
Further, the frequency of the input signal can be digitally detected by combining the delay characteristics of the delay elements 7a to 7c with powers of 2 and combining the proportional characteristics of each voltage and frequency.

Embodiment 3 FIG.
A frequency detection apparatus 1B according to the present embodiment will be described with reference to FIGS. In FIG. 7, the frequency detection device 1B includes a limiter amplifier 5 that converts a signal input from the signal input terminal 4 on the semiconductor substrate 2 into a rectangular wave signal, that is, a signal conversion unit, as in the second embodiment. Buffer amplifiers 6a and 6b that amplify the branched rectangular wave signal, and delay element units 7a to 7d that delay the rectangular wave signal from the buffer amplifier 6a with different delay amounts according to the control voltage, that is, the first and second delay elements 7a to 7d. Phase comparators 8a to 8d constituted by signal delay means and XOR logic gates for comparing the phase differences between the respective delayed rectangular wave signals from the delay element units 7a to 7d and the rectangular wave signal from the buffer amplifier 6b, ie, the first And the second phase comparison means and LPFs 9a to 9d for smoothing the phase difference pulses obtained as a result of the phase comparison to DC voltages, respectively, ie, the first and second The pressure conversion means, the comparators 20a to 20c for comparing the outputs of the LPFs 9a to 9c with respect to whether the output of the reference voltage source 21 applied from the outside is higher or not, that is, the comparison means, and the comparators 20a to 20c The frequency range of the input signal is determined based on the combination of the comparison results and the preset voltage and frequency characteristic data, and the DC voltage from the LPF 9d is digitized by the AD converter 10 and the preset voltage and frequency. The voltage frequency converter 11b that detects the frequency of the input signal from the determined frequency range, that is, frequency detection means, and the output terminal 12 that outputs the detected frequency to the outside of the semiconductor substrate 2 are provided.
The number of delay element units 7a to 7c constituting the first signal delay unit may be one. In this case, the number of the first phase comparison unit, the first voltage conversion unit, and the comparison unit is also the number of delay element units. It consists of a corresponding one.

  The control voltage is feedback-controlled so that the output becomes constant by the PLL circuit 3 including the external reference signal source 14, the phase comparator 15, and the loop filter 16, and the control voltage input terminal 18 provided on the semiconductor substrate 2 is connected to the control voltage. To the delay element portions 7a to 7d. Further, in the middle of the feedback path of the PLL circuit 3, the output of the N-stage ring oscillator 19 whose delay amount is changed by its own control voltage as well as the delay element units 7a to 7d and the loop filter 16 are stably supplied. A delay control voltage source 17 such as a regulator is provided.

  The delay element units 7a to 7d and the ring oscillator 19 are configured by a delay element 70a having the same delay characteristic with respect to the control voltage. Each of the delay element units 7a to 7d includes one or a plurality of delay elements 70a connected in series so that the delay amount is 1 / 2Td, Td, 2Td, 4Td and a power of 2, and the ring oscillator 19 (N-1) delay elements 70a and one delay element 70b having the same delay characteristic and outputting an inverter are connected in a ring shape. The delay element 70b only needs to be able to oscillate the ring oscillator 19, and any number of delay elements 70b may be used as long as it is an odd number. In this case, the total number of delay elements 70a and 70b is adjusted to be N. Further, the delay amount of the delay element units 7a to 7c is not limited to a power of 2, and may be a power of 2 or more integers.

Next, the operation will be described.
The signal input from the input terminal 4 is converted into a rectangular wave signal having the same cycle Tsig as the input signal by the limiter amplifier 5, branched into two, and then amplified by the buffer amplifiers 6a and 6b. The rectangular wave signal amplified by the buffer amplifier 6a is further branched into four and delayed by delay amounts 1 / 2Td, Td, 2Td, and 4Td by the delay element units 7a to 7d, respectively, and a phase comparator as a delayed rectangular wave signal. 8a to 8d.

  On the other hand, the rectangular wave signal amplified by the buffer amplifier 6b is directly transmitted to the phase comparators 8a to 8d. The phase comparators 8a to 8d each output the phase difference between the input delayed rectangular wave signal and rectangular wave signal as a rectangular phase difference pulse signal, and these phase difference pulse signals are respectively smoothed to DC voltages by the LPFs 9a to 9d. It becomes.

  When the DC voltages output from the LPFs 9a to 9d are normalized in the same manner as in the first embodiment, voltage-frequency characteristics as shown in FIG. 8 are obtained. Assuming that the voltage of the reference voltage source 21 applied from the outside is ½ of the normalized voltage as shown by the broken line in the figure, each comparator 20a-20c compares the DC voltage of the LPFs 9a-9c with the voltage of the reference voltage source 21, respectively. And output as a binary value of High / Low.

The comparison results of the comparators 20a to 20c are transmitted to the voltage frequency converter 11b via the output terminal 12 as a 3-bit signal having the output of the comparator 20a as the highest order. At the same time, the DC voltage smoothed by the LPF 9d is digitized by the AD converter 10 and transmitted to the voltage frequency converter 11b.
In the voltage frequency converter 11b, a frequency range based on the voltage and frequency characteristics corresponding to the 3-bit signal from the comparators 20a to 20c is set in advance, and the frequency range of the input signal is set according to the value of the input 3-bit signal. It is determined.

  Voltage and frequency characteristic data are also set in advance in the voltage frequency converter 11b, and when the DC voltage signal digitized by the AD converter 10 is input, the voltage frequency converter 11b detects the direct current from the determined frequency range. The frequency corresponding to the voltage is detected from the characteristic data characteristic as the frequency of the input signal.

  For example, in FIG. 9, when the 3-bit signal from the comparators 20a to 20c is LHH, the frequency range is determined to be 2Fd / 8 to 3Fd / 8. At this time, the voltage frequency converter 11b detects the frequency corresponding to the digitized value of the DC voltage of the LPF 9d from the range of 2Fd / 8 to 3Fd / 8.

  As shown in FIG. 8, the output voltage of the LPF 9d has a periodicity every Fd / 8. The voltage frequency converter 11b detects the input frequency by adding / subtracting the frequency corresponding to the characteristic data to the reference frequency.

  For example, when the frequency range determined by the outputs of the comparators 20a to 20c is mFd / 8 ≦ Fsig <(m + 1) Fd / 8 (where m is an even number greater than or equal to 0), the voltage and the frequency are in a positive proportional relationship. Therefore, as indicated by the addition symbol in FIG. 9, the frequency corresponding to the characteristic data is added to the minimum frequency mFd / 8 in this range and detected as the frequency of the input signal.

On the other hand, when the frequency range is (m + 1) Fd / 8 ≦ Fsig <(m + 2) Fd / 8, the voltage and the frequency are in a negative proportional relationship. Therefore, as shown in the subtraction symbol in FIG. The frequency corresponding to the characteristic data is subtracted from the frequency (m + 2) Fd / 8 and detected as the frequency of the input signal.
Thus, the frequency of the input signal can be detected by adding / subtracting the frequency obtained from the LPF 9 to the characteristic data in accordance with the voltage-frequency characteristics in each frequency range.

  Since the operation of the control voltage applied to the delay element units 7a to 7d is the same as that in the first embodiment, the description thereof will be omitted. Since it is fixed, the output timing of the phase difference pulse output from each phase comparator 8a-8d is fixed, and the DC voltage smoothed by the LPFs 9a-9d is constant. Thereby, the outputs of the comparators 20a to 20c are stabilized, and the voltage frequency converter 11b can determine the frequency range of the input signal. Further, since the value obtained by digitizing the DC voltage of the LPF 9d is also stably output, the voltage frequency converter 11b detects the frequency corresponding to the DC voltage from the LPF 9d in the determined frequency range, and provides detailed frequency information of the input signal. Can be obtained.

According to this embodiment, the frequency detection device 1B includes the delay element units 7a to 7d and the ring oscillator 19 by using the delay elements 70a and 70b having the same delay characteristic with respect to the control voltage, thereby enabling the input. Since the value of the DC voltage obtained from the phase difference pulse of the signal is constant, the frequency can be detected from the proportional characteristic of voltage and frequency, and a frequency detection device that can be easily integrated on the semiconductor substrate 2 can be obtained. .
Further, the frequency range of the input signal is determined by combining the proportional characteristics of each voltage and frequency by setting the delay amounts of the delay element units 7a to 7c to powers of 2, respectively. In this frequency range, the DC voltage of the LPF 9d is changed. Since the frequency corresponding to the digitized value is detected, detailed frequency information of the input signal can be obtained .

DESCRIPTION OF SYMBOLS 1 , 1A , 1B frequency detection apparatus 2 Semiconductor substrate 3 PLL circuit 4 Signal input terminal 5 Limiter amplifier 6a, 6b Buffer amplifier
7,7A～7 d delay element portion 8,8A～8 d phase comparator 9,9a~9 d LPF
10 AD converter 11, 11a, 11b Voltage frequency converter 12 Output terminal
1 4 external reference signal source 15 phase comparator 16 loop filter 17 delay control voltage source 18 the control voltage input terminal 19 ring oscillator 20A～20 c comparator 2 1 Criterion voltage source 70a, 70b delay element

Claims (3)

A frequency detection device integrated on a semiconductor substrate,
A delay control voltage source that supplies a control voltage; and a ring oscillator that includes a delay element that changes a delay amount based on the control voltage and that changes a delay amount based on the control voltage of the delay control voltage source. A PLL circuit that keeps the output of the control voltage of the delay control voltage source constant;
Signal converting means for converting the input signal into a rectangular wave signal;
On the semiconductor substrate, the control circuit includes a plurality of delay units having different delay amounts configured from delay elements having the same delay characteristics as the delay elements of the ring oscillator with respect to the control voltage. Signal delay means for delaying each based on
Phase comparison means for comparing the phase of the rectangular wave signal and the phase of each of a plurality of delayed rectangular wave signals delayed by the signal delay means;
Voltage conversion means for converting the comparison result of the phase comparison means into a DC voltage;
Comparison means for comparing the DC voltage with a predetermined voltage set in advance,
Frequency detecting apparatus according to claim Rukoto a frequency detection means for detecting the frequency of the input signal based on the characteristics of voltage and frequency set combination and advance of the comparison result by the comparison means. A frequency detection device integrated on a semiconductor substrate,
A delay control voltage source that supplies a control voltage; and a ring oscillator that includes a delay element that changes a delay amount based on the control voltage and that changes a delay amount based on the control voltage of the delay control voltage source. A PLL circuit that keeps the output of the control voltage constant;
Signal converting means for converting the input signal into a rectangular wave signal;
A first signal delay unit configured to delay the rectangular wave signal based on the control voltage, the delay element having delay characteristics having the same delay characteristics as the delay element of the ring oscillator with respect to the control voltage on the semiconductor substrate; ,
First phase comparison means for comparing phases of the rectangular wave signal and the delayed rectangular wave signal delayed by the first signal delay means;
First voltage conversion means for converting the comparison result of the first phase comparison means into a DC voltage;
A comparing means for comparing the DC voltage with a predetermined voltage set in advance;
A delay element having the same delay characteristics as the delay element of the ring oscillator with respect to the control voltage, having a delay amount larger than that of the first signal delay means, and delaying the rectangular wave signal; Signal delay means,
Second phase comparison means for comparing the phases of the rectangular wave signal and the delayed rectangular wave signal delayed by the second signal delay means;
Second voltage conversion means for converting the comparison result of the second phase comparison means into a DC voltage;
The frequency range of the input signal is determined based on the comparison result by the comparison means and the characteristics of the preset voltage and frequency, and the DC voltage converted by the second voltage conversion means and the preset voltage and frequency are determined. based on the characteristics, the frequency detection apparatus according to claim Rukoto a frequency detection means for detecting the frequency of the input signal from the frequency range.   The first signal delay unit includes a plurality of delay units whose delay amounts are different by a power, and the first phase comparison unit, the first voltage conversion unit, and the comparison unit each include the plurality of delay units. The frequency detection device according to claim 2, wherein a plurality of delay units are provided corresponding to the number of delay units.

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