JP5780363B2 - Composite interconnect technology - Google Patents

Description

  This disclosure relates generally to integrated circuit packaging.

  Integrated circuit (IC) packaging can be considered the final step in the manufacture of semiconductor devices. In this step of the manufacturing process, an IC chip is mounted on a substrate to form an IC package. Examples of different types of IC packages include dual in-line packages (DIP), pin grid array (PGA) packages, leadless chip carrier (LCC) packages, surface mount packages, small outline integrated circuit (SOIC) packages, plastic leads Includes chip carrier (PLCC) package, plastic quad flat pack (PQFP) package, thin small outline package (TSOP), and ball grid array (BGA) package. In a flip chip ball grid array (FCBGA) package, the chip is turned upside down and bonded to a BGA substrate.

  The disclosed embodiments provide composite interconnect technology.

  In one aspect, an interconnect structure between an integrated circuit (IC) chip and a substrate comprises a plurality of materials.

It is a figure which shows an example of the IC package in junction temperature. It is a figure which shows an example of IC package after cooling. It is a figure which shows an example of pillar type packaging. It is a figure which shows the example of an interconnect structure. FIG. 3 illustrates an example of a method for constructing an interconnect structure having two different materials. FIG. 3 illustrates an example of an interconnect structure having two different materials. FIG. 3 illustrates an example of an interconnect structure having two different materials. It is a figure which shows an example of a computer system.

  At the stage of integrated circuit (IC) packaging, IC chips are mounted on a substrate using a variety of suitable mounting techniques to form an IC package. FIG. 1 shows an IC package 100 according to an example, and the IC package 100 has an IC chip 110 mounted on a substrate 120. IC chip 110 may be constructed of silicon and substrate 120 may be constructed of ceramic or plastic. In certain embodiments, the IC chip 110 can be soldered onto the substrate 120, and the solder material can be tin-lead, tin-silver, and so on.

  Certain materials have various properties including coefficient of thermal expansion and Young's modulus. Thermal expansion is a property of a substance that changes in volume in response to temperature changes. For example, certain materials may expand when heated and contract when cooled. The amount of thermal expansion of each material can be measured by its coefficient of thermal expansion (CTE). The coefficient of thermal expansion is defined as the degree of material expansion divided by the temperature change. When a force is applied to a solid object, the object can undergo stress. Stress can be measured as the ratio between the applied force and the cross-sectional area of the object. The deformation of a solid due to stress is distortion. The stress and strain experienced by a solid object can be expressed using a stress-strain curve. In solid mechanics, the slope of the stress-strain curve at any point is called the tangent coefficient. The tangential coefficient of the first linear part of the stress-strain curve is called Young's modulus (this name comes from Thomas Young, a 19th century British scientist). Young's modulus, also known as the tensile modulus, is defined as the ratio of uniaxial stress to uniaxial strain in the stress range where Hooke's law is valid.

  Different materials have different CTEs. Similarly, objects made of different materials have different tangent coefficients and thus different stress-strain curves. For example, in FIG. 1, since silicon has a relatively low CTE, IC chip 110 expands only slightly when heated (eg, during the soldering process). On the other hand, plastic has a relatively high CTE, so that the substrate 120 expands even more when heated. Therefore, when the IC chip 110 and the substrate are cooled together, the IC chip 110 contracts slightly than the substrate 120, as shown in FIG. This creates a thermomechanical stress in the IC package 100. The thermomechanical stress gradually increases as the IC chip 110 is cooled from the bonding temperature (eg, during bonding) from room temperature to room temperature.

  One type of flip chip technology IC packaging is pillar packaging as illustrated in FIG. With pillar packaging, a number of interconnect structures 130, also referred to as pillars, may be formed on the IC chip 110 in certain embodiments. The other end of each interconnect structure 130 is soldered to the substrate 120. Alternatively, in certain embodiments, multiple interconnect structures 130 may be formed on the substrate 120 and the other end of each interconnect structure 130 may be soldered to the IC chip 110.

  In certain embodiments, each interconnect structure 130 is constructed of a single material, such as copper. Since copper does not collapse into a spherical shape during bonding, packaging with copper pillars is advantageous at fine pitches. However, copper has a much higher tangent coefficient than typical solder materials, such as tin-silver, so packaging with copper pillars has higher thermomechanical stress than packaging with conventional solder bumps. It tends to induce.

  Certain embodiments construct each interconnect structure between the IC chip and the substrate using multiple materials instead of a single material. Such an interconnect structure may be referred to as a composite (hybrid) interconnect structure. Any number of different materials may be used to construct the interconnect structure. Certain embodiments may select a plurality of different materials to complement each other with respect to their properties and properties, such as CTE and tangent coefficient. For example, if the interconnect structure is constructed of two different materials, one material may have a relatively high CTE while the other material has a relatively low CTE, or one material may be compared The other material may have a relatively low rigidity while having a relatively high rigidity. The combination of multiple materials can help reduce the thermomechanical stress of the IC chip. Certain embodiments may reduce thermomechanical stress by optimizing the spatial location of the multiple materials used.

  FIG. 4 shows an example of an interconnect structure constructed with different materials. The interconnect structure 410 is constructed of a single material, such as copper (eg, formed by electroplating). The interconnect structure 420 is constructed of two different materials, for example, copper as the first material and gold as the second material, a copper-tin alloy, or a tin-silver alloy (eg, formed by electroplating). Yes. Interconnect structure 430 is constructed of three different materials. Interconnect structure 440 is constructed of four different materials. It should be noted that different amounts of different materials may be present within a single interconnect structure.

  FIG. 5 shows an example of a method for constructing an interconnect structure using two different materials. FIG. 5 only illustrates the case with two materials, and this process is also applicable when building an interconnect structure with more than two materials. FIG. 6 is used to help explain the steps shown in FIG. 5 and shows an example interconnect structure 600.

  For a given interconnect structure, certain embodiments may divide the interconnect structure into n sections as shown in step 501. The n sections may or may not have the same thickness. In certain embodiments, n is a number greater than 1 and may be selected based on experimentation. If n is excessive (eg, greater than 100), this process may require a long computation time. If n is too small (eg, 4 or less), the final result may be unsatisfactory. In certain embodiments, n is a number divisible by 2 (eg, 6, 8, 10,...). In certain embodiments, the greater the number of materials used to construct the interconnect structure, the greater n is preferred. Based on experiments, for two materials, a number between 10 and 20 (eg, 12) can be a good choice for n. For illustrative purposes, the interconnect structure 600 is divided into eight sections, as shown in FIG. 6A.

  Certain embodiments may assign a first material (eg, copper) to all n sections of the interconnect structure, as shown in step 503. For interconnect structure 600, all eight sections are assigned the same first material (FIG. 6A). A particular embodiment then has a current stress level corresponding to this interconnect structure (ie, a stress level corresponding to an interconnect structure that has all n sections assigned the same first material), as shown in step 503. Can be recorded. In some examples, the recorded stress level is at a location where crushing can occur (eg, an integrated circuit on the chip, or the pillar itself).

  For each of the n sections having the first material, a particular embodiment assigns a second material to the section, one section at a time, as shown in step 505, and has the current structure. A stress level corresponding to the structure can be determined. For interconnect structure 600, at this point (FIG. 6A), all eight sections have the first material. First, only the section 1 is replaced with the second material, and the sections 2-8 still have the first material, and the stress level corresponding to the interconnect structure 600 in this configuration is determined. Second, only section 2 is replaced with the second material, and sections 1 and 3-8 still have the first material, and the stress level corresponding to this configuration of interconnect structure 600 is determined. Third, only the section 3 is replaced with the second material, and the sections 1-2 and 4-8 still have the first material so that the stress level corresponding to the interconnect structure 600 of this configuration is determined. . Continuing similarly, finally, only the section 8 is replaced with the second material, and the sections 1-7 still have the first material, and the stress level corresponding to the interconnect structure 600 of this configuration is determined. . There are 8 different configurations, so 8 different stress levels are determined.

  Certain embodiments, as shown in step 507, may determine the section that gives the interconnect structure the lowest stress level in the above case of step 5 when assigned a second material. In other words, the configuration having the lowest stress level in the above case of step 505 is determined. For example, for interconnect structure 600, of the eight configurations described above, the configuration in which section 3 has the second material and sections 1-2 and 4-8 have the first material (FIG. 6B) is the lowest. Assume that a stress level of

  Certain embodiments compare this current lowest stress level to a previously recorded stress level, as shown in step 509, such that the current lowest stress level is greater than the previously recorded stress level. It can be determined whether it is low. For interconnect structure 600, the stress level corresponding to the configuration in which section 3 has the second material and sections 1-2 and 4-8 have the first material (ie, the lowest stress level at present, FIG. 6B). ) Is compared to the stress level corresponding to the configuration in which all eight sections have the first material (ie, the previously recorded stress level, FIG. 6A).

  If the current lowest stress level is lower than the previously recorded stress level (“YES” in step 509), the particular embodiment is the section corresponding to the current lowest stress level, as shown in step 511. Can be changed to the second material and the lowest stress level can be recorded at this time. For interconnect structure 600, the stress level corresponding to the configuration in which section 3 has the second material and sections 1-2 and 4-8 have the first material (FIG. 6B) has a stress level of all eight sections. Assume that the stress level is below that corresponding to the configuration with one material (FIG. 6A). Section 3 is changed to the second material (FIG. 6B) and the stress level corresponding to this configuration is recorded.

  Certain embodiments may repeat steps 505, 507, 509 and 511 in another iteration. For interconnect structure 600, at the beginning of the second iteration, section 3 already has the second material and sections 1-2 and 4-8 still have the first material (FIG. 6B) The stress level corresponding to this configuration is recorded. At this point, seven sections still have the first material. Each section still having the first material is assigned a second material, one section at a time, and the stress level corresponding to each configuration is determined (step 505). First of all, replace only section 1 with the second material and sections 2 and 4-8 still have the first material (section 3 already has the second material) A stress level corresponding to the interconnect structure 600 of the configuration is determined. Second, replace only section 2 with the second material and sections 1 and 4-8 still have the first material (section 3 already has the second material). The stress level corresponding to the interconnect structure 600 is determined. Third, replace only section 4 with the second material so that sections 1-2 and 5-8 still have the first material (section 3 already has the second material) A stress level corresponding to the interconnect structure 600 of this configuration is determined. And continue as well. In this second iteration, seven sections (ie, sections 1-2 and 4-8) have the first material, so there are seven different configurations and seven corresponding stress levels. Exists. Among these seven configurations, the configuration having the lowest stress level at present is determined (step 507). Assume that the configuration in which sections 3 and 7 have a second material and sections 1-2, 4-6 and 8 have a first material (FIG. 6C) gives the lowest stress level at the present time. This current lowest stress level is the previously recorded stress level (i.e., configuration where section 3 has the second material and sections 1-2 and 4-8 have the first material (Figure 6B)). (Step 509).

  For interconnect structure 600, there is currently the lowest stress level corresponding to the configuration in which sections 3 and 7 have a second material and sections 1-2, 4-6 and 8 have a first material (FIG. 6C). Assume that section 3 has a second material and sections 1-2 and 4-8 are below the previously recorded stress level corresponding to the configuration having the first material (FIG. 6B). Here, section 7 is changed to the second material (FIG. 6C) and the stress level corresponding to this configuration is recorded (step 511).

  Once again, steps 505, 507, 509 and 511 may be repeated. For interconnect structure 600, at the beginning of the third iteration, sections 3 and 7 already have the second material and sections 1-2, 4-6 and 8 still have the first material ( FIG. 6C), the stress level corresponding to this configuration is recorded. At this point, the six sections still have the first material. Each section still having the first material is assigned a second material, one section at a time, and the stress level corresponding to each configuration is determined (step 505). First, replace only section 1 with the second material, so that sections 2, 4-6 and 8 still have the first material (sections 3 and 7 already have the second material. The stress level corresponding to the interconnect structure 600 of this configuration is determined. Second, replace only section 2 with the second material, so that sections 1, 4-6 and 8 still have the first material (sections 3 and 7 already have the second material) ), The stress level corresponding to the interconnect structure 600 of this configuration is determined. Third, replace only section 4 with the second material, so that sections 1-2, 5-6 and 8 still have the first material (sections 3 and 7 already have the second material) The stress level corresponding to the interconnect structure 600 of this configuration is determined. And continue as well. In this third iteration, six sections (ie, sections 1-2, 4-6 and 8) have the first material, thus six different configurations and six corresponding stresses. There is a level. Among these six configurations, the configuration having the lowest stress level at present is determined (step 507). Assume that the configuration in which sections 3 and 7-8 have a second material and sections 1-2 and 4-6 have a first material (FIG. 6D) currently gives the lowest stress level. This current lowest stress level is the previously recorded stress level (ie, sections 3 and 7 have the second material and sections 1-2, 4-6 and 8 have the first material. (Stress level corresponding to FIG. 6C) (step 509).

  For interconnect structure 600, the current lowest stress level corresponding to the configuration in which sections 3 and 7-8 have the second material and sections 1-2 and 4-6 have the first material (FIG. 6D) Assume that sections 3 and 7 have a second material and sections 1-2, 4-6 and 8 are below the previously recorded stress level corresponding to the configuration having the first material (FIG. 6C). To do. Here, section 8 is changed to the second material (FIG. 6D) and the stress level corresponding to this configuration is recorded (step 511).

  Once again, steps 505, 507, 509 and 511 may be repeated. For interconnect structure 600, at the beginning of the fourth iteration, sections 3 and 7-8 already have the second material and sections 1-2 and 4-6 still have the first material ( FIG. 6D), the stress level corresponding to this configuration is recorded. At this point, the five sections still have the first material. Each section still having the first material is assigned a second material, one section at a time, and the stress level corresponding to each configuration is determined (step 505). First, replace only section 1 with the second material, so that sections 2 and 4-6 still have the first material (sections 3 and 7-8 already have the second material. The stress level corresponding to the interconnect structure 600 of this configuration is determined. Second, replace only section 2 with the second material, so that sections 1 and 4-6 still have the first material (sections 3 and 7-8 already have the second material) ), The stress level corresponding to the interconnect structure 600 of this configuration is determined. Third, replace only section 4 with the second material, so sections 1-2 and 5-6 still have the first material (sections 3 and 7-8 already have the second material) The stress level corresponding to the interconnect structure 600 of this configuration is determined. And continue as well. In this fourth iteration, five sections (ie, sections 1-2 and 4-6) have the first material, so there are five different configurations and five corresponding stress levels. Exists. Among these five configurations, the configuration having the lowest stress level at present is determined (step 507). Assume that configurations in which sections 3-4 and 7-8 have a second material and sections 1-2 and 5-6 have a first material give the lowest stress level at the present time. This current lowest stress level is the previously recorded stress level (ie, sections 3 and 7-8 have the second material and sections 1-2 and 4-6 have the first material). (Stress level corresponding to FIG. 6D) (step 509).

  For interconnect structure 600, the current lowest stress level corresponding to a configuration in which sections 3-4 and 7-8 have a second material and sections 1-2 and 5-6 have a first material is If 3 and 7-8 have a second material and sections 1-2 and 4-6 are higher than or equal to the previously recorded stress level corresponding to the configuration having the first material (FIG. 6D) Assume. In certain embodiments, the iterative process ends (“NO” at step 509). Note that section 4 is not changed to the second material. This is because doing so does not help reduce the stress level corresponding to the interconnect structure 600.

  Note that in each iteration, the number of sections having the first material at the present time is always n or less. That is, if each section currently has m sections having the first material, m ≦ n.

  In certain embodiments, upon completion of the iterative process (steps 505, 507, 509, 511), all of the n sections of the interconnect structure still have the same first material, as shown in step 513. You can verify that you are doing. If so (“YES” in step 513), this means that an interconnect structure having only the first material (eg, FIG. 6A) provides the lowest stress level. In that case, a particular embodiment may finalize the interconnect structure such that it is constructed with only the first material (ie, there is no combination of materials), as shown in step 515. In the opposite case (“NO” at step 513), certain embodiments determine whether there is a section with the first material adjacent to the section with the second material, as shown in step 517. . If so (“YES” at step 517), certain embodiments may further test each such section, as shown at step 519.

  In certain embodiments, a larger number of sections may yield better results. However, a larger number of sections often requires longer computation times. Thus, certain embodiments may further test a section still having the first material adjacent to the section having the second material to ensure the quality of the final result, particularly when n is relatively small.

  For interconnect structure 600, at the end of the iterative process, sections 3 and 7-8 have a second material and sections 1-2 and 4-6 have a first material (FIG. 6D) The stress level corresponding to this configuration is recorded. In this case, not all eight sections still have the first material. Further, sections 2 and 4 having a first material are adjacent to section 3 having a second material. Also, section 6 that has the first material is adjacent to section 7 that has the second material. Therefore, each of sections 2, 4 and 6 needs to be tested.

  First, consider sections 2 and 4 adjacent to section 3. To test sections 2 and 4 independently for section 3, section 3 is returned to the first material (FIG. 6E). Section 2 is assigned a second material (FIG. 6F) and the stress level corresponding to this configuration is determined. Section 2 is then returned to the first material, and the second material is assigned to section 4 (FIG. 6G), and the stress level corresponding to this configuration is determined. The three stress levels of each of the three configurations of FIGS. 6D, 6F, and 6G are compared to each other, and the configuration having the lowest stress level among these three is selected and the corresponding stress level is recorded.

  Second, consider section 6 adjacent to section 7. To test section 6 independently with respect to section 7, section 7 is returned to the first material (FIG. 6H). Section 6 is assigned a second material (FIG. 6I) and the stress level corresponding to this configuration is determined. This stress level is compared to the stress level corresponding to the configuration of FIG. 6D, the configuration having the lower stress level is selected, and the corresponding stress level is recorded.

  For interconnect structure 600, the effect of step 519 is that the four stress levels of the four configurations shown in FIGS. 6D, 6F, 6G, and 6I, respectively, are compared to each other, and the configuration with the lowest stress level among these four is Is to be selected. This configuration is the final result of the interconnect structure 600.

  For different interconnect structures, the process shown in FIG. 5 can result in different configurations of the two materials. Some examples of the structure of an interconnect structure constructed using two materials are shown in FIG. Note that there may be different amounts of two materials within one interconnect structure, and the two materials may be alternated in multiple sections of the interconnect structure.

  Particular embodiments may be implemented on one or more computer systems. In certain embodiments, the process illustrated in FIG. 5 may be implemented as a computer program stored on a non-transitory computer readable medium and executed on a computer system. FIG. 8 illustrates an example computer system 800. In certain embodiments, one or more computer systems 800 perform one or more steps of one or more methods described or illustrated herein. In certain embodiments, one or more computer systems 800 provide the functionality described or illustrated herein. In certain embodiments, software that is run on one or more computer systems 800 performs, or is described or illustrated in, one or more steps of one or more methods described or illustrated herein. Provide functionality. Particular embodiments include one or more portions of one or more computer systems 800.

  This disclosure contemplates any suitable number of computer systems 800. This disclosure contemplates computer system 800 taking any physical form. By way of a non-limiting example, the computer system 800 may be an embedded computer system, system on chip (SOC), single board computer system (SBC) (eg, computer on module (COM) or system on Module (SOM), desktop computer system, laptop or notebook computer system, interactive kiosk terminal, mainframe, mesh computer system, mobile phone, personal digital assistant (PDA), server, or these Or a combination of two or more. As required, the computer system 800 can be single or distributed; span multiple locations; span multiple machines; or in the cloud (which can include one or more cloud elements in one or more networks) One or more computer systems 800 may be included. If desired, one or more computer systems 800 may perform one or more steps of one or more methods described or illustrated herein without substantial spatial or temporal constraints. As a non-limiting example, one or more computer systems 800 may perform one or more steps of one or more methods described or illustrated herein in real time or batch mode. If desired, one or more computer systems 800 may perform one or more steps of one or more methods described or illustrated herein at different times or at different locations.

  In certain embodiments, computer system 800 includes a processor 802, memory 804, storage 806, input / output (I / O) interface 808, communication interface 810, and bus 812. Although this disclosure illustrates and describes a particular computer system having a particular number of particular components in a particular configuration, this disclosure does not imply any preferred number of any preferred configurations in any preferred arrangement. Any suitable computer system having elements is contemplated.

  In particular embodiments, processor 802 includes hardware that executes instructions, such as instructions for building a computer program, for example. As a non-limiting example, to execute an instruction, processor 802 retrieves (ie, fetches) an instruction from an internal register, internal cache, memory 804, or storage 806; decrypts and executes it; One or more results may be written to an internal register, internal cache, memory 804, or storage 806. In certain embodiments, processor 802 may include one or more internal caches for data, instructions or addresses. This disclosure contemplates that processor 802 may include any suitable number of any suitable internal cache as required. By way of a non-limiting example, the processor 802 can include one or more instruction caches, one or more data caches, and one or more translation lookaside buffers (TLBs). The instructions in the instruction cache may be a copy of the instructions in memory 804 or storage 806, and the instruction cache may speed up the retrieval of these instructions by processor 802. Data in the data cache is a copy of data in memory 804 or storage 806 to be processed by instructions being executed by processor 802; for access by subsequent instructions executed by processor 802, or memory May be the result of a previous instruction executed by processor 802 to write to 804 or storage 806; or other suitable data. The data cache can speed up the reading process or the writing process by the processor 802. The TLB may speed up virtual address translation for the processor 802. In certain embodiments, processor 802 may include one or more internal registers for data, instructions or addresses. This disclosure contemplates that processor 802 may include any suitable number of any suitable internal registers as appropriate. If desired, processor 802 may include one or more arithmetic logic units (ALUs); may be a multi-core processor; or may include one or more processors 802. Although this disclosure illustrates and describes a particular processor, this disclosure contemplates any suitable processor.

  In particular embodiments, memory 804 includes main memory that stores instructions executed by processor 802 or data processed by processor 802. As a non-limiting example, computer system 800 may load instructions into memory 804 from storage 806 or another source (eg, another computer system 800, etc.). Thereafter, processor 802 may load instructions from memory 804 into an internal register or internal cache. In order to execute the instruction, the processor 802 retrieves the instruction from the internal register or the internal cache, and decodes the retrieved instruction. During or after execution of the instruction, processor 802 may write one or more results (which may be intermediate or final results) to an internal register or internal cache. Processor 802 can then write one or more of those results to memory 804. In certain embodiments, processor 802 may only execute instructions in one or more internal registers or internal caches or memory 804 (unlike executing instructions in storage 806 or elsewhere) Also, only data in one or more internal registers or internal caches or memory 804 may be processed (unlike processing data in storage 806 or elsewhere). One or more memory buses 812 (each of which may include an address bus and a data bus) may couple processor 802 to memory 804. Bus 812 may include one or more memory buses, as described below. In certain embodiments, one or more memory management units (MMUs) may exist between the processor 802 and the memory 804 to facilitate access to the memory 804 required by the processor 802. In certain embodiments, memory 804 includes random access memory (RAM). This RAM may be volatile memory if appropriate. If desired, the RAM can be dynamic RAM (DRAM) or static RAM (SRAM). Also, if necessary, this RAM can be a single-port or multi-port RAM. This disclosure contemplates any suitable RAM. Memory 804 may include one or more memories 804 as desired. Although this disclosure illustrates and describes a particular memory, this disclosure contemplates any suitable memory.

  In certain embodiments, storage 806 includes mass storage for data or instructions. As a non-limiting example, the storage 806 may be an HDD, floppy disk drive, flash memory, optical disk, magnetic optical disk, magnetic tape, or universal serial bus (USB) drive, or two or more of these. Combinations can be included. Storage 806 may include removable (removable) or non-removable (ie, fixed) media as required. The storage 806 may be internal or external to the computer system 800 as necessary. In certain embodiments, storage 806 is non-volatile solid state memory. In certain embodiments, the storage 806 includes read only memory (ROM). As required, this ROM may be a mask programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically erasable rewritable ROM (EAROM), or It may be flash memory or a combination of two or more of these. This disclosure contemplates mass storage device 806 having any suitable physical form. Storage 806 may include one or more storage controllers that facilitate communication between processor 802 and storage 806, as appropriate. The storage 806 may include one or more storages 806 as needed. Although this disclosure illustrates and describes a particular storage, this disclosure contemplates any suitable storage.

  In certain embodiments, the I / O interface 808 is hardware, software, or both that provides one or more interfaces for communication between the computer system 800 and one or more I / O devices. including. Computer system 800 may include one or more of these I / O devices, where appropriate. One or more of these I / O devices may allow communication between an individual and computer system 800. As a non-limiting example, the I / O device may be a keyboard, keypad, microphone, monitor, mouse, printer, scanner, speaker, still camera, stylus pen, tablet, touch screen, trackball, video camera, or other suitable Such I / O devices, or a combination of two or more thereof. The I / O device may include one or more sensors. This disclosure contemplates any suitable I / O device and any suitable I / O interface 808 for it. If desired, the I / O interface 808 may include one or more devices or software drivers that allow the processor 802 to drive one or more of these I / O devices. The I / O interface 808 may include one or more interfaces 808 as desired. Although this disclosure illustrates and describes a particular I / O interface, this disclosure contemplates any suitable I / O interface.

  In certain embodiments, the communication interface 810 is one for communication (eg, packet-based communication, etc.) between the computer system 800 and one or more other computer systems or one or more networks. It includes hardware, software, or both that provide the above interfaces. As a non-limiting example, the communication interface 810 is a network interface controller (NIC) or network adapter for communicating with an Ethernet or other wire-based network, or a wireless network such as a Wi-Fi network, for example. A wireless NIC (WNIC) or wireless adapter for communication may be included. This disclosure contemplates any suitable network and any suitable communication interface 810 for it. As a non-limiting example, computer system 800 can include one or more of an ad hoc network, a personal area network (PAN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or the Internet. It may communicate with a portion, or a combination of two or more of these. One or more portions of one or more of these networks may be wired or wireless. As an example, the computer system 800 includes a wireless PAN (WPAN) (eg, Bluetooth® WPAN, etc.), a Wi-Fi network, a Wi-MAX network, a mobile phone network (eg, Global System for Mobile Communications). (Such as a GSM network), or other suitable wireless network, or a combination of two or more thereof. Computer system 800 may include any suitable communication interface 810 for any of these networks, where appropriate. Although this disclosure illustrates and describes a particular communication interface, this disclosure contemplates any suitable communication interface.

  In particular embodiments, bus 812 includes hardware, software, or both, for coupling components of computer system 800 to each other. As a non-limiting example, the bus 812 may be an accelerated graphics port (AGP) or other graphics-only bus, an EISA (Extended Industry Standard Architecture) bus, a front side bus (FSB), a hyper transport (HT). Interconnect, industry standard architecture (ISA) bus, InfiniBand interconnect, LPC (low-pin-count) bus, memory bus, micro channel architecture (MCA) bus, extended bus architecture (PCI) bus for computers, PCI Express (PCI-X) bus, serial ATA (SATA) bus, VLB (Video Electronics Standards Association local) bus, or other suitable bus, or a combination of two or more thereof. Bus 812 may include one or more buses 812 as desired. Although this disclosure illustrates and describes a particular bus, this disclosure contemplates any suitable bus or interconnect.

  Here, reference to a computer-readable storage medium includes one or more non-transitory tangible computer-readable storage medium holding structures. As a non-limiting example, a computer readable storage medium may be a semiconductor-based or other integrated circuit (IC), such as a field programmable gate array (FPGA), or an application specific IC (ASIC), as appropriate. ), Etc.), hard disk, HDD, hybrid hard drive (HHD), optical disk, optical disk drive (ODD), magnetic optical disk, magnetic optical drive, floppy disk, floppy disk drive (FDD), magnetic tape, holographic Storage medium, solid state drive (SSD), RAM drive, secure digital (SD) card, secure digital drive, or other suitable computer readable storage medium, or a combination of two or more thereof It may include. The computer-readable non-transitory storage medium can be volatile, non-volatile, or a combination of volatile and non-volatile, as appropriate.

  This disclosure contemplates one or more computer readable storage media that implement any suitable storage. In certain embodiments, the computer-readable storage medium may optionally include one or more portions of processor 802 (eg, one or more internal registers or caches), one or more portions of memory 804, storage, and the like. One or more portions of 806, or combinations thereof, may be implemented. In certain embodiments, the computer readable storage medium implements RAM or ROM. In certain embodiments, the computer readable storage medium implements volatile or permanent memory. In certain embodiments, one or more computer readable storage media embody software. Here, reference to software may refer to one or more applications, bytecodes, one or more computer programs, one or more executables, one or more instructions, logic, machine language, one or more scripts, Or it includes source code and vice versa. In certain embodiments, the software includes one or more application programming interfaces (APIs). This disclosure contemplates any suitable software written or otherwise expressed in any suitable programming language or combination of programming languages. In particular embodiments, software may be expressed as source code or object code. In certain embodiments, the software is expressed in a higher level (high level) programming language, such as C, Perl, or a suitable extension thereof. In certain embodiments, the software is expressed in a lower level programming language such as assembly language (or machine language). In certain embodiments, the software is expressed in JAVA, C, or C ++. In certain embodiments, the software is expressed in Hypertext Markup Language (HTML), Extensible Markup Language (XML), or other suitable markup language.

  As used herein, “or” is compatible and not exclusive unless otherwise indicated explicitly or contextually. Thus, “A or B” means “A, B, or both” unless otherwise explicitly or contextually indicated. Also, “and” are both combined and both, unless explicitly stated otherwise or contextually. Thus, herein, “A and B” means “coupled or individually A and B” unless otherwise explicitly or contextually indicated.

  This disclosure is intended to cover all modifications, substitutions, variations, modifications and improvements to the embodiments illustrated herein that would be understood by one of ordinary skill in the art. Similarly, the appended claims are intended to cover all modifications, substitutions, variations, modifications and improvements as appropriate to those skilled in the art to the embodiments illustrated herein as appropriate. Also in the claims to a device or system or component thereof adapted, configured, enabled, configured, enabled, enabled or operating to perform a particular function Reference to the device, system or component is activated, turned on, or turned on as long as the device, system or component is so adapted, configured, enabled, configured, enabled, enabled or operated, or It is intended to encompass the device, system or component whether released or not.

Claims (13)

Having one or more interconnect structures between an integrated circuit (IC) chip and a substrate, each interconnect structure having a plurality of materials;
Building each interconnect structure
Dividing the interconnect structure into n sections;
Providing a first material for all of the n sections;
Recording the current stress level corresponding to the interconnect structure;
Until the lowest selected stress level is greater than or equal to the recorded stress level:
For each of the m sections currently having the first material, where m ≦ n,
Assign a second material to the section and determine a current stress level corresponding to the interconnect structure;
From the determined m stress levels, select the lowest stress level,
If the lowest selected stress level is lower than the recorded stress level,
Applying the second material to a section of the m sections corresponding to the selected lowest stress level, and recording the selected lowest stress level;
Repeating that,
Having
METHODS. The method of claim 1 , wherein n is 10 or more. Building each interconnect structure further includes when at least one of the n sections has the second material:
For each pair of adjacent first section having the first material and second section having the second material,
Assigning the second material to the first section;
Assigning the first material to the second section;
Determining a current stress level corresponding to the interconnect structure, and if the determined current stress level is lower than the recorded stress level;
Providing the first section with the second material;
Applying the first material to the second section and recording the determined current stress level;
The method of claim 1 , comprising: The one or more interconnect structures are formed on the IC chip, and the IC chip is connected to the substrate by soldering one end of each interconnect structure to the substrate;
The method of claim 1. The one or more interconnect structures are formed on the substrate, and the IC chip is connected to the substrate by soldering one end of each interconnect structure to the IC chip;
The method of claim 1.   The method of claim 1, wherein each interconnect structure has one or more first sections of copper and one or more second sections of tin-silver. A computer readable storage medium having software stored therein, wherein the software builds one or more interconnect structures between an integrated circuit (IC) chip and a substrate when executed by one or more computer systems. Act to
Each interconnect structure has multiple materials,
Building each interconnect structure
Dividing the interconnect structure into n sections;
Providing a first material for all of the n sections;
Recording the current stress level corresponding to the interconnect structure;
Until the lowest selected stress level is greater than or equal to the recorded stress level:
For each of the m sections currently having the first material, where m ≦ n,
Assign a second material to the section and determine a current stress level corresponding to the interconnect structure;
From the determined m stress levels, select the lowest stress level,
If the lowest selected stress level is lower than the recorded stress level,
Applying the second material to a section of the m sections corresponding to the selected lowest stress level, and recording the selected lowest stress level;
Repeating that,
Having
Serial憶媒body. The storage medium according to claim 7 , wherein n is 10 or more. Building each interconnect structure further includes when at least one of the n sections has the second material:
For each pair of adjacent first section having the first material and second section having the second material,
Assigning the second material to the first section;
Assigning the first material to the second section;
Determining a current stress level corresponding to the interconnect structure, and if the determined current stress level is lower than the recorded stress level;
Providing the first section with the second material;
Applying the first material to the second section and recording the determined current stress level;
The storage medium according to claim 7 . The one or more interconnect structures are formed on the IC chip, and the IC chip is connected to the substrate by soldering one end of each interconnect structure to the substrate;
The storage medium according to claim 7 . The one or more interconnect structures are formed on the substrate, and the IC chip is connected to the substrate by soldering one end of each interconnect structure to the IC chip;
The storage medium according to claim 7 . The storage medium of claim 7 , wherein each interconnect structure has one or more first sections of copper and one or more second sections of tin-silver. A system for have a means for constructing one or more interconnect structure between the integrated circuit (IC) chip and the substrate,
Each interconnect structure have a plurality of materials,
The means for constructing includes a computer readable storage medium having software stored thereon, the software between the integrated circuit (IC) chip and the substrate when executed by one or more computer systems. Acts to build one or more interconnect structures,
Building each interconnect structure
Dividing the interconnect structure into n sections;
Providing a first material for all of the n sections;
Recording the current stress level corresponding to the interconnect structure;
Until the lowest selected stress level is greater than or equal to the recorded stress level:
For each of the m sections currently having the first material, where m ≦ n,
Assign a second material to the section, and
Determining a current stress level corresponding to the interconnect structure;
From the determined m stress levels, select the lowest stress level,
If the lowest selected stress level is lower than the recorded stress level,
Providing the second material to a section of the m sections corresponding to the selected lowest stress level; and
Record the selected minimum stress level;
Repeating that,
Having
system.

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