JP5779871B2 - Magnetoresistive element, semiconductor memory, and method of manufacturing magnetoresistive element - Google Patents

Description

  The present invention relates to a magnetoresistive element and a semiconductor memory.

  An MRAM (Magnetoresistive Random Access Memory) is known as a semiconductor memory having memory cells that store logic according to a resistance value. A ferromagnetic tunnel junction (MTJ) element used as a memory element of an MRAM has two ferromagnetic layers (a fixed layer and a free layer) stacked via a tunnel insulating film. For example, in order to reduce a write current required when information is stored in a ferromagnetic tunnel junction element, it has been proposed to include Ta in the free layer (see, for example, Patent Document 1).

A ferromagnetic tunnel junction element is formed by etching a fixed layer, a tunnel insulating film, a free layer, and the like laminated on a semiconductor substrate with CO-NH ₃ gas or methanol gas using a hard mask such as Ta, for example. Is done. The hard mask is formed by selectively forming a photoresist using a photolithography technique and etching a portion not covered with the photoresist with a halogen-based gas such as Cl (chlorine) or CF ₄ . In order to prevent the ferromagnetic tunnel junction element from being etched when the hard mask is etched, for example, a stopper layer such as Ru is disposed between the hard mask and the free layer. Further, the stopper layer is laminated on the free layer through a cap layer of Ta or the like whose crystallization temperature is higher than the crystallization temperature of the free layer so that the crystallization of the free layer starts from the tunnel insulating film side. .

JP 2007-48790 A

The cap layer made of Ta or the like has a low etching rate with CO—NH ₃ gas or methanol gas and is difficult to be etched, so it needs to be formed thin. On the other hand, when the cap layer is thinned, the distance between the stopper layer, the free layer, and the tunnel insulating film is reduced, and the influence of Ru of the stopper layer on the free layer and the tunnel insulating film is increased. For example, if the cap layer is thinner than 1 nm, Ru that volatilizes during etching of the ferromagnetic tunnel junction element tends to adhere to the side surface of the tunnel insulating film, causing a short circuit failure. Further, Ru becomes easy to diffuse to the tunnel insulating film side during the heat treatment. When Ru appears at the interface of the free layer due to diffusion, the interface between the free layer and the tunnel insulating film is contaminated, so that the electrical characteristics of the magnetoresistive element are deteriorated. As described above, the cap layer of Ta or the like is preferably thin in consideration of the etching rate, but is preferably thick in consideration of contamination by Ru.

In one embodiment of the present invention, a magnetoresistive element includes a fixed layer disposed on a semiconductor substrate, a tunnel insulating film disposed on the fixed layer, and a first free layer disposed on the tunnel insulating film and including Fe. A second free layer that is disposed on the first free layer and includes Fe and Ta, a stopper layer that is disposed on the second free layer and includes Ru, and a hard mask disposed on the stopper layer, The second free layer has a thickness of 2 of the first free layer, which is set according to the restrictions on the contamination of the tunnel insulating film due to the Ru of the stopper layer, the ease of etching, and the write current for changing the resistance state. It has a thickness in the range from double to triple .

  The distance between the first free layer and the stopper layer can be increased by the second free layer, the Ru of the stopper layer can be prevented from adhering to the tunnel insulating film, and the Ru of the stopper layer can appear at the interface of the first free layer. Can be prevented. The second free layer containing Fe and Ta has a higher etching rate than pure Ta. As a result, the tunnel insulating film can be prevented from being contaminated without increasing the etching time, and the electrical characteristics of the magnetoresistive element can be prevented from deteriorating.

The example of the magnetoresistive element in one Embodiment is shown. An example of a manufacturing method of the magnetoresistive element shown in FIG. 1 is shown. An example of a manufacturing method of the magnetoresistive element shown in FIG. 1 is shown. An example of a manufacturing method of the magnetoresistive element shown in FIG. 1 is shown. The relationship between the film thickness of the free layer FL2 of the magnetoresistive element shown in FIG. 1 and the magnetoresistance ratio is shown. The relationship between the film thickness of the free layer FL1 of the magnetoresistive element shown in FIG. 1 and the magnetoresistance ratio is shown. The relationship between the film thickness of the free layer FL2 of the magnetoresistive element shown in FIG. The relationship between the film thickness of the free layer FL2 of the magnetoresistive element shown in FIG. 1 and surface resistance is shown. 2 shows an example of a semiconductor memory having memory cells including the magnetoresistive element shown in FIG. 3 shows another example of a semiconductor memory having memory cells including the magnetoresistive element shown in FIG. 11 shows an example of the structure and write operation of the memory cell shown in FIG. An example of a system in which the above-described semiconductor memory is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a magnetoresistive element MRE in one embodiment. For example, the magnetoresistive element MRE is formed as a memory element of a spin injection type MRAM or a wiring current magnetic field type MRAM which is a kind of nonvolatile semiconductor memory. The magnetoresistive element MRE includes an antiferromagnetic layer AFL, a ferromagnetic tunnel junction element MTJ, a stopper layer STOP, and a hard mask HM stacked on the lower electrode BEL.

  For example, the lower electrode BEL is formed of Ta (for example, thickness 5 nm), Ru (for example, thickness 50 nm) and Ta (for example, thickness 15 nm). The antiferromagnetic layer AFL is formed of IrMn (thickness 7 to 12 nm) or PtMn (thickness 10 to 20 nm).

  The ferromagnetic tunnel junction element MTJ has a fixed layer PL (ferromagnetic layer), a tunnel insulating film TL, a free layer FL1 (ferromagnetic layer), and a free layer FL2 (ferromagnetic layer) which are sequentially stacked. For example, the fixed layer PL includes, from the antiferromagnetic layer AFL side, CoFe (thickness 1.5 to 3.0 nm), Ru (thickness 0.6 to 0.9 nm), and CoFeNiB (thickness 1.5 to 3). .0 nm) in order. The tunnel insulating film TL is formed of MgO (thickness 0.8 to 1.2 nm). Note that the tunnel insulating film TL may be formed of AlO (aluminum oxide), TiO, or HfO.

  The free layer FL1 is formed of CoFeB (thickness 0.5 to 2 nm). The free layer FL2 is made of CoFeBTa (thickness 1 to 4 nm). The thickness of the free layer FL2 is larger than the thickness of the free layer FL1. Note that the free layer FL1 may be formed of any one of Fe, FeB, NiFeB, and CoNiFeB. The free layer FL2 may be formed of any one of FeTa, FeBTa, NiFeBTa, and CoNiFeBTa. The stopper layer STOP is formed of Ru (thickness 5 to 10 nm). The hard mask HM is formed of Ta (thickness 2 to 10 nm) or TiN.

2 to 4 show an example of a manufacturing method of the magnetoresistive element MRE shown in FIG. First, as shown in FIG. 2A, an insulating film INS1 of SiN or SiO ₂ is formed on the diffusion layer DL of the semiconductor substrate SUB such as silicon by CVD (Chemical Vapor Deposition) or the like. Next, a via hole VIA1 (plug contact) is formed in the insulating film INS1. For example, the diffusion layer DL to which the via hole VIA1 is connected is the drain DR of the selection transistor ST shown in FIG. Thereafter, the lower electrode BEL, the antiferromagnetic layer AFL, the ferromagnetic tunnel junction element MTJ, the stopper layer STOP, and the hard mask HM are sequentially formed on the insulating film INS1 by sputtering.

Next, as shown in FIG. 2B, a photoresist RES is applied, and a mask made of the photoresist RES is selectively formed using a photolithography technique. Then, the first reactive ion etching (RIE) is performed with a halogen-based gas such as Cl (chlorine) or CF ₄ . The portion of the hard mask HM that is not covered with the photoresist RES is etched to form a hard mask HM having a shape corresponding to the cross-sectional shape of the ferromagnetic tunnel junction element MTJ. The stopper layer STOP (Ru) is hardly etched because the etching rate with the halogen-based gas is low. That is, the stopper layer STOP acts as a stopper when forming the hard mask HM. Thereafter, the photoresist RES is removed.

Next, as shown in FIG. 3A, the second reactive ion etching (RIE) is performed with CO—NH ₃ gas or methanol gas using the hard mask HM as a mask. Then, the stopper layer STOP, the free layers FL2 and FL1, the tunnel insulating film TL, the fixed layer PL, and the antiferromagnetic layer AFL are sequentially etched to form the ferromagnetic tunnel junction element MTJ shown in FIG. Ta of the lower electrode BEL is hardly etched because the etching rate with CO—NH ₃ gas or methanol gas is low.

  At this time, the free layer FL2 containing Ta has a higher etching rate than a pure Ta film, and therefore can be easily etched. For example, the etching rate of the free layer FL2 containing 33 atomic% of Ta is about three times that of a pure Ta film. Therefore, when the etching time is the same, a free layer FL2 that is three times thicker than the cap layer can be formed instead of the conventional Ta cap layer.

  By forming the thick free layer FL2, the distance between the stopper layer STOP and the tunnel insulating film TL is increased, and Ru of the stopper layer STOP is difficult to adhere to the side surface of the tunnel insulating film TL. Therefore, it is possible to prevent the fixed layer PL and the free layer FL1 from being short-circuited by Ru adhering to the side wall of the tunnel insulating film TL.

  In addition, since the free layer FL2 is disposed between the stopper layer STOP and the free layer FL1, Ru becomes difficult to diffuse to the free layer FL1 side. Thereby, interface contamination between the free layer FL1 and the tunnel insulating film TL can be prevented, and deterioration of the electrical characteristics of the free layer FL1 can be prevented.

  Furthermore, the free layer FL2 containing Ta can reduce the saturation magnetization amount to about one third as compared with the free layer not containing Ta. For this reason, even when the free layer FL2 is thickened, it is possible to prevent an increase in the write current necessary for rewriting the resistance state of the ferromagnetic tunnel junction device MTJ. As will be described later, the magnetoresistance ratio MR and the sheet resistance RA can be made equal to or less than the conventional one. As described above, by forming the free layer FL2 instead of the conventional cap layer (Ta), it is possible to prevent contamination and deterioration of electrical characteristics due to Ru without extending the etching time.

  Next, as shown in FIG. 3B, a photoresist RES is applied, and reactive ion etching is performed with a gas such as Cl (chlorine) using a photolithography technique to form the lower electrode BEL. . The insulating film INS1 is hardly etched because the etching rate with a chlorine-based gas is low. Thereafter, the photoresist RES is removed.

Next, as shown in FIG. 4A, an insulating film INS2 such as SiN or SiO ₂ is formed on the insulating film INS1 by CVD (Chemical Vapor Deposition) or the like. Next, as shown in FIG. 4B, a via hole VIA2 (plug contact) is formed in the insulating film INS2, and the magnetoresistive element MRE is manufactured. For example, the via hole VIA2 is connected to the bit line BL shown in FIGS.

  FIG. 5 shows the relationship between the film thickness of the free layer FL2 of the magnetoresistive element MRE shown in FIG. 1 and the magnetoresistance ratio MR. The composition of the free layer FL2 is CoFeBTa. The white square marks indicate the characteristics of the free layer FL2 in which the content ratios of CoFeB and Ta are 66 atomic% and 34 atomic%, respectively. The black circles indicate the characteristics of the free layer FL2 in which the content ratios of CoFeB and Ta are 56 atomic% and 44 atomic%, respectively. The free layer FL1 is CoFeB having a thickness of 0.5 nm, and the contents of Co, Fe, and B are 42 atomic%, 42 atomic%, and 16 atomic%, respectively.

The magnetoresistance ratio MR is expressed by Equation (1) using the resistance value RAP in the high resistance state and the resistance value RP in the low resistance state of the ferromagnetic tunnel junction element MTJ. For example, in the memory cell MC (FIGS. 9 and 10) using the magnetoresistive element MRE, the logic held in the memory cell MC is determined by the current or voltage generated in the source line SL according to the resistance values RAP and RP. Is done. For this reason, the read margin of the memory cell MC can be increased as the value of the magnetoresistance ratio MR is increased. In order to ensure a read margin, the magnetoresistance ratio MR is desirably 80% or more, for example.
MR = (RAP-RP) / RP. . . (1)
In the characteristics of FIG. 5, the magnetoresistance ratio MR is saturated and becomes almost constant when the thickness of the free layer FL2 is 1.5 nm or more. It is estimated that the characteristics of the free layer FL2 containing 50 atomic% Ta show a broken line. As described above, when the free layer FL2 is provided, the magnetoresistance ratio MR can be made equivalent to the conventional one. In consideration of the magnetoresistance ratio MR (80% or more) and the ease of etching, the Ta content in the free layer FL2 is preferably 50 atomic% or less.

  FIG. 6 shows the relationship between the thickness of the free layer FL1 of the magnetoresistive element MRE shown in FIG. 1 and the magnetoresistance ratio MR. The composition of the free layer FL1 is CoFeB, and the contents of Co, Fe, and B are 42 atomic%, 42 atomic%, and 16 atomic%, respectively. The composition of the free layer FL2 is CoFeBTa. White square marks indicate the characteristics of the free layer FL2 having a CoFeB and Ta content of 66 atomic% and 34 atomic%, respectively, and a film thickness of 1.2 nm. The black circles indicate the characteristics of the free layer FL2 having a CoFeB and Ta content of 56 atomic% and 44 atomic%, respectively, and a film thickness of 1.4 nm. The magnetoresistance ratio MR increases as the thickness of the free layer FL1 increases. The film thickness of the free layer FL1 required to increase the magnetoresistance ratio MR to 80% or more is 0.5 nm or more.

  FIG. 7 shows the relationship between the film thickness of the free layer FL2 of the magnetoresistive element MRE shown in FIG. The composition of the free layer FL2 is CoFeBTa, and the contents of CoFeB and Ta are 66 atomic% and 34 atomic%, respectively. The composition of the free layer FL1 is CoFeB, and the contents of Co, Fe, and B are 42 atomic%, 42 atomic%, and 16 atomic%, respectively. The film thickness of the free layer FL1 is 0.5 nm.

  The short-circuit defect rate converges to approximately 7.5% when the thickness of the free layer FL2 is 1.6 nm or more. When the film thickness of the free layer FL2 is thin (for example, 1.5 nm or less), the distance between the stopper layer STOP and the tunnel insulating film TL shown in FIG. 1 is shortened. For this reason, Ru that is volatilized during etching is likely to adhere to the side surface of the tunnel insulating film TL, and a short circuit defect occurs. In other words, when the thickness of the free layer FL2 is 1.6 nm or more, a short circuit failure due to adhesion of Ru to the tunnel insulating film TL does not occur. A failure rate of 7.5% that does not depend on the thickness of the free layer FL2 is found to be caused by a short circuit between a via hole (plug contact) and another wiring or the like, based on failure analysis.

  Even if the free layer FL1 is thickened, the distance between the stopper layer STOP and the tunnel insulating film TL can be increased. However, increasing the thickness of the free layer FL1 having a large saturation magnetization is not desirable because the write current increases. Therefore, it is desirable that the distance between the stopper layer STOP and the tunnel insulating film TL be increased by increasing the thickness of the free layer FL2. In consideration of contamination by Ru, ease of etching, and write current, the thickness of the free layer FL2 is preferably, for example, 2 to 3 times the thickness of the free layer FL1.

  FIG. 8 shows the relationship between the film thickness of the free layer FL2 of the magnetoresistive element MRE shown in FIG. 1 and the sheet resistance RA. The compositions of the free layers FL1 and FL2 are the same as those in FIG. The sheet resistance RA shown in FIG. 8 is, for example, a value when the ferromagnetic tunnel junction device MTJ shown in FIG. 1 is in a low resistance state. The sheet resistance RA becomes substantially constant when the thickness of the free layer FL2 is 1.6 nm or more. This shows that the film thickness of the free layer FL2 is preferably 1.6 nm.

  FIG. 9 shows an example of a semiconductor memory MEM having memory cells MC including the magnetoresistive element MRE shown in FIG. For example, the semiconductor memory MEM is a spin transfer torque MRAM having a ferromagnetic tunnel junction element MTJ. The semiconductor memory MEM includes a memory cell array ARY, a word line driver WLDRV, a bit line driver BLDRV, a source line driver SLDRV, and a sense amplifier SA.

  The memory cell array ARY has a plurality of memory cells MC arranged in a matrix. The memory cells MC arranged in the horizontal direction in FIG. 9 are connected to a common word line WL. The memory cells MC arranged in the vertical direction in FIG. 9 are connected to a common source line SL and a common bit line BL. The memory cell MC includes the magnetoresistive element MRE shown in FIG. 1 and a selection transistor ST. For example, each memory cell MC stores a logic 1 when the ferromagnetic tunnel junction element MTJ is in a high resistance state, and stores a logic 0 when the ferromagnetic tunnel junction element MTJ is in a low resistance state. In the ferromagnetic tunnel junction element MTJ, the hard mask HM side shown in FIG. 1 is connected to the bit line BL, and the lower electrode BEL side is connected to the source line SL via the selection transistor ST. The gate of the selection transistor ST is connected to the word line WL. The arrow shown in the ferromagnetic tunnel junction element MTJ indicates that the free layer FL2 (hard mask HM side) is disposed on the tip side.

  The word line driver WLDRV activates one of the word lines WL to a high level and deactivates another word line WL to a low level according to an address signal AD during a write operation and a read operation. The bit line driver BLDRV sets the bit line BL to a low level (for example, ground voltage) or a high level (write voltage) according to the logic of the write data DI during a write operation. The bit line driver BLDRV sets the bit line BL to a high level (read voltage) during a read operation.

  The source line driver SLDRV sets the source line SL to a high level (write voltage) or a low level (for example, ground voltage) according to the logic of the write data DI during a write operation. Thereby, the voltage level of the source line SL is set to be opposite to the voltage level of the corresponding bit line BL during the write operation. The source line driver SLDRV sets the source line SL in a floating state during a read operation. Then, a voltage or current corresponding to the logic of data held in the memory cell MC is generated on the source line SL.

  The sense amplifier SA operates during a read operation, determines the logic held in the memory cell MC connected to the activated word line WL based on the voltage or current of the source line SL, and determines the determined logic. Is output as read data DO.

  FIG. 10 shows another example of the semiconductor memory MEM having the memory cell MC including the magnetoresistive element MRE shown in FIG. For example, the semiconductor memory MEM is a wiring current magnetic field type MRAM having a ferromagnetic tunnel junction element MTJ. In the wiring current magnetic field type MRAM, the write word line WWL is wired near the ferromagnetic tunnel junction element MTJ. For example, the write word line WWL is wired along the ferromagnetic tunnel junction elements MTJ arranged in the horizontal direction in FIG.

  The word line driver WLDRV drives the write word line WWL during the write operation and drives the word line WL during the read operation. The bit line driver BLDRV and the source line driver SLDRV are driven only during a read operation. Other configurations and functions of the semiconductor memory MEM are the same as those in FIG.

  FIG. 11 shows an example of the structure and write operation of the memory cell MC shown in FIG. The ferromagnetic tunnel junction element MTJ is formed on the selection transistor ST formed on the surface of the semiconductor substrate SUB. For example, the semiconductor substrate SUB is a p-type substrate, and the selection transistor ST is an nMOS transistor.

  The drain DR of the selection transistor ST is connected to the fixed layer PL side of the ferromagnetic tunnel junction element MTJ through the via hole VIA1 (plug contact) and the connection wiring CN1. The bit line BL is connected to the free layer FL1 side of the ferromagnetic tunnel junction device MTJ. The source SC of the selection transistor ST is connected to the source SL shown in FIG. 10 via a via hole VIA2 (plug contact). The drain DR and the source SC are a kind of diffusion layer.

  The write word line WWL is wired along the word line WL between the word line WL and the ferromagnetic tunnel junction element MTJ. Although not particularly limited, the word line WL is formed using a polysilicon wiring layer. The write word line WWL, the bit line BL, the connection wiring CN1, and the source line SL shown in FIG. 10 are formed using a metal wiring layer.

In the write operation of the wiring current magnetic field type MRAM, the ferromagnetic tunnel junction element MTJ has a magnetic field MF1 generated by the current I1 flowing through the bit line BL and a magnetic field MF2 generated by the current I2 flowing through the write word line WWL. The resistance value is rewritten and the data logic is written. The logic of data to be written is set by the direction of current flowing through the bit line BL.
For example, as indicated by an arrow in the ferromagnetic tunnel junction element MTJ, when the magnetization directions of the fixed layer PL and the free layer FL1 are opposite (antiparallel), the ferromagnetic tunnel junction element MTJ is set in a high resistance state. Yes. On the other hand, when the magnetization directions of the fixed layer PL and the free layer FL1 are the same (parallel), the ferromagnetic tunnel junction device MTJ is set in a low resistance state. The memory cell MC of the spin injection MRAM is almost the same as the structure in which the write word line WWL is removed from FIG.

  As described above, in this embodiment, by increasing the distance between the tunnel insulating film TL and the stopper layer STOP by the interposition of the free layer FL2, it is possible to prevent the Ru of the stopper layer STOP from adhering to the tunnel insulating film TL during etching. By increasing the distance between the free layer FL1 and the stopper layer STOP by the interposition of the free layer FL2, it is possible to prevent the Ru of the stopper layer STOP from appearing at the interface of the free layer FL1, and the electrical characteristics of the magnetoresistive element MRE deteriorate. Can be prevented.

  By forming the free layer FL2 having a smaller saturation magnetization than the free layer FL1 thicker than the free layer FL1, the distance between the tunnel insulating film TL and the stopper layer STOP or the free layer FL1 and the stopper can be increased without increasing the write current. The distance from the layer STOP can be increased. Since the free layer FL2 containing Ta has a higher etching rate than that of pure Ta, it is possible to prevent the etching time from becoming long even when the free layer FL2 is formed. As described above, the contamination of the tunnel insulating film TL can be prevented without increasing the etching time, and the electrical characteristics of the magnetoresistive element MRE can be prevented from deteriorating.

  FIG. 12 shows an example of a system SYS on which the above-described semiconductor memory MEM is mounted. The system SYS (user system) includes at least a part of a microcomputer system such as a portable device. The system SYS may be a system-on-chip in which a plurality of macros are integrated on a silicon substrate, or a system-in-package in which a plurality of chips are mounted on a package substrate.

  For example, the system SYS includes a CPU, a ROM, a peripheral circuit PERI, and any of the semiconductor memories MEM described above. The CPU, ROM, peripheral circuit PERI, and semiconductor memory MEM are connected to each other by a system bus SBUS. The ROM stores a program executed by the CPU. The CPU accesses the ROM and also accesses the semiconductor memory MEM to control the operation of the entire system. Note that the ROM is not necessary when the program executed by the CPU is stored in the semiconductor memory MEM. The peripheral circuit PERI controls at least one of an input device and an output device connected to the system SYS. The semiconductor memory MEM performs a write operation and a read operation in response to an access request from the CPU.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A fixed layer disposed on a semiconductor substrate;
A tunnel insulating film disposed on the fixed layer;
A first free layer disposed on the tunnel insulating film and containing Fe;
A second free layer disposed on the first free layer and comprising Fe and Ta;
A magnetoresistive element comprising: a stopper layer that is disposed on the second free layer and includes Ru; and a hard mask that is disposed on the stopper layer.
(Appendix 2)
The magnetoresistive element according to claim 1, wherein a thickness of the second free layer is larger than a thickness of the first free layer.
(Appendix 3)
The magnetoresistive element according to appendix 1 or appendix 2, wherein the second free layer further contains B.
(Appendix 4)
The magnetoresistive element according to claim 3, wherein the second free layer further includes at least one of Co and Ni.
(Appendix 5)
A magnetic layer having a fixed layer, a tunnel insulating film, a first free layer containing Fe, a second free layer containing Fe and Ta, a stopper layer containing Ru, and a hard mask arranged in order on a semiconductor substrate A resistance element;
A memory cell including a select transistor having a drain connected to the fixed layer;
A bit line connected to the hard mask;
A source line connected to a source of the selection transistor;
A word line connected to the gate of the select transistor;
A semiconductor memory comprising: a driver for driving the bit line, the source line, and the word line.
(Appendix 6)
The semiconductor memory according to appendix 5, wherein a thickness of the second free layer is larger than a thickness of the first free layer.
(Appendix 7)
The semiconductor memory according to appendix 5 or appendix 6, wherein the second free layer further contains B.
(Appendix 8)
The semiconductor memory according to appendix 7, wherein the second free layer further includes at least one of Co and Ni.
(Appendix 9)
A laminating step of sequentially laminating a fixed layer, a tunnel insulating film, a first free layer containing Fe, a second free layer containing Fe and Ta, a stopper layer containing Ru, and a hard mask on a semiconductor substrate; ,
A first etching step of selectively etching the hard mask using a photolithography technique;
Second etching for selectively etching the stopper layer, the second free layer, the first free layer, the tunnel insulating film, and the fixed layer using the hard mask left after etching as a mask A method of manufacturing a magnetoresistive element comprising the steps of:
(Appendix 10)
The method of manufacturing a magnetoresistive element according to claim 9, wherein, in the stacking step, the thickness of the second free layer is formed larger than the thickness of the first free layer.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and changes, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  AFL: Antiferromagnetic layer; ARY: Memory cell array; BEL: Lower electrode; BL: Bit line; BLDRV: Bit line driver; CN1: Connection wiring: DL: Diffusion layer; DR: Drain; FL1, FL2: Free layer; INS, INS2, insulating film, MC, memory cell, MEM, semiconductor memory, MF1, MF2, magnetic field, MRE, magnetoresistive element, MTJ, ferromagnetic tunnel junction element, PERI, peripheral circuit, PL, fixed layer RES, photoresist, SA, sense amplifier, SBUS, system bus, SC, source, SL, source line, SLDRV, source line driver, ST, selection transistor, STOP, stopper layer, SUB, semiconductor substrate, SYS, system; TL Tunnel insulating film; VIA1, VIA2 Via hole; WL Word line; W DRV ‥ word line driver; WWL ‥ write word line

Claims (3)

A fixed layer disposed on a semiconductor substrate;
A tunnel insulating film disposed on the fixed layer;
A first free layer disposed on the tunnel insulating film and containing Fe;
A second free layer disposed on the first free layer and comprising Fe and Ta;
A stopper layer disposed on the second free layer and including Ru; and a hard mask disposed on the stopper layer,
The second free layer is set according to constraints on contamination of the tunnel insulating film due to Ru of the stopper layer, etching ease, and a write current for changing a resistance state. A magnetoresistive element having a thickness in a range of 2 to 3 times the thickness. A magnetic layer having a fixed layer, a tunnel insulating film, a first free layer containing Fe, a second free layer containing Fe and Ta, a stopper layer containing Ru, and a hard mask arranged in order on a semiconductor substrate A resistance element;
A memory cell including a select transistor having a drain connected to the fixed layer;
A bit line connected to the hard mask;
A source line connected to a source of the selection transistor;
A word line connected to the gate of the select transistor;
A driver for driving the bit line, the source line, and the word line;
The second free layer is set according to constraints on contamination of the tunnel insulating film due to Ru of the stopper layer, etching ease, and a write current for changing a resistance state. A semiconductor memory having a thickness in the range of 2 to 3 times the thickness. A laminating step of sequentially laminating a fixed layer, a tunnel insulating film, a first free layer containing Fe, a second free layer containing Fe and Ta, a stopper layer containing Ru, and a hard mask on a semiconductor substrate; ,
A first etching step of selectively etching the hard mask using a photolithography technique;
Second etching for selectively etching the stopper layer, the second free layer, the first free layer, the tunnel insulating film, and the fixed layer using the hard mask left after etching as a mask A process,
In the stacking step, the second free layer is set according to restrictions on contamination of the tunnel insulating film due to Ru of the stopper layer, etching ease, and a write current for changing a resistance state, A method of manufacturing a magnetoresistive element, comprising forming the thickness within a range of 2 to 3 times the thickness of the first free layer.

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