JP5772139B2 - Data reading apparatus, data reading method, and program - Google Patents

Description

  The present technology relates to a data reading device, a data reading method, and a program. Specifically, the present invention relates to a data reading apparatus, a data reading method, and a program that can selectively process one signal from different broadcast signals that are multiplexed and transmitted in the time direction.

  In recent years, a modulation scheme called an orthogonal frequency division multiplexing (OFDM) scheme has been used as a scheme for transmitting digital signals. In this OFDM system, a number of orthogonal subcarriers are prepared in the transmission band, data is allocated to the amplitude and phase of each subcarrier, and digital modulation is performed by PSK (Phase Shift Keying) or QAM (Quadrature Amplitude Modulation). It is.

  The OFDM system is often applied to terrestrial digital broadcasting that is strongly affected by multipath interference. Examples of such terrestrial digital broadcasting employing the OFDM system include DVB-T (Digital Video Broadcasting-Terrestrial) and ISDB-T (Integrated Services Digital Broadcasting-Terrestrial).

  By the way, DVB (Digital Video Broadcasting) -T.2 is being established as a next-generation digital terrestrial broadcasting standard by ETSI (European Telecommunication Standard Institute) (see Non-Patent Document 1).

DVB BlueBook A122 Rev.1, Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system (DVB-T2) September 1, 2008, DVB website, [Search March 17, 2011], Internet <URL: http://www.dvb.org/technology/standards/>

  In DVB-T.2, a system called M-PLP (Multiple PLP (Physical Layer Pipe)) is used. In this M-PLP, a packet sequence called Common PLP in which common packets are extracted from a plurality of transport streams (hereinafter referred to as TS), and a packet called Data PLP in which common packets are extracted. Data is transmitted by series. On the receiving side, one TS is restored from the Common PLP and Data PLP.

  However, on the receiving side, the TS is restored and output in synchronization with the Common PLP and the Data PLP. However, if the output timing is too early, the restored TS before the next frame arrives. There is a possibility that a non-output period may occur in the TS output period.

  If a TS non-output period occurs, decoding by a subsequent decoder may fail, and therefore it is required to suppress the TS non-output period.

  The present invention has been made in view of such a situation, and avoids a TS non-output period and enables reliable decoding.

A first data reading device according to an aspect of the present technology includes a system clock generated when the device itself operates and a clock for reading the buffered data from information signaled to received data. And the signaled information is the length of one T2 frame in DVD-T2 and ISCR, and the generation unit uses the length of the T2 frame as a first time, According to the number of clocks M 1 set as the number of clocks corresponding to the first time and the number of clocks N 1 of the system clock existing within the first time, the system clock is represented by N 1 : by dividing by the division ratio of M 1, clock for reading a first clock generator for generating a first clock, the buffered data As the difference between the values of two of the ISCR a second time, the number of clocks N 2 corresponding to the second time, to the number of clocks M 2 corresponding to the number of data bytes in the second time Accordingly, the first clock generation unit includes a second clock generation unit that generates a second clock by dividing the first clock by a frequency division ratio of N 2 : M 2 .

A first data reading method according to an aspect of the present technology is a data reading method of a data reading device including a buffer for buffering data, and a system clock generated when the device itself operates and signaling to received data Generating a clock for reading the buffered data from the information being recorded, wherein the signaled information is the length of one T2 frame in DVD-T2 and the ISCR, and the generation The length of the T2 frame is a first time, the number of clocks M 1 set as the number of clocks corresponding to the first time, and the number of clocks of the system clock existing within the first time depending on the N 1, the system clock, N 1: by dividing by the division ratio of M 1, the first black Generates a click, as a clock for reading out the buffered data, the difference between the values of two of the ISCR a second time, the number of clocks N 2 corresponding to the second time, the second Generating a second clock by dividing the first clock by a division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of data bytes within including.

A first program according to an aspect of the present technology is received by a computer that executes a data reading process of a data reading device including a buffer that buffers data, and a system clock generated when the device itself operates Generating a clock for reading the buffered data from the information signaled in the data, the signaled information being the length of one T2 frame in DVD-T2 and the ISCR The generation uses the length of the T2 frame as a first time, the number of clocks M 1 set as the number of clocks corresponding to the first time, and the system clock existing within the first time depending of the clock number N 1, the system clock, N 1: by dividing by the division ratio of M 1, Generates a first clock, as the clock for reading out the buffered data, the difference between the values of two of the ISCR a second time, the number of clocks N 2 corresponding to the second time, the A second clock is generated by dividing the first clock by a division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of data bytes in the second time. The process including the step to perform is performed.

In the first data reading device, the data reading method, and the program according to one aspect of the present technology, buffering is performed from a system clock generated when the device itself operates and information signaled to received data. A clock is generated to read the data. The information being signaled is the length of one T2 frame in DVD-T2 and the ISCR. The length of the T2 frame is the first time, and the clock is set as the number of clocks corresponding to the first time. The first clock is divided by dividing the system clock by a division ratio of N 1 : M 1 according to the number M 1 and the number N 1 of system clocks existing in the first time. As a clock for reading out the generated and buffered data, the difference between the two ISCR values is set as the second time, the number of clocks N 2 corresponding to the second time, and the data within the second time The second clock is generated by dividing the first clock by the division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of bytes.

  According to one aspect of the present technology, it is possible to generate an accurate clock for reading buffered data.

It is a figure which shows the outline | summary of a structure of the transmitter and receiver in the case of using M-PLP system in DVB-T.2. It is a figure which shows the structure of the packet of a transmission side. It is a figure which shows the structure of Common PLP and Data PLP of a transmission side. It is a figure which shows the structure of Common PLP and Data PLP in Null packet duration mode of a transmission side. It is a figure which shows the structure of one Embodiment of a receiver. It is a figure which shows the structural example of output I / F. It is a figure which shows the structure of Common PLP and Data PLP of a receiving side. It is a figure for demonstrating the restoration method of TS of the receiving side. It is a figure for demonstrating the detail of the decompression | restoration method of TS of the receiving side. It is a figure for demonstrating the calculation method of TS rate. It is a figure for demonstrating the timing of writing and reading of a buffer. It is a figure which shows the structural example of a clock generation part. It is a figure for demonstrating operation | movement of a clock generation part. It is a figure for demonstrating the clock numbers M and N. FIG. It is a figure for demonstrating the generated pulse. It is a figure for demonstrating the clock numbers M and N. FIG. It is a figure for demonstrating the generated pulse. It is a figure for demonstrating the timing of writing and reading of a buffer. It is a figure for demonstrating a recording medium.

  Hereinafter, embodiments of the present technology will be described with reference to the drawings.

[Overview of overall configuration]
1 is a diagram illustrating an outline of the configuration of a transmission device (Tx) and a receiver (Rx) when the M-PLP scheme is used in DVB-T.2. As shown in FIG. 1, when a plurality of TSs (TS1 to TSN in the figure) are input at a constant bit rate on the transmitting apparatus side, a common packet is extracted from the packets constituting those TSs. Thus, a packet sequence (TSPSC (CPLP) in the figure) called Common PLP is generated. The TS from which the common packet is extracted becomes a packet series (TSPS1 (PLP1) to TPSSN (PLPN) in the figure) called Data PLP.

  That is, on the transmitting apparatus side, N Data PLPs and one Common PLP are generated from N TSs. Thereby, it is possible to adaptively assign an error correction coding rate and a modulation scheme such as OFDM for each PLP. In the present embodiment, when only PLP is described, both Common PLP and Data PLP are included. In addition, the description of “Common PLP” and “Data PLP” includes the meanings of the individual packets constituting the Common PLP and Data PLP.

  For example, in the case of MPEG TS (Transport Stream) packets, some data PLPs contain the same information, such as control information such as SDT (Service Description Table) and EIT (Event Information Table). By cutting out and transmitting such common information as Common PLP, it is possible to avoid a decrease in transmission efficiency.

  On the other hand, the receiver side demodulates the received Data PLP (TSPS1 (PLP1) to TPSN (PLPN) in the figure) and Common PLP (TSPSC (CPLP) in the figure) using a demodulation method such as OFDM. By extracting only the desired PLP (TSPS2 (PLP2) in the figure) and performing error correction processing, it is possible to restore the desired TS.

  For example, as shown in FIG. 1, when TSPS2 (PLP2) is selected from TSPS1 (PLP1) to TPSSN (PLPN), TSPS2 (PLP2) as Data PLP and TPSSC (CPLP) as Common PLP TS2 is restored using. As a result, if one Data PLP and Common PLP are taken out, the TS can be restored, so that there is an advantage that the operation efficiency of the receiver is improved. Then, the TS restored on the receiver side is output to the subsequent decoder. The decoder, for example, MPEG-decodes the encoded data included in the TS and outputs image and audio data obtained as a result.

  As described above, when the M-PLP method is used in DVB-T.2, N Data PLPs and one Common PLP are generated from N TSs on the transmission device (Tx) side. On the receiver (Rx) side, the desired TS is restored (regenerated) from the desired Data PLP and one common PLP.

[Transmitter processing]
Next, processing performed by the transmission apparatus will be described with reference to FIGS. 2 to 4, and then processing performed at the receiver will be described with reference to FIGS. 5 to 8. In the description of the transmission / reception process, for the sake of simplicity, four TSs TS1 to TS4 are input to the transmission apparatus, and the PLP generated from these TSs is used for error correction, OFDM modulation, and the like. After processing, it shall be transmitted to the receiver.

  As shown in FIG. 2, five squares corresponding to TS1 to TS4 represent packets. In this embodiment, TS packets constituting these TSs are a TS packet, a Null packet, and a common packet, respectively. There are three types of packets.

  Here, the TS packet is a packet storing data for providing each service (services 1 to 4 in the figure) such as MPEG encoded data. The Null packet is adjustment data transmitted for the purpose of keeping the amount of information output from the transmission side constant when there is no data to be transmitted on the transmission side. For example, the Null packet specified by MPEG is a packet in which the first 4 bytes of the TS packet are 0x47, 0x1F, 0xFF, 0x1F, and 1 is adopted as the payload bit, for example. The

  A common packet is a packet in which stored data is common in a plurality of TSs. For example, in the case of MPEG, the above-described control information such as SDT and EIT corresponds to this common packet. That is, in the example of FIG. 2, the third packet from the left in the figure among the five packets constituting each of TS1 to TS4 is a common packet. Since this common packet contains the same information, it is extracted as a Common PLP as shown in FIG.

  Specifically, when there is a common packet common to each TS in TS1 to TS4 in FIG. 2, as shown in FIG. 3, the common packet is extracted as a common PLP and extracted. Is replaced with a null packet. Then, each TS from which the common packet is extracted becomes a sequence called Data PLP, that is, Data PLP1 to Data PLP4.

  Also, when the transmitter is operating in a mode called Null Packet Deletion, the Null packet must be transmitted as a 1-byte DNP (Deleted Null Packet) signal (signaling). become. For example, in Data PLP1 in FIG. 3, the second and third packets from the left in the figure are Null packets, and when two Null packets are consecutive, a value of 2 as shown in FIG. Is replaced by a 1-byte signal with That is, the value of DNP corresponds to the number of consecutive Null packets. For example, in Data PLP3 in FIG. 3, the third and fifth packets from the left in the figure are independent Null packets. As shown in the figure, each is replaced with a 1-byte signal having a value of 1.

  When the Null packet is replaced with 1-byte DNP in this way, Data PLP1 to Data PLP4 and Common PLP in FIG. 3 are in the state shown in FIG. As a result, Data PLP1 to Data PLP4 and Common PLP are generated in the transmission apparatus.

  As described above, in the transmission apparatus, four Data PLPs and one Common PLP are generated from four TSs, and predetermined processing such as error correction and OFDM modulation is performed on these signals. Then, the OFDM signal obtained thereby is transmitted to the receiver via a predetermined transmission path.

[Receiver processing]
Next, processing of the receiver will be described with reference to FIGS. As described above, the OFDM signal received by the receiver is subjected to processing such as error correction and OFDM modulation on Data PLP1 to Data PLP4 and Common PLP in FIG. 4 in accordance with the processing of the transmission apparatus. It shall be. First, the configuration of a receiving apparatus that receives and processes an OFDM signal generated and transmitted on the transmitting apparatus side as described above will be described with reference to FIGS.

  FIG. 5 is a diagram illustrating a configuration of an embodiment of a reception device. The receiving device 10 illustrated in FIG. 5 includes an antenna 11, an acquisition unit 12, a transmission path decoding processing unit 13, a decoder 14, and an output unit 15. The antenna 11 receives an OFDM signal transmitted from a transmission device via a transmission path, and supplies it to the acquisition unit 12. The acquisition unit 12 includes, for example, a tuner, a set top box (STB), and the like, converts an OFDM signal (RF signal) received by the antenna 11 into an IF (Intermediate Frequency) signal, and performs transmission path decoding. This is supplied to the processing unit 13.

  The transmission path decoding processing unit 13 restores the TS from the PLP obtained by performing necessary processing such as demodulation and error correction on the OFDM signal from the acquisition unit 12 and supplies the TS to the decoder 14. That is, the transmission path decoding processing unit 13 includes a demodulation unit 21, an error correction unit 22, and an output I / F (interface) 23.

  The demodulation unit 21 demodulates the OFDM signal from the acquisition unit 12 and outputs a desired Data PLP and one common PLP to the error correction unit 22 as a demodulation signal obtained as a result. The error correction unit 22 performs a predetermined error correction process on the PLP that is the demodulated signal obtained from the demodulation unit 21, and outputs the PLP obtained as a result to the output I / F 23.

  Here, in the transmission apparatus, for example, data such as an image or sound as a program is MPEG (Moving Picture Experts Group) encoded, and a PLP generated from a TS composed of TS packets including the MPEG encoded data is generated. And transmitted as an OFDM signal. In the transmission apparatus, as a countermeasure against errors that occur on the transmission path, PLP is encoded into codes such as RS (Reed Solomon) code and LDPC (Low Density Parity Check) code. Accordingly, the error correction unit 22 performs a process of decoding the code as the error correction code process.

  The output I / F 23 restores TS from the PLP supplied from the error correction unit 22 and performs output processing for outputting the restored TS to the outside at a predetermined constant rate (hereinafter referred to as TS rate). Specifically, the output I / F 23 is used to restore the TS after the common PLP and the data PLP are synchronized based on the delay time calculation information supplied from the demodulation unit 21 and the PLP supplied from the error correction unit 22. A predetermined delay time until the start is obtained. Then, the output I / F 23 does not start the TS restoration immediately after the common PLP and the data PLP are synchronized, but restores the TS after a predetermined delay time elapses. To supply. Details of the configuration of the output I / F 23 will be described later with reference to FIG.

  The decoder 14 performs MPEG decoding on the encoded data included in the TS supplied from the output I / F 23, and supplies image and audio data obtained as a result to the output unit 15. The output unit 15 includes, for example, a display, a speaker, and the like, displays an image corresponding to image and audio data supplied from the decoder 14, and outputs audio.

[Detailed configuration example of output I / F]
FIG. 6 shows a configuration example of the output I / F 23 of FIG. In the example of FIG. 6, the output I / F 23 includes a buffer 31, a write control unit 32, a read rate calculation unit 33, and a read control unit 34. PLP (Common PLP, Data PLP) supplied from the error correction unit 22 is supplied to the buffer 31, the write control unit 32, the read rate calculation unit 33, and the read control unit 34, respectively.

  The buffer 31 sequentially accumulates the PLPs supplied from the error correction unit 22 according to the write control by the write control unit 32. Further, the buffer 31 reads the accumulated PLP, restores the TS, and outputs it to the decoder 14 according to the read control by the read control unit 34. The write control unit 32 controls the write address for the buffer 31 based on the PLP supplied from the error correction unit 22 and accumulates the PLP in the buffer 31.

  The read rate calculation unit 33 calculates the TS rate based on the PLP supplied from the error correction unit 22 and supplies the TS rate to the read control unit 34. Details of the TS rate calculation processing performed by the read rate calculation unit 33 will be described later with reference to FIG. Further, the TS rate calculated by the calculation may cause underflow or overflow as will be described later. After describing the TS rate calculated by such an operation, a method of generating a TS clock for preventing underflow and overflow will be described.

  The read control unit 34 controls the read address for the buffer 31 so that the TS restored from the PLP read from the buffer 31 is output according to the TS rate supplied from the read rate calculation unit 33.

  The output I / F 23 also has a smoothing function. As shown in FIG. 6, even if the input PLP is intermittent, the output TS needs to be output as continuously as possible, and the buffer is output so as to output continuously. Reading from 31 is performed.

  Further, the processing in the receiving device 10 will be described. In the receiving apparatus 10, an OFDM signal transmitted from the transmitting apparatus via a predetermined transmission path is received, and predetermined processing such as OFDM demodulation is performed by the demodulator 21, so that the data PLP1 in FIG. Data PLP1 to Data PLP4 and Common PLP in FIG. 7 corresponding to Data PLP4 and Common PLP are acquired. For example, when the service 2 is selected by a user operation, Data PLP2 is extracted from Data PLP1 to Data PLP4, and the extracted Data PLP2 and Common PLP are subjected to predetermined correction such as error correction by the error correction unit 22. Processing is performed and input to the output I / F 23.

  That is, only the Data PLP2 surrounded by the thick frame in FIG. 7 and the Common PLP corresponding to Data PLP2 are input to the output I / F 23. Then, as shown in FIG. 8, the output I / F 23 replaces the Null packet arranged in the Data PLP2 with the common packet arranged in the corresponding Common PLP for the input Data PLP2 and Common PLP. As a result, as shown in FIG. 8, the original TS2 similar to the TS2 of FIG. 2 is restored.

  FIG. 9 is a diagram for explaining details of desired Data PLP (Data PLP2) and Common PLP input to the output I / F 23 and TS output from the output I / F 23. As shown in FIG. 9, DNP and information called ISSY (Input Stream Synchronizer) are added to the Data PLP and Common PLP input to the output I / F 23 in units of TS packets.

  This ISSY is signaled with information such as ISCR (Input Stream Time Reference), BUFS (Buffer Size), or TTO (Time to Output). The ISCR is information indicating a time stamp added on the transmission device side when each TS packet is transmitted. BUFS is information indicating the required buffer amount of PLP. By referring to this information, the receiving apparatus 10 can determine the buffer area.

  TTO is information indicating the time from the beginning of the P1 symbol arranged in a T2 frame (T2 frame) in which processing for a TS packet is performed until the TS packet is output. Further, as described above, the DNP is information added when operating in the null packet duration mode, and continuous Null packets are transmitted as a 1-byte signal. For example, in the case of DNP = 3, the receiving apparatus 10 can reproduce the original packet sequence on the assumption that three Null packets are continuous.

  The output I / F 23 uses these pieces of information obtained from the PLP to detect a combination of two packets synchronized from the Data PLP and the Common PLP, and synchronizes with the timing of the Data PLP and the Common PLP. . Specifically, in the output I / F 23, the read rate calculation unit 33 uses the DNP added to the Data PLP to restore the Data PLP to the original packet sequence, and reads the ISCR added to the TS packet. Thus, the TS output rate (TS rate) can be obtained by the following equation (1).

  In Expression (1), N_bits is the number of bits per packet, for example, 1504 (bit / packet) is substituted. T is a unit of elementary period (Elementary Period). For example, a value of 7/64 us is substituted in the case of an 8 MHz band.

  FIG. 10 is a diagram for explaining a calculation example of the TS rate executed by the read rate calculation unit 33. In FIG. 10, the time direction is a direction from the left to the right in the figure, as indicated by the lower arrow. As shown in FIG. 10a, the read rate calculator 33 receives a TS packet and DNP and ISCR added to each TS packet as a data PLP. In the case of this example, DNP added to the first TS packet from the right in the figure indicates 3, and ISCR indicates 3000 [T]. Similarly, the DNP of the second TS packet is 0, ISCR is 1000 [T], the DNP of the third TS packet is 2, and the ISCR is 500 [T].

  When the Null packet is returned to the original state using these DNPs, the Data PLP in FIG. 10a becomes as shown in FIG. 10b. That is, three Null packets ("NP" in the figure) are arranged after the first TS packet, and after the second and third TS packets, two more Null packets are arranged. Become. Therefore, if the packet rate is Pts, this Pts is obtained as follows.

  Pts = (ISCR_b−ISCR_b) / (N_packets + ΣDNP) = (3000 [T] −500 [T]) / 5 [packet] = 500 [T / packet]

  If the TS rate is RTS, this RTS can be obtained from Equation (1) and the above Pts as follows.

  RTS = N_bits / Pts x T = 1504 [bit / packet] / 500 [T / packet] x (7/64 [us]) = 27.5 [Mbps]

  The RTS = 27.5 [Mbps] calculated in this way is supplied to the read control unit 34 as a TS rate. By reading from the buffer 31 based on this TS rate, as described with reference to FIG. 6, even if the input PLP is intermittent due to the smoothing function by the output I / F 23, The output TS is output continuously.

  However, depending on the TS rate, there is no TS buffered in the buffer 31, and a TS non-output period may occur. As a result, the PCR jitter becomes large, and it is necessary to output at a rate at which the jitter becomes as small as possible. If the TS output rate is set to the rate obtained by the above calculation and a fixed-rate TS clock is generated using the system clock, it will be faster than the original output rate due to the frequency error of the system clock. There is a possibility that a malfunction such as a delay will occur. Reading at this fast rate can cause underflow, and reading at a slow rate can cause overflow.

  For example, an underflow as shown in FIG. 11 may occur and a TS non-output period may occur. In the timing chart of FIG. 11, the horizontal axis represents the time axis, and the time direction is a direction from the left to the right in the figure. The vertical axis represents the address of the data stored in the buffer 31, and means that the address advances as it goes up in the figure. In FIG. 11, dotted lines indicate write addresses, and solid lines indicate read addresses. In the figure, the upper bar-shaped line represents the TS to be output.

  As shown in FIG. 11, in the output I / F 23, when a TS packet of the T2 frame is input, the write control unit 32 starts storing the input TS packet in the buffer 31, and the read control unit 34 Thus, reading of the TS packet stored in the buffer 31 is started. This reading is started based on the TTO, and the TS packets stored in the buffer 31 are read after being accumulated to some extent.

  In addition, as shown in FIG. 11, the slope indicating the speed of the write address and the read address is different. That is, the read control unit 34 reads TS packets asynchronously with TS packet writing. Even after the writing of the TS packet for one T2 frame is completed, the TS packet for the next T2 frame is continuously read.

  In the example of FIG. 11, the read (output) rate is a constant rate, and this is a case where early output is performed to avoid overflow. In such a case, there is a possibility that the read address catches up with the write address, the read data is not buffered, and a TS non-output period occurs. As described above, when a problem such as a rate that is faster or slower than a rate that should be output due to a frequency error of the system clock occurs, an underflow or an overflow may occur.

  In order to avoid PCR jitter, the number of system clocks during a certain period is observed, and a TS clock is generated using an integer ratio counter of the number of clocks and the TS byte amount to be output in the meantime, There is a method of outputting based on the TS clock. However, in the case of ISSY, since the amount of TS to be output is known only at the time interval of T units called ISCR, such a method cannot be applied.

  For this reason, it is a clock that does not cause underflow or overflow due to a frequency error of the system clock, etc., and it can be generated even at a special unit time interval of T unit called ISCR. Is described below.

[About clock generation]
In the generation of the clock described below, the TS clock to be finally generated is generated in two stages. And eyes one step, from the division ratio of the system clock number and T, the clock of T units is generated, as the second stage, the division ratio of the number of the T clock and TS bytes generated, TS clock Generated. By reading from the buffer 31 based on such a TS clock, it is possible to prevent underflow or overflow.

  FIG. 12 is a diagram illustrating a configuration example of a clock generation unit that generates a TS clock. The clock generation unit 100 includes a T unit clock generation unit 101 that generates a T unit clock and a TS clock generation unit 102 that generates a TS clock. A system clock is supplied to the T unit clock generator. The T unit clock generated by the T unit clock generation unit 101 is supplied to the TS clock generation unit 102. The TS clock generated by the TS clock generation unit 102 is supplied to the read control unit 34 (FIG. 6).

  Each of the T unit clock generation unit 101 and the TS clock generation unit 102 includes a fractional frequency divider. In FIG. 12, the T unit clock generation unit 101 includes an M setting unit 111, a flip-flop 112, an adder 113, an adder 114, a selector 115, and an N setting unit 116. Similarly, the TS clock generation unit 102 includes an M setting unit 121, a flip-flop 122, an adder 123, an adder 124, a selector 125, and an N setting unit 126.

  First, the T unit clock generation unit 101 will be described. The M setting unit 111 of the T unit clock generation unit 101 is supplied with information on what [T] is the length of one T2 frame from the demodulation unit 43 of FIG. The M setting unit 111 sets the length of one T2 frame supplied from the demodulation unit 43 as M [T], and supplies it to the adder 113 as the clock number M. Data of clock number M, data of clock number N, and data handled by flip-flop 112, adder 113, adder 114, and selector 115 are each represented by two's complement.

  A system clock is supplied to the flip-flop 112 from a system clock output unit (not shown). The flip-flop 112 latches the data supplied from the selector 115 in synchronization with the supplied system clock and supplies the latched data to the adder 113. The adder 113 adds the data supplied from the flip-flop 112 and the clock number M supplied from the M setting unit 111, and supplies the data A obtained as a result of the addition to the adder 114 and the selector 115. .

  A value N obtained by counting the number of clocks in one T2 frame period for each frame is supplied from the N setting unit 116 to the adder 114 as the clock number N. The adder 114 subtracts the data A from the clock number N by adding the clock number N and the value obtained by inverting the sign of the data A supplied from the adder 113, and the data obtained as a result of the subtraction B is supplied to the selector 115.

  Further, the adder 114 supplies the most significant bit (MSB (Most Significant Bit)) of the data B as a selection control signal to the selector 115 and also supplies it to the flip-flop 122 as a T unit clock. That is, when the data B is equal to or greater than 0, the adder 114 supplies the most significant bit 0 of the data B to the selector 115 as a selection control signal and the flip-flop 122 of the TS clock generation unit 102 as a T unit clock. To supply. Further, when the data B is negative, the adder 114 supplies 1 of the most significant bit of the data B as a selection control signal to the selector 115 and also supplies it to the flip-flop 122 of the TS clock generation unit 102 as a T unit clock. To do.

  The selector 115 selects one of the data A supplied from the adder 113 and the data B supplied from the adder 114 based on the selection control signal supplied from the adder 114, and the flip-flop Supplied to That is, the selector 115 selects the data A supplied from the adder 113 and supplies it to the flip-flop 112 when the selection control signal supplied from the adder 114, that is, when the most significant bit of the data B is 0. The selector 115 selects the data B supplied from the adder 114 when the selection control signal supplied from the adder 114, that is, the most significant bit of the data B is 1, and supplies the selected data B to the flip-flop 112.

  FIG. 13 is a diagram for explaining the operation of the T unit clock generator 101. In FIG. 13, the vertical axis indicates the value of data A output from the adder 113 of the T unit clock generation unit 101. Assuming that the value of data supplied from the flip-flop 112 to the adder 113 is 0 at the first clock of the system clock, the adder 113 adds the value 0 and the number of clocks M, and the result of the addition The obtained value M is supplied as data A to the adder 114 and the selector 115.

  In the adder 114, the value M of the data A is subtracted from the clock number N by adding the clock number N and the value -M obtained by inverting the sign of the data A from the adder 113. The resulting value NM is supplied to the selector 115 as data B. Since M is never greater than N, the value NM of data B is 0 or more, and the adder 114 supplies the most significant bit 0 of data B to the selector 115 as a selection control signal. And supplied to the flip-flop 122 as a T unit clock.

  When the selection control signal having a value of 0 is supplied from the adder 114, the selector 115 selects the value M as the data A from the adder 113 and supplies it to the flip-flop 112. In the flip-flop 112, the value M as the data A from the selector 115 is latched at the second clock of the system clock and supplied to the adder 113. In the adder 113, the value M of the data from the flip-flop 112 and the clock number M are added, and a value 2 × M obtained as a result of the addition is supplied as data A to the adder 114 and the selector 115.

  In the adder 114, the value 2 × M of the data A is subtracted from the clock number N by adding the clock number N and the value −2 × M obtained by inverting the sign of the data A from the adder 113. The value N−2 × M obtained as a result of the subtraction is supplied to the selector 115 as data B. Assuming that the value N−2 × M of the data B is 0 or more, the adder 114 supplies the most significant bit 0 of the data B to the selector 115 as a selection control signal, and at the T unit. It is supplied to the flip-flop 122 as a clock.

  Similarly, when data B is 0 or more, that is, when the most significant bit of data B is 0, data A is selected by selector 115 and supplied to flip-flop 112.

  Here, at the kth (k × M ≦ N) clock of the system clock, the value of the data that the flip-flop 112 supplies to the adder 113 is (k−1) × M, and therefore the adder 113 outputs The value of the data A to be performed is k × M. Thereafter, when the number of system clocks reaches the Kth clock satisfying the formula (K-1) × M ≦ N <K × M, the value of the data A output from the adder 113 is K × M, which is larger than N. It becomes.

  In this case, the value N−K × M obtained by subtracting the value K × M of the data A from the clock number N obtained by the adder 114 is negative, and the negative value N−K × M is used as the data B as the selector 115. To be supplied. Since the value N−K × M of the data B is negative, the adder 114 supplies the most significant bit 1 of the data B to the selector 115 as a selection control signal and flips it as a T unit clock. Is supplied to In this case, the selector 115 selects the data B from the adder 113 and supplies it to the flip-flop 112.

  In the flip-flop 112, the value N−K × M as the data B from the selector 115 is latched and supplied to the adder 113 at the (K + 1) th clock of the system clock. In the adder 113, the value N−K × M from the flip-flop 112 and the clock number M are added, and N− (K−1) × M having a value of 0 or more is used as data A as the adder 114 and the selector. 115, and the same processing is performed thereafter. As described above, the T unit clock generation unit 101 outputs a T unit clock that is H level (value is 1) only once for K clocks or K + 1 clocks of the system clock.

  With reference to FIG. 14, the clock number M and the clock number N will be described. The T unit clock generation unit 101 is provided to absorb a frequency error of the system clock and generate a T unit clock. Then, the T unit clock generation unit 101 counts how many system clocks are present in the T unit time, and generates a T unit pulse using the ratio.

  For example, in DVB-T2, what [T] is the length of one T2 frame can be uniquely determined from transmission parameters. The length of one T2 frame that can be uniquely determined is M [T]. The T2 frame includes a preamble signal called P1, and the preamble signal includes information for determining whether or not the target frame is a T2 frame and processing such as demodulation of an OFDM signal. Contains necessary information. In addition, the T2 frame includes a preamble signal called P2 in addition to P1, and in this P2, information such as the length of the T2 frame (T2_frame_length) is included in addition to information necessary for the demodulation processing of the T2 frame. included.

  Since the information included in this P2 is obtained after demodulation, the M setting unit 111 is supplied with information on the length of one T2 frame from the demodulation unit 21 (FIG. 5) to the M setting unit 111. The number 111 of clocks is set by the unit 111.

The number N of clocks set by the N setting unit 116 counts the number of clocks in one T2 frame period for each frame, and this count value is set to N. As shown in FIG. 14, the number of clocks in one T2 frame period is counted as N _ck1 [CK], N _ck2 [CK], N _ck3 [CK] _,. [CK]. N _ck1 [CK], N _ck2 [CK], N _ck3 [CK],..., N _ckN [CK] are the number of clocks observed in M [T], which is a fixed interval.

M and N are used, and as described above, the T unit clock generation unit 101 generates a T unit clock. That is, N _ck1 [CK], N _ck2 [CK], N _ck3 [CK],..., N _ckN [CK] are used,
N _ck1 : M, N _ck2 : M, N _ck3 : M, ..., N _ckN : M
A T-unit clock is generated at a frequency division ratio of If the N _ck1 clock period, the N _ck2 clock period, the N _ck3 clock period,..., The N _ckN clock period are used, a T-unit pulse is generated M times. This makes it possible to generate a T-unit clock that absorbs the frequency error of the system clock.

  In this way, the generation of the first stage clock is performed by using a ratio of a predetermined time, which is the length of the T2 frame read from the signaled information, and the number of system clocks existing at the predetermined time, and T A unit clock is generated.

  FIG. 15 shows a system clock pulse supplied to the T unit clock generation unit 101 from an output unit that outputs a system clock (not shown), and a T unit clock generated by the T unit clock generation unit 101 and supplied to the flip-flop 122. A unit clock pulse is shown. The upper part of FIG. 15 shows system clock pulses, and the lower part of FIG. 15 shows T unit clock pulses.

  In the T unit clock generation unit 101, N clocks per one frame time according to the clock number N acquired by counting the number of clocks in one frame and the clock number M representing the length of one frame. The system clock is divided by an N: M division ratio, so that a T unit clock of M clocks per frame time is generated.

  That is, the system clock is divided by a frequency division ratio of N: M according to the number of clocks M corresponding to the time read from the signaled information and the number of clocks N of the system clock existing within that time. As a result, a T unit clock is generated.

  The T unit clock generated in this way is supplied to the flip-flop 122 of the TS clock generator 102. Next, the TS clock generation unit 102 will be described. The TS clock generation unit 102 has the same configuration as the T unit clock generation unit 101, and the basic operation is the same as that of the T unit clock generation unit 101. . For this reason, redundant description will be omitted as appropriate in the following description.

With reference to FIG. 16, a description will be given of the clock number M and the clock number N in the TS clock generation unit 102. The clock number M and the clock number N are determined by observing the input side of the output I / F 23 (FIG. 6). As shown in the upper side of FIG. 16, two arbitrary ISCRs are extracted from ISSY inserted in units of TS packets, and the difference between the two ISCR values is N ₁ [T], N ₂ [T]. , N ₃ [T],..., N _n [T]. These N ₁ [T], N ₂ [T], N ₃ [T],..., N _n [T] are determined so as not to overlap or leak. The N is set by the N setting unit 126 observing the input of the output I / F 23.

The number of data bytes sandwiched between the two ISCR, M setting unit 121 observes, its number of data bytes _{M 1 [byte], M 2} [byte], M 3 [byte], ···, M n [Byte]. Using information obtained by monitoring the input to these output I / Fs 23, pulses in units of TS clocks such as M _x [byte] are generated in the N _x [T] period. The N _x [T] period is a period measured based on the T unit clock generated by the T unit clock generation unit 101. By doing this without interruption every N _x [T] interval, the TS clock does not accumulate errors in units of T and bytes, and the buffer 31 (FIG. 6) does not overflow or underflow at the TS clock. Can be generated.

  As described above, the generation of the second stage clock is performed by setting the ISCR difference read from the signaled information as a predetermined time, and from the ratio of the number of data bytes within the predetermined time, the desired clock, this If so, a TS clock is generated.

  FIG. 17 shows a T-unit pulse supplied from the T-unit clock generation unit 101 and a TS clock pulse output from the TS clock generation unit 102. 17 shows the pulse of the T unit clock, and the lower part of FIG. 17 shows the pulse of the TS clock. In the TS clock generation unit 102, N clocks corresponding to the number of clocks N that is the difference between the values of any two ISCRs from ISSY and the number of clocks M that is the number of data bytes sandwiched between the two ISCRs. The T unit clock is divided by a frequency division ratio of N: M, whereby an M clock TS is generated.

  That is, according to the clock number N corresponding to a predetermined time read from the signaled information (calculated from the two ISCRs) and the clock number M corresponding to the number of data bytes within the predetermined time, The TS clock is generated by dividing the T unit clock by the N: M division ratio.

  A T unit clock is supplied from the T unit clock generation unit 101 to the flip-flop 122 of the TS clock generation unit 102 that generates such a TS clock. The flip-flop 122 latches the data supplied from the selector 125 in synchronization with the supplied T-unit clock and supplies the latched data to the adder 123. The adder 123 adds the data supplied from the flip-flop 122 and the clock number M supplied from the M setting unit 121, and supplies the data A obtained as a result of the addition to the adder 124 and the selector 125. .

  The adder 124 is supplied with a value N which is a difference between two arbitrary ISCR values from ISSY as the clock number N. The adder 124 subtracts the data A from the clock number N by adding the clock number N and the value obtained by inverting the sign of the data A supplied from the adder 123, and the data obtained as a result of the subtraction B is supplied to the selector 125.

  Further, the adder 124 supplies the most significant bit (MSB) of the data B as a selection control signal to the selector 125 and also supplies it to the read control unit 34 (FIG. 6) as a TS clock. That is, when the data B is 0 or more, the adder 124 supplies the most significant bit 0 of the data B to the selector 125 as a selection control signal and supplies it to the read control unit 34 (FIG. 6) as a TS clock. To do. Further, when the data B is negative, the adder 124 supplies the most significant bit 1 of the data B to the selector 125 as a selection control signal and supplies it to the read control unit 34 (FIG. 6) as a TS clock.

  The selector 125 selects either the data A supplied from the adder 123 or the data B supplied from the adder 124 based on the selection control signal supplied from the adder 124, and the flip-flop Supplied to That is, the selector 125 selects the data A supplied from the adder 123 and supplies it to the flip-flop 122 when the selection control signal supplied from the adder 124, that is, when the most significant bit of the data B is 0. The selector 125 selects the data B supplied from the adder 124 and supplies it to the flip-flop 122 when the selection control signal supplied from the adder 124, that is, when the most significant bit of the data B is “1”.

  In this way, reading from the buffer 31 is performed based on the generated TS clock, so that TS can be output without underflow or overflow as shown in FIG. The upper diagram in FIG. 18 shows input and output. The input T2 frame is processed, and reading is performed based on the generated TS clock, so that the TS is output without interruption. The reason why the TS is output without interruption is that writing to the buffer 31 and reading from the buffer 31 are performed as in the timing chart shown in the lower part of FIG.

  In the timing chart shown at the bottom of FIG. 18, the horizontal axis represents the time axis, and the time direction is from left to right in the figure. The vertical axis represents the address of the data stored in the buffer 31, and means that the address advances as it goes up in the figure. In FIG. 18, dotted lines indicate write addresses, and solid lines indicate read addresses.

  As shown in FIG. 18, in the output I / F 23, when the TS packet of the T2 frame is input, the write control unit 32 starts storing the input TS packet in the buffer 31, and at the same time, the reading is performed. The control unit 34 starts reading the TS packet stored in the buffer 31. The reading is started based on the TTO. At this time, as shown in FIG. 18, the gradient indicating the speed of the write address and the read address is different, and the TS packets accumulated in the buffer 31 are read out after being accumulated to some extent.

  In the example of FIG. 18, the read (output) rate is a constant rate and is a rate based on the TS clock generated by the TS clock generation unit 102. In such a case, since the reading can be performed without catching up with the writing address, the TS non-output period does not occur.

  As described above, the buffered data is read based on the TS clock generated by the present technology, thereby causing a problem that the rate becomes faster or slower than the original output rate due to the frequency error of the system clock. It is possible to prevent the occurrence of underflow and overflow.

  In the above-described embodiment, DVB-T2 has been described as an example. However, the present technology can also be applied to other broadcasting systems such as DVB-C2.

  In the above-described embodiments, the system clock (clock required for operating the receiving device itself), the length of one frame (T2_frame_length), the difference between the ISCR values, and the ISCR are included. An example in which the clock (TS clock) to be finally obtained is generated using the number of data bytes has been described. Among these, T2_frame_length and ISCR are information signaled in the frame. As described above, according to the present technology, a desired clock is generated using a clock generated when the apparatus itself operates and information signaled in received data. Therefore, the present technology described above can be applied to any device that can acquire a clock and signaling.

[About recording media]
The series of processes described above can be executed by hardware or can be executed by software. When a series of processing is executed by software, a program constituting the software is installed in the computer. Here, the computer includes, for example, a general-purpose personal computer capable of executing various functions by installing various programs by installing a computer incorporated in dedicated hardware.

  FIG. 19 is a block diagram illustrating an example of a hardware configuration of a computer that executes the series of processes described above according to a program. In a computer, a CPU (Central Processing Unit) 201, a ROM (Read Only Memory) 202, and a RAM (Random Access Memory) 203 are connected to each other via a bus 204. An input / output interface 205 is further connected to the bus 204. An input unit 206, an output unit 207, a storage unit 208, a communication unit 209, and a drive 210 are connected to the input / output interface 205.

  The input unit 206 includes a keyboard, a mouse, a microphone, and the like. The output unit 207 includes a display, a speaker, and the like. The storage unit 208 includes a hard disk, a nonvolatile memory, and the like. The communication unit 209 includes a network interface and the like. The drive 210 drives a removable medium 211 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory.

  In the computer configured as described above, the CPU 201 loads, for example, the program stored in the storage unit 208 to the RAM 203 via the input / output interface 205 and the bus 204 and executes the program, and the series described above. Is performed.

  The program executed by the computer (CPU 201) can be provided by being recorded in, for example, a removable medium 211 such as a package medium. The program can be provided via a wired or wireless transmission medium such as a local area network, the Internet, or digital satellite broadcasting.

  In the computer, the program can be installed in the storage unit 208 via the input / output interface 205 by attaching the removable medium 211 to the drive 210. The program can be received by the communication unit 209 via a wired or wireless transmission medium and installed in the storage unit 208. In addition, the program can be installed in advance in the ROM 202 or the storage unit 208.

  The program executed by the computer may be a program that is processed in time series in the order described in this specification, or in parallel or at a necessary timing such as when a call is made. It may be a program for processing.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  In addition, this technique can also take the following structures.

(1) A data reading device comprising: a generation unit that generates a clock for reading the buffered data from a system clock and information signaled to the data.

(2) The generation unit includes:
A first clock generator for generating a first clock using a ratio of the number of system clocks existing during a first time read from the signaled information;
A second clock generation unit that generates a second clock based on a ratio between a second time read from the signaled information and the number of data bytes in the second time; and the data according to (1) Reading device.

(3) The generation unit includes:
According to the number of clocks M corresponding to the first time read from the signaled information and the number of clocks N of the system clock existing within the first time, the system clock is expressed as N: M A first clock generation unit that generates a first clock by dividing the frequency by a division ratio of
Depending on the number of clocks N corresponding to the second time read from the signaled information and the number of clocks M corresponding to the number of data bytes within the second time, the first clock is N A second clock generation unit that generates a second clock by dividing by a frequency division ratio of M, and the data reading device according to (1).

(4) The data reading device according to any one of (1) to (3), wherein the signaled information is a length of one T2 frame in DVD-T2 and ISCR.

(5) The generation unit includes:
The length of the T2 frame is defined as a first time, and a first clock corresponding to the unit of the length of the T2 frame is generated from the ratio of the number of system clocks existing during the first time. 1 clock generator;
A difference between the two ISCR values as a second time, and a second clock generation unit that generates a second clock based on a ratio to the number of data bytes in the second time; and (4) Data reading device.

(6) In a data reading method of a data reading device including a buffer for buffering data,
Obtaining information signaled in the data;
A data reading method including a step of generating a clock for reading the data buffered in the buffer from the information and a system clock.

(7) A computer that executes a data reading process of a data reading device including a buffer for buffering data;
Controlling the acquisition of information signaled in the data;
A program for executing processing including a step of controlling generation of a clock for reading out the data buffered in the buffer from the information and a system clock.

  DESCRIPTION OF SYMBOLS 10 Receiver, 11 Antenna, 12 Acquisition part, 13 Transmission path decoding process part, 14 Decoder, 15 Output part, 21 Demodulator, 22 Error correction part, 23 Output I / F, 31 Buffer, 32 Write control part, 33 Reading Rate calculation unit, 34 readout control unit, 100 clock generation unit, 101 T unit clock generation unit, 111 M setting unit, 112 flip-flop, 113 adder, 114 adder, 115 selector, 111 TS clock generation unit, 121 M setting Part, 122 flip-flop, 123 adder, 124 adder, 125 selector

Claims (3)

A generation unit that generates a clock for reading out the buffered data from a system clock generated when the device itself operates and information signaled in the received data;
The signaled information is the length of one T2 frame in DVD-T2 and ISCR,
The generator is
The length of the T2 frame is a first time, the number of clocks M 1 set as the number of clocks corresponding to the first time, and the number of clocks N 1 of the system clock existing within the first time. And a first clock generation unit that generates a first clock by dividing the system clock by a division ratio of N 1 : M 1 ,
As a clock for reading out the buffered data, the difference between the two ISCR values is set as a second time, the number of clocks N 2 corresponding to the second time, and the data within the second time A second clock generation unit that generates a second clock by dividing the first clock at a frequency division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of bytes. A data reading device comprising: In a data reading method of a data reading device including a buffer for buffering data,
Generating a clock for reading out the buffered data from a system clock generated when the device itself operates and information signaled in the received data;
The signaled information is the length of one T2 frame in DVD-T2 and ISCR,
The generation is
The length of the T2 frame is a first time, the number of clocks M 1 set as the number of clocks corresponding to the first time, and the number of clocks N 1 of the system clock existing within the first time. And generating a first clock by dividing the system clock by a division ratio of N 1 : M 1 ,
As a clock for reading out the buffered data, the difference between the two ISCR values is set as a second time, the number of clocks N 2 corresponding to the second time, and the data within the second time A data reading method including a step of generating a second clock by dividing the first clock by a division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of bytes . In a computer that executes a data reading process of a data reading device including a buffer for buffering data,
Generating a clock for reading out the buffered data from a system clock generated when the device itself operates and information signaled in the received data;
The signaled information is the length of one T2 frame in DVD-T2 and ISCR,
The generation is
The length of the T2 frame is a first time, the number of clocks M 1 set as the number of clocks corresponding to the first time, and the number of clocks N 1 of the system clock existing within the first time. And generating a first clock by dividing the system clock by a division ratio of N 1 : M 1 ,
As a clock for reading out the buffered data, the difference between the two ISCR values is set as a second time, the number of clocks N 2 corresponding to the second time, and the data within the second time A process including a step of generating a second clock by dividing the first clock by a frequency division ratio of N 2 : M 2 according to the number of clocks M 2 corresponding to the number of bytes is executed. Program to let you.

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