JP5767941B2 - Inductive load drive - Google Patents

Description

The present invention relates to an inductive load driving device.

  In Patent Document 1 below, a first switching element interposed between one end of an inductive load and an external power supply, and a second switching element interposed between the other end of the inductive load and ground. A switching circuit, a reflux circuit for returning a back electromotive current generated in the inductive load to the inductive load through the ground when the first switching element is off and the second switching element is on, and the first and second An inductive load driving device is disclosed that includes a counter electromotive current reduction circuit that reduces (regenerates) a counter electromotive current generated in an inductive load to an external power supply when both of the switching elements are off.

  In the inductive load driving apparatus having such a configuration, the rise of the load current is controlled by controlling the ratio (duty ratio) of the ON / OFF period of the first switching element while maintaining the second switching element in the ON state. Properties can be controlled. Further, by controlling the duty ratio of the second switching element while maintaining the first switching element in the OFF state, the back electromotive current generated in the inductive load is controlled while controlling the falling characteristic of the load current. Can be regenerated.

JP 2008-85046 A

  Although not specified in the above-mentioned Patent Document 1, as a method for arbitrarily controlling the waveform of the load current flowing through the inductive load, a shunt resistor is provided between the second switching element and the ground, and the terminal voltage of this shunt resistor is Is sampled by a sample and hold circuit, and the sampling value (that is, the load current value) is fed back to a microcomputer that performs switching control.

In the technique of Patent Document 1, the second switching is performed in a period in which the duty ratio of the second switching element is controlled while maintaining the first switching element in the off state (period in which the falling waveform of the load current is controlled). When the element is on, the load current flows through the route of inductive load → second switching element → earth → circulation circuit → inductive load (current circulation route). When the second switching element is off, the load current flows The current flows through a route (current regeneration route) of earth, reflux circuit, inductive load, back electromotive force reduction circuit, and external power supply.

  Therefore, to sample the load current during the period when the falling waveform of the load current is controlled, the sample switch of the sample hold circuit is turned on and the voltage across the shunt resistor is sampled during the period when the load current flows through the current return route. In addition, it is necessary to turn off the sample switch and hold the voltage across the terminals of the shunt resistor (hold the charge in the hold capacitor) while the load current flows through the current regeneration route.

  Here, when switching from the current regeneration route to the current return route, that is, when switching the second switching element from OFF to ON, the second switching element is delayed from the sampling timing (sample switch ON timing) due to circuit factors. When is switched on, there is a problem in that the hold capacitor loses charge and the follow-up of current value sampling decreases (current detection accuracy decreases).

The present invention has been made in view of the above-described circumstances, and is an inductive load drive capable of realizing improvement in current detection accuracy by suppressing charge loss of a hold capacitor when switching from a current regeneration route to a current return route. An object is to provide an apparatus.

In order to achieve the above object, in the present invention, as a first solving means related to an inductive load driving device, a first switching element interposed between a power source and one end of an inductive load, and the inductive load A second switching element interposed between the other end of the inductive load and the ground, and an output from the other end of the inductive load when the first switching element is off and the second switching element is on When the both the first and second switching elements are turned off, and the return circuit for returning the counter electromotive current to the one end of the inductive load through the ground, the other end of the inductive load is output. From the inductive load drive circuit comprising a back electromotive current regeneration circuit for regenerating the back electromotive current to the power source, and a shunt resistor interposed between the second switching element and the ground, the inductive load Drive supplied An inductive load driving device for detecting a flow, a differential amplifier having two input terminals connected to both ends of the shunt resistor, a processor for controlling the first and second switching elements, and the differential amplifier A sample switch inserted in a wiring connecting the output terminal of the first switch and the sample switch after a predetermined delay time has elapsed since a control signal output from the processor to the second switching element has shifted to an on level. A means of providing a delay circuit to be turned on is adopted.

According to the present invention, as the second solving means related to the inductive load driving device, in the first solving means, the delay circuit has an ON control signal output from the processor to the second switching element. A means is adopted in which the sample switch is turned on after a delay time determined by the capacitance of the capacitor has elapsed since the transition to the level.

  Further, in the present invention, as a third solving means related to the inductive load driving device, in the second solving means, an external terminal used for externally attaching the delay circuit and the capacitor, and the external attaching A means of providing an external capacitor connected to the terminal is adopted.

  According to the present invention, the sample switch is turned on after a lapse of a predetermined delay time after the control signal output from the processor to the second switching element transits to the on level. Even if the timing at which the second switching element is actually switched on after the transition to the on-level is delayed, the sampling timing and the on-timing of the second switching element can be made coincident with each other. It is possible to improve the current detection accuracy by suppressing the charge loss of the hold capacitor when switching from the route to the current return route.

It is a schematic block diagram of the inductive load drive device 1 which concerns on this embodiment. 2 is a diagram illustrating a detailed circuit configuration of a delay circuit 109 provided in the control circuit 100. FIG. Temporal correspondence relationship between the first control signal S1, the second control signal S2, and the third control signal S3 output from the control circuit 100 to the inductive load drive circuit 200 and the drive current flowing through the inductive load L It is a timing chart which shows. It is a figure which shows the effect (The charge loss suppression effect of hold capacitor Ch at the time of switching from a current regeneration route to a current return route) of this embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of an inductive load driving device 1 according to the present embodiment. As shown in FIG. 1, the inductive load driving device 1 includes a control circuit 100, an inductive load driving circuit 200, and a processor 300 such as a CPU. The inductive load drive circuit 200 supplies a drive current to the inductive load L such as a solenoid coil or a motor coil under the control of the processor 300, and a first load connected to one end of the inductive load L. A connection terminal 201, a second load connection terminal 202 connected to the other end of the inductive load L, a first switching element 203, a second switching element 204, a third switching element 205, a regeneration A diode 206 and a shunt resistor 207 are provided.

  The first switching element 203 is an n-type inserted between a power supply PL1 to which a relatively high power supply voltage (for example, 30 V) is applied and the first load connection terminal 201 (that is, one end of the inductive load L). The MOS-FET has a drain terminal connected to the power supply PL1, a source terminal connected to the first load connection terminal 201, and a gate terminal connected to the control circuit 100 (first control signal output terminal 113). . The first switching element 203 is switched on / off according to a first control signal (pulse width modulated signal) S1 input from the processor 300 via the control circuit 100.

The second switching element 204 is an n-type MOS-FET interposed between the second load connection terminal 202 (that is, the other end of the inductive load L) and the ground, and the drain terminal is the second load. Connected to the connection terminal 202, the source terminal is connected to the ground via the shunt resistor 207, and the gate terminal is connected to the control circuit 100 (second control signal output terminal 114). The second switching element 204 is switched between on and off states according to a second control signal S2 input from the processor 300 via the control circuit 100.

  The third switching element 205 is inserted between the first load connection terminal 201 (that is, one end of the inductive load L) and the ground so that the on / off state is reversed with respect to the first switching element 203. The n-type MOS-FET to be controlled has a drain terminal connected to the first load connection terminal 201, a source terminal connected to the ground, and a gate terminal connected to the control circuit 100 (third control signal output terminal 115). It is connected.

The third switching element 205 is switched between on and off states according to a third control signal S3 (a signal whose level is inverted with respect to the first control signal S1) input from the control circuit 100. The third switching element 205 transmits a back electromotive current output from the other end of the inductive load L via the ground when the first switching element 203 is off and the second switching element 204 is on. This circuit is provided as a reflux circuit for refluxing to one end of the inductive load L.

The regenerative diode 206 has an anode terminal connected to the second load connection terminal 202 and a cathode terminal connected to the power supply PL1. The regenerative diode 206 is provided as a back electromotive current regeneration circuit that regenerates the back electromotive current output from the other end of the inductive load L to the power source PL1 when both the first and second switching elements 203 and 204 are off. It is what was done. The shunt resistor 207 is a resistance element used for detecting the drive current flowing through the inductive load L by the control circuit 100, and one end is connected to the source terminal of the second switching element 204 and the other end is connected to the ground. Has been.

  On the other hand, the control circuit 100 is a custom IC that detects the drive current supplied from the inductive load drive circuit 200 to the inductive load L, and includes a first input circuit 101, a second input circuit 102, The first output circuit 103, the second output circuit 104, the first inverter 105, the third output circuit 106, the operational amplifier 107, the sample switch 108, and the delay circuit 109 are provided.

The control circuit 100 also includes a first control signal input terminal 111 for inputting the first control signal S1 from the processor 300 and a second control for inputting the second control signal S2 from the processor 300. A signal input terminal 112, a first control signal output terminal 113 connected to the gate terminal of the first switching element 203, and a second control signal output terminal 114 connected to the gate terminal of the second switching element 204. The third control signal output terminal 115 connected to the gate terminal of the third switching element 205, the first resistance connection terminal 116 connected to one end of the shunt resistor 207, and the other end of the shunt resistor 207. The connected second resistance connection terminal 117 is connected to the A / D input port of the processor 300 and the hold capacitor Ch is connected. A sample output terminal 118, and an external terminal 119 used for connecting an external capacitor Cd.

  The first control signal S1 input from the processor 300 to the first control signal input terminal 111 passes through the first input circuit 101 and the first output circuit 103, and then passes through the first control signal output terminal 113. Via the first switching element 203. On the other hand, the second control signal S2 input from the processor 300 to the second control signal input terminal 112 passes through the second input circuit 102 and the second output circuit 104, and then the second control signal output terminal. It is output to the second switching element 204 via 114.

  The first control signal S 1 branches from the first input circuit 101 and is input to the first inverter 105. The first inverter 105 inverts the level of the first control signal S1 input from the first input circuit 101, and uses the third control signal S3 as the third control signal S3. Output to the output circuit 106. The third control signal S3 passes through the third output circuit 106 and is then output to the third switching element 205 via the third control signal output terminal 115.

Note that the first input circuit 101 and the second input circuit 102 are constituted by, for example, a pull-down resistor, a Schmitt circuit, or the like, and the first output circuit 103, the second output circuit 104, and the third output circuit 106. Is composed of, for example, a level shifter and an output buffer.

  The operational amplifier 107 has a non-inverting input terminal connected to the first resistor connection terminal 116 (that is, one end of the shunt resistor 207), and an inverting input terminal connected to the second resistor connection terminal 117 (that is, the other end of the shunt resistor 207). The differential amplifier amplifies the voltage across the shunt resistor 207 and outputs it.

The sample switch 108 is a sample-and-hold switching element inserted in a wiring connecting the output terminal of the operational amplifier 107 and the processor 300 (more specifically, a wiring connecting the output terminal of the operational amplifier 107 and the sample output terminal 118). Yes, the on / off state is switched according to the sample timing signal S4 input from the delay circuit 109 described later.

The delay circuit 109 receives the second control signal S2 branched from the second input circuit 102, and after the second control signal S2 transitions to an on level (high level in this embodiment), A sample timing signal S4 for turning on the sample switch 108 is output to the sample switch 108 after a delay time determined by the capacitance of the capacitor Cd externally attached to the external terminal 119.

Specifically, as shown in FIG. 2, the delay circuit 109 includes a second inverter 121, a control switching element 122, for example, an n-type MOS-FET, a constant current source 123, a resistance element 124, and a comparator. 125. The second inverter 121 is a level inverting circuit that inverts the level of the second control signal S <b> 2 input from the second input circuit 102 and outputs the inverted signal to the gate terminal of the control switching element 122.

The control switching element 122 has a drain terminal connected to a low voltage (for example, 3.3V) power supply PL2 via a constant current source 123, a source terminal connected to the ground, and a gate terminal output from the second inverter 121. The on / off state is switched according to the second control signal S2 after level inversion input from the second inverter 121 and connected to the terminal. The constant current source 123 generates a constant current, and has one end connected to the power supply PL2 and the other end connected to the drain terminal of the control switching element 122.

One end of the resistance element 124 is connected to the other end of the constant current source 123, and the other end is connected to an external terminal 119 for externally attaching a capacitor Cd. The comparator 125 has a non-inverting input terminal connected to the other end of the constant current source 123, and when the reference voltage V1 applied to the non-inverting input terminal becomes equal to or higher than the reference voltage Vref applied to the inverting input terminal. An on level (high level) sample timing signal S4 for turning on the sample switch 108 is output, and an off level (low level) for turning off the sample switch 108 when the reference voltage V1 becomes less than the reference voltage Vref. ) Sample timing signal S4.

According to the delay circuit 109 having such a configuration, when the second control signal S2 transits to a high level, the control switching element 122 is turned off and the external capacitor Cd starts to be charged. As the capacitor Cd is charged, the reference voltage V1 applied to the non-inverting input terminal of the comparator 125 increases, and the sample timing signal that is the output of the comparator 125 when the reference voltage V1 becomes equal to or higher than the reference voltage Vref. S4 switches to high level.

On the other hand, when the second control signal S2 transitions to a low level, the control switching element 122 is turned on, and the electric charge stored in the capacitor Cd starts to be discharged to the ground. As the capacitor Cd is discharged, the reference voltage V1 applied to the non-inverting input terminal of the comparator 125 decreases and the sample timing signal S4 is switched to the low level when the reference voltage V1 becomes less than the reference voltage Vref. Change.

As described above, by adopting the delay circuit 109 of this embodiment, the delay time (determined by the capacitance of the capacitor Cd externally attached to the external terminal 119 after the second control signal S2 transits to the high level ( The sample switch 108 can be turned on after the elapse of the time from when the reference voltage V1 starts to rise to the reference voltage Vref or higher.

The processor 300 detects the voltage between the terminals of the shunt resistor 207 by A / D converting the input voltage to the A / D input port, and converts the voltage between the terminals of the shunt resistor 207 into a drive current value. The feedback control of the first and second switching elements 203 and 204 (duty ratio control of the first and second control signals S1 and S2) is performed so that the drive current value matches the target value.

Next, the operation of the inductive load driving device 1 configured as described above will be described in detail with reference to FIG.
FIG. 3 shows the time of the first control signal S1, the second control signal S2, and the third control signal S3 output from the control circuit 100 to the inductive load drive circuit 200 and the drive current flowing through the inductive load L. It is a timing chart which shows a typical correspondence.

  As shown in FIG. 3, in the period from the time t1 to the time t2, the first control signal S1 and the third control signal S3 that have a predetermined duty ratio and whose levels are mutually inverted, and the on-state A second control signal S 2 having a constant level (high level) is output from the control circuit 100 to the inductive load driving circuit 200. That is, in the period from time t1 to time t2, the first switching element 203 and the third switching element 205 are controlled to be turned on / off at a predetermined duty ratio while the second switching element 204 is maintained in the on state. Is done. Note that the on / off state of the third switching element 205 is inverted with respect to the first switching element 203.

  In such a period from time t1 to time t2, when the first switching element 203 is on and the third switching element 205 is off, one end of the inductive load L is connected to the power source via the first switching element 203. The other end of the inductive load L is connected to the ground via the second switching element 204. At this time, since the power supply voltage (about 30 V) is applied to the inductive load L, the drive current flowing through the inductive load L increases with a certain slope. The drive current at this time flows through a route (load energization route) of power supply PL1 → first switching element 203 → inductive load L → second switching element 204 → earth.

  On the other hand, during the period from time t1 to time t2, when the first switching element 203 is off and the third switching element 205 is on, one end of the inductive load L is grounded via the third switching element 205. Connected (the other end of the inductive load L remains connected to the ground via the second switching element 204). At this time, since the power supply voltage is not applied to the inductive load L, a counter electromotive voltage is generated in the inductive load L, and a counter electromotive current is output from the other end of the inductive load L.

This back electromotive current flows into the ground via the second switching element 204 and then flows back to one end of the inductive load L via the third switching element 205. That is, the drive current flows through a route (current return route) of inductive load L → second switching element 204 → ground → third switching element 205 → inductive load L. As a result, even when the first switching element 203 is turned off, the drive current of the inductive load L is kept constant (strictly, it can be ignored although it decreases).

As described above, in the period from time t1 to time t2, the first switching element 203 and the third switching element are switched so that the on / off states are reversed while the second switching element 204 is maintained in the on state. By performing PWM control or on / off control of 205, the rising characteristics of the drive current flowing through the inductive load L can be controlled.

Note that in the period from time t1 to time t2 (period in which the second control signal S2 is always at a high level), the sample circuit 108 always outputs a sample timing signal S4 at a high level from the delay circuit 109. Is always on, and the voltage across the shunt resistor 207 is continuously input from the operational amplifier 107 to the A / D input port of the processor 300. That is, the processor 300 always maintains the second control signal S2 at the high level during the period from time t1 to time t2, and the drive current value converted from the voltage across the shunt resistor 207 matches the target value. In this way, feedback control of the first switching element 203 (duty ratio control of the first control signal S1) is performed.

  Subsequently, in a period from time t2 to time t3, the first control signal S1 having a constant high level, the third control signal S3 having a constant high level, and a pulse-shaped second control having a predetermined duty ratio. The signal S2 is output from the control circuit 100 to the inductive load driving circuit 200. That is, in the period from time t2 to time t3, the second switching element 204 is turned on / off at a predetermined duty ratio while the first switching element 203 is kept off and the third switching element 205 is kept on. Controlled off.

  In such a period from time t2 to time t3, when the second switching element 204 is off, one end of the inductive load L is connected to the ground via the third switching element 205, and the inductive load L The other end is connected to the power supply PL1 via the regenerative diode 206. At this time, since no power source voltage is applied to the inductive load L, a counter electromotive voltage is generated in the inductive load L.

  When the back electromotive voltage becomes larger than the power supply voltage, a back electromotive current is regenerated from the other end of the inductive load L to the power supply PL1 via the regenerative diode 206. That is, the drive current flowing through the inductive load L flows through a route (current regeneration route) of ground → third switching element 205 → inductive load L → regenerative diode 206 → power source PL1. As a result, the drive current of the inductive load L decreases with a constant slope.

On the other hand, during the period from time t2 to time t3, when the second switching element 204 is on, the other end of the inductive load L is connected to the ground via the second switching element 204 (inductive load L Is connected to the ground via the third switching element 205). At this time, since the power supply voltage is not applied to the inductive load L, a counter electromotive voltage is generated in the inductive load L, and the counter electromotive current from the other end of the inductive load L is grounded through the second switching element 205. Then, it flows back to one end of the inductive load L via the third switching element 205 (a driving current flows through the current return route). As a result, the drive current is kept constant (strictly decreases, but can be ignored).

In this manner, during the period from time t2 to time t3, PWM control is performed on the second switching element 204 while maintaining the first switching element 203 in the off state and the third switching element 205 in the on state. The falling characteristic of the drive current flowing through the inductive load L can be controlled.

In such a period from time t2 to time t3 (period in which the falling waveform of the drive current is controlled), a period in which the drive current flows in the current return route (a period in which the second switching element 204 is on), a current Periods in which the drive current flows through the regeneration route (periods in which the second switching element 204 is off) appear alternately.

Therefore, in order to sample the drive current value during the period for controlling the falling waveform of the drive current, the sample switch 108 is turned on during the period when the drive current flows in the current return route, and the voltage across the shunt resistor 207 is sampled. It is necessary to turn off the sample switch 108 and hold the voltage across the shunt resistor 207 (hold the charge in the hold capacitor Ch) while the drive current flows through the current regeneration route.

Here, conventionally, as shown in FIG. 4A, when switching from the current regeneration route to the current return route, that is, when the second switching element 204 is switched from OFF to ON, the sampling timing ( When the second switching element 204 is turned on after the sample switch 108 is turned on, the charge of the hold capacitor Ch is lost, and the follow-up capability of current value sampling is lowered (current detection accuracy is lowered). There was a problem.

In contrast, the delay circuit 109 according to the present embodiment, as described above, has a delay determined by the capacitance of the capacitor Cd externally attached to the external terminal 119 after the second control signal S2 transitions to a high level. After a lapse of time, the sample switch 108 can be turned on by outputting a high level sample timing signal S4.

That is, by adjusting the capacitance of the capacitor Cd, the delay time from when the second control signal S2 transitions to the high level until the sample timing signal S4 switches to the high level, the second control signal S2 is at the high level. As shown in FIG. 4B, the sampling timing (on timing of the sample switch 108) and the second timing are made to coincide with the delay time until the second switching element 204 is actually turned on after the transition to. The ON timing of the second switching element 204 can be matched.

As described above, according to the present embodiment, even if the timing at which the second switching element 204 is actually turned on is delayed after the second control signal S2 transitions to a high level due to circuit factors. Thus, the sampling timing and the on-timing of the second switching element 204 can be made coincident with each other, and as a result, the charge detection of the hold capacitor Ch at the time of switching from the current regeneration route to the current return route is suppressed, and the current detection accuracy is improved. Improvements can be realized.

In addition, this invention is not limited to the said embodiment, The following modifications are mentioned.
(1) In the above embodiment, the circuit configuration as shown in FIG. 2 is given as a specific example of the delay circuit 109. However, the second control signal S2 output to the second switching element 204 transitions to the on level. Any circuit configuration may be employed as long as the sample switch 108 can be turned on after a predetermined delay time has elapsed.
Further, it is not always necessary to provide the capacitor Cd externally, and a configuration in which a capacitor Cd having an optimized capacity is provided in the delay circuit 109 in advance may be employed. Further, a configuration in which the hold capacitor Ch is provided inside the control circuit 100 may be employed.

(2) In the above embodiment, the back electromotive current regeneration circuit including the regenerative diode 206 has been exemplified. However, when both the first and second switching elements 203 and 204 are off, the output is output from the other end of the inductive load L. As long as the back electromotive current can be regenerated in the power source PL1, the configuration of the back electromotive current regeneration circuit is not limited to this. For example, a counter electromotive current reduction circuit (synonymous with a counter electromotive current regeneration circuit) as described in JP 2008-85046 A may be used.

(3) In the above embodiment, the reflux circuit including the third switching element 205 is illustrated, but from the other end of the inductive load L when the first switching element 203 is off and the second switching element 204 is on. The configuration of the return circuit is not limited to this as long as the back electromotive force that is output can be returned to one end of the inductive load L through the ground. For example, a reflux circuit as described in JP 2008-85046 A may be used.

1. Inductive load driving device 100 Control circuit 200 Inductive load driving circuit 300 Processor 107 Operational amplifier (differential amplifier) 108 Sample switch 109 Delay circuit 119 External terminal 203-1st switching element, 204-2nd switching element, 205-3rd switching element (reflux circuit), 206-Regenerative diode (back electromotive force regeneration circuit), 207-Shunt resistance, Cd-capacitor, Ch・ Hold capacitor

Claims (3)

A first switching element interposed between the power source and one end of the inductive load;
A second switching element interposed between the other end of the inductive load and the ground;
Reflux that causes a back electromotive current output from the other end of the inductive load to return to one end of the inductive load via the ground when the first switching element is off and the second switching element is on. Circuit,
A counter electromotive current regeneration circuit that regenerates a counter electromotive current output from the other end of the inductive load to the power supply when both the first and second switching elements are off;
A shunt resistor interposed between the second switching element and ground;
An inductive load driving device for detecting a driving current supplied to the inductive load from an inductive load driving circuit comprising:
A differential amplifier having two input terminals connected to both ends of the shunt resistor;
A sample switch interposed in a wiring connecting a processor for controlling the first and second switching elements and an output terminal of the differential amplifier;
A delay circuit that turns on the sample switch after a lapse of a predetermined delay time after a control signal output from the processor to the second switching element transits to an on level;
An inductive load driving device comprising:   The delay circuit turns on the sample switch after a lapse of a delay time determined by a capacitance of a capacitor after a control signal output from the processor to the second switching element transitions to an on level. The inductive load driving device according to claim 1. And external terminal used for connecting an external said capacitor to said delay circuit,
The inductive load driving device according to claim 2, further comprising an external capacitor connected to the external terminal.

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