JP5758434B2 - ΔΣ A / D converter - Google Patents

Description

  The present invention relates to a ΔΣ A / D converter using a probabilistic A / D converter using the statistical properties of a large number of comparators in a multi-bit quantizer of a ΔΣ A / D modulator.

  In recent years, with the development of the information society, the demand for wireless communication technology is also increasing. Information communication terminals such as mobile phones are required to have higher functions, smaller sizes, and lower power consumption, and a fine CMOS process is indispensable. On the other hand, with the miniaturization of the CMOS process, device variations are relatively increased, and the accompanying deterioration in circuit performance is a problem. For this reason, it is difficult to achieve both miniaturization of the CMOS process and high accuracy of the circuit.

  Generally, in an electronic circuit, noise and device variations deteriorate circuit performance, but there are cases where such noise and variations are useful. This is a stochastic resonance phenomenon in which a signal below a threshold value is amplified due to noise and variations. By using this phenomenon in an electronic circuit, it is considered that a weak signal that could not be detected in the past can be detected, and the resolution of the signal processing system can be increased.

  Device variations are statistical and many follow a Gaussian distribution. By making positive use of this statistical property, it becomes possible to detect a weak signal that is equal to or lower than the threshold value, and the resolution of the circuit system can be improved.

  For example, Patent Document 1 proposes an A / D conversion device that can detect a signal even when a large amount of noise is included inside the circuit by performing signal processing based on statistical properties of internal noise. In the A / D converter, a plurality of comparators are arranged in an array, and two threshold values B and -B are used. The number N + of comparators whose input signals exceed the threshold value B, and threshold values A small input signal waveform buried in noise is estimated from the number N− of comparators that are less than −B. Thereby, the dynamic range of A / D conversion can be greatly improved by applying this apparatus to a communication receiver.

  Non-Patent Document 1 proposes a design method for a high-speed sampling parallel A / D converter using element characteristic mismatch. In order to solve the problem of performance degradation of the A / D converter, an A / D converter that can effectively use the offset of the comparator and detect a signal below the offset is proposed. Here, it is confirmed that a signal is detected from the statistical property of the offset without requiring a technique for reducing the offset or a calibration circuit for canceling the offset.

JP 2010-045622 A JP 2010-245765 A

Ham Hyun-ju et al., "Design of high-speed sampling parallel type stochastic A / D converter using device characteristic mismatch", IEEJ Transactions C (Electronics, Information & Systems Division), Vol.131, No.11, pp .1848-1857, November 2011

  However, since the A / D conversion devices proposed in Patent Document 1 and Non-Patent Document 1 have a parallel configuration using an array of many comparators, there is a problem that it is difficult to improve the dynamic range as it is. It was.

  In order to overcome this problem, when it is applied to a ΔΣ A / D converter, the required performance of D / A converter dynamic element matching (DEM) becomes strict. As the circuit becomes complicated, the circuit becomes complicated, the occupied area increases, and the power consumption increases. Here, DEM is a method of averaging the mismatch by reducing the influence by using a plurality of unit analog elements, changing the number of selections according to the analog output, and cyclically selecting the elements. For example, see Patent Document 2).

  An object of the present invention is to provide an A / D conversion apparatus that solves the above-described problems and does not use a DEM, has a simple circuit configuration compared to the prior art, and can perform A / D conversion stably with high accuracy. There is.

The A / D converter according to the present invention is
Subtracting means for subtracting the analog voltage from the D / A conversion means from the input analog voltage and outputting the analog voltage of the subtraction result;
A filter that outputs the analog voltage from the subtracting means by low-pass or band-pass filtering;
Including a plurality of quantizers each having nonlinear input / output characteristics, having a plurality of variable quantization levels, and A / D converting the analog voltage from the filter into digital data of a first bit code A / D conversion means for outputting;
The D / A conversion means for D / A converting the digital data of the first bit code from the A / D conversion means into an analog voltage and outputting the analog data to the subtraction means;
A mapping table for decoding digital data of the first bit code into digital data of a second bit code having a number of bits larger than the number of bits of the first bit code; the digital data bits code decoding means and outputting the decoded digital data of the second bit codes,
Control means for setting at least one of the plurality of quantization levels of the A / D conversion means and the mapping table of the decoding means so that the error of the D / A conversion means is minimized ;
The decoding means corrects nonlinear input / output characteristics of each quantizer of the A / D conversion means so as to obtain digital data of the second bit code linearly corresponding to the input analog voltage. And decoding .

In the A / D conversion device, the A / D conversion means includes:
A parallel type stochastic A that includes a plurality of comparators each having a different threshold value and an adder that adds output signals from the plurality of comparators, and A / D converts the analog voltage from the filter into digital data / D conversion means;
Digital quantization means having a plurality of changeable quantization levels and digitally quantizing digital data from the parallel stochastic A / D conversion means to output digital data of a predetermined first bit code; It is characterized by having.

Also, in the A / D converter, said control means, upon inputting a predetermined reference signal, and the digital data output from the A / D converter, the reference signal from the A / D converter by minimizing the error between the digital data when a / D conversion by at even higher precision a / D conversion another a / D converter possible to minimize the error of the D / a converter It is characterized by that.

  Further, in the A / D conversion apparatus, the control means may convert at least one of a plurality of quantization levels of the digital quantization means and a mapping table of the decoding means to an error of the D / A conversion means. It is characterized in that it is adapted so as to minimize.

Still further, in the A / D conversion device, the plurality of comparators of the A / D conversion means are configured by being divided into a first comparator group and a second comparator group,
Each threshold value of the first comparator group is set to a standard deviation of a predetermined offset,
Each threshold value of the second comparator group is set to a value of an opposite sign of the standard deviation of the offset.

The A / D conversion device according to the present invention has the following effects.
(1) It is possible to provide an A / D converter that does not use a DEM, has a simpler circuit configuration than the prior art, and can perform A / D conversion stably with high accuracy. As a result, the A / D converter can be reduced in power and area.
(2) In the A / D converter, the statistical property of the comparator offset is analyzed and controlled, a signal below the offset level can be detected, and a dynamic range can be secured even in a fine process with a large element characteristic mismatch.
(3) The design efficiency of the high-accuracy ΔΣ A / D converter is improved, and it becomes easy to respond to market demands and manufacturing technology changes.

1 is a block diagram showing a configuration of a ΔΣ A / D conversion device 100 according to an embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration of a general feedback type ΔΣ modulator. It is a circuit diagram which shows the structure of a general feedforward type delta-sigma modulator. It is a circuit diagram showing an equivalent circuit of a ΔΣ A / D conversion device used in the present embodiment. 5 is a table showing numerical examples of gains of the multipliers in FIG. 4. It is a block diagram which shows the structure of the parallel type A / D converter which concerns on a prior art. 8 is a graph showing a probability density distribution with respect to a threshold value of a comparator in the parallel type A / D converter of FIG. 7. It is a block diagram which shows the structure of the parallel type | mold stochastic A / D converter (henceforth a SF-A / D converter) used as a quantizer in this embodiment. 9 is a graph showing a probability density distribution with respect to a threshold value of a comparator in the SF-A / D converter of FIG. 8. It is a block diagram which shows the structure of the modification of the SF-A / D converter of FIG. It is a graph which shows the probability density distribution with respect to the threshold value of a comparator in the modification of the SF-A / D converter of FIG. It is a graph which shows the cumulative probability density distribution with respect to the threshold value of a comparator in the modification of the SF-A / D converter of FIG. It is a circuit diagram which shows the structural example of the multibit D / A converter which concerns on a prior art. It is a graph which shows the relationship of the comparator number N of 1 output with respect to the quantizer input voltage in this embodiment. It is a graph which shows the analog value with respect to the digital code which shows the code | cord | chord correction used by this embodiment. FIG. 2 is a block diagram showing a configuration of an adaptation device for adapting register values of register tables 7a and 7b in the ΔΣ A / D conversion device 100 of FIG. 1. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows relation of output analog voltage to input digital data in a D / A converter. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows the relation of the digital code with respect to the number of comparators N of 1 output. It is a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment, and is a graph showing an analog voltage value with respect to a digital code for showing the effect of code correction. It is a simulation result of delta-sigma A / D conversion device 100 concerning this embodiment, and is a graph which shows power spectrum density (PSD) when a 3 bit code is used. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows power spectrum density (PSD) by code amendment when 12 bit code is used. It is a table | surface which shows the simulation conditions of (DELTA) (Sigma) A / D conversion device 100 concerning this embodiment. It is a graph which shows the probability density with respect to the offset value of the comparator of SF-A / D converter. It is a graph which shows the probability density with respect to the offset value of the comparator of a flash A / D converter. Quantizer is a graph showing the relationship between the SF-A / D converter (σ ₁ ≒ 100mV) in a number of comparators N and peak SNDR when (Signal to Noise and Distortion Ratio) . It is a graph which shows the relationship between standard deviation (sigma) ₂ and peak SNDR when a quantizer is a flash A / D converter. It is a table | surface which shows the area ratio of a quantizer when an SF-A / D converter is used. It is a table showing the relationship between the number of comparators N and the standard deviation sigma ₂ when the SF-A / D converter (σ ₁ ≒ 100mV). In the ΔΣ A / D converter 100 according to the present embodiment, the resolution (peak SNDR) when the SF-A / D converter and the flash A / D converter are respectively used as the quantizer (when the area of the quantizer is the same). ). It is a simulation result of delta-sigma A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SFDR with respect to input amplitude. 6 is a table showing simulation results of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and showing peak SNDR in consideration of variations with respect to the number of comparators N. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 16. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 32. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 64. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 128. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 256. It is a simulation result of ΔΣ A / D conversion device 100 concerning this embodiment, and is a graph which shows SNDR with respect to input amplitude when the number of comparators N = 512. Is a simulation result of the Delta-Sigma A / D converter 100 according to the present embodiment is a graph showing a peak in consideration of variations SNDR (SNDR _w) with respect to number of comparators N.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. First, the outline and features of the embodiment will be described.

  FIG. 1 is a block diagram showing a configuration of a ΔΣ A / D converter 100 according to an embodiment of the present invention. ΔΣ (hereinafter, “Δ−Σ” is unified into “ΔΣ”) A / D conversion apparatus 100 according to the present embodiment includes a subtracter 1, a low-pass filter (LPF) 2, and a plurality of N comparators 11. SF-A / D converter 3 including -1 to 11-N and an adder 12, a variable level digital quantizer 4 having a variable quantization level, a decoder 5, and a D / A converter 6. A register table 7a for storing the quantization level of the variable level digital quantizer 4 and a register table 7b for storing a 12-bit code value of a mapping table for converting the 3-bit code into a 12-bit code and correcting the code in the decoder 5 are included. And a table memory 7. In this embodiment, the low-pass filter 2 including the signal frequency in the pass band is used. However, the present invention is not limited to this, and the signal frequency is included in the pass band. A band-pass filter (BPF) that also removes may be used. In the following embodiments, since generality is not impaired, only the low-pass filter (LPF) 2 will be described.

  Here, the Δ−Σ A / D conversion apparatus 100 is particularly characterized by including a variable level digital quantizer 4, a decoder 5, and a table memory 7. The object is to realize a high-resolution A / D converter using a fine CMOS process by being applied to a D modulator. In other words, in the present embodiment, as shown in FIG. 1, the variable level digital quantizer 4 that is a multi-bit quantizer of the ΔΣ A / D converter 100 has a statistical property of a large number of comparators 11-1 to 11-N. The SF-A / D converter 3 which is a stochastic A / D converter using the above is used. Further, by making the quantization level of the SF-A / D converter 3 coincide with the quantization level of the D / A converter 6, the DEM of the D / A converter 6 of the multi-bit ΔΣ A / D modulator is not required. To do. Further, along with the adjustment of the quantization level of the SF-A / D converter 3, the decoder 5 performs code correction on the digital output. It is effective when the number of D / A converters 6 is one, such as a feedforward type ΔΣ modulator having a low distortion feature.

In FIG. 1, a subtracter 1 subtracts the analog voltage from the D / A converter 6 from the input analog voltage, and outputs the voltage resulting from the subtraction to the SF-A / D converter 3 via the low-pass filter 2. To do. SF-A / D converter 3, after comparing each using a plurality of N comparators 11-1 to 11-N having a threshold voltage Δ ₁ ~Δ _N, the comparators 11-1 to 11-N A / D conversion is performed by the adder 12 to add the output signal from the output signal to the variable level digital quantizer 4. The variable level digital quantizer 4 has a plurality of variable quantization levels stored in the register table 7a of the table memory 7 and having a plurality of different quantization levels with a predetermined interval, for example. The digital data is quantized into, for example, 3-bit code digital data and output to the decoder 5 and the D / A converter 6. The D / A converter 6 D / A converts the input digital data into an analog voltage, and then outputs it to the subtracter 1. The decoder 5 uses a mapping table including a plurality of 12-bit code values stored in the register table 7a of the table memory 7 to perform decoding by converting a 3-bit code into a 12-bit code and correcting the code. Output the converted digital data. Here, as for data in the register tables 7a and 7b of the table memory 7, as will be described in detail later with reference to FIG. 16, an error from the quantization level of the D / A converter 6 is minimized. The adaptation controller 110 shown in FIG. 16 is used for adaptation, and the variable level digital quantizer 4 and the decoder 5 constitute a D / A converter error correction circuit 8.

  Next, the detailed configuration of the proposed method will be described below.

  In general, A / D converters have variations in circuit element characteristics (element characteristic mismatch), most of which follow a Gaussian distribution. In the conventional quantizer, this element characteristic mismatch deteriorates the performance of the circuit, which is a serious problem in circuit miniaturization. On the other hand, an SF-A / D converter has been proposed as a method of performing A / D conversion by actively utilizing this element characteristic mismatch. The present embodiment proposes a method capable of detecting and miniaturizing a weak signal by using this as a quantizer of a ΔΣ modulator. Further, the present embodiment aims to realize a seven-level ΔΣ modulator using a fine process, and performance degradation due to a D / A converter error becomes a problem. Therefore, this embodiment proposes a method for correcting the D / A converter error using the variable level digital quantizer 4 and the decoder 5.

  In this embodiment, a 7-level fourth-order feedforward type ΔΣ modulator is handled. There is an advantage that the effect of noise shaping is increased by increasing the order of the filter. However, since the ΔΣ modulator is a negative feedback circuit, there is a possibility that the system becomes unstable in the second or higher order. Therefore, it is necessary to stabilize by adjusting the gain. A necessary condition for the system to be stable is that the filter poles must be inside the unit circle on the complex plane. By adjusting the gain inside the ΔΣ modulator, the pole of the filter can be operated, and stabilization can be achieved. However, if stabilization and adjustment of the gain are performed, the filter order is effectively lowered, so that the obtained signal-to-noise power ratio (SNR) is lowered.

  FIG. 2 is a circuit diagram showing a configuration of a general fourth-order feedback ΔΣ modulator, and FIG. 3 is a circuit diagram showing a configuration of a general fourth-order feedforward ΔΣ modulator.

  As a configuration of the ΔΣ modulator for stabilization, a feedback type ΔΣ modulator as shown in FIG. 2 or a feedforward type ΔΣ modulator as shown in FIG. 3 is used. In FIG. 2, the feedback-type ΔΣ modulator includes four integrators 21 to 24, a quantizer (A / D converter) 25, four subtractors 31 to 34, and a multiplier (D / A). (Comprising a converter) 41-44. In FIG. 3, the feedforward type ΔΣ modulator includes four integrators 21 to 24, a quantizer (A / D converter) 25, a subtractor 31, adders 35 to 37, 4 Each of the multipliers 51 to 54 and a D / A converter 26 are provided.

  Here, the amplitude of the integrator differs between the feedback type ΔΣ modulator and the feedforward type ΔΣ modulator. The feedforward type ΔΣ modulator has a smaller amplitude and is advantageous for stabilization. Further, the feedforward type ΔΣ modulator is suitable for reducing the sensitivity to the nonlinearity of the integrator. In the structure shown in FIG. 3, the zero point of the noise transfer function (hereinafter referred to as NTF) is at z = 1, that is, the DC point, but it is possible to improve the stability by optimizing the zero point of NTF. Become. Zero optimization can be achieved by adding local feedback inside the loop filter.

  FIG. 4 is a circuit diagram showing an equivalent circuit of the ΔΣ A / D converter used in the present embodiment. For this reason, this embodiment uses a delta-sigma modulator having a structure in which local feedback is added to a fourth-order feedforward type delta-sigma modulator as shown in FIG. Since it is assumed that differential signals are handled, the quantizer is set to 7 levels. The gain of each multiplier is as shown in FIG. 4, the ΔΣ A / D converter according to the present embodiment includes four integrators 21 to 24, two subtractors 31, 33, an adder 27, and a quantizer (A / D converter). ) 25, D / A converter 26, four multipliers 51 to 54, and four multipliers 51 to 54, 61 to 65.

  Next, the quantizer will be described below. In the present embodiment, the SF-A / D converter 3 using the statistical property of the element characteristic mismatch is used as a quantizer to achieve high resolution.

  FIG. 6 is a block diagram showing a configuration of a parallel A / D converter according to the prior art. In FIG. 6, the parallel A / D converter includes a reference voltage generator 13, a plurality of N comparators 11-1 to 11 -N, and a thermometer binary conversion encoder 15. The parallel A / D converter can perform high-speed operation because the comparison is simultaneously performed by N comparators connected in parallel. For this reason, the parallel A / D converter is also called a flash A / D converter. Note that the plurality of N adders 14-1 to 14-N are virtual in order to equivalently show the influence of an offset described later.

FIG. 7 is a graph showing the probability density distribution with respect to the threshold value of the comparator in the parallel A / D converter of FIG. The parallel A / D converter has threshold values distributed at equal intervals as shown in FIG. However, offsets (voltages) Δ _{off, 1 to} Δ _{off, N} are generated in the threshold values of the comparators 11-1 to 11-N due to element characteristic mismatch, and an error occurs in the conversion characteristics. For this reason, a weak signal below the offset cannot be detected, and it is difficult to achieve high resolution in a fine process. For the above reasons, when used as a quantizer of a multi-bit ΔΣ modulator, it is necessary to improve resolution degradation due to offset.

  FIG. 8 is a block diagram showing the configuration of the SF-A / D converter 3 used as a quantizer in this embodiment, and FIG. 9 shows the threshold value of the comparator in the SF-A / D converter 3 of FIG. It is a graph which shows probability density distribution. In the system proposed in this embodiment, an SF-A / D converter 3 shown in FIG. 8 is used as a quantizer. This system does not require a circuit for generating reference voltages by the number N of comparators unlike a conventional parallel A / D converter, and uses a comparator offset as a threshold value. For this reason, the threshold value follows a Gaussian distribution as shown in FIG.

In FIG. 8, if the reference voltage θ _REF is given, the center of the distribution can be set to an arbitrary voltage. In the conventional method, the resolution is limited by the comparator offset, but in this method, the comparator offset is actively used, so that a weak signal below the offset can be detected. Further, in the conventional parallel A / D converter, in order to generate the reference voltage, the resistor is often stacked from the ground to the power supply voltage, and the mismatch of the resistor also becomes an error, and the resolution is limited. On the other hand, since the SF-A / D converter does not require a reference voltage, this problem can be solved.

  The conversion mechanism of the SF-A / D converter 3 will be described below. As described above, the SF-A / D converter 3 has a random threshold value according to a Gaussian distribution. Therefore, the output of the comparator group is not a thermometer code like a flash A / D converter but a random output of 0 (low level) or 1 (high level). Therefore, in the SF-A / D converter 3, the input values are compared by a number of comparators 11-1 to 11-N, and the outputs are added. Since the relationship between the added value (corresponding to the number of comparators that output 1) and the input voltage follows the cumulative distribution of Gaussian distribution, A / D conversion can be performed by determining the digital output according to the addition result. is there.

Since the SF-A / D converter uses a threshold value according to a Gaussian distribution, it has nonlinearity. Further, distortion occurs because the number of comparators is finite. In order to ensure the linearity, it is necessary to use a linearly changing range of the cumulative distribution, so that the input range becomes narrow or many comparators are not used. The input range is determined by the standard deviation σ _off of the offset, and it is necessary to use the SF-A / D converter 3 in the range of ± σ _{off in} order to maintain linearity.

  10 is a block diagram showing a configuration of a modification of the SF-A / D converter of FIG. 9, and FIG. 11 is a probability density with respect to the threshold value of the comparator in the modification of the SF-A / D converter of FIG. It is a graph which shows distribution. FIG. 12 is a graph showing the cumulative probability density distribution with respect to the threshold value of the comparator in the modification of the SF-A / D converter of FIG.

Therefore, in order to reduce nonlinearity and expand the input range, the comparators 11-1 to 11-N are divided into two groups G1 and G2 as shown in FIG. 10, and reference voltages + σ _off and −σ _off having opposite signs are respectively obtained. give. The absolute value of the reference voltage is a standard deviation value σ _off of the comparator offset. Here, the group G1 includes comparators 11-1 to 11- (N / 2), and the group G2 includes comparators 11- (N / 2 + 1) to 11-N. Thus, the threshold distribution can be flattened as shown in FIG. The cumulative distribution of the flattened threshold distribution is as shown by the solid line in FIG. From FIG. 12, it can be seen that the non-linearity of the SF-A / D converter can be reduced and the input range can be expanded by flattening the threshold distribution. In the method proposed in this embodiment, this nonlinearity reduction technique is used, so the full-scale input range is set to ± 2σ _off .

  Next, correction of the D / A converter error will be described below.

  As described above, the ΔΣ modulator can improve the dynamic range and stability by increasing the number of bits. On the other hand, with the increase in the number of bits, an error of the D / A converter due to an element characteristic mismatch occurs and the resolution is greatly reduced. Therefore, it is necessary to reduce the influence of the D / A converter error by some method. A typical D / A converter error correction technique is DEM.

  FIG. 13 is a circuit diagram showing a configuration example of a multi-bit D / A converter according to the prior art. FIG. 13 shows a configuration example of a multi-bit D / A converter using capacitors C1 to CN having substantially the same capacitance value, switches S1 to SN, and a DC voltage source 70. Usually, in the D / A converter, an element selected for an input digital signal is uniquely determined. For this reason, a certain error is included in the output of the D / A converter due to mismatch of elements constituting the D / A converter, leading to performance degradation. In the DEM, the error of the D / A converter is averaged by selecting different elements for each clock. Thereby, the influence of the D / A converter error can be reduced, and the performance deterioration in the multi-bit ΔΣ modulator is reduced. In this method, it is necessary to select elements at random, but depending on the input signal of the D / A converter, there are cases where the elements are selected periodically and the error cannot be sufficiently averaged. This affects the output signal as distortion and reduces the resolution. In addition, since a circuit for selecting an element is driven for each clock, it is disadvantageous in terms of reducing power consumption.

  In the method proposed in the present embodiment, the SF-A / D converter 3 is used as a quantizer of the ΔΣ modulator to improve the resolution and correct an error generated in the feedback D / A converter. The principle will be described below.

  FIG. 14 is a graph showing the relationship of the number of comparators N with respect to the quantizer input voltage in this embodiment. The SF-A / D converter 3 determines the quantization output by the total number N of the comparators 11-1 to 11 -N that output 1 for the input value. When the feedback type (“type” is unnecessary) D / A converter 6 is ideal, the quantized output may be changed linearly in accordance with the number of comparators that react as shown in FIG. However, if there is an error in the D / A converter 6, an error in the quantization level occurs with the quantizer 4, and the error is accumulated inside the ΔΣ modulator, so the resolution is greatly reduced. Therefore, in this embodiment, the input / output characteristics of the quantizer 4 are changed according to the error of the D / A converter 6 to reduce the error of the quantization level, thereby correcting the error of the D / A converter 6. . As a result, the linearity within the ΔΣ modulator is improved, and the reduction in resolution can be reduced.

Here, the error at a point corresponding to the i-th digital code and delta _i. In FIG. 14, the numbers of comparators corresponding to the upper limit and the lower limit of the input range are Nu and Nl, respectively. At this time, the number of comparators having an input range threshold is (Nu-Nl). Further, the number of comparators corresponding to the i-th level with N _i, and 2FS the full-scale input range. Since the number of comparators corresponding to each level has only to be changed by an amount corresponding to the error of the D / A converter 6, the number of comparators N _i ′ changed according to the error of the D / A converter 6 is It is expressed by a formula.

However, since the number of comparators N _i ′ is an integer, it is necessary to approximate the nearest integer value. Thus, the error of the D / A converter 6 can be statically corrected by simply adjusting the number of comparators corresponding to each quantization level according to the error. In the SF-A / D converter 3, since the number of comparators that output 1 corresponds to the quantized output, the quantization level can be adjusted by a digital circuit. However, this causes the quantizer to have non-linearity corresponding to the error of the D / A converter 6, and the linearity is improved inside the ΔΣ modulator, but the digital value output from the ΔΣ modulator is reduced. Corresponds to a non-linear value corresponding to the error of the D / A converter.

  Similar quantization level adjustment can also be realized by providing a D / A converter in the reference voltage generator 13 in the parallel A / D converter of FIG. The SF-A / D converter 3 and the variable level digital quantizer 4 can be replaced. In this case, the output of the D / A converter in the reference voltage generator 13, that is, the reference voltage is adjusted according to the register table 7a. However, as will be described later, the advantages of the SF-A / D converter 3 when the resolution and the area are taken into account are great, and the advantage that the quantization level can be digitally adjusted without the D / A converter is as follows. Now, an embodiment realized using the SF-A / D converter 3 and the variable level digital quantizer 4 will be described.

  Further, code correction will be described below.

  FIG. 15 is a graph showing an analog value for a digital code indicating code correction used in the present embodiment. As described above, by correcting the error of the D / A converter 6 with the quantizer, the linearity is improved inside the ΔΣ modulator, but a non-linear value corresponds to the quantized output. . For this reason, in order to realize an A / D conversion device using the ΔΣ modulator of this system, the digital code of the output must be corrected so that a linear value corresponds. For this reason, in this embodiment, the decoder adds 9 bits to the output of the quantizer and finely divides the output range to correct the code so that the output corresponds to a linear value. Normally, the output of a 7-level quantizer can be represented by 3 bits.

  However, since the quantizer 4 is non-linear in this method, the relationship between the digital code and the analog value deviates from a linear characteristic with 3 bits. On the other hand, when the output range is further finely divided by the 12-bit code, the digital code and the analog value can be adjusted so as to correspond linearly as shown in FIG.

  FIG. 16 is a block diagram showing a configuration of an adapting device for adapting the register values of the register tables 7a and 7b in the ΔΣ A / D converting device 100 of FIG. In FIG. 16, the adaptation device includes a reference voltage generator 101, a high-precision A / D converter 102, an error calculator 103, and an adaptation controller 110.

  In FIG. 16, the reference voltage generator 101 sequentially generates a plurality of different predetermined reference voltages and inputs them to the Δ-Σ A / D converter 100 and the A / D converter 102. The A / D converter 102 is an A / D converter capable of performing A / D conversion with higher accuracy than the Δ-Σ A / D conversion device 100, and A / D converts the input voltage and outputs it to the error calculator 103. To do. The error calculator 103 calculates and adapts an error between the digital value from the Δ-Σ A / D converter 100 and the digital value from the A / D converter 102 (hereinafter referred to as D / A converter error). To the controller 110. The adaptation controller 110 uses the quantization level of the variable level digital quantizer 4 in the register tables 7a and 7b of the table memory 7 and the 12-bit code of the mapping table so that the D / A converter error is minimized. A multivariate parameter including a value is obtained and set before the operation of the Δ-Σ A / D converter 100.

  That is, the values held in the register tables 7a and 7b are adjusted in advance so that the Δ-Σ A / D conversion apparatus 100 obtains normal output digital data using a test reference voltage as a reference. Specifically, the expected output value digitally estimated based on a desired operation model of the A / D converter 102 for the digital value generated by the high-precision A / D converter 102 as the test reference analog voltage. Compare the time series with the time series of the output digital data from the Δ-Σ A / D converter 100 obtained in the actual test, and minimize the mean square error of both in a certain time range. By adjusting the parameter values held in 7a and 7b, an optimum parameter value can be obtained. As a method for searching for the optimum value, for example, an LMS (Least Mean Square) algorithm based on the steepest descent method is used. The value held in this register is updated by the above method when power is turned on or operation is interrupted. For example, a genetic algorithm, a two-part maximum likelihood search method, a neural network learning algorithm, or the like may be used as a search method for the optimum value.

  As described above, in this embodiment, the stochastic A / D converter using the statistical mismatch of the comparator is used for the multi-bit quantizer of the ΔΣ A / D modulator. This quantizer is realized using the statistical properties of many comparators, and the quantization level can be set easily and flexibly by changing the number of comparators that output the corresponding high-level signal. it can. Specifically, ideally, out of 256 comparators, when 128 comparators output a high level signal and code “000” is output, this corresponds to the mismatch of D / A converter 6. For example, the code “000” is output when 120 comparators output a high level signal. By setting the quantization level corresponding to the non-linearity associated with the mismatch in the D / A converter 6, the DEM is unnecessary. As a result, the quantizer has non-linear input / output characteristics, but for this correction, a digital output linearly corresponding to the analog input signal is obtained through the decoder 5. The mapping table of the decoder 5 and the setting of the quantization level described above are stored in the table memory 7, and the content is updated by calibration using the reference signal.

In the above embodiment, the variable level digital quantizer 4 outputs 3-bit code digital data, and the decoder 5 decodes the 3-bit code digital data into 12-bit code digital data for the code correction. ing. However, the number of bits of the bit code of the digital data used in the variable level digital quantizer 4 and the decoder 5 is not limited to this, and at least the decoder 5 uses the digital data of the first bit code for the code correction. Is mapped to the digital data of the second bit code having a larger number of bits than the number of bits of the first bit code, and the first from the variable level digital quantizer 4 the digital data bits code may be configured to decode the digital data of the second bit codes.

  In the above embodiment, the parameter values of the register tables 7a and 7b (the quantization level of the variable level digital quantizer 4 and the mapping table of the decoder 5 (particularly, the converted digital data value) are obtained using the system of FIG. ) May be determined and set in advance so as to obtain a value adapted to minimize the D / A converter error. The parameter value to be adapted may be at least one of the quantization level of the variable level digital quantizer 4 and the mapping table of the decoder 5 (particularly, the converted digital data value). Further, the adaptation is executed at a predetermined time interval during operation, for example, when the power is turned on.

  The present inventors perform numerical simulations on the Δ-Σ A / D converter according to the present embodiment, evaluate its performance, and consider it. Note that MATLAB was used for the numerical simulation.

  FIG. 17 is a graph showing a simulation result of the ΔΣ A / D converter 100 according to the present embodiment and showing a relationship between an output analog voltage and input digital data in the D / A converter. First, regarding the D / A converter error correction, the difference in input / output relationship between the case where the error is corrected in the quantizer and the case where the error is not compared was compared. FIG. 17 shows input / output characteristics when the D / A converter 6 is ideal and when an error occurs.

  The input / output characteristics of the quantizer when the D / A converter error was corrected according to the equation (1) were simulated. Note that the number of comparators N = 256, and the above-described nonlinearity reduction technique by flattening the offset distribution was used. Also in the following simulation, unless otherwise noted, a non-linearity reduction technique (modified example of FIG. 10) by flattening the offset distribution is used.

  FIG. 18 is a graph showing the simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and showing the relationship of the digital code to the number N of comparators that output 1. That is, FIG. 18 shows the correspondence between the number of comparators that output 1 and the corresponding digital code (−3 to 3). The characteristic indicated by the solid line is the characteristic when the D / A converter error is corrected. It can be seen that the relationship between the number of comparators N and the digital code changes nonlinearly according to the D / A converter error.

  The inventors then performed a simulation for code correction.

  FIG. 19 is a graph showing a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and showing an analog voltage value with respect to a digital code for indicating the effect of code correction. Since the input / output characteristics of the quantizer are non-linear in order to correct the D / A converter error, the non-linear value corresponds to the 3-bit digital code as shown by the dotted line in FIG. Here, a 9-bit code is added to further divide the input range divided by 7 levels, and codes are assigned so that the relationship between the digital value and the analog value is linear. By this code correction, it can be seen that the relationship between the digital code and the analog value can be made close to linear as shown by the solid line in FIG.

  FIG. 20A is a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and is a graph showing a power spectral density (PSD) when a 3-bit code is used, and FIG. 20B is a ΔΣ A according to the present embodiment. 4 is a graph showing a result of simulation of the / D conversion apparatus 100 and a power spectral density (PSD) by code correction when a 12-bit code is used. FIG. 21 is a table showing simulation conditions for the ΔΣ A / D converter 100 according to the present embodiment.

  FIG. 20A and FIG. 20B show changes in power spectral density (PSD) due to code correction. In the 3-bit code, the noise in the low band is increased due to the influence of the non-linear error of the quantizer caused by the correction of the D / A converter error, but in the 12-bit code, the noise is reduced by correcting the non-linear error. It can be confirmed that it is made.

  Next, based on the above simulation results, a simulation was performed assuming that the quantizer of the SF-A / D converter 3 and the D / A converter error correction thereby were applied to the ΔΣ modulator. A frequency spectrum was obtained by performing a fast Fourier transform (FFT) on the output signal, a signal-to-noise and distortion power ratio (SNDR) was calculated, and the performance was compared. Here, for the 7-level quantizer, the peak SNDR was obtained and the performance was compared for the case where the flash A / D converter was used and the case where the SF-A / D converter was used. Note that the D / A converter is ideal in all cases.

In order to compare the performance, the area ratio of the quantizer on the chip when obtaining the same peak SNDR was obtained. The method for obtaining the area ratio is as follows. According to semiconductor engineering, the standard deviation ΔV _th (mV) of the threshold voltage of MOSFET is approximated by the following equation as gate oxide film thickness t _ox (nm), gate length L (μm), and gate width W (μm). it can.

It is assumed that the comparator offset is caused by variations in the threshold voltage of the MOSFET, and that the standard deviation σ _{off of the} offset follows the following equation.

  However, K is a proportionality coefficient and A = LW is a gate area.

FIG. 22A is a graph showing the probability density with respect to the offset value of the comparator of the SF-A / D converter. FIG. 22B is a graph showing the probability density with respect to the offset value of the comparator of the flash A / D converter. Here, the standard deviations of the comparator offsets are σ ₁ and σ ₂ , respectively, and the areas on the chip per comparator are A ₁ and A ₂ , respectively. The number of comparators of the SF-A / D converter is N. Since the number of comparators of the 7-level flash A / D converter is 6, the chip areas of the SF-A / D converter and the flash A / D converter are as follows.

Therefore, the area ratio is as follows.

First, the peak SNDR was obtained by changing the number of comparators in the case of the SF-A / D converter. The standard deviation σ ₁ of the comparator offset was set to satisfy σ ₁ ≈100 mV.

FIG. 23 is a graph showing the relationship between the number of comparators N and peak SNDR (Signal to Noise and Distortion Ratio) when the SF-A / D converter (σ ₁ ≈100 mV). This data is an average value obtained by performing simulation 100 times. The simulation conditions are as shown in FIG.

  Next, the inventors simulated the relationship between the magnitude of threshold variation and PeakSNDR in the case of a flash A / D converter.

FIG. 24 is a graph showing the relationship between the standard deviation σ ₂ and the peak SNDR for the flash A / D converter. This data is an average of 100 simulations. The simulation conditions are as shown in FIG. As is clear from FIG. 24, the relationship between the standard deviation σ ₂ of the comparator threshold variation and the peak SNDR is approximated by a linear expression. The approximate expression obtained by regression analysis is as follows.

From this equation, the peak SNDR at an arbitrary σ ₂ can be obtained approximately. From these results, σ ₂ for obtaining the same peak SNDR was obtained for each number N of comparators of the SF-A / D converter 3 using Equation (7), and the areas of the quantizers were compared.

  FIG. 25 is a table showing the area ratio of the quantizer when the SF-A / D converter is used. As can be seen from FIG. 25, when the same resolution is realized, it is possible to reduce the size by using the method of this embodiment as compared with the conventional method. However, when the number N of comparators of the SF-A / D converter 3 is increased, the peak SNDR is improved, but the area occupied by the quantizer is increased.

  Next, assuming that the areas are the same, the resolution (PeakSNDR) was compared between when the SF-A / D converter was used and when the flash A / D converter was used. When the area of the quantizer is the same, the value of Equation (6) is 1. That is, the following formula is obtained.

At this time, the relationship between σ ₁ and σ ₂ is as follows.

FIG. 26 is a table showing the relationship between the number of comparators N and the standard deviation σ ₂ when the SF-A / D converter (σ ₁ ≈100 mV). In FIG. 26, the value of σ ₂ at each N is shown. However, when N = 256 or less, the standard deviation σ ₂ becomes large with respect to LSB = 57.1 mV if the area of the quantizer is made the same with the same full-scale input amplitude. For this reason, if N = 256 or less, the monotonicity of the quantizer cannot be ensured, and therefore SNDR cannot be compared. That is, by using an SF-A / D converter as a quantizer, it is possible to handle a minute signal that cannot be detected by the conventional method. Assuming that the monotonicity of the flash A / D converter is secured at N = 512, the peak SNDR can be obtained from Equation (7).

  FIG. 27 is a table showing a comparison of resolution (peak SNDR) when an SF-A / D converter and a flash A / D converter are respectively used as quantizers in the ΔΣ A / D converter 100. As is clear from FIG. 27, it can be seen that using the SF-A / D converter in the case of the same area enables higher resolution than the flash A / D converter.

Furthermore, the present inventors input the case where the D / A converter error is corrected using the SF-A / D converter as the quantizer in order to verify the effect of the method proposed in the present embodiment. The relationship between amplitude and SNDR was simulated. The standard deviation of the D / A converter error was set to be σ _DAC ≈0.15LSB. In this simulation, code correction is performed, a corresponding analog value is generated, and FFT is performed. The simulation conditions are as shown in FIG.

  FIG. 28 is a graph showing a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and showing SNDR with respect to input amplitude. Note that the number of comparators is N = 256. For comparison, an ideal flash A / D converter is used as a quantizer, and a simulation result when an error occurs in the D / A converter is also shown.

  As described above, if the level is 7 in the conventional method, miniaturization is difficult due to the influence of the error of the quantizer and the D / A converter, and the resolution is lowered. On the other hand, as can be seen from FIG. 28, the resolution can be maintained even at 7 levels by using the method proposed in this embodiment. In particular, it can be confirmed that the SNDR is greatly improved by correcting the D / A converter error. Compared with the case where there is no D / A converter error, SNDR is reduced by about 10 to 15 dB. This is because the error of the D / A converter, which is a continuous value, is corrected by the number of comparators, which is a discrete value. This is considered to be the effect of errors caused by In addition, it is considered that the nonlinearity of the quantizer, which could not be corrected by the 12-bit code, also has an influence. Therefore, it can be improved by increasing the number of quantization levels and the number of bits of the corrected code.

  FIG. 29 is a graph showing SFDR with respect to input amplitude, which is a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment. As can be seen from FIG. 29, SFDR is greatly improved by the D / A converter error correction as in SNDR, and it can be confirmed that the linearity is improved. As is clear from FIG. 29, it can be seen that the non-linearity of the D / A converter affects the distortion of the output signal because the SFDR greatly decreases when the D / A converter error is not corrected. In this case, the SFDR shows a peak when the input amplitude is in the vicinity of −30 dBFS. This is probably because the level used is small when the amplitude is small.

  Next, changes due to the number of comparators will be described below.

The SF-A / D converter can be expected to improve SNDR as the number of comparators N increases. However, if N increases more than necessary, the occupied area increases. Therefore, it is necessary to examine the optimum number of comparators N when using an SF-A / D converter for the ΔΣ modulator. Therefore, the number of comparators N was changed from 16 to 512, and the relationship between the input amplitude and SNDR was simulated. The simulation conditions are as shown in FIG. In addition to performing 100 simulations to obtain an average value, a SNDR standard deviation σ _SNDR was obtained in order to consider the yield.

  31A to 31F are simulation results of the ΔΣ A / D conversion device 100 according to this embodiment, and show SNDR with respect to input amplitude when the number of comparators N = 16, 32, 64, 128, 256, and 512, respectively. It is a graph. Here, in order to consider the yield, the following values are calculated for the peak SNDR.

SNDR _w represents the peak SNDR in the worst case. Statistically, it can be said that SNDR higher than this is obtained in the case of 99.7. That is, even if the average value is large, if the variation σ _SNDR is large, the value of the equation (10) becomes small.

FIG. 32 is a graph showing a simulation result of the ΔΣ A / D conversion apparatus 100 according to the present embodiment and showing a peak SNDR (SNDR _w ) in consideration of a yield with respect to the number N of comparators. As is apparent from FIG. 32, it can be seen that as the number of comparators N increases, the rate of improvement in SNDR decreases. Further, it can be said that the larger the number N of comparators, the smaller the SNDR variation and the better the yield. From this result, the number of comparators can be determined if the required SNDR is determined.

  As described above, the element characteristic mismatch increases with miniaturization, and becomes a big problem in maintaining the accuracy of the LSI device. Even in the ΔΣ modulator, due to the increase in the number of bits, the influence of the element characteristic mismatch on the quantizer and the D / A converter increases, leading to a decrease in resolution. Therefore, in the present embodiment, a method has been proposed in which element characteristic mismatch is positively used using a probabilistic method to achieve high resolution of the ΔΣ A / D converter. The conventional quantizer is difficult to miniaturize because the resolution is limited by the comparator offset. In view of this, the present embodiment has proposed a method capable of miniaturization and detection of a weak signal by using an SF-A / D converter using statistical properties of an offset as a quantizer.

  Moreover, it was confirmed that miniaturization and high resolution can be achieved by using an SF-A / D converter as a quantizer by performing a system level simulation. In the conventional method, when the ΔΣ modulator is multi-bit, the error of the D / A converter becomes a big problem, and it is difficult to maintain the resolution. For this reason, a D / A converter error correction technique such as DEM is required. However, this method has problems that distortion occurs due to periodic selection and power consumption increases.

  Therefore, in this embodiment, a method for correcting the D / A converter error by the SF-A / D converter has been proposed. It was confirmed by simulation that the D / A converter error can be corrected by using this method, and the resolution of the multi-bit ΔΣ modulator can be improved. As a result, it is possible to reduce the performance degradation accompanying the increase in the number of bits of the ΔΣ modulator, and to increase the dynamic range and stability.

  Therefore, the high-resolution A / D converter using the fine CMOS process can be realized by the quantizer using the SF-A / D converter proposed in the present embodiment and the D / A converter error correction using the quantizer. Become.

As described above in detail, the A / D converter according to the present invention has the following effects.
(1) It is possible to provide an A / D converter that does not use a DEM, has a simpler circuit configuration than the prior art, and can perform A / D conversion stably with high accuracy. As a result, the A / D converter can be reduced in power and area.
(2) In the A / D converter, the statistical property of the comparator offset is analyzed and controlled, a signal below the offset level can be detected, and a dynamic range can be secured even in a fine process with a large element characteristic mismatch.
(3) The design efficiency of the high-accuracy ΔΣ A / D converter is improved, and it becomes easy to respond to market demands and manufacturing technology changes.

1 ... subtractor,
2 ... Low-pass filter (LPF),
3 ... Parallel type stochastic A / D converter,
4 ... Variable level digital quantizer,
5 ... Decoder,
6 ... D / A converter,
7 ... Table memory,
7a, 7b ... register table,
8: D / A converter error correction circuit,
11-1 to 11-N: Comparator,
12 ... adder,
13: Reference voltage generator,
14-1 to 14-N ... adder,
15 ... Thermometer binary conversion encoder,
21-24 ... integrators,
25 ... Quantizer (A / D converter),
26 ... D / A converter,
27. Adder,
31-34 ... subtractor,
35-37 ... adder,
41-44 ... multiplier (comprising D / A conversion),
51-54, 61-65 ... multiplier,
70: DC voltage source,
100: ΔΣ A / D converter,
101 ... Reference voltage generator,
102 ... A / D converter,
103 ... error calculator,
110 ... Adaptation controller,
C1 to CN: capacitors,
G1, G2 ... Comparator group,
S1 to SN: switches.

Claims (5)

Subtracting means for subtracting the analog voltage from the D / A conversion means from the input analog voltage and outputting the analog voltage of the subtraction result;
A filter that outputs the analog voltage from the subtracting means by low-pass or band-pass filtering;
Including a plurality of quantizers each having nonlinear input / output characteristics, having a plurality of variable quantization levels, and A / D converting the analog voltage from the filter into digital data of a first bit code A / D conversion means for outputting;
The D / A conversion means for D / A converting the digital data of the first bit code from the A / D conversion means into an analog voltage and outputting the analog data to the subtraction means;
A mapping table for decoding digital data of the first bit code into digital data of a second bit code having a number of bits larger than the number of bits of the first bit code; the digital data bits code decoding means and outputting the decoded digital data of the second bit codes,
Comprising a plurality of quantization levels of the A / D converting means, and a mapping table of said decoding means, and control means an error of the D / A converter is set to be minimum,
The decoding means corrects nonlinear input / output characteristics of each quantizer of the A / D conversion means so as to obtain digital data of the second bit code linearly corresponding to the input analog voltage. And an A / D converter characterized by decoding . The A / D conversion means is
A parallel type stochastic A that includes a plurality of comparators each having a different threshold value and an adder that adds output signals from the plurality of comparators, and A / D converts the analog voltage from the filter into digital data / D conversion means;
Digital quantization means having a plurality of changeable quantization levels and digitally quantizing digital data from the parallel stochastic A / D conversion means to output digital data of a predetermined first bit code; The A / D conversion apparatus according to claim 1, further comprising: The control means can A / D convert the digital data output from the A / D converter and the reference signal with higher accuracy than the A / D converter when a predetermined reference signal is input. by minimizing the error between the digital data when a / D conversion by a separate a / D converter, according to claim 1 or 2, characterized in that to minimize the error of the D / a converter The A / D conversion device described. The control means adapts at least one of the plurality of quantization levels of the digital quantization means and the mapping table of the decoding means so that the error of the D / A conversion means is minimized. The A / D converter according to claim 2 . The plurality of comparators of the A / D conversion means are configured to be divided into a first comparator group and a second comparator group,
Each threshold value of the first comparator group is set to a standard deviation of a predetermined offset,
3. The A / D converter according to claim 2 , wherein each threshold value of the second comparator group is set to a value of an opposite sign of the standard deviation of the offset.

Images