JP5756594B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing technique.

  In recent years, the resolution of images input to video display devices such as projectors, liquid crystal televisions, and plasma televisions has been increasing, and in such devices, in order to complete image processing for a large number of pixels constituting a screen in a short time. The input image data may be divided into a plurality of partial image data and processed in parallel. When data that is divided into a plurality of partial image data and input is processed by a plurality of image processing units, each image processing unit uses pixel data in the peripheral area of each divided image partial image data. A so-called filter process referring to (hereinafter also referred to as peripheral pixel data) is performed. An example of a technique for performing filter processing with reference to peripheral pixel data is Patent Document 1.

JP 2006-5524 A

  Conventionally, the following method has been adopted as a method of directly exchanging peripheral pixel data between image processing units. Each image processing unit is connected to a plurality of image processing units in charge of processing of adjacent partial image data, each with a line for exchanging peripheral pixel data, and each communicates directly to exchange peripheral pixel data It is a method to do. In this method, one image processing unit needs to communicate with a maximum of eight other image processing units in the vicinity. Specifically, it is responsible for processing each partial image data adjacent to each of the upper, lower, left, right, upper right diagonal, upper left diagonal, lower left diagonal, and lower right diagonal, centered on one partial image. It is necessary to exchange peripheral pixel data with a total of eight image processing units. As a result, the number of transceivers, the number of wires, the number of pins of the device, and the like increase.

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.
[Form]
An image processing apparatus for processing image data representing an image composed of a plurality of pixels, corresponding to each partial image obtained by two-dimensionally dividing a display image corresponding to the image data in a horizontal direction and a vertical direction Input image data corresponding to the partial image, and process the data of each pixel constituting the partial image with reference to peripheral pixel data that is pixel data of the partial image outside the partial image A plurality of image processing units; and an image output unit that outputs display image data using pixel data after the image processing is performed by the image processing unit , and each of the plurality of image processing units . Is between each image processing unit adjacent to each image processing unit in the horizontal direction or the vertical direction at each of the two timings prior to the image processing, The peripheral pixel data is exchanged, and at the first timing, the peripheral pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction. At the second timing different from the second timing, the neighboring pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction, and the two times The image processing is performed by including peripheral pixel data of the diagonally adjacent partial image diagonally adjacent to the partial image corresponding to the image processing unit acquired by the exchange.

[Application Example 1]
An image processing apparatus for processing image data representing an image composed of a plurality of pixels, provided corresponding to each partial image obtained by dividing a display image corresponding to the image data, and an image corresponding to the partial image A plurality of image processing units that input data and process data of each pixel constituting the partial image with reference to data of peripheral pixels of the pixel, and after the image processing is performed by the image processing unit An image output unit that outputs image data for display using pixel data, and the plurality of image processing units include at least the first portion when performing the image processing on the first partial image. Among the pixels constituting the other partial image adjacent to the image, at least the pixel data of the region adjacent to the first partial image is acquired and used as the peripheral pixel data. The first image processing unit used for the image processing and the second partial image different from the first partial image are subjected to the image processing, and pixels processed by the first image processing unit as the peripheral pixels are processed. A second image processing unit that mediates at least a portion of data from an image processing unit that processes a partial image adjacent to a partial image handled by the first image processing unit toward the first image processing unit; And an image processing apparatus.

According to this image processing apparatus, since the second image processing unit mediates peripheral pixel data of another partial image adjacent to the first partial image referred to by the first image processing unit, the first image processing The unit can acquire peripheral pixel data without directly acquiring from other adjacent partial images.
[Application Example 2]
The image processing apparatus according to Application Example 1, wherein the second image processing unit is configured to acquire the first image together with acquisition of peripheral pixel data necessary for the reference by the second image processing unit. An image processing apparatus in which a processing unit mediates the peripheral pixel data necessary for the reference.
According to this image processing apparatus, since the second image processing unit mediates the peripheral pixel data referred to by the first image processing unit in conjunction with the acquisition of the peripheral pixel data, it is compared with a case where acquisition and mediation are performed separately. Thus, these processes can be performed at high speed.

[Application Example 3]
The image processing apparatus according to Application Example 2, wherein each partial image is an image obtained by two-dimensionally dividing the display image corresponding to the image data in a horizontal direction and a vertical direction, and the first image processing When the unit refers to peripheral pixel data of a diagonally adjacent partial image that is diagonally adjacent to the first partial image, the second partial image is the first partial image and the diagonally adjacent The second image processing unit is positioned adjacent to one of the partial images in the horizontal direction and the other in the vertical direction, and the second image processing unit includes the diagonally adjacent partial image that the first image processing unit requires for the reference. Image processing apparatus that mediates peripheral pixel data of
According to this image processing apparatus, each image processing unit has a path for acquiring and mediating peripheral pixel data compared to a case where image processing units adjacent in the diagonal direction directly exchange peripheral pixel data with each other. Can be simplified.

[Application Example 4]
The image processing apparatus according to Application Example 3, wherein each of the image processing units exchanges the peripheral pixel data at two time-divided timings, and the image is processed at the first of the two timings. The peripheral pixel data is exchanged with the image processing unit adjacent to the processing unit in either the horizontal direction or the vertical direction, and the image processing unit in the horizontal direction at the second of the two timings. Alternatively, an image processing apparatus that exchanges the peripheral pixel data with the image processing unit adjacent to the other in the vertical direction.
According to this image processing apparatus, it is possible to minimize the timing at which all image processing units exchange peripheral pixel data necessary for processing.

[Application Example 5]
The image processing apparatus according to Application Example 1, wherein the plurality of image processing units include an odd number of image processing units among a plurality of other image processing units respectively corresponding to partial images adjacent to a corresponding partial image. The image processing unit includes 0 or 2 image processing units that acquire data of a part of pixels in a region adjacent to the corresponding partial image as the peripheral pixel data for reference, and the image processing units are The image processing units are connected to each other by a data acquisition path that is a path for directly acquiring the peripheral pixel data, and each image processing unit is constituted by the data acquisition path. An image processing apparatus in which a data communication path is formed.

  According to this image processing apparatus, the data communication path has a so-called “one-stroke writing” path configuration that passes through all the image processing units. Therefore, in the case of a one-stroke writing path configuration in which the start point and end point of the data communication path are different, each image processing unit only directly acquires peripheral pixel data from two adjacent image processing units. It is possible to configure a data acquisition path that can acquire the peripheral pixel data necessary for processing in the case of a one-stroke path configuration in which the start point and end point of the data communication path are the same, that is, a closed path configuration. When the path is a loop, and the path configuration is configured as the shortest path, each image processing unit is necessary for processing by repeating the process of acquiring peripheral pixel data from only one adjacent image processing unit. It is possible to acquire peripheral pixel data.

[Application Example 6]
The image processing apparatus according to any one of Application Examples 1 to 5, further comprising: an image data input unit that inputs the image data; and the display image corresponding to the image data that is two-dimensionally divided. An image processing apparatus comprising: an image dividing unit configured to input a plurality of partial images to the respective image processing units.
According to this image processing apparatus, since the image dividing unit is provided, image data corresponding to the display image is directly input to the image processing apparatus, and divided into partial images by the image dividing unit. Can be processed.

[Application Example 7]
The image processing apparatus according to any one of Application Examples 1 to 6, further comprising: a timing control unit that controls a plurality of time-divided timings in which each of the image processing units exchanges the peripheral pixel data. An image processing apparatus.
According to this image processing apparatus, since the timing control unit is provided, it is possible to acquire peripheral pixel data without providing a control device for controlling the timing of acquiring peripheral pixel data externally or inputting a control signal for controlling timing. It is possible to control the timing.

[Application Example 8]
Image data representing an image composed of a plurality of pixels is provided corresponding to each partial image obtained by dividing a display image corresponding to the image data, and image data corresponding to the partial image is input. Is processed using a plurality of image processing units that process the data of each pixel constituting the pixel with reference to the data of peripheral pixels of the pixel, and the first of the plurality of image processing units using the image processing unit, when performing the image processing with the first portion picture image, among the pixels constituting the other partial images adjacent to the said first partial image, at least the first portion A second portion different from the first partial image is obtained by acquiring pixel data of a region adjacent to the image, and using the second image processing unit as the peripheral pixel data for the image processing. image The image processing is performed, and at least a part of the data handled by the first image processing unit as the peripheral pixel is processed as a partial image adjacent to the partial image handled by the first image processing unit. Image processing that mediates from the image processing unit toward the first image processing unit and outputs display image data using pixel data after the image processing is performed by the plurality of image processing units Method.

  According to this image processing method, since the second image processing unit mediates peripheral pixel data of another partial image adjacent to the first partial image referred to by the first image processing unit, the first image processing The unit can acquire peripheral pixel data without directly acquiring from other adjacent partial images.

It is a block diagram which shows the structure of the image processing apparatus 1 as 1st Example. 6 is a block diagram showing an internal configuration of a fifth image processing unit 35. FIG. It is a block diagram which shows typically the process in the 5th image process part. 3 is a flowchart showing a flow of image processing in the image processing apparatus 1. It is explanatory drawing explaining the surrounding pixel data which the 5th image process part 35 requires. It is explanatory drawing explaining the exchange path | route of the surrounding pixel data of each image block DIn. It is the flowchart explaining the flow of the surrounding pixel data exchange process. It is explanatory drawing which shows the mode of replacement | exchange of surrounding pixel data. It is explanatory drawing which showed an example of the exchange path | route of the surrounding pixel data in 2nd Example. 12 is an explanatory diagram illustrating a specific example of Modification 3. FIG. 10 is an explanatory diagram illustrating a specific example of Modification 5. FIG. 12 is an explanatory diagram showing a specific example of Modification 6. FIG.

Embodiments of the present invention will be described based on examples.
A. First embodiment:
(A1) Configuration of image processing apparatus:
In this embodiment, an image processing apparatus mounted on a high-resolution liquid crystal projector will be described as an example. FIG. 1 is a configuration diagram showing a configuration of an image processing apparatus 1 as a first embodiment of the present invention mounted on a liquid crystal projector. The liquid crystal projector is externally connected to the video storages St1 to St9, and inputs image data via the image input units 21 to 29 included in the image processing apparatus 1. As shown in FIG. 1, each of the video storages St1 to St9 stores image blocks DIn1 to DIn9 which are partial images obtained by dividing DIn0 which is image data for one screen into 3 × 3 (total nine). DIn1 to DIn9 are input from the video storages St1 to St9 to the image input units 21 to 29 included in the image processing apparatus 1. The image blocks DIn1 to DIn9 are input to the image processing apparatus 1 from the video storages St1 to St9 as digital data. Each video storage St1 to St9 is provided in each computer in a PC cluster composed of a plurality of computers.

  The image processing apparatus 1 includes the above-described image input units 21 to 29, first image processing units 31 to 9 that are nine image processing units that process the image blocks DIn1 to 9 in parallel, and each image. An image composition unit 40 that composes image data DOut1 to 9 corresponding to image blocks processed in parallel by the processing unit into image data of one screen, and a liquid crystal panel drive of a liquid crystal projector (not shown) An image output unit 50 that outputs to the unit as an output signal and a timing instruction unit 60 are provided.

  In each of the image processing units 31 to 39, the first image processing unit 31 processes DIn1 and the second image processing unit 32 processes DIn2, and the number of each image processing unit and each image block Each of the image blocks DIn1 to DIn9 is processed in correspondence with the number. Hereinafter, the configuration of the fifth image processing unit 35 will be mainly described.

FIG. 2 is a block diagram showing an internal configuration of the fifth image processing unit 35. The fifth image processing unit 35 includes a CPU 71 having a function as a digital signal processor (DSP), a ROM 73 storing operation programs, a RAM 75 used as a work area, image data obtained by dividing the image data DIn0, that is, an image block A frame memory 80 having a slightly larger storage capacity than DIn5, an input interface 81 that receives the image block DIn5 from the video storage St5, an output interface 83 that outputs the image data DOut5 to the image composition unit 40, and a timing signal from the timing instruction unit 60 An instruction input interface 85 is provided. The CPU 71 controls the overall operation of the fifth image processing unit 35, but is a dedicated processor that can access the frame memory 80 at high speed and perform predetermined image processing (filter processing). Note that the function of the CPU 71 may be realized using an FPGA (Field Programmable Array), an image processing dedicated LSI, or the like.

  Next, a functional configuration of each image processing unit will be described. FIG. 3 is a block diagram schematically showing processing in the fifth image processing unit 35. Functionally, the fifth image processing unit 35 includes a divided image input unit 351, a data exchange unit 352, a frame memory control unit 353, a frame memory 354, a filter processing unit 355, and a divided image output unit 356. The operations of these blocks are actually realized by the CPU 71 executing a predetermined program. Details of these functional units will be described later.

(A2) Image processing:
Next, image processing performed by the image processing apparatus 1 will be described. FIG. 4 is a flowchart showing the flow of image processing in the image processing apparatus 1. The image processing is started by inputting image blocks DIn1 to DIn9 from the image storages St1 to St9 (see FIG. 1) to the image input units 21 to 29.

  Image blocks DIn1 to 9 are input to the image processing units 31 to 39 from the image input units 21 to 29 via the divided image input units 351 to 391 (see FIG. 3), respectively (step S120). The frame memory control unit of each image processing unit stores the input image block DIn in the frame memory. When the storage of the image block DIn in the frame memory is completed, the frame memory control unit notifies the timing instruction unit 60 of this. The timing instruction unit 60 analyzes the accumulation state of the image blocks DIn in the image processing units 31 to 39, and determines that the input to all the image processing units of all the image blocks DIn1 to 9 is completed (step S130: Yes), the data exchange unit of each image processing unit is instructed to start data exchange. When each data exchange unit receives an instruction to start data exchange from the timing instruction unit 60, the peripheral pixel data necessary for the processing of the image block that each image processing unit is in charge of with the data exchange unit in the predetermined image processing unit Peripheral pixel data exchange processing to be exchanged is performed (step S140). The peripheral pixel data exchange process will be described in detail later. In view of the fact that the image data is received sequentially, the data exchange may be instructed sequentially from the data exchange between the image processing units capable of data exchange. In this embodiment, the data exchange is shown in step S130. As described above, in order to facilitate understanding of the present invention, data exchange is performed after all of the first to ninth image processing units 31 to 39 have received image data.

When the exchange of the surrounding pixel data is completed by the data exchange unit of each image processing unit, each frame memory control unit obtains the image block DIn stored in the frame memory and the surrounding pixel data acquired by the surrounding pixel data exchange process. The data is output to each filter processing unit, and each filter processing unit performs filter processing using these two data (step S150). When the filter processing ends, the filter processing unit outputs the processed data to the image composition unit 40 via each divided image output unit. The image synthesizing unit 40 synthesizes the image data DOut1 to 9 received from the respective divided image output units (step S160), and outputs the synthesized image data Dout0 to the image output unit 50. The image output unit 50 outputs the input image data DOut0 as an output signal to the liquid crystal panel drive unit (step S170). Such image processing is repeatedly performed on the input image blocks DIn1 to DIn9, and the image processing apparatus 1 performs image processing.

(A3) Peripheral pixel data exchange processing:
Next, the surrounding pixel data exchange process (see FIG. 4: step S140) will be described. First, peripheral pixel data will be described. FIG. 5 is an explanatory diagram illustrating peripheral pixel data necessary for the fifth image processing unit 35 to perform the filter processing of the image block DIn5 as a specific example. The filter processing unit 355 uses a 5 × 5 filter matrix centered on a pixel to be processed in the image block DIn5 (hereinafter also referred to as a target pixel), and pixel data for each two pixels around the target pixel. The target pixel is filtered while referring to FIG. Specifically, filter processing is performed using a Laplacian filter or median filter for edge enhancement or noise removal, and other image processing filters such as a Kalman filter. When such filter processing is performed, pixels of 2 pixels inward from the total of 4 sides (upper side, lower side, left side, and right side) in the vertical direction of the image block DIn5 in the vertical direction and the left and right in the horizontal direction are each set as the target pixel. When it becomes a processing target, the pixels referred to as filter processing extend to pixels included in the image blocks DIn1 to 4, 6 to 9, which are image blocks around the image block DIn5. Therefore, the fifth image processing unit 35 needs to acquire the peripheral pixel data illustrated in FIG. 5 as the peripheral pixel data from the image blocks DIn1 to 4, 6 to 9 around the image block DIn5. The data exchange unit 352 of the fifth image processing unit 35 acquires these neighboring pixel data by the neighboring pixel data exchange process (see FIG. 4: step S140). Hereinafter, the upward and downward directions in the vertical direction may be simply referred to as “up and down”, and the left and right directions in the horizontal direction may be simply referred to as “left and right”.

  Next, a path through which each image processing unit exchanges peripheral pixel data will be described. FIG. 6 is an explanatory diagram schematically illustrating an exchange path of peripheral pixel data of each image block DIn. Actually, the data exchange units of the image processing units are connected to each other and exchange the peripheral pixel data. However, in order to facilitate understanding, the peripheral pixel data is processed by the image blocks DIn1 to DIn9 that each image processing unit is responsible for processing. The exchange route will be schematically described. The arrows shown in FIG. 6 indicate the exchange path of peripheral pixel data between the image processing units, and bidirectional data exchange is possible with one data exchange. In this embodiment, the neighboring pixel data is exchanged at two timings. In FIG. 6, the exchange path used in the first data exchange is indicated by a solid arrow, and the exchange used in the second data exchange. The route is indicated by a dashed arrow.

  As shown in FIG. 6, for example, the image block DIn5 (actually the fifth image processing unit 35) includes, as the positional relationship of the image block DIn in the image data DIn0, the image blocks DIn2, DIn4, DIn6, and DIn8 that are adjacent vertically and horizontally. It is connected to the data exchange unit of each image processing unit in charge of processing. Then, peripheral pixel data exchange is performed only with these image processing units. Similarly, in the other image processing units, the image block corresponding to the image processing unit is connected only to the image processing unit corresponding to the image block adjacent in the vertical and horizontal directions as the positional relationship of the image blocks. Exchange pixel data. Therefore, for example, the data exchange unit of DIn5 (fifth image processing unit 35) is connected by four communication lines, two DIn1 and DIn3 are connected by three data exchange communication lines. In this embodiment, each of the data exchange units of the image processing units 31 to 39 includes four data exchange processing devices, and communicates with the data exchange processing devices according to the required number of communication paths shown in FIG. By connecting the lines, a communication path for exchanging peripheral pixel data is configured.

  Next, a flow of peripheral pixel data exchange processing performed between the image processing units will be described. FIG. 7 is a flowchart for explaining the flow of the peripheral pixel data exchange process. The peripheral pixel data exchange processing is performed as a subroutine (FIG. 4: step S140) of image processing (see FIG. 4) in the image processing apparatus 1. When the peripheral pixel data exchange processing is started, first, as the positional relationship of the image block DIn, the peripheral pixel data is exchanged between the image processing units in charge of image processing of the image block DIn adjacent in the vertical direction (step) S142). FIG. 8 is an explanatory diagram showing how the surrounding pixel data is exchanged. FIG. 8A shows a state in which the image blocks DIn1 to DIn9 are stored in each image processing unit. FIG. 8B is an explanatory diagram illustrating a state in which neighboring pixel data is exchanged between the image processing units adjacent in the vertical direction as the positional relationship of the image block DIn described in step S142. A portion surrounded by a dotted line in FIG. 8B indicates peripheral pixel data exchanged between the image processing units in charge of image processing of the image blocks DIn adjacent to each other vertically. As shown in FIG. 8B, for example, the second image processing unit 32 in charge of image processing of the image block DIn2 is mutually adjacent to the fifth image processing unit 35 in charge of the image block DIn5 adjacent in the downward direction. The fifth image processing unit 35 that exchanges data and is in charge of image processing of the image block DIn5 is adjacent to the upper and lower directions, the second image processing unit 32 and the second image processing unit 32 that are in charge of the image block DIn8 and the image block DIn8, respectively. The peripheral image data is exchanged with the 8 image processing unit 38.

At this time, for example, the image block DIn1 transmits the peripheral image data required for the image processing by the image block DIn4 to the DIn4, and the image block DIn5 is included in the image block DIn1 among the peripheral pixel data required for the image processing. The neighboring pixel data (horizontal line hatched portion in FIG. 8B) is also transmitted to the image block DIn 4 at the same time. The data exchanging unit 341 of the fourth image processing unit 34 corresponding to the image block DIn4 temporarily stores the peripheral pixel data in the frame memory 344 included in the fourth image processing unit. In this case, among the peripheral pixel data transmitted from the image block DIn1 to the image block DIn4, the peripheral pixel data required for the processing by the image block DIn5 is included in the peripheral pixel data required for the processing by the image block DIn4. . That is, for convenience of explanation, the two neighboring pixel data have been described as separate, but actually, the image block DIn1 transmits the neighboring pixel data necessary for the processing to the image block DIn4.

  When each image processing unit completes the exchange of the peripheral pixel data in the vertical direction, each data exchange unit notifies the timing instruction unit 60 of this. The timing instruction unit 60 analyzes the status of the exchange of the peripheral pixel data in each data exchange unit, and determines that the exchange of the peripheral pixel data has been completed in all the image processing units (step S144: Yes). As the positional relationship of the image block DIn, peripheral pixel data is exchanged between the image processing units in charge of image processing of the image block DIn adjacent in the left-right direction (step S146). FIG. 8C is an explanatory diagram showing a state in which the neighboring pixel data is exchanged between the image processing units in charge of image processing of the image blocks DIn adjacent in the left-right direction. The hatched portion in FIG. 8C is the peripheral pixel acquired by each image block DIn by exchanging the peripheral pixel data between the image blocks adjacent in the vertical direction described in FIG. 8B. It is data. Further, a portion surrounded by a dotted line of each image block DIn in FIG. 8C indicates peripheral pixel data exchanged between the image processing units in charge of image processing of the image blocks DIn adjacent to each other in the left-right direction. . As shown in FIG. 8C, for example, the image block DIn4 exchanges peripheral pixel data with the image block DIn5 adjacent in the right direction, and the image block DIn5 is the image block DIn4 and image block adjacent in the left-right direction. The peripheral pixel data is exchanged with DIn6.

  At this time, the image block DIn4 transmits the peripheral pixel data included in the image block DIn4 required for processing by the image block DIn5, and among the peripheral pixel data acquired by the image block DIn4 from the image block DIn1 in step S142, The peripheral pixel data (see FIG. 8C) required for processing by the image block DIn5 (fifth image processing unit 35) is also transmitted simultaneously. That is, the image block DIn4 (fourth image processing unit 34) mediates peripheral pixel data transmitted from the image block DIn1 (first image processing unit 31) to the image block DIn5 (fifth image processing unit 35). In other words, the image block DIn4 (fourth image processing unit 34) uses at least part of the data handled by the image block DIn5 (fifth image processing unit 35) as peripheral pixels as the image block DIn1 (first image processing unit). From the unit 31) to the image block DIn5 (fifth image processing unit 35). When attention is paid to the fact that the fourth image processing unit 34 mediates peripheral pixel data transmitted from the first image processing unit 31 to the fifth image processing unit 35, the fifth image processing unit 35 is described in the claims. “When performing image processing on the first partial image, at least pixel data of a region adjacent to the first partial image among pixels constituting another partial image adjacent to the first partial image. The acquired image data corresponds to a first image processing unit used for image processing as peripheral pixel data, and the fourth image processing unit 34 is different from the “first partial image” described in the claims. The image processing is performed on the second partial image, and at least a part of the data handled by the first image processing unit as a peripheral pixel is processed, and the partial image adjacent to the partial image handled by the first image processing unit is processed. Image processing From knit, it corresponds to the second image processing unit "that mediates toward the first image processing unit. In addition, the neighboring pixel data is exchanged between the other image processing units by the same method. For example, the peripheral pixel data included in the image block DIn5 required for the processing by the image block DIn1 is transmitted to the image block DIn2 in the process of step S142, and is transmitted from the image block DIn2 to the image block DIn1 in the process of step S146. . In this way, when each image processing unit completes the exchange of the peripheral pixel data in the left-right direction, each data exchange unit notifies the timing instruction unit 60 of this. When the timing instruction unit 60 analyzes the status of the exchange of the peripheral pixel data in each data exchange unit and determines that the exchange of the peripheral pixel data has been completed in all the image processing units (step S148: Yes), the peripheral pixel data The exchange process ends. FIG. 8D is an explanatory diagram showing peripheral pixel data exchanged by the peripheral pixel data exchange processing described with reference to FIGS. 8B and 8C. The hatched portion is the peripheral pixel data acquired by each image block DIn by the peripheral pixel data exchange process. By exchanging peripheral pixel data in this way, it is possible for each image processing unit to exchange peripheral pixel data necessary for image processing.

  As described above, by using the peripheral pixel data exchanging method in the first embodiment, the peripheral pixel data of the vertical direction (FIG. 7: step S142) and the horizontal direction (FIG. 7: step S146) are totaled twice. By exchanging, it is possible for each image processing unit to exchange peripheral pixel data necessary for image processing, and it is possible to exchange peripheral pixel data at high speed. Further, as can be seen from FIG. 6, each image processing unit does not have to be connected to all the image processing units, and is responsible for image processing of the image block DIn that is adjacent vertically and horizontally as the positional relationship of the image block DIn. It is only necessary to be connected to the image processing unit. That is, it is sufficient that one image processing unit is connected to a maximum of four image processing units. Therefore, each image processing unit is connected to all adjacent image processing units by a line for exchanging peripheral pixel data, and compared with a case where each of the image processing units directly communicates and exchanges peripheral pixel data, Due to the structure of the image processing apparatus, the number of transceivers, the number of wires, the number of pins of the device, and the like can be reduced. In addition, as a correspondence relationship with the claims, the image blocks DIn1 to 9 correspond to the partial images described in the claims, and each image processing unit corresponds to the image processing unit described in the claims. The image synthesizing unit 40 corresponds to the image output unit described in the claims.

  In the first embodiment, the example in which the image data DIn0 is divided into 3 × 3 has been described. However, the image data DIn0 may be divided into a larger number of divisions, for example, 4 × 4, 10 × 10, 16 × 9, or the like. The same effects as in the first embodiment can be obtained. That is, as the positional relationship of the image block DIn, if each image processing unit in charge of processing of each image block DIn is connected to the image processing unit in charge of image processing of the image block DIn adjacent in the vertical and horizontal directions, 1 By connecting a maximum of four image processing units to a maximum of four image processing units, the peripheral pixel data is exchanged in a total of two times in the vertical and horizontal directions. It is possible to exchange the peripheral pixel data at high speed.

  In this embodiment, among the plurality of image processing units, there are an image processing unit that mediates peripheral pixel data necessary for processing by other image processing units, and an image processing unit that does not mediate, but all image processing units May have an intermediary function, and an intermediary process may be performed according to the arrangement relationship in the image data DIn0 of the image block DIn in charge of the process. In this case, the plurality of image processing units at least “when performing image processing on the first partial image, at least the first of the pixels constituting the other partial image adjacent to the first partial image. The pixel data of the area adjacent to the partial image is acquired, and as the peripheral pixel data, the “first image processing unit used for image processing” and “the second partial image different from the first partial image” From the image processing unit that performs image processing and processes at least a part of data of pixels handled by the first image processing unit as peripheral pixels, a partial image adjacent to the partial image handled by the first image processing unit, And a second image processing unit that mediates toward the first image processing unit.

B. Second embodiment:
Next, a second embodiment will be described. The difference between the first embodiment and the second embodiment is the exchange path of the peripheral pixel data of each image block DIn. Accordingly, the flow of exchanging peripheral pixel data is also different between the first embodiment and the second embodiment. The peripheral pixel data exchange path in the second embodiment is configured such that the image blocks DIn1 to 9 are connected by one path and without passing through the same path twice in the positional relationship of the image block DIn. To do. In other words, a path is constructed between the image blocks DIn1 to DIn9 in the manner of a so-called “one stroke writing (an Eulerian path (when closed) or a traversable figure (when starting point and ending point are different))”. An example is shown in FIG. FIG. 9A is an explanatory diagram showing an example of an exchange path of peripheral pixel data of each image block DIn in the second embodiment. Image blocks (actually image processing units) are connected by an exchange path. This exchange path is a path through which image blocks (actually image processing units) directly acquire peripheral pixel data. This exchange route corresponds to the data acquisition route described in the claims. As shown in FIG. 9A, the replacement path of the peripheral pixels is configured to connect the image blocks DIn1 to 9 with one path and without passing through the same image block twice. Using such an exchange path, each image processing unit exchanges peripheral pixel data. Note that the arrows shown in FIG. 9A indicate the exchange path of the peripheral pixel data between the image processing units, and bidirectional data exchange is possible with one data exchange. In addition, as a condition that a single stroke can be drawn, one stroke is drawn when “the number of vertices with odd numbers of vertices is 0 (closed) or 2 (start point and end point are different)”. Can be written. When this is replaced with the present embodiment, “when the number of image processing units having an odd number of peripheral pixel data exchange paths connected to the image processing unit is 0 or 2,” A simple one-stroke path configuration is possible. In other words, one-stroke path configuration is possible when “the number of data exchange units that directly exchange data with an odd number of other data exchange units among the data exchange units is 0 or 2”. It is. In this way, each image processing unit and the data acquisition path are configured, and a path that passes through all the image processing units once is formed. Note that such a series of peripheral pixel data exchange paths that allow one-stroke writing correspond to the data communication paths described in the claims.

  Next, a method for exchanging peripheral pixel data will be described. For example, when the peripheral pixel data (see FIG. 5) included in the image block DIn1 necessary for image processing of the image block DIn5 is exchanged, the peripheral pixel data is transferred to DIn5 through the exchange path of DIn1 → DIn2 → DIn3 → DIn6 → DIn5. Is sent. In addition, as described above, data exchange can be performed bidirectionally with a single data exchange. For example, DIn1 and DIn4 (or DIn6 and DIn9) that are farthest as the peripheral pixel data exchange path can exchange the peripheral pixel data by performing data exchange at five times.

  FIG. 9B is an explanatory diagram illustrating the timing of data exchange required for data exchange between DIn1 and DIn4 and the direction of the exchange. For convenience of explanation, the exchange path of peripheral pixel data from DIn1 to DIn4 is expressed in a straight line. A solid line arrow indicates that peripheral pixel data included in DIn1 that requires DIn4 is transmitted to DIn4 sequentially from DIn1 via DIn2, DIn3, DIn6, and DIn5. On the other hand, the broken arrow indicates that the peripheral pixel data included in DIn4 that requires DIn1 is transmitted to DIn1 sequentially from DIn4 via DIn5, DIn6, DIn3, and DIn2.

  The numbers above the arrows indicate the timing at which data exchange is performed. That is, at the timing of the first data exchange, data exchange of DIn1 → DIn2 and data exchange of DIn4 → DIn5 are performed. At the timing of the second data exchange, data exchange of DIn2-> DIn3 and data exchange of DIn5-> DIn6 are performed. By exchanging the peripheral pixel data in this way, DIn1 and DIn4 can exchange the peripheral pixel data at the timing of data exchange five times. Further, within the timing of the five data exchanges, for example, DIn2 and DIn5, DIn3 and DIn5, and the like can exchange peripheral pixel data via other image blocks DIn. Of course, DIn1 and DIn2 and DIn5 and DIn4 that directly exchange peripheral pixel data can directly exchange the peripheral pixel data within the timing of the five data exchanges.

  Similarly, the peripheral pixel data required by each of the other image processing units requires the peripheral image data via the other image processing unit via the exchange path shown in FIG. 9A. To the image processing unit. The exchange path shown in FIG. 9A corresponds to “when the start point and the end point are different” in a single stroke. In this case, each image processing unit exchanges peripheral pixel data bidirectionally, and each image processing unit acquires the necessary peripheral pixel data. Note that the exchange path can also be configured as a “closed circuit” in a single stroke. In this case, since the exchange path is a loop, each image processing unit has peripheral pixels in only one direction on the exchange path. The data may be transmitted, and each pixel processing unit may acquire (or refer to) the peripheral pixel data when the peripheral pixel data necessary for processing passes through the image processing unit. The specific route will be described in a later modification.

  As described above, by using the peripheral pixel data exchange method in the second embodiment, each image processing unit does not have to be connected to all the image processing units, and one or two image processing units. As long as it is connected. Therefore, compared with the first embodiment, the number of transceivers, the number of wires, the number of device pins, and the like can be further reduced due to the structure of the image processing apparatus.

C. Variation:
The present invention is not limited to the above-described examples and embodiments, and can be implemented in various modes without departing from the gist thereof. For example, the following modifications are possible.

(C1) Modification 1:
In the above embodiment, the image data DIn0 is divided into 3 × 3, but the same effect can be obtained even if the image data is divided into M × N (M and N are positive integers of 2 or more) such as 4 × 4 and 4 × 3. Can be obtained. When the number of divisions is increased, the number of pixels processed by each image processing unit is reduced, so that the processing speed of image processing is further increased compared to the above-described embodiment.

(C2) Modification 2:
In the first embodiment, the peripheral pixel data exchange processing is performed in the up-down direction (vertical direction) first and then in the left-right direction (horizontal direction). However, as Modification 2, the left-right direction (horizontal direction) is first performed. It may be performed later, and the vertical direction (vertical direction) may be performed later. Even if it does in this way, it is possible to acquire the effect similar to the said 1st Example.

(C3) Modification 3:
In the second embodiment, the peripheral pixel data is exchanged by the peripheral pixel data exchange path shown in FIG. 9, but the present invention is not limited to this, and DIn0 may be divided into 3 × 3 or other division numbers. Is possible. For example, it is possible to exchange peripheral pixel data by configuring the exchange path shown in FIG. The exchange paths shown in FIGS. 10A and 10B are configured to connect the image blocks DIn with one path and without passing the same path twice. FIG. 10B shows the “ closed circuit” path configuration described above. When the surrounding pixel data is exchanged by the exchange path configured as described above, as described above, each data exchange unit may transmit the surrounding pixel data only in one direction on the path. Even with such a path configuration, it is possible to obtain the same effect as in the second embodiment.

(C4) Modification 4:
In the above embodiment, after the partial image data is accumulated in each image processing unit, the timing instruction unit outputs an instruction to start data exchange to each image processing unit. However, in this modification, the timing instruction unit 60 Analyzing the state of image data storage in each of the image processing units 31 to 39, and instructing the processing unit that can exchange data among the first to ninth image processing units 31 to 39 to start data exchange. To do. By exchanging data in this way, it is possible to exchange data at a higher speed than in the above embodiment.

(C5) Modification 5:
In the above embodiment, the image blocks DIn1 to 9 are input from the video storages St1 to St9 to the projector via the image input units 21 to 29. However, in the fifth modification, the image data DIn0 is input to the projector. In the image processing apparatus 1a, the image data DIn0 is divided into image blocks DIn1 to DIn9. FIG. 11 is an explanatory diagram illustrating the configuration of the image processing device 1a according to the fifth modification. The functional parts having the same functions as those in the first embodiment are denoted by the same reference numerals. As shown in FIG. 11, the image data DIn0 is input from the video storage St0 storing the image data DIn0 to the image image input unit 20a, and the image dividing unit 90 included in the image processing apparatus 1a converts the image data DIn0 into the image block DIn1. Are divided into DIn9 and transmitted to the image processing units 31 to 39. The subsequent processes are the same as those in the first embodiment. Even if it is such a structure, the effect similar to the said Example is acquired.

(C6) Modification 6:
In the above embodiment, the data exchange unit exchanges data with a plurality of other image processing units by providing a plurality of data exchange processing devices that exchange peripheral pixel data with other image processing units. As a sixth modification, a configuration is possible in which the number of data exchange processing devices is smaller than that of the above-described embodiment by providing a changeover switch SW for switching the direction of data exchange.

  FIG. 12 is an explanatory diagram illustrating a specific example of the sixth modification. As shown in FIG. 12, in the image processing apparatus, as in the first embodiment, each image processing unit is connected to adjacent image processing units in the vertical and horizontal directions. Furthermore, as a feature of the modification 6, a changeover switch SW is provided on the connection path as necessary. In FIG. 12, the selector switch SW is provided outside the image processing unit, but may be provided inside the image processing unit. In the case of the specific example of FIG. 12, when exchanging neighboring pixel data between the image processing units, a maximum of four image processes can be performed by switching the changeover switch SW as necessary at the time of data exchange. Communication is possible, and data exchange substantially equivalent to that of the first embodiment is possible. With this configuration, it is not necessary for the image processing unit to include four data exchange processing devices, and the number of data exchange processing devices can be reduced.

  In addition, the connection path to each image processing unit is a so-called one-stroke writing configuration as in the second embodiment, and the image processing unit that exchanges data with two or more image processing units includes a changeover switch SW and is necessary. Accordingly, the selector switch SW may be switched at the data exchange timing. In this way, the number of data exchange processing devices can be reduced as compared with the second embodiment.

DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus 10 ... Image input part 20 ... Image division part 31-39 ... 1st-9th image processing part 40 ... Image composition part 50 ... Image output part 60 ... Timing instruction | indication part 71 ... CPU
DESCRIPTION OF SYMBOLS 80 ... Frame memory 81 ... Input interface 83 ... Output interface 85 ... Instruction input interface 341 ... Data exchange part 344 ... Frame memory 351 ... Divided image input part 352 ... Data exchange part 353 ... Frame memory control part 354 ... Frame memory 355 ... Filter Processing unit 356 ... Divided image output unit DIn0 ... Image data DIn1-9 ... Image block DOut0 ... Image data St1-St9 ... Video storage SW ... Changeover switch PC1-PC9 ... Computer

Claims (4)

An image processing apparatus that processes image data representing an image composed of a plurality of pixels,
The display image corresponding to the image data is provided corresponding to each partial image obtained by two-dimensionally dividing the display image in the horizontal direction and the vertical direction, and the image data corresponding to the partial image is input to configure each partial image. A plurality of image processing units that process pixel data with reference to peripheral pixel data that is pixel data of the partial image outside the partial image ;
An image output unit that outputs image data for display using pixel data after the image processing is performed by the image processing unit;
Each of the plurality of image processing units is
At each of the two timings prior to the image processing, the peripheral pixel data is exchanged with the image processing units respectively adjacent to the image processing units in the horizontal direction or the vertical direction,
At the first timing, the peripheral pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction,
The peripheral pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction at a second timing different from the first timing,
An image processing apparatus that performs the image processing including peripheral pixel data of a diagonally adjacent partial image that is acquired by the two-time exchange and that is adjacent to the partial image corresponding to the image processing unit in a diagonal direction . The image processing apparatus according to claim 1, further comprising:
An image data input unit for inputting the image data;
An image processing apparatus comprising: an image dividing unit configured to two-dimensionally divide the display image corresponding to the image data into a plurality of partial images and input the partial images to the image processing units. The image processing apparatus according to claim 1 , further comprising:
An image processing apparatus comprising: a timing control unit that controls a plurality of time-divided timings at which the image processing units exchange the peripheral pixel data. Image data representing an image composed of a plurality of pixels is provided corresponding to each partial image obtained by two-dimensionally dividing the display image corresponding to the image data in the horizontal direction and the vertical direction. A plurality of image processing units that input the processed image data and process the data of each pixel constituting the partial image with reference to peripheral pixel data that is pixel data of the partial image outside the partial image An image processing method for processing,
Each of the plurality of image processing units is
At each of the two timings prior to the image processing, the peripheral pixel data is exchanged with the image processing units respectively adjacent to the image processing units in the horizontal direction or the vertical direction,
At the first timing, the peripheral pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction,
The peripheral pixel data is exchanged with the image processing unit adjacent to the image processing unit in either the horizontal direction or the vertical direction at a second timing different from the first timing,
An image processing method for performing the image processing including peripheral pixel data of a diagonally adjacent partial image diagonally adjacent to the partial image corresponding to the image processing unit acquired by the two exchanges .

Images