JP5749317B2 - Magnetic resonance imaging system - Google Patents

Description

  The present invention relates to magnetic resonance imaging.

  In general, in a magnetic resonance image diagnostic apparatus, the acquisition system has become multi-channel, and a large number of coil units can be connected to a control unit. For this reason, since the number of connection cables between the coil unit and the control unit is increased and inconvenient, it is desired to wirelessly transmit the signal transmission between the coil unit and the control unit.

  Under such circumstances, a technique for wirelessly transmitting a signal between the coil unit and the control unit has already been proposed (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 05-261085 JP 2001-76439 A

  In recent years, the multi-functionalization of the coil unit has progressed, and it is necessary to be able to control the operation state of the coil unit from the control unit. If the control signal for that purpose is transmitted wirelessly, the number of wireless channels further increases.

  On the other hand, the present applicant has already proposed as a Japanese Patent Application No. 2009-122247 a technology that uses a digital wireless system for signal transmission between a coil unit and a control unit (main unit). According to the technology of this Japanese Patent Application No. 2009-122247, a radio channel for transmitting a sampling clock and a carrier wave is required.

  As described above, signal transmission between the coil unit and the control unit requires a large number of radio channels, and there is a problem that the circuit scale for transmitting and receiving radio signals increases.

  The present invention has been made in view of such circumstances. The purpose of the present invention is firstly to reduce the number of radio channels, thereby reducing the circuit scale for transmission and reception of radio signals. An object of the present invention is to provide an image diagnostic apparatus and a phase comparator suitable for such a magnetic resonance image diagnostic apparatus.

  A magnetic resonance imaging apparatus according to an aspect of the present invention is a magnetic resonance imaging apparatus including a control unit and a coil unit that is separate from the control unit, and the control unit outputs a first clock signal. A clock signal generation unit for generating, a control signal generation unit for generating a control signal for instructing an operating state of the coil unit, and modulating the first clock signal with the control signal to thereby convert the control signal into the control signal A modulation unit for obtaining a modulation signal multiplexed with the first clock signal, a clock transmission signal generation unit for generating a clock transmission signal including the modulation signal, and a clock transmission antenna for radiating the clock transmission signal to space And the coil unit converts a clock transmission signal propagated through the space into an electric signal state. A detection unit that detects the modulation signal from the clock transmission signal converted into an electric signal state by the clock receiving antenna, and a first unit that is synchronized with the first clock signal from the modulation signal detected by the detection unit. A clock reproducing unit that generates a clock signal of 2; a coil that detects a magnetic resonance signal generated in the subject; and the magnetic resonance signal detected by the coil is digitally converted in synchronization with the second clock signal. Instructed by a digital conversion unit, a data detection unit that detects the control signal using the second clock signal from the modulation signal detected by the detection unit, and the control signal detected by the data detection unit A control unit that controls the operation state of the coil unit so as to be in an operation state.

  According to the present invention, it is possible to reduce the number of radio channels, thereby reducing the circuit scale for transmitting and receiving radio signals.

1 is a diagram showing a configuration of a magnetic resonance imaging apparatus (MRI apparatus) according to an embodiment of the present invention. The block diagram of the coil unit and radio | wireless unit in FIG. FIG. 3 is a block diagram of a detection unit, a clock recovery unit, and a data detection unit in FIG. 2. The figure which shows an example of a modulation signal. The figure which shows an example of a modulation signal. The figure which shows an example of a modulation signal. The timing diagram of a data signal and the change of an operating state. The timing diagram of a data signal and the change of an operating state. The block diagram in 1st Embodiment of the clock reproduction | regeneration part in FIG. FIG. 10 is a timing chart in an example of the operation of the phase comparator 33a in FIG. 9; The block diagram in the 1st modification of 1st Embodiment of the clock reproduction | regeneration part in FIG. FIG. 12 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in the 2nd modification of 1st Embodiment of the clock reproduction | regeneration part in FIG. FIG. 14 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in 2nd Embodiment of the clock reproduction | regeneration part in FIG. FIG. 16 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in the 1st modification of 2nd Embodiment of the clock reproduction | regeneration part in FIG. FIG. 18 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in the 2nd modification of 2nd Embodiment of the clock reproduction | regeneration part in FIG. FIG. 20 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The timing diagram in the modification of the operation | movement of the phase comparator 33a in FIG. FIG. 18 is a timing chart in a modified example of the operation of the phase comparator 33a in FIG. FIG. 20 is a timing chart in a modified example of the operation of the phase comparator 33a in FIG. The block diagram in 3rd Embodiment of the clock reproduction | regeneration part 33 in FIG. The timing diagram in an example of operation | movement of the phase comparator 33a in FIG. The block diagram in the 1st modification of 3rd Embodiment of the clock reproduction | regeneration part in FIG. FIG. 27 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in the 2nd modification of 3rd Embodiment of the clock reproduction | regeneration part in FIG. FIG. 29 is a timing chart in an example of the operation of the phase comparator 33a in FIG. The block diagram in the 3rd modification of 3rd Embodiment of the clock reproduction | regeneration part in FIG. The block diagram in the 4th modification of 3rd Embodiment of the clock reproduction | regeneration part in FIG. The figure which shows the concept implement | achieved by connecting the phase comparator to the existing PLL in the 3rd and 4th modification of 3rd Embodiment.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing the configuration of a magnetic resonance imaging apparatus (MRI apparatus) 100 according to this embodiment. The MRI apparatus 100 includes a static magnetic field magnet 1, a gradient magnetic field coil 2, a gradient magnetic field power source 3, a bed 4, a bed control unit 5, coil units 6a and 6b, a transmission unit 7, a clock signal generation unit 8, a high frequency pulse / gradient magnetic field control. Unit 9, driver 10, wireless unit 11, system reconfiguration front end 15, reconfiguration system 20, storage unit 21, display unit 22, input unit 23, main control unit 24, and data signal generation unit 25. Of these components, the components other than the coil unit 6b are provided in a main unit separate from the coil unit 6b. The main unit may be divided into a gantry and a processing unit. In this case, for example, the static magnetic field magnet 1, the gradient magnetic field coil 2, the gradient magnetic field power source 3, the bed 4, the bed control unit 5, the coil unit 6a, the transmission unit 7, the high frequency pulse / gradient magnetic field control unit 9, and the wireless unit 11 are The processing unit includes a clock signal generation unit 8, a driver 10, a system reconfiguration front end 15, a reconfiguration system 20, a storage unit 21, a display unit 22, an input unit 23, and a main control unit 24. Thus, the main unit or the processing unit has a function as a control unit.

  The static magnetic field magnet 1 has a hollow cylindrical shape and generates a uniform static magnetic field in an internal space. As the static magnetic field magnet 1, for example, a permanent magnet, a superconducting magnet or the like is used.

  The gradient magnetic field coil 2 has a hollow cylindrical shape and is disposed inside the static magnetic field magnet 1. The gradient magnetic field coil 2 is a combination of three types of coils corresponding to the X, Y, and Z axes orthogonal to each other. The gradient magnetic field coil 2 generates a gradient magnetic field in which the above three types of coils are individually supplied with current from the gradient magnetic field power supply 3 and the magnetic field strength is inclined along the X, Y, and Z axes. The Z-axis direction is the same as the static magnetic field direction, for example. The gradient magnetic fields of the X, Y, and Z axes correspond to, for example, the slice selection gradient magnetic field Gs, the phase encoding gradient magnetic field Ge, and the readout gradient magnetic field Gr, respectively. The slice selection gradient magnetic field Gs is used to arbitrarily determine an imaging section. The phase encoding gradient magnetic field Ge is used to change the phase of the magnetic resonance signal in accordance with the spatial position. The readout gradient magnetic field Gr is used for changing the frequency of the magnetic resonance signal in accordance with the spatial position.

  The subject 200 is inserted into a space (imaging space) inside the gradient magnetic field coil 2 while being placed on the top 4 a of the bed 4. Under the control of the bed control unit 5, the bed 4 moves the top plate 4a in the longitudinal direction (left and right direction in FIG. 1) and in the vertical direction. Usually, the bed 4 is installed such that the longitudinal direction thereof is parallel to the central axis of the static magnetic field magnet 1.

  The coil unit 6a is configured by housing one or more coils in a cylindrical case. The coil unit 6 a is disposed inside the gradient magnetic field coil 2. The coil unit 6a receives a high frequency pulse (RF pulse) from the transmitter 7 and generates a high frequency magnetic field.

  The coil unit 6b is placed on the top plate 4a, built in the top plate 4a, or attached to the subject 200. At the time of imaging, the magnetic resonance signal inserted into the imaging space together with the subject 200 and radiated as electromagnetic waves from the subject 200 is received to obtain an electrical magnetic resonance signal. As the coil unit 6b, various types can be arbitrarily mounted. Two or more receiving coil units may be mounted. The coil unit 6b has a function of digitally transmitting a magnetic resonance signal obtained as an electrical signal.

  The transmitter 7 supplies an RF pulse corresponding to the Larmor frequency to the coil unit 6a.

  The clock signal generator 8 generates a first clock signal having a predetermined frequency. This first clock signal may also be used as a system clock that serves as a reference for the overall operation timing of the MRI apparatus 100.

  The high-frequency pulse / gradient magnetic field control unit 9 controls the gradient magnetic field power supply 3 and the transmission unit 7 so as to change each gradient magnetic field according to a required pulse sequence and transmit an RF pulse under the control of the main control unit 24. . The high-frequency pulse / gradient magnetic field controller 9 is supplied with the first clock signal after its level is appropriately adjusted by the driver 10. The high-frequency pulse / gradient magnetic field control unit 9 advances the pulse sequence in synchronization with the first clock signal.

  The wireless unit 11 receives the magnetic resonance signal digitally transmitted from the coil unit 6b. The wireless unit 11 digitally demodulates the received magnetic resonance signal in the digital state and outputs the demodulated signal to the system reconstruction front end 15. The wireless unit 11 wirelessly transmits the first clock signal and the modulation / demodulation clock signal to the coil unit 6b. Further, the wireless unit 11 wirelessly transmits the data signal together with the first clock signal by modulating the first clock signal with the data signal output from the data signal generation unit 25.

  The system reconstruction front end 15 performs gain control, frequency conversion, and quadrature detection on the magnetic resonance signal given from the wireless unit 11. Furthermore, the system reconfiguration front end 15 performs a restoration process of the amplitude compression in the coil unit 6b on the magnetic resonance signal.

  The reconstruction system 20 reconstructs an image related to the subject 200 based on at least one of the magnetic resonance signals after being processed by the system reconstruction front end 15.

  The storage unit 21 stores various data such as image data indicating an image reconstructed by the reconstruction system 20.

  The display unit 22 displays various information such as images reconstructed by the reconstruction system 20 and various operation screens for the user to operate the MRI apparatus 100 under the control of the main control unit 24. A display device such as a liquid crystal display can be used as the display unit 22.

  The input unit 23 receives various commands and information input from the operator. As the input unit 23, a pointing device such as a mouse or a trackball, a selection device such as a mode change switch, or an input device such as a keyboard can be used as appropriate.

  The main control unit 24 includes a CPU, a memory, and the like (not shown), and controls the MRI apparatus 100 overall.

  The data signal generator 25 generates a data signal for instructing the operating state of the coil unit 6b under the instruction of the main controller 24.

  FIG. 2 is a block diagram of the coil unit 6b and the wireless unit 11 in FIG.

  The coil unit 6b includes a clock reception antenna 31, a detection unit 32, a clock reproduction unit 33, a carrier wave generation unit 35, a plurality of coils 36, a coupling circuit 37, a selector 38, a LOG amplifier 39, a digital conversion unit 40, and a start signal addition unit. 41, a modulation processing unit 42, a driver 43, a resonance signal transmitting antenna 44, a data detection unit 45, and a control unit 46. The wireless unit 11 includes a modulation unit 51, a carrier signal generation unit 52, an amplitude modulation unit 53, a driver 54, a clock transmission antenna 55, a modulation / demodulation signal generation unit 56, and a demodulation processing unit 63.

  The modulation unit 51 generates a modulation signal by modulating the first clock signal output from the clock signal generation unit 8 with the data signal output from the data signal generation unit 25.

  The carrier signal generation unit 52 generates a carrier signal having a predetermined frequency for wirelessly transmitting the modulation signal. The frequency of the carrier signal is set to a value that avoids a frequency that is 1 / integer of the magnetic resonance frequency.

  The amplitude modulation unit 53 generates a clock transmission signal by amplitude-modulating the carrier signal with the modulation signal.

  The driver 54 adjusts the clock transmission signal to a level suitable for wireless transmission.

  Thus, the carrier signal generation unit 52, the amplitude modulation unit 53, the driver 54, and the clock transmission antenna 55 constitute a clock transmission signal generation unit that generates a clock transmission signal including the modulation signal.

  When an electrical clock transmission signal output from the driver 54 is supplied to the clock transmission antenna 55, the clock transmission antenna 55 radiates this as an electromagnetic wave to the space.

  The clock receiving antenna 31 receives electromagnetic waves including those radiated from the clock transmitting antenna 55 and outputs an electrical signal corresponding to the electromagnetic waves.

  The detector 32 detects the modulation signal from the clock transmission signal included in the electrical signal output from the clock transmission antenna 55.

  The clock recovery unit 33 generates a second clock signal that is synchronized with the component of the first clock signal included in the modulation signal detected by the detection unit 32.

  The modulation / demodulation signal generation unit 56 generates a demodulation signal having a predetermined frequency.

  The carrier wave generation unit 35 generates a carrier wave using the second clock signal reproduced by the clock reproduction unit 33. The frequency of the carrier wave is set to a value different from the frequency of the carrier signal while avoiding a frequency that is 1 / integer of the magnetic resonance frequency. Then, the carrier wave generation unit 35 appropriately adjusts the level of the reproduced carrier wave and supplies it to the modulation processing unit 42.

  At least two coils 36 are provided. Although only two are illustrated in FIG. 2, three or more may be provided. The plurality of coils 36 form a phased array coil (PAC). Each of the coils 36 receives a magnetic resonance signal radiated as an electromagnetic wave from the subject 200 and outputs an electrical magnetic resonance signal corresponding thereto.

  The coupling circuit 37 switches coupling / decoupling between two of the plurality of coils 36. The coupling circuit 37 uses, for example, a PIN diode for switching between coupling / decoupling. In the case where three or more coils 36 are provided, two or more coupling circuits 37 may be provided for each of the different combinations of the coils 36.

  The selector 38 activates the selected coil 36 by selecting one of the plurality of coils 36 under the control of the control unit 46. The selector 38 inputs the magnetic resonance signal output from the selected coil 36 to the LOG amplifier 39. Note that the selector 38 may be able to select all of the plurality of coils 36 or a part of at least two coils 36 at the same time. For example, if the plurality of coils 36 are divided into several sections and at least two coils 36 belong to each section, the selector 38 simultaneously selects at least two coils 36 belonging to the same section.

  The LOG amplifier 39 compresses the amplitude of the magnetic resonance signal input from the selector 38 according to a predetermined logarithmic function.

  The digital conversion unit 40 digitizes the analog magnetic resonance signal output from the LOG amplifier 39. The digital conversion unit 40 performs sampling of the magnetic resonance signal for digitization described above in synchronization with the second clock signal supplied from the clock reproduction unit 33.

  The start signal adding unit 41 adds a start signal indicating the start timing of the echo signal to the magnetic resonance signal digitized by the digital conversion unit 40 under the control of the control unit 46.

  The modulation processing unit 42 performs encoding for digital transmission on the magnetic resonance signal after adding the start signal. For this encoding, for example, a convolutional code, a Reed-Solomon code, a turbo code, or an LDCP code can be applied. Further, the modulation processing unit 42 obtains a transmission signal by modulating the carrier wave supplied from the carrier wave generating unit 35 with the encoded magnetic resonance signal.

  The driver 43 adjusts the transmission signal output from the modulation processing unit 42 to a level suitable for wireless transmission and supplies the signal to the resonance signal transmitting antenna 44.

  Thus, the carrier wave generation unit 35, the modulation processing unit 42, and the driver 43 constitute a resonance signal transmission unit.

  The resonance signal transmitting antenna 44 radiates an electric transmission signal supplied from the driver 43 to the space as an electromagnetic wave.

  The antenna 62 receives an electromagnetic wave including that radiated from the resonance signal transmitting antenna 44 and outputs an electrical signal corresponding to the electromagnetic wave.

  The demodulation processing unit 63 demodulates the electrical signal output from the antenna 62 using the carrier wave supplied from the modulation / demodulation signal generation unit 56 to the digital magnetic resonance signal.

  FIG. 3 is a block diagram of the detection unit 32, the clock recovery unit 33, and the data detection unit 45.

  The detector 32 includes an envelope detector 32a and a filter 32b.

  The envelope detection unit 32a performs envelope detection on the clock transmission signal included in the electrical signal output from the clock transmission antenna 55, and extracts a signal component corresponding to the modulation signal.

  The filter 32b extracts a modulated signal by suppressing a signal outside the desired band by band limitation from the signal component extracted by envelope detection.

  The clock recovery unit 33 includes a phase comparator 33a, a loop filter 33b, and an oscillator (hereinafter referred to as VCO) 33c.

  The phase comparator 33a compares the phase of the modulation signal supplied from the detector 32 and the second clock signal output from the VCO 33c, and outputs a clock phase difference signal.

  The loop filter 33b generates a control voltage for the VCO 33c by band-limiting the clock phase difference signal.

  The VCO 33c oscillates the second clock signal. The VCO 33c changes the oscillation frequency in accordance with the voltage of the control signal given from the loop filter 33b.

  The data detection unit 45 includes a sampling unit 45a and a detection unit 45b.

  The sampling unit 45 a samples the modulation signal supplied from the detection unit 32 in synchronization with the second clock signal supplied from the clock recovery unit 33.

  The detection unit 45b detects the data signal by comparing the code string obtained by the sampling unit 45a with a predetermined data pattern as a data signal.

  Based on the data signal detected by the data detection unit 45, the control unit 46 includes a coupling circuit 37, a selector 38, a LOG amplifier 39, a digital conversion unit 40, a start signal addition unit 41, a modulation processing unit 42, and a driver 43. The operation state is controlled as described later.

  Next, the operation of the MRI apparatus 100 configured as described above will be described. However, an operation similar to that of an existing MRI apparatus such as an operation of generating an echo signal in the subject 200, collecting the echo signal, and reconstructing an image related to the subject 200 based on the collected echo signal. The description will be omitted, and the characteristic operation of the MRI apparatus 100 will be mainly described.

  In the coil unit 6b, for example, the operation state can be changed for the following items.

  (1) Selection state of the coil 36 by the selector 38.

  (2) Coupling mode / decoupling mode selected.

  (3) Add start signal to magnetic resonance signal.

  (4) Transmission / non-transmission of magnetic resonance signals.

  These operating states are determined by the main control unit 24.

  When it becomes necessary to change any operation state in the coil unit 6b, the main control unit 24 instructs the data signal generation unit 25 to generate a data signal for instructing such a change in the operation state. Upon receiving this instruction, the data signal generator 25 generates a data signal designated by the main controller 24. The data signal is represented by a series in which “0” or “1” is arranged, and the pattern of the series varies depending on the contents to be instructed. Different data patterns are assigned in advance in association with the items in the operation state as described above. The data signal generator 25 generates a series of data signals having a data pattern corresponding to the item instructed from the main controller 24.

  The data signal generated by the data signal generation unit 25 is given to the modulation unit 51. When the data signal is supplied in this way, the modulation unit 51 modulates the first clock signal supplied from the clock signal generation unit 8 with the data signal to obtain a modulation signal. For this modulation, for example, OOK (ON-OFF-Keying) and ASK (Amplitude-shift-Keying) can be used.

  4, 5 and 6 are diagrams showing examples of modulated signals.

  In FIGS. 4, 5, and 6, sections 301, 401, and 501 represent the period of the first clock signal. In the examples of FIGS. 4, 5, and 6, the data signal is multiplexed by changing the amplitude in units of the period of the first clock signal. For example, “1” is set when the amplitude of the first clock signal is left as it is, and “0” is set when the amplitude is decreased. Thus, data signals having sequences of “10010110”, “01001011”, and “01001110” are multiplexed in the sections 302, 402, and 502, respectively.

  The modulation signal obtained in this way by the modulation unit 51 is used to amplitude-modulate the carrier signal generated by the carrier signal generation unit 52 in the amplitude modulation unit 53. The clock transmission signal obtained by the amplitude modulation unit 53 is supplied to the clock transmission antenna 55 via the driver 54 and radiated as a radio wave from the clock transmission antenna 55 to the space. When this radio wave propagates through the space and reaches the clock reception antenna 31, the clock transmission signal is returned to the electrical signal state by the clock reception antenna 31. Then, when the clock transmission signal is detected by the detection unit 32, a modulation signal is extracted from the clock transmission signal. This modulated signal is supplied to the clock recovery unit 33 and the data detection unit 45, respectively.

  In the clock reproduction unit 33, the second clock signal synchronized with the modulation signal is generated, whereby the first clock signal included in the modulation signal is reproduced in a pseudo manner. The data detection unit 45 samples the modulation signal in synchronization with the second clock signal generated by the clock recovery unit 33, and further compares the code string obtained by this sampling with a predetermined data pattern. A data signal is detected. Then, the data signal itself or a command associated with the instruction indicated by the data signal is given from the data detection unit 45 to the control unit 46.

  In this way, an instruction regarding any change in the operating state of the coil unit 6b is wirelessly sent to the control unit 46 of the coil unit 6b in a state of being superimposed on the first clock signal.

  In accordance with the instruction given in this way, the control unit 46 changes the operation state for each of the above items as follows.

  (1) If the change of the coil 36 to be activated among the plurality of coils 36 is instructed, the control unit 46 controls the selector 38 so as to select the coil 36 to be newly activated.

  (2) If the setting of the coupling mode is instructed, the control unit 46 sets the coupling circuit 37 to the coupling state, and if the setting of the decoupling mode is instructed, sets the coupling circuit 37 to the decoupling state. .

  (3) If the addition of the start signal to the magnetic resonance signal is instructed, the control unit 46 controls the start signal adding unit 41 to add the start signal to the magnetic resonance signal.

  (4) The control unit 46 operates the LOG amplifier 39, the digital conversion unit 40, the modulation processing unit 42, and the driver 43 when the transmission of the magnetic resonance signal is instructed, and the LOG amplifier 39 when the non-transmission is instructed. Then, the digital conversion unit 40, the modulation processing unit 42, and the driver 43 are stopped.

  In this embodiment, the data signal is handled as a trigger signal. That is, the main control unit 24 causes the data signal generation unit 25 to generate a data signal at a timing when it is necessary to change some operation state in the coil unit 6b. Then, the control unit 46 changes the operation state in response to the data signal being detected by the data detection unit 45. However, as shown in FIG. 7, only the timing for switching from the first operation state to the second operation state is instructed by the data signal, and after the second operation state is continued for a predetermined period, The first operation state may be switched without depending on the instruction in the data signal, and the timing for switching from the first operation state to the second operation state and the second operation as shown in FIG. It may be instructed by a data signal at any timing for switching from the state to the first operation state. In the latter case, the data pattern of the data signal is further changed between the timing of switching from the first operating state to the second operating state and the timing of switching from the second operating state to the first operating state. Also good.

  For the change of the operation state (1), the form shown in FIG. 8 is generally suitable. Regarding the change of the operation state (2), either the form shown in FIG. 7 or the form shown in FIG. 8 may be suitable depending on the coupling mode change sequence. That is, if one of the modes is set only for a certain period and the change sequence for setting the other mode is adopted for the other period, the configuration shown in FIG. 7 is suitable, and the period for setting both modes is used. If a change sequence that can be changed is adopted, the form shown in FIG. 8 is suitable. Regarding the change of the operation state of (3) above, the start signal adding unit 41 should stop the process after adding a predetermined start signal to the magnetic resonance signal. Is suitable. Regarding the change of the operation state of (4) above, either the form shown in FIG. 7 or the form shown in FIG. The purpose of non-transmission of the magnetic resonance signal may be to avoid interference when generating a high-frequency magnetic field from the coil unit 6a (when transmitting a 90 degree pulse or when transmitting a 180 degree pulse). For this purpose, the form shown in FIG. 7 can be used if the period for generating the high-frequency magnetic field is constant, but the form shown in FIG. 8 is used if the period for generating the high-frequency magnetic field changes. Should. Furthermore, during a period when a series of operations for imaging is not performed, the LOG amplifier 39, the digital conversion unit 40, the modulation processing unit 42, and the driver 43 are set in an operation state in which the magnetic resonance signal is not transmitted. It is conceivable to suppress battery consumption due to operation.

  As described above, according to the present embodiment, the operation state of the coil unit 6b can be controlled from the main unit, but the data signal for the control is transmitted by being superimposed on the clock signal. There is no need to secure a wireless channel. As a result, the number of radio channels for transmitting information between the coil unit 6b and the main unit can be reduced, thereby reducing the circuit scale for transmitting and receiving radio signals.

  Incidentally, a known PLL can be used for the clock recovery unit 33. The PLL compares the phase of the input clock signal and the output clock signal, and adjusts the frequency of the output clock signal so that the phase difference between the two clock signals is small, so that the output clock signal phase-synchronized with the input clock signal is obtained. Is to be generated. However, the clock signal here represents a signal in which rising and falling of the signal occur periodically, such as CW (Continuous Wave) and rectangular wave.

  As the PLL, for example, one disclosed in Patent Document 2 is known. In this PLL, a phase comparator that outputs a phase difference signal limited to the appearance timing of the rising edge (positive edge) of the signal, and a phase difference signal limited to the appearance timing of the falling edge (negative edge) of the signal. And a phase comparator for output, and a VCO control voltage is obtained by passing a signal obtained by adding the phase difference signals output from each of the two phase comparators through a low-pass filter (LPF).

  However, the input signal to the clock recovery unit 33 of this embodiment is a modulated signal obtained by modulating the first clock signal with a data signal using OOK, ASK, or the like. In this modulated signal, since the amplitude of the first clock signal is partially reduced, it is difficult to detect some edges in the first clock signal. For this reason, when a PLL as disclosed in Patent Document 2 is applied to the clock regeneration unit 33, the phase of the second clock signal is erroneously detected as if it is greatly delayed, and the second The phase noise of the clock signal may increase.

  Therefore, it is desirable to employ any one of the configurations of the following embodiments as the clock recovery unit 33.

(First embodiment)
FIG. 9 is a block diagram of the clock recovery unit 33 in the first embodiment. In FIG. 9, the same parts as those in FIG.

  The phase comparator 33a in the clock recovery unit 33 of the first embodiment includes a positive edge phase comparator (POS phase comparator) 71, a negative edge phase comparator (NEG phase comparator) 72, and a phase difference synthesizer 73. .

  The modulation signal output from the detector 32 and the second clock signal output from the VCO 33c are input to the positive edge phase comparator 71 and the negative edge phase comparator 72, respectively.

  The positive edge phase comparator 71 observes the positive edges of the modulation signal and the second clock signal and outputs a positive phase difference signal corresponding to the phase difference. Specifically, when the positive edge phase comparator 71 detects the positive edge of the second clock signal before the positive edge of the modulation signal, the positive edge phase comparator 71 detects the positive of the modulation signal from the positive edge of the second clock signal. The positive phase difference signal is set to the first level during the period up to the edge. When the positive edge phase comparator 71 detects the positive edge of the modulation signal before the positive edge of the second clock signal, the positive edge phase comparator 71 is in a period from the positive edge of the modulation signal to the positive edge of the second clock signal. The positive phase difference signal is set to the second level. In other periods, the positive edge phase comparator 71 sets the positive phase to the third level.

  The negative edge phase comparator 72 observes the negative edges of the modulated signal and the second clock signal, and outputs a negative phase difference signal corresponding to the phase difference. Specifically, when the negative edge phase comparator 72 detects the negative edge of the second clock signal before the negative edge of the modulation signal, the negative edge phase comparator 72 detects the negative of the modulation signal from the negative edge of the second clock signal. The negative phase difference signal is set to the first level during the period up to the edge. When the negative edge phase comparator 72 detects the negative edge of the modulation signal before the negative edge of the second clock signal, the negative edge phase comparator 72 is in a period from the negative edge of the modulation signal to the negative edge of the second clock signal. The negative phase difference signal is set to the second level. In other periods, the negative edge phase comparator 72 sets the negative phase to the third level.

  Thus, the positive phase difference signal and the negative phase difference signal indicate that the phase of the second clock signal is ahead of the modulation signal when it is at the first level, and the second phase when it is at the second level. This indicates that the phase of the clock signal is delayed from that of the modulation signal, and that the phase difference cannot be detected when it is at the third level. These first to third levels are set to voltage values such as + X [V], −X [V], and 0 [V] represented by a certain constant value X, for example. Or it is good also as -X [V], + X [V], and 0 [V] with an opposite value. Moreover, it is good also as a value more than 0 like + X [V], 0 [V], + X / 2 [V]. Alternatively, 2-bit values such as 10, 01 and 00 may be taken using logical values. In the following, the first to third levels are assumed to be + X [V], -X [V], and 0 [V].

  The phase difference synthesizer 73 sets the clock phase difference signal to the third level when both the positive phase difference signal and the negative phase difference signal are at the third level, and determines which of the positive phase difference signal and the negative phase difference signal. When only one of them is the third level, the clock phase difference signal is set to the sum of the levels of the positive phase difference signal and the negative phase difference signal. That is, when the third level is set to 0 [V], the phase difference synthesizer 73 obtains an exclusive OR of the positive phase difference signal and the negative phase difference signal, and outputs the result as a clock phase difference signal. To do. The clock phase difference signal output from the phase difference synthesizer 73 is given to the loop filter 33b.

  Next, the operation of the clock recovery unit 33 in the first embodiment as described above will be described.

  FIG. 10 is a timing chart in an example of the operation of the phase comparator 33a in the first embodiment.

  When only the component of the first clock signal appears in the modulation signal (hereinafter referred to as “no defect”), the timing at which the first level or the second level appears in the positive edge phase difference signal and the negative phase difference signal is As shown in FIG. 10, it is shifted by about half of the period of the second clock signal. That is, in a situation where the phase of the modulation signal and the second clock signal are in some degree, the first level or the second level does not appear simultaneously in the positive edge phase difference signal and the negative phase difference signal. On the other hand, if the first clock signal component is missing and an edge that should be present in the first clock signal cannot be detected, the first level or the second level as in periods 701 to 704 in FIG. It can happen that the level occurs over a period of one or more periods of the second clock signal. Then, as in a period 705 in which the period 701 and the period 703 overlap, a period 706 in which the period 702 and the period 704 overlap, the positive edge phase difference signal and the negative phase difference signal have the first level or the second level at the same time. appear. Therefore, when the first level or the second level appears simultaneously in the positive edge phase difference signal and the negative phase difference signal, the positive edge phase difference signal and the negative phase difference are caused by the lack of the first clock signal component. It can be said that the signal is likely to be wrong. Thus, in the periods 705 and 706 in which the first level or the second level appears simultaneously in the positive edge phase difference signal and the negative phase difference signal, the exclusive OR of the positive edge phase difference signal and the negative phase difference signal is the first. In other periods, the exclusive OR of the positive edge phase difference signal and the negative phase difference signal is the sum of the levels of the positive edge phase difference signal and the negative phase difference signal. Then, for example, a clock phase difference signal having such a level change as shown in FIG. 10 is generated.

  The clock phase difference signal generated by the phase comparator 33a in this way is input to the loop filter 33b and band-limited, and is then supplied to the VCO 33c as a control voltage.

  The VCO 33c reduces the frequency of the second clock signal when the clock phase difference signal is at the first level. When the clock phase difference signal is at the first level, the phase of the second clock signal is more advanced than that of the modulation signal. Therefore, this phase difference reduces the frequency of the second clock signal. Will be reduced. The VCO 33c increases the frequency of the second clock signal when the clock phase difference signal is at the second level. When the clock phase difference signal is at the second level, the phase of the modulation signal is more advanced than that of the second clock signal. This phase difference increases the frequency of the second clock signal. Will be reduced. The VCO 33c does not change the frequency of the second clock signal when the clock phase difference signal is at the third level. Thus, by repeating the adjustment of the frequency of the second clock signal, the second clock signal is phase-synchronized with the component of the first clock signal included in the modulation signal.

  In the conventional PLL disclosed in the cited document 2, the clock phase difference signal is also at the first level in the periods 705 and 706, and the frequency of the second clock signal is excessively changed accordingly. On the other hand, the clock recovery unit 33 in the first embodiment ignores the phase shift detected by the positive edge phase comparator 71 and the negative edge phase comparator 72 in the periods 705 and 706, and the second. Since the frequency of the clock signal is adjusted, the phase noise of the second clock signal is reduced as compared with the case where the conventional PLL is used.

(First modification of the first embodiment)
FIG. 11 is a block diagram showing a configuration of the clock regeneration unit 33 in the first modification of the first embodiment. In FIG. 11, the same parts as those in FIGS. 3 and 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33a in the clock recovery unit 33 of this modification includes a positive edge phase comparator 71, a negative edge phase comparator 72, a phase difference synthesizer 73, and a stop 74.

  The stop unit 74 receives the positive phase difference signal output from the positive edge phase comparator 71 and the signal output from the phase difference synthesizer 73 as a stop control signal. The output signal of the stop device 74 is given to the loop filter 33b as a clock phase difference signal. The stop device 74 outputs the positive phase difference signal as it is during the period when the stop control signal is at the first level or the second level, and stops the output of the positive phase difference signal during other periods. A phase difference signal is generated. That is, the stop 74 has the level of the positive phase difference signal during the period in which the stop control signal is at the first level or the second level, and has the third level in other periods. A clock phase difference signal is generated as a signal as shown.

  In this way, the error in the negative phase difference signal occurring in the periods 707 and 708 due to the lack of the component of the first clock signal is not reflected in the clock phase difference signal, so that the second clock signal can be obtained. Phase noise is further reduced. However, the number of phase difference detections reflected in the clock phase difference signal is halved to the basic configuration of the first embodiment.

(Second modification of the first embodiment)
FIG. 13 is a block diagram showing a configuration of the clock regeneration unit 33 in the second modification of the first embodiment. In FIG. 13, the same parts as those in FIGS. 3, 9, and 11 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33a in the clock recovery unit 33 of this modification includes a positive edge phase comparator 71, a negative edge phase comparator 72, a phase difference synthesizer 73, and a stop 74.

  The stop unit 74 receives the negative phase difference signal output from the negative edge phase comparator 72 and the signal output from the phase difference synthesizer 73 as stop control signals. The output signal of the stop device 74 is given to the loop filter 33b as a clock phase difference signal. The stop device 74 outputs the negative phase difference signal as it is during the period when the stop control signal is at the first level or the second level, and stops the output of the negative phase difference signal during other periods. A phase difference signal is generated. That is, the stop device 74 has the level of the negative phase difference signal during the period in which the stop control signal is the first level or the second level, and has the third level in the other periods. A clock phase difference signal is generated as a signal as shown.

  In this way, the error in the positive phase difference signal occurring in the periods 709 and 710 due to the lack of the component of the first clock signal is not reflected in the clock phase difference signal, so that the second clock signal can be obtained. Phase noise is further reduced. However, the number of phase difference detections reflected in the clock phase difference signal is halved compared to the basic configuration of the first embodiment.

  If the clock recovery unit 33 of this embodiment is employed in place of a conventional PLL having a phase comparator that detects only a positive edge or negative edge phase difference, the configuration shown in FIG. 11 or FIG. 13 is used. If applied, the same performance as in the prior art can be obtained in a period in which the component of the first clock signal is not missing. Further, if the clock recovery unit 33 of this embodiment is adopted instead of the conventional PLL disclosed in Patent Document 2, if the configuration shown in FIG. 9 is applied, the component of the first clock signal is used. The performance similar to the conventional one can be obtained during a period without any chipping.

(Second Embodiment)
FIG. 15 is a block diagram of the clock recovery unit 33 in the second embodiment. In FIG. 15, the same parts as those in FIGS. 3 and 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33a in the clock recovery unit 33 of the second embodiment includes a positive edge phase comparator 71, a negative edge phase comparator 72, and a phase difference synthesizer 75. That is, in the second embodiment, a phase difference synthesizer 75 is provided instead of the phase difference synthesizer 73 in the first embodiment.

  The phase difference synthesizer 75 outputs the clock phase difference signal in the output stop period from when the positive phase difference signal and the negative phase difference signal both become levels other than the third level until the specified time elapses. The clock phase difference signal is the sum of the levels of the positive phase difference signal and the negative phase difference signal during the other periods. That is, when the third level is set to 0 [V], the phase difference synthesizer 75 obtains an OR composite value and an AND composite value of the positive phase difference signal and the negative phase difference signal, and basically OR. The combined value is output as a clock phase difference signal, but the clock phase difference signal is set to the third level only during a period from when the AND combined value reaches the first or second level until a specified time elapses. . The clock phase difference signal output from the phase difference synthesizer 75 is given to the loop filter 33b.

  Next, the operation of the clock recovery unit 33 in the second embodiment as described above will be described.

  FIG. 16 is a timing chart in an example of the operation of the phase comparator 33a in the second embodiment. Note that the example of FIG. 16 relates to the same situation as the example shown in FIG. 10, and the same reference numerals are given to the same period, and detailed description thereof is omitted.

  The first level or the second level appears simultaneously in the positive edge phase difference signal and the negative phase difference signal, such as the period 705 in which the period 701 and the period 703 overlap, the period 706 in which the period 702 and the period 704 overlap, and the like. During the period, the AND composite value becomes the first or second level. In this way, the output stop periods 713 and 714 from the timings 711 and 712 when the AND composite value becomes the first or second level to the output stop periods 713 and 714 are set to the third level, and during other periods. For example, a clock phase difference signal as shown in FIG.

  The measurement of the specified time for obtaining the output stop period in the phase difference synthesizer 75 can be performed, for example, using a counter driven using the second clock signal or the modulation signal. However, since the second clock signal is a signal generated by the VCO 33c and is less likely to be chipped, the specified time is measured more accurately when the second clock signal is used than when the modulation signal is used. be able to. However, even if the measurement accuracy of the specified time is slightly worse, the effect that the phase noise of the second clock signal can be reduced as compared with the case of using the conventional PLL is obtained. Therefore, the specified time is measured using the modulation signal. May be. Further, the elapsed time is measured by both the counter driven using the second clock signal and the counter driven using the modulation signal, and when either counter reaches the specified time first, the output stop period It may be determined that has ended. In this way, if there is no chip in the clock, it is possible to measure the period more accurately by measuring with both the second clock signal and the modulation signal, and there is a chip in the modulation signal. Even if only one counter is used, measurement can be performed with the same accuracy as when only one counter is used.

  Note that which edge of the modulation signal and the second clock signal occurs first in the portion where the first clock component is missing depends on the method of multiplexing the data signals. For example, when multiplexing as shown in FIGS. 4 to 6 is performed, since the signal amplitude is changed with the period from the rising edge to the falling edge as one cycle, the first clock signal component is missing. In the period, the positive edge is detected first.

(First Modification of Second Embodiment)
FIG. 17 is a block diagram showing a configuration of the clock regeneration unit 33 in the first modification of the second embodiment. In FIG. 17, the same parts as those in FIGS. 3 and 15 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33 a in the clock recovery unit 33 of this modification includes a positive edge phase comparator 71, a negative edge phase comparator 72, a phase difference synthesizer 76, and a stop device 77.

  The phase difference synthesizer 76 generates a stop control signal based on the positive phase difference signal and the negative phase difference signal. Specifically, the phase difference synthesizer 76 obtains an AND composite value of the positive phase difference signal and the negative phase difference signal, and a specified time elapses from the time when the AND composite value becomes the first or second level. The stop control signal is generated as a signal representing the stop only during the period up to.

  The stop unit 77 receives the positive phase difference signal output from the positive edge phase comparator 71 and the stop control signal output from the phase difference synthesizer 76. The output signal of the stop device 77 is given to the loop filter 33b as a clock phase difference signal. The stop unit 77 outputs the positive phase difference signal as it is during the period when the stop control signal indicates stop, and generates the clock phase difference signal by stopping the output of the positive phase difference signal during the other period. In other words, the stop device 77 has a third level during the period when the stop control signal indicates stop, and the clock phase difference as a signal as shown in FIG. 18 having the level of the positive phase difference signal during the other periods. Generate a signal.

  In this way, an error in the negative phase difference signal that occurs in the period 715 due to the lack of the component of the first clock signal is not reflected in the clock phase difference signal, so that the phase noise of the second clock signal is reduced. Further reduced. However, the number of phase difference detections reflected in the clock phase difference signal is halved to the basic configuration of the second embodiment.

(Second modification of the second embodiment)
FIG. 19 is a block diagram showing a configuration of the clock regeneration unit 33 in the second modification of the second embodiment. 19, the same parts as those in FIGS. 3, 15, and 17 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33 a in the clock recovery unit 33 of this modification includes a positive edge phase comparator 71, a negative edge phase comparator 72, a phase difference synthesizer 76, and a stop device 77.

  The stop unit 77 receives the negative phase difference signal output from the negative edge phase comparator 72 and the stop control signal output from the phase difference synthesizer 76. The output signal of the stop device 77 is given to the loop filter 33b as a clock phase difference signal. The stop unit 77 outputs the negative phase difference signal as it is during the period when the stop control signal indicates the stop, and generates the clock phase difference signal by stopping the output of the negative phase difference signal during the other period. That is, the stop device 77 has the third level in the period in which the stop control signal indicates the stop, and the clock phase difference as a signal as shown in FIG. 20 having the level of the negative phase difference signal in the other period. Generate a signal.

  In this way, the error in the positive phase difference signal occurring in the periods 709 and 710 due to the lack of the component of the first clock signal is not reflected in the clock phase difference signal, so that the second clock signal can be obtained. Phase noise is further reduced. However, the number of phase difference detections reflected in the clock phase difference signal is halved to the basic configuration of the second embodiment.

  If the clock recovery unit 33 of the present embodiment is employed in place of the conventional PLL having a phase comparator that detects only the positive edge or negative edge phase difference, the configuration shown in FIG. If applied, the same performance as in the prior art can be obtained in a period in which the component of the first clock signal is not missing. If the clock recovery unit 33 of the present embodiment is adopted instead of the conventional PLL disclosed in Patent Document 2, the configuration shown in FIG. 15 is applied to the first clock signal component. The performance similar to the conventional one can be obtained during a period without any chipping.

  Incidentally, it is desirable that the output stop period in the second embodiment be the same as the length of the signal sequence of the data signal. This is because if the period is shorter than the signal sequence, there is a high possibility that the first clock component will be missing after restarting from the output stop period, and if the period is longer than the signal sequence. This is because there is a possibility that the time until an effective phase comparison can be reduced and the time until the PLL is locked may be lengthened. Here, the length of the signal sequence represents a period in which the data signal is multiplexed with the first clock signal as represented by the periods 302, 402, and 502 in FIGS. However, when the signal series is known in advance, it may be a period in which the component of the first clock signal is actually missing. For example, in the examples of FIGS. 3 to 5, the periods 303, 403, and 503 are used. By doing so, the length of the output stop period can be minimized. However, when only the length of the signal sequence is known and the value of the signal sequence is not known, or when the period during which the component of the first clock signal is actually missing in each of the plurality of data signals changes It is desirable to use periods 302, 402, and 502. By doing so, it is possible to avoid a state in which the clock is missing after restarting from the stop period regardless of the value of the signal sequence. On the other hand, if there is a possibility that a lack of clock in a shorter period than the signal sequence length may occur due to, for example, noise other than signal sequence multiplexing, the stop period may be shorter than the signal sequence length. good. By doing so, even when the operation is stopped due to the influence of noise or the like, it is possible to return from the stop period in a shorter time and to effectively perform the phase comparison.

  21 to 23 are timing diagrams in an example of the operation of the phase comparator 33a when the length of the output stop period is set to be the same as the length of the signal sequence of the data signal in each of the configurations of FIGS. In both cases, the clock phase difference signal is set to the third level in the output stop period 716.

(Third embodiment)
FIG. 24 is a block diagram of the clock recovery unit 33 in the third embodiment. 24, the same parts as those in FIGS. 3 and 9 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The phase comparator 33a in the clock recovery unit 33 of the third embodiment includes a positive edge phase comparator 78, a negative edge phase comparator 79, a phase difference synthesizer 80, and a reset unit 81.

  The positive edge phase comparator 78 and the negative edge phase comparator 79 output a positive phase difference signal and a negative phase difference signal basically in the same manner as the positive edge phase comparator 71 and the negative edge phase comparator 72. However, the positive edge phase comparator 78 and the negative edge phase comparator 79 have a function of resetting the operation state to the initial state under the control of the reset device 81.

  The phase difference synthesizer 80 sets the clock phase difference signal to the first or second level when either the positive phase difference signal or the negative phase difference signal is at the first or second level. The clock phase difference signal output from the phase difference synthesizer 80 is provided to the loop filter 33b. In addition, the phase difference synthesizer 80 outputs a reset signal to the reset device 81 in response to both the positive phase difference signal and the negative phase difference signal having a level other than the third level. That is, when the third level is set to 0 [V], the phase difference synthesizer 80 obtains an OR composite value of the positive phase difference signal and the negative phase difference signal and outputs this as a clock phase difference signal. Further, the phase difference synthesizer 80 obtains an AND composite value of the positive phase difference signal and the negative phase difference signal, and outputs this as a reset signal.

  The reset device 81 resets the positive edge phase comparator 78 and the negative edge phase comparator 79 to the initial state in response to the reset signal from the phase difference synthesizer 80. The initial state of the positive edge phase comparator 78 and the negative edge phase comparator 79 is to reset the detection result of any edge so far, and the previous edge is detected from either the modulation signal or the second clock signal. It represents a state of waiting for The positive phase difference signal and the negative phase difference signal are also returned to the third level by the reset.

  Next, the operation of the clock recovery unit 33 in the third embodiment as described above will be described.

  FIG. 25 is a timing chart in an example of the operation of the phase comparator 33a in the third embodiment. Note that the example of FIG. 25 relates to the same situation as the example shown in FIG. 10, and the same reference numerals are given to the same period, and detailed description thereof is omitted.

  Since each of the positive phase difference signal and the negative phase difference signal becomes a level other than the third level at each of the time points 717, 718, and 719, the AND composite value becomes the first level or the second level. Accordingly, a reset signal is given to the reset device 81. Then, the reset device 81 resets the positive edge phase comparator 78 and the negative edge phase comparator 79 to the initial state.

  Thus, both the positive phase difference signal and the negative phase difference signal are returned to the third level, and the state where both are at a level other than the third level is eliminated. As a result, the adjustment of the frequency of the second clock based on the phase difference erroneously detected due to the lack of the component of the first clock signal is prevented and the second clock is prevented. The phase noise of the signal is reduced. In particular, in the third embodiment, resetting is performed each time a level other than the third level appears simultaneously in the positive phase difference signal and the negative phase difference signal, so that the lack of the first clock signal component occurs sporadically. When it occurs, the phase difference that is erroneously output can be reduced particularly effectively.

  Note that the positive phase difference signal and the negative phase difference signal may be input to the resetter 81, and the AND combined value may be calculated in the resetter 81.

(First Modification of Third Embodiment)
FIG. 26 is a block diagram showing a configuration of the clock regeneration unit 33 in the first modification of the third embodiment. In FIG. 26, the same parts as those in FIGS. 3 and 24 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the phase comparator 33a in the clock recovery unit 33 of the present modification, the positive phase difference signal is directly supplied to the loop filter 33b as the clock phase difference signal.

  FIG. 27 is a timing chart in an example of the operation of the phase comparator 33a in the first modification of the third embodiment.

(Second modification of the third embodiment)
FIG. 28 is a block diagram showing the configuration of the clock regeneration unit 33 in the second modification of the third embodiment. In FIG. 28, the same parts as those in FIGS. 3 and 24 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the phase comparator 33a in the clock recovery unit 33 of the present modification, the negative phase difference signal is directly supplied to the loop filter 33b as the clock phase difference signal.

  FIG. 29 is a timing chart in an example of the operation of the phase comparator 33a in the second modification of the third embodiment.

  This embodiment can be variously modified as follows.

(Third Modification of Third Embodiment)
FIG. 30 is a block diagram of a third modification of the third embodiment of the clock recovery unit 33. 30, the same parts as those in FIGS. 3 and 24 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The clock recovery unit 33 of this modification includes a phase comparator 33a, a loop filter 33b, a VCO 33c, and a positive edge phase comparator (POS phase comparator) 33d. The phase comparator 33a includes a positive edge phase comparator 78, a negative edge phase comparator 79, a phase difference synthesizer 80, and a reset device 81.

  The modulation signal is supplied to the positive edge phase comparator 33d in addition to the phase comparator 33a. The positive edge phase comparator 33 d generates a positive phase difference signal in the same manner as the positive edge phase comparator 78. The positive phase difference signal generated by the positive edge phase comparator 33d is supplied to the loop filter 33b as a clock phase difference signal. Further, the positive edge phase comparator 33 d has a function of resetting the operation state to the initial state under the control of the reset device 81.

  Thus, the second clock signal similar to the second modification of the third embodiment is also generated in this modification. According to this modification, a known PLL circuit is configured by the loop filter 33b, the VCO 33c, and the positive edge phase comparator 33d. Therefore, the phase comparator 33a can be easily added to such an existing PLL circuit. It is possible to realize.

(Fourth modification of the third embodiment)
FIG. 31 is a block diagram of a fourth modification of the third embodiment of the clock recovery unit 33. In FIG. 31, the same parts as those in FIGS. 3 and 24 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The clock recovery unit 33 of this modification includes a phase comparator 33a, a loop filter 33b, a VCO 33c, and a negative edge phase comparator (NEG phase comparator) 33e. The phase comparator 33a includes a positive edge phase comparator 78, a negative edge phase comparator 79, a phase difference synthesizer 80, and a reset device 81.

  The modulation signal is supplied to the negative edge phase comparator 33e in addition to the phase comparator 33a. The negative edge phase comparator 33e generates a negative phase difference signal in the same manner as the negative edge phase comparator 79. The negative phase difference signal generated by the negative edge phase comparator 33e is given to the loop filter 33b as a clock phase difference signal. Further, the negative edge phase comparator 33e has a function of resetting the operation state to the initial state under the control of the reset device 81.

  Thus, also in this modification, a second clock signal similar to that in the third modification of the third embodiment is generated. According to this modification, since a known PLL circuit is configured by the loop filter 33b, the VCO 33c, and the negative edge phase comparator 33e, the phase comparator 33a can be easily added to such an existing PLL circuit. It is possible to realize.

  FIG. 32 is a diagram illustrating a concept realized by connecting the phase comparator 33a to the existing PLL 91 in the third and fourth modifications of the third embodiment.

  The coil unit 6b may also be used for RF transmission. In this case, the operation state of receiving the magnetic resonance signal and the operation state of performing the RF transmission can be controlled from the main control unit 24 by the data signal.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  DESCRIPTION OF SYMBOLS 1 ... Static magnetic field magnet, 2 ... Gradient magnetic field coil, 3 ... Gradient magnetic field power supply, 4 ... Bed, 5 ... Bed control part, 6a, 6b ... Coil unit, 7 ... Transmission part, 8 ... Clock signal generation part, 9 ... High frequency Pulse / gradient magnetic field control unit, 10 ... driver, 11 ... wireless unit, 15 ... system reconstruction front end, 20 ... reconstruction system, 21 ... storage unit, 22 ... display unit, 23 ... input unit, 24 ... main control unit 25 ... Data signal generation unit, 31 ... Clock receiving antenna, 32 ... Detection unit, 32a ... Envelope detection unit, 32b ... Filter, 33 ... Clock recovery unit, 33a ... Phase comparator, 33b ... Loop filter, 33c ... Voltage Control oscillator (VCO), 33d ... positive edge phase comparator, 33e ... negative edge phase comparator, 35 ... carrier wave generation unit, 36 ... coil, 37 ... coupling circuit, DESCRIPTION OF SYMBOLS 8 ... Selector, 39 ... LOG amplifier, 40 ... Digital conversion part, 41 ... Start signal addition part, 42 ... Modulation process part, 43 ... Driver, 44 ... Resonance signal transmission antenna, 45 ... Data detection part, 45a ... Sampling part, 45b ... detection unit 46 ... control unit 51 ... modulation unit 52 ... carrier signal generation unit 53 ... amplitude modulation unit 54 ... driver 55 ... clock transmission antenna 56 ... modulation / demodulation signal generation unit 62 ... antenna 63 ... Demodulation processing unit, 71 ... Positive edge phase comparator, 72 ... Negative edge phase comparator, 72 ... Negative edge phase comparator, 73 ... Phase difference synthesizer, 74 ... Stopper, 75 ... Phase difference synthesizer, 76 ... Phase difference synthesizer 77. Stopper 78. Positive edge phase comparator 79. Negative edge phase comparator 80. Phase difference synthesizer 81. Sorter, 100 ... Magnetic Resonance Imaging (MRI apparatus), 200 ... subject.

Claims (5)

A magnetic resonance diagnostic imaging apparatus comprising a control unit and a coil unit separate from the control unit,
The control unit is
A clock signal generator for generating a first clock signal;
A control signal generation unit that generates a control signal for instructing an operation state of the coil unit;
A modulation unit that obtains a modulation signal obtained by multiplexing the control signal with the first clock signal by modulating the first clock signal with the control signal;
A clock transmission signal generator for generating a clock transmission signal including the modulation signal;
A clock transmission antenna that radiates the clock transmission signal to space;
The coil unit is
A clock receiving antenna that converts the clock transmission signal propagated through the space into an electrical signal state;
A detector for detecting the modulated signal from the clock transmission signal converted into an electric signal state by the clock receiving antenna;
A clock recovery unit that generates a second clock signal synchronized with the first clock signal from the modulation signal detected by the detection unit;
A coil for detecting a magnetic resonance signal generated in the subject;
A digital converter that digitally converts the magnetic resonance signal detected by the coil in synchronization with the second clock signal;
A data detection unit for detecting the control signal from the modulation signal detected by the detection unit using the second clock signal;
A magnetic resonance diagnostic imaging apparatus comprising: a control unit that controls an operation state of the coil unit so as to be in an operation state instructed by the control signal detected by the data detection unit. The coil unit is
A plurality of the coils;
Furthermore, a coil selection unit that activates a part of the plurality of coils for detection of the magnetic resonance signal,
The control signal generation unit generates the control signal as indicating a coil to be activated among the plurality of coils,
2. The magnetic resonance imaging apparatus according to claim 1, wherein the control unit controls the operation state by controlling the coil selection unit so as to validate a coil indicated by the control signal. . The coil unit includes, as the operation state, a transmission mode in which a high-frequency pulse for exciting a spin in the subject is radiated from the coil, and a reception mode in which the magnetic resonance signal is detected by the coil,
The control signal generation unit generates the control signal as indicating either the transmission mode or the reception mode,
The magnetic resonance imaging apparatus according to claim 1, wherein the control unit switches an operation state so as to set a mode instructed by the control signal. The coil unit is
A plurality of the coils;
And a switching unit that selectively forms a coupling mode for coupling between at least two of the plurality of coils and a decoupling mode for decoupling,
The control signal generation unit generates the control signal as indicating either the coupling mode or the decoupling mode,
Wherein, the magnetic resonance imaging apparatus according to claim 1, wherein the controller controls the switching unit so designated mode is formed by the control signal.   The magnetic resonance imaging apparatus according to claim 4, wherein the switching unit switches the coupling mode and the decoupling mode using a PIN diode.

Images