JP5748126B2 - Synchronous control system - Google Patents

Description

  The present invention relates to a synchronous control system for controlling a drive device such as a servo or an inverter in synchronization with a control cycle of a controller device.

This type of synchronous control system includes a controller device that operates according to a constant control cycle, and a plurality of drive devices that periodically drive a load such as a motor by a torque command, a current command, a position command, and the like. It is known that a device controls a load in synchronization with a synchronization signal output from a controller device.
In this synchronous control system, as described in Patent Document 1, for example, the synchronization signal output from the controller device and the deviation amount of the start counter value of the drive cycle of the drive device are calculated, and the start counter value is slightly set. The amount of deviation is decreased by increasing / decreasing, and finally, the synchronization timing from the controller device is synchronized with the start timing of the start counter value.

Here, FIG. 4 is a block diagram showing a synchronous control system substantially the same as the prior art described in Patent Document 1. In FIG.
In the figure, 1 is a controller device, 3A to 3C are drive devices such as servos and inverters controlled synchronously by the controller device 1, 4A to 4C are motors as loads driven by the drive devices 3A to 3C, respectively. This is a signal transmission path for transmitting synchronization signals and drive data between the controller device 1 and the drive devices 3A to 3C.
Note that the configurations of the drive devices 3A to 3C are the same, and the number of drive devices is not limited to three, and may be any number.

Next, the operation of this prior art will be described together with the configurations of the controller device 1 and the drive device 3A.
The controller device 1 performs a cycle process 11 for determining a constant control cycle. The synchronization signal generation means 12 outputs a synchronization signal that serves as a reference for starting timing at which the drive devices 3A, 3B, and 3C start the periodic processing in accordance with the end / start of the periodic processing 11. This synchronization signal is output, for example, every control cycle by the application program of the controller device 1, and the drive devices 3A, 3B, 3C drive the motors 4A to 4C in synchronization with the synchronization signal.

  The drive device 3 </ b> A includes a synchronization signal acquisition unit 31 that acquires a synchronization signal input via the signal transmission path 2, a period timing correction unit 33 that corrects the start timing of the period process, and an output from the period timing correction unit 33. And a periodic start timing generating means 34 for generating a periodic start timing based on the start timing, and a periodic process 35 started in accordance with the start timing.

Next, the synchronization process of the drive device 3A will be described based on the timing charts of FIGS.
First, before starting the synchronization processing, the relationship between the cycle processing timer value indicating the drive cycle by the drive device 3A and the cycle start timing with respect to the synchronization signal output from the synchronization signal generating means 12 of the controller device 1 is shown in FIG. 5 (a) [No periodic processing timer correction]. As can be seen from the figure, the cycle activation timing occurs when the cycle processing timer value is zero. In addition, the synchronization signal and the period activation timing are generally different from each other, and the period of the synchronization signal is not different from the period of the period activation timing (the timing at which the period processing timer times up). It remains unchanged.

Next, an example of the synchronization processing will be described with reference to FIG. 5B [periodic processing timer correction operation 1] and FIG. 5C [periodic processing timer correction operation 2].
Periodic timing correction means 4 33 latches the periodic processing timer value when detecting the synchronizing signal through the synchronizing signal obtaining unit 31, latched timer value T ₁ and determines the drive cycle of the drive device 3A of the periodic processing timer The difference from the time-up value T _up is obtained. At this time, as shown in FIG. 5B, when the period activation timing is ahead of the synchronization signal, the period is lengthened by temporarily increasing the time-up value T _up, and the period shown in FIG. as shown at time t _b, periodic processing timer value to the synchronization signal, cyclic timing so locking can be established approaches.

On the other hand, when the period activation timing is delayed from the synchronization signal as shown in FIG. 5C, the period is shortened by temporarily reducing the time-up value _Tup, and the period shown in FIG. as shown at time t _c, periodic processing timer value to the synchronization signal, cyclic timing so locking can be established approaches.
Here, the periodic activation timing generation means 34 in FIG. 4 generates a periodic activation timing simultaneously with the time-up of the periodic processing timer value, and activates the periodic processing 35 to drive the motor 4A.

In this case, for example, the synchronization process shown in FIG. 5B or 5C is performed on the first synchronization signal, and the period is started by returning the shifted time-up value T _up to the original position at the next synchronization signal. The timing is restored. In this way, it is possible to perform synchronization correction at a rate of once every two synchronization signals.

  Patent Document 2 discloses a system that transmits and receives a position command, a speed command, a torque command, and the like by serial communication between a host control device and a plurality of motor drive devices.

Japanese Patent Laying-Open No. 2005-094933 (paragraphs [0013] to [0023], FIG. 1 and the like) Japanese Patent Laying-Open No. 2003-189654 (paragraphs [0002] to [0005], FIG. 9 and the like)

4 and 5, the control cycle T _c of the controller device 1 and the drive cycle T _d of each drive device are assumed to be equal (that is, T _c = T _d ) for each control cycle T _c. The cycle start timing of the drive device is adjusted based on the synchronization signal output from the controller device 1.
However, in general, a drive device such as a servo or an inverter often repeats an operation with a drive cycle T _d shorter than the control cycle T _c of the controller device 1.

Now, when the control cycle T _c of the controller device 1 is 1600 [μs] and the drive cycle T _d of each of the drive devices 3A to 3C is 80 [μs], processing before synchronization and after synchronization (after synchronization acquisition) The relationship with the time axis is shown in FIG.
In FIG. 6A before synchronization, since the controller device 1 and the drive devices 3A to 3C are not synchronized, the cycle activation timing of the drive devices 3A to 3C does not match the synchronization signal. The cycle start timing is also shifted between the drive devices 3A to 3C.

By synchronizing from this state, as shown in FIG. 6B, the synchronization signal coincides with the cycle activation timing of the drive devices 3A to 3C, and all the drive devices are synchronized with the control cycle _Tc of the controller device 1. The driving process of 3A to 3C is started.
Here, in FIG. 6B, as described above, T _c = 1600 [μs], T _d = 80 [μs], and T _c is an integral multiple of T _d (T _c = n × T _d , n is a positive integer). If synchronization is established with the drive devices 3A to 3C when the first synchronization signal is generated, synchronization is ensured when the next synchronization signal is generated.

However, when T _c is not an integral multiple of T _d (when T _c ≠ n × T _d ), for example, the processing cycle of the controller device 1 is 1500 [μs] (T _d = for the drive cycles of the drive devices 3A to 3C _). 80 [μs]), the result is as shown in FIG. 6C. Even if the synchronization signal is once synchronized with the drive devices 3A to 3C, the synchronization signal is generated when the next synchronization signal is generated. A deviation occurs between the drive timings of the drive devices 3A to 3C and the synchronization is lost.

Therefore, in the prior art shown in FIG. 4 and FIG. 5, in order to always maintain synchronization between the controller device 1 and the drive devices 3A to 3C, it is necessary that T _c = n × T _d . There was a problem that there was no freedom in system construction.
Therefore, the problem to be solved by the present invention is that synchronization can be ensured even when the control cycle T _c of the controller device is not an integral multiple of the drive cycle T _d of the drive device, and a highly flexible system can be constructed. It is to provide a synchronous control system.

In order to solve the above-described problem, the invention according to claim 1 includes a controller device that outputs a synchronization signal every fixed control cycle, and a drive device that drives a load according to a drive cycle shorter than the control cycle. ,
The drive device is
Period timing correction means for adjusting the activation timing so as to synchronize the activation timing of the drive period with the synchronization signal received from the controller device;
Means for periodically driving the load according to a driving cycle based on the start timing adjusted by the cycle timing correcting unit,
When the control cycle is not an integral multiple of the drive cycle,
The number of drive cycles included in the control cycle and fractional time are obtained, and the total time of increase when the drive cycle is increased by one or more without changing the number of drive cycles coincides with the fractional time. The total period of decrease when the drive period is calculated or the number of times of the drive period is increased to reduce one or more drive periods is the difference between the original drive period and the fractional time. Comprising a cycle calculating means for calculating the drive cycle so as to match
The drive cycle calculated by the cycle calculation means is given to the cycle timing correction means.

  The invention according to claim 2 includes a plurality of the drive devices, and synchronizes the start timings of all the drive devices with a synchronization signal output from the controller device.

  According to the present invention, even when the control cycle of the controller device is not an integral multiple of the drive cycle of the drive device, synchronization between the controller device and the drive device can be ensured, and the degree of freedom in system construction can be increased.

It is a block diagram which shows embodiment of this invention. It is a flowchart which shows the process of the period calculating means in embodiment of this invention. It is a timing diagram for demonstrating the effect of embodiment of this invention. It is a block diagram which shows a prior art. FIG. 5 is a timing chart for explaining a synchronization process of the drive device in FIG. 4. It is a figure which shows the relationship between the process before a synchronization in a prior art, and after a synchronization, and a time axis.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of this embodiment, and the same reference numerals are assigned to the same components as those in FIG. Below, it demonstrates centering on a different part from FIG.

That is, the drive device 30A in the synchronization control system of the present embodiment (the configuration of the other drive devices 30B and 30C is the same) includes the period calculation means 32 between the synchronization signal acquisition means 31 and the period timing correction means 33. Yes.
This period calculation means 32 is used for synchronization between the controller device 1 and the drive apparatus 30A based on the synchronization signal output from the synchronization signal acquisition means 31 and the period processing timer value of the period calculation means 32. A function of adjusting the drive cycle of the drive device 30 </ b> A is provided, and the output of the cycle calculation means 32 is sent to the cycle timing correction means 33.
The configuration other than the period calculation means 32 is the same as that shown in FIG.

Next, the operation of this embodiment will be described.
The flowchart of FIG. 2 shows the processing of the cycle calculation means 32 in accordance with the relationship between the control cycle T _c of the controller device 1 and the drive cycle T _d of the drive device 30A (the drive cycles of the other drive devices 30B and 30C are the same). Show.
Here, when the flow chart of FIG. 2, the control period T _c is assumed that not an integer multiple of the drive period T _d, the control period T _c is an integer multiple of the drive period T _d is described later Since the fractional time ΔT and the number of times M in steps S2 to S5 are zero, the processing is not substantially performed, and the operation is the same as that in which the period calculating means 32 in FIG. 1 is removed.

Now, in FIG. 2, the number N of drive cycles and the fractional time ΔT of the drive device that occur within one control cycle are obtained by Equations 1 and 2. (Steps S1 and S2 in FIG. 2)
[Formula 1]
N = int (T _c / T _d )
[Formula 2]
ΔT = mod (T _c / T _d )
The number of driving cycles N = int () in Equation 1 is an integer obtained by rounding down the remainder of the division in parentheses, and indicates the number of driving cycles _Td included in the control cycle _Tc . Also, the fractional time ΔT = mod () in Equation 2 is the remainder of the division in parentheses.
Therefore, the relationship of N × T _d + ΔT = T _c is established.

Next, it is determined whether or not the fraction time ΔT is smaller than ½ of the drive cycle T _d (step S3). If it is smaller than ½ (step S3 Yes), the number of times of T _d included in T _c is determined. Keep N unchanged and increase _Td by ΔT in total. For example, when the drive cycle T _d is set with the processing reference timer value t as a reference (step size), the increase is calculated by Equation 3 (step S4), and this M times are included in N times T _d . Is distributed at any number of times (step S5). For example, when M = 2 and N = 18, _Td of 2 times out of 18 _Td is increased so that the total time of the increase becomes ΔT.
[Formula 3]
M = ΔT / t

If the fractional time ΔT is ½ or more of the drive cycle T _d (No in step S3), N is incremented to increase the number of T _d included in T _c by one (step S6). _d is reduced by (T _d −ΔT) in total.
Similarly to the above, when the drive cycle T _d is set with the processing reference timer value t as the reference (step size), Equation 4 is calculated (step S7), and this M number is calculated as N + 1 T _d . It distributes in (step S5). For example, when M = 2 and N = 18, since N + 1 = 19, two _Td out of 19 _Td are decreased, and the total time of the decrease (T _d− ΔT).
[Formula 4]
M = (T _d −ΔT) / t

As a specific example, when T _c = 1500 [μs] and T _d = 80 [μs], calculation of the formulas 1 and 2 yields the following (steps S1 and S2).
N = int (1500/80) = 18 times
ΔT = mod (1500/80) = 60 [μs]

Since ΔT = 60 [μs] is ½ or more of _Td , N is incremented to 19 times (step S3 No, step S6). Further, when the processing reference timer value t = 10 [μs], the following expression is obtained by calculating Equation 4 (step S7).
M = (T _d −ΔT) / t = (80−60) / 10 = 2
Therefore, reducing the two _{T d} of 19 times _{T d,} may be the total time of the decrease in the _{(T d -ΔT) = 20 [} μs], for example, of 19 times _{T d} Of these, the _Td of 2 times may be decreased by 10 [μs] to 70 [μs], and the remaining 17 _Td may be left at 80 [μs].

FIG. 3A is a timing chart when the period alignment (period timing correction) according to the present embodiment is not performed, and FIG. 3B is a timing chart when the period alignment according to the present embodiment is performed. In these drawings, the drive cycle a: 80 [μs] of the drive device indicates that the drive cycle T _d = 80 [μs], and similarly the drive cycle b: 70 [μs] is the drive cycle T _d = 70 [μs]. ].

FIG. 3 corresponds to the case of T _c = 1500 [μs], T _d = 80 [μs], and t = 10 [μs] in the specific example described above, and this embodiment shown in FIG. According to the embodiment, by providing the drive cycle T _d = 80 [μs] 17 times and the drive cycle T _d = 70 [μs] twice in the control cycle T _c of the controller device 1, the synchronization signal and the drive device It is possible to synchronize with the periodic start timing of the same.
Therefore, even when the control cycle of the controller device 1 is not an integral multiple of the original drive cycle of the drive device, it is possible to perform synchronous control of the drive device.

  In the above embodiment, the number of drive devices is not necessarily plural, and the present invention can also be applied to a system including one controller device and one drive device.

1: Controller device 11: Periodic processing 12: Periodic signal generation means 2: Signal transmission path 30A, 30B, 30C: Drive device 31: Synchronization signal acquisition means 32: Period calculation means 33: Period timing correction means 34: Period start timing generation Means 35: Periodic processing 4A, 4B, 4C: Motor

Claims (2)

A controller device that outputs a synchronization signal every fixed control cycle; and a drive device that drives a load according to a drive cycle shorter than the control cycle;
The drive device is
Period timing correction means for adjusting the activation timing so as to synchronize the activation timing of the drive period with the synchronization signal received from the controller device;
Means for periodically driving the load according to a driving cycle based on the start timing adjusted by the cycle timing correcting unit,
When the control cycle is not an integral multiple of the drive cycle,
The number of drive cycles included in the control cycle and fractional time are obtained, and the total time of increase when the drive cycle is increased by one or more without changing the number of drive cycles coincides with the fractional time. The total period of decrease when the drive period is calculated or the number of times of the drive period is increased to reduce one or more drive periods is the difference between the original drive period and the fractional time. Comprising a cycle calculating means for calculating the drive cycle so as to match
A synchronous control system, characterized in that the driving cycle calculated by the cycle calculating means is given to the cycle timing correcting means. In the synchronous control system according to claim 1,
A synchronization control system comprising a plurality of the drive devices, wherein the start timings of all the drive devices are synchronized with a synchronization signal output from the controller device.

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