JP5743383B2 - Piezoelectric element and method for manufacturing piezoelectric device - Google Patents

Description

  The present invention relates to a method for manufacturing a piezoelectric element.

  Among electronic devices, a piezoelectric element has a piezoelectric material as a component and utilizes a conversion function between a machine and electricity, and some materials such as quartz have conventionally been applied to sensors, actuators, etc. Has been made. In addition, some ceramic materials such as oxides and nitrides are known to have piezoelectric characteristics, and are applied to various applications.

  In recent years, in order to apply a piezoelectric element to an electronic circuit such as an integrated circuit, development of a small electronic device having a good electrical characteristic called a micro-electro-mechanical system (MEMS) element has become active. A MEMS element is an element expected to be applied to wireless communication technology, display, biotechnology, etc. by taking advantage of its good electrical characteristics. Among these, especially in the case of wireless communication technology, it is driven by a rechargeable battery due to the advantages such as high Q value (Quality factor), good linearity between input and output, and relatively low operating voltage. Circuit applications for wireless terminals such as mobile phones are expected.

  The piezoelectric drive type MEMS element is composed of a plurality of components as follows. The first component includes a substrate. The substrate is used as a part of a part that supports the MEMS element or as a part of an electrode layer or an insulating layer. The second component includes a MEMS electrode layer and a metal layer that functions as a grounding and mounting pattern. The third component includes an insulator layer that functions as a MEMS shim layer, a support layer, a piezoelectric layer, an interlayer insulating layer between electrodes, and the like. Among these, what adversely affects the final MEMS characteristics include the occurrence of an in-plane distribution of film thickness within the wafer, a decrease in controllability of residual stress, and an in-plane distribution of etching rate. .

  The causes of these adverse effects include fluctuations in the potential of the substrate surface and in-plane non-uniformity during film formation and etching in the film formation apparatus. In particular, this tendency is remarkable when a substrate or a thin film used for film formation and etching is a highly insulating material, such as a shim layer, a support layer, and an interlayer insulating layer in electrostatic MEMS. And a piezoelectric layer such as a piezoelectric layer and an interlayer insulating layer. When the substrate and the thin film formed on the substrate are insulative, in a normal film forming apparatus or etching apparatus, potential distribution is generated due to incomplete contact with the substrate holder, and charge induced on the front and back surfaces is not generated. As a result, the amount of ion assist on the substrate surface during film formation fluctuates due to the occurrence of potential distribution due to uniformity and the like, which affects various characteristics of the thin film.

JP 2008-105162 A

Here, in the method for manufacturing a piezoelectric element according to the present invention, conductive films are formed on the entire front and back surfaces except for the side surfaces of the substrate, and the conductive films on the front and back surfaces of the substrate are electrically connected by the through holes formed in the substrate. And a step of forming a piezoelectric layer by sputtering on one surface of the conductive film on the surface of the substrate. In the step of forming the piezoelectric layer, the conductivity of the conductive film on the front and back of the substrate and the conductivity of the through hole The membrane is characterized by having the same potential .

  Moreover, it is preferable that at least a part of the wiring for electrically connecting the conductive film on the front and back of the substrate is constituted by a through wiring penetrating the front and back of the substrate.

  The piezoelectric layer is preferably formed by sputtering.

  Further, it is preferable that the conductive film is processed so that the through wiring constitutes at least a part of the electrodes of the piezoelectric element.

According to another aspect of the present invention, there is provided a method for manufacturing a piezoelectric device, wherein the conductive film formed on the front and back surfaces of the piezoelectric element manufactured by the above-described manufacturing method is used as at least a part of a metal pattern for a package. And a step of packaging the piezoelectric device.

  Residual stress of the piezoelectric layer generated during the manufacture of the piezoelectric element was reduced.

FIG. 1 is a schematic view showing an example of the piezoelectric element of the present invention. FIG. 2 is a schematic view of a substrate provided with a conductive film and through wiring on the substrate. It is a schematic diagram which shows the modification of the pattern of the electroconductive film and penetration wiring formed in the board | substrate of this invention. FIG. 4 is a schematic view of an example of a sputtering apparatus used for manufacturing the piezoelectric element or the piezoelectric device of the present invention. FIG. 5 is a schematic diagram showing a charged state of a substrate (A) not provided with a conductive film and a through wiring under plasma and a substrate (B) provided with a conductive film and a through wiring. FIG. 6 is a graph showing the residual stress measurement results of the substrates of Example 1-3 and Comparative Example 1-3. FIG. 7 is a schematic view of an example of an RF ion etching apparatus used for manufacturing the piezoelectric element or the piezoelectric device of the present invention. FIG. 8 is a graph showing the etching rates of the substrates of Example 4 and Comparative Example 4. FIG. 9 shows patterns of the conductive film and the through wiring formed on the substrate (A) of Example 5, the substrate (B) of Example 6, the substrate (C) of Example 7, and the substrate (D) of Example 8. FIG. FIG. 10 is a graph showing the etching rate of the substrate of Example 5-8. FIG. 11 is a schematic view showing the piezoelectric element manufacturing process of the present invention. FIG. 12 is a graph showing the results of the piezoelectric element characteristic evaluation in Example 9. FIG. 13 is a schematic diagram showing an example of the piezoelectric element manufacturing process of the present invention. FIG. 14 is a graph showing the results of the piezoelectric element characteristic evaluation in Examples 9 and 10. FIG. 15 is a schematic view showing an example of a piezoelectric element manufacturing process at the wafer level of the present invention.

  The inventors have made various studies and found the following facts.

  Using a conductive material, a conductive film is formed on the front and back of the substrate with the substrate sandwiched between them, and the substrate is electrically connected to make the potentials on the front and back of the substrate the same. I found it.

Furthermore, the present inventors have found a method for manufacturing a piezoelectric element and a piezoelectric device that reduce the number of process steps by using a conductive material formed on the front and back of a substrate for bonding of an outer layer or the like when packaging an electrode of a piezoelectric element or packaging.

  An example of a piezoelectric element manufactured by the method for manufacturing a piezoelectric element of the present invention is shown in the schematic diagram of FIG. The piezoelectric element shown in FIG. 1 is a substrate in which a through electrode, an electrode pad, a piezoelectric layer, an electrode layer, and the like are formed. The electrode pad is obtained by processing a conductive film formed in advance.

  First, a substrate on which a conductive film is formed will be described. The substrate on which the conductive film is formed may be either a highly insulating substrate such as pure quartz glass or a semiconductor substrate. Specific examples include insulators such as pure quartz glass, alkali glass, silicon, sapphire, and a sintered ceramic substrate, or semiconductor substrates. Note that the effect of the conductive film is greater on the semiconductor substrate, particularly the high resistance semiconductor substrate, but the effect of the conductive film can be obtained even on the low resistance semiconductor substrate.

  Next, the conductive film will be described. The conductive film formed on the substrate is formed on the front and back of the substrate, and the front and back of the substrate are electrically connected. As an example of a form of electrically connecting the front and back of the substrate, a wiring is provided on at least a part of the entire side surface of the substrate, and the wiring is connected to a conductive film on the front and back of the substrate, or through holes are provided in the substrate. The through hole is plugged with a conductive material to form a through wire, and the front and back of the substrate are electrically connected by the through wire.

  As a method for forming the through wiring, after forming a conductive film on the substrate surface, a through hole is formed in a part of the substrate, and the through hole is plugged using a conductive material. And a method of plugging through-holes at the same time as forming the conductive film on the front and back of the substrate after forming the substrate. The method for plugging is not particularly limited, such as a plating method.

The conductive material used for the wiring that electrically connects the conductive film and the front and back of the substrate may be any material that is conductive to some extent. Specifically, transition metals (Ti, Ni, Fe, Cu, Mo, W, Ta, etc.), noble metals (Ag, Au, PT, Ir, etc.), oxide thin films (ITO, YBCO, ReO ₆ etc.) and organic Examples thereof include organic films such as conductive polymers. In particular, an organic conductive polymer is preferable because it can be easily applied to a substrate and filled with a through hole. When a low-melting substance such as an organic conductive polymer is used as the conductive material, the piezoelectric element and the piezoelectric device must be manufactured with particular attention to the melting point.

  If the thickness of the conductive film formed on the front and back of the substrate is less than 1 nm, it is difficult to form a film, and if it is more than 1000 nm, the cost of film formation and etching increases. In addition, the conductive film is preferably formed by a sputtering method, a CVD method, a vacuum evaporation method, a plating method, or the like.

  FIG. 2 is a schematic view in which a conductive film 2 and a through wiring 3 are formed on an insulating or semiconductor substrate 1. Even if the substrate 1 is an insulating substrate or a semiconductor substrate by forming the conductive film 2 and the through wiring 3 as shown in FIG. 2 in the subsequent formation process of the piezoelectric layer and the like, the substrate holder and the through wiring And the electric potential of the substrate front and back can be made the same electric potential.

  FIG. 3 shows some examples of patterns for forming the conductive film 2 (hatched or thick line portion) and the through wiring 3 (white cylindrical portion) formed on the front and back of the substrate according to the chip area and the like. In the substrate 1 in which the conductive film 3 is formed on both sides of the substrate in FIG. 3A, the through wiring 3 is formed at the apex of each square chip according to the periodicity of one side of the square chip. In addition, in the substrate 1 in which the conductive film 2 is formed on the front and back of the substrate in FIG. 3B, the through wiring 3 is not formed near the center of the wafer on which the chip is formed, but penetrates to the outermost periphery used as a wafer handling area A wiring 3 is formed. Further, in the substrate 1 of FIG. 3C, the conductive film 2 indicated by a thick line is patterned in a slit shape in the X and Y directions, and a back surface conductive film and a through-wiring are formed immediately below each intersection (node) of the slit. To do. In this case, it is possible to form an element on the original substrate while maintaining a good substrate potential.

  When a piezoelectric layer is formed on a substrate on which no conductive film is formed on the front and back surfaces of the substrate and through-holes using a film forming apparatus as shown in FIG. 4, the influence due to the non-uniformity of the charge in the plasma near the substrate surface As shown in FIG. 5A, the charge amount on the front and back sides of the substrate disposed in the substrate holder 10 becomes non-uniform as shown in the schematic diagram showing the charged state of the substrate. Note that − and + in FIG. 5 indicate electric charges.

  However, when the substrate having the conductive film and the wiring for electrically connecting the conductive film is formed with a piezoelectric layer on the conductive film using an apparatus as shown in FIG. 5, the substrate of FIG. As shown in the schematic diagram showing the charged state, the conductive film 2 and the through wiring 3 on the substrate surface have the same potential as the substrate holder 10 and the potential becomes uniform, and the intensity of ion bombardment of Ar ions on the substrate (acceleration voltage). ) And Ar ion irradiation amount (ion current) are controlled, so that the micro growth mode of the thin film is controlled.

  Accordingly, when a piezoelectric layer or the like is formed on a substrate having the same front and back surface and through-hole potential as shown in FIG. 2, the orientation, residual stress, and in-plane distribution of the piezoelectric layer formed on the substrate can be easily controlled. . Further, such a piezoelectric layer has excellent etching characteristics, can reduce variations in elements in the same chip, and can improve the retention.

Next, as a reference example, an outline of a method for manufacturing a piezoelectric element using a conductive film as at least a part of a fixed electrode will be described with reference to a schematic diagram illustrating an example of a manufacturing process of the piezoelectric element in FIG.
A method for manufacturing a piezoelectric element using a conductive film based on a method for manufacturing a unimorph type tunable capacitor having a cantilever bridge will be described. However, the present invention can be applied to other than a unimorph type tunable capacitor. Is possible.

First, as shown in the schematic diagram of the piezoelectric element manufacturing process in FIG. 11B, on the surface of the substrate having the piezoelectric element substrate front and back and the through wiring 3 as shown in FIG. 11A, a dielectric that finally becomes the piezoelectric body of the capacitor. Layer 23 is patterned. As a material of the dielectric layer 23, a substance generally used as a piezoelectric material such as AlN, PZT, ZnO, crystalline SiO ₂ can be adopted.

  Next, as shown in the schematic diagram of the piezoelectric element manufacturing process in FIG. 11D, the lower electrode layer 25 is formed on the sacrificial layer 24 and the sacrificial layer. After forming the lower electrode layer, the two through wirings are processed by etching or the like to be electrically separated. 11F, the upper electrode layer 27 is formed on the piezoelectric layer 26 and the piezoelectric layer 26. The piezoelectric layer 26 is preferably formed by a sputtering method, MOCVD method, laser ablation method, sol-gel method, or the like, and the sacrificial layer 24 may be a generally used sacrificial layer such as poly-Si.

In the schematic diagram of the piezoelectric element manufacturing process of FIG. 11G, the conductive film 2 formed on the back surface of the substrate is electrically used for the purpose of ensuring the function as a pad of each electrode before the sacrificial layer 24 removing process. Pattern the backside pad to be separated into two. Actually, the conductive film is divided by the wet etching, dry etching, mechanical polishing process, and the like as in the piezoelectric element manufacturing process of FIG. 11G.
In order to improve the etching rate in the sacrificial layer removal step and to ensure in-plane uniformity of etching, it is preferable to open a slit in a part of the area where the sacrificial layer is scheduled to be removed.

  Finally, as shown in the schematic diagram of the piezoelectric element in FIG. 11I, when the sacrificial layer 24 and the conductive film 2 are etched, the sacrificial layer is removed, and the electrode pads 32, 33, and 36 on the substrate surface are patterned. Thus, a tunable capacitor structure is completed. The through electrode constitutes a part of the electrode (fixed electrode) of the piezoelectric element.

  Next, a method of manufacturing the piezoelectric device shown in FIG. 13D by using the conductive film 2 as the package metal films 39 and 40 and packaging the piezoelectric device will be described. The metal film for a package is used for a joint portion when sealing the piezoelectric element.

  There are two types of packaging methods: dicing before dicing and dicing. Both are processed by the same method until patterning of the back surface pad in the piezoelectric element manufacturing process. Specifically, the sacrificial layer, the conductive film in the unprotected portion, and the protection after dicing and dicing before or after forming the etching protective film on the portion that becomes the package metal film to which the package material is bonded A first packaging method in which the film is removed and the individual chips are individually packaged, and an etching protective film is formed on a portion that becomes a package metal film to which the package material is bonded, and a sacrificial layer, a protection layer This is a second packaging method in which the conductive film and the etching protection film in the unexposed portion are removed and packaged, and then dicing is performed to separate the wafer.

  The wafer level package, which is the second packaging method, can be packaged without producing a device at the wafer level, and then dicing into chips to separate the chips. This contributes to the conversion. Therefore, it is particularly preferable that the second packaging method does not require packaging for each chip. In addition, these packaging methods include not only piezoelectric elements but also piezoelectric element drive circuits, memories, and other circuits, so that the final chip is formed in an integrated state, and the packaging is less integrated. It is possible to use an area, and the mounting cost can be extremely low.

  Note that it is preferable to use a diamond dicer, a laser dicing apparatus, or the like as an apparatus for separating the elements. Table 1 shows examples of various conductive materials used for the conductive film and process conditions suitable for each.

In the method for manufacturing a piezoelectric element and a piezoelectric device, the sacrificial layer, the unprotected conductive film, and the protective film are preferably removed by ion milling using Ar gas or etching using fluorine gas. When removing the protective layer, the gas used varies depending on the material and thickness of the etching protective film. For example, when SiO ₂ is used as the protective film, the thickness of the SiO ₂ layer is preferably 1-100 nm. It is preferable to remove the SiO ₂ layer of about 100 nm for CF ₄ gas, about 10 nm for SF ₆ gas, and about 1 nm for XeF ₂ gas.

(Example 1-3, Comparative example 1-3)
In Example 1-3 and Comparative Example 1-3, an example of manufacturing a piezoelectric thin film using the 6-inch substrate shown in Table 2 will be described. In the substrate of the example, a 100 nm Ti film is formed on the front and back of the substrate by sputtering, and a through wiring plugged with a through hole is formed so as to electrically connect the front and back of the substrate. Further, the conductive film and the through wiring using a conductive material are not formed on the substrate of the comparative example. In the present embodiment, an AlN piezoelectric layer was formed on each of the substrates shown in Table 2 by a sputtering film forming process using a sputtering apparatus as shown in FIG. Table 3 shows the sputtering conditions for forming the AlN layer. In the example of this embodiment, when forming an AlN layer, RF power is simultaneously applied to the substrate, a voltage is applied to the substrate, and ion assist from the plasma is controlled, thereby ensuring orientation of the thin film and residual stress. Control is implemented.

  The graph of FIG. 6 shows the result of forming the piezoelectric layer on the substrates of Example 1-3 and Comparative Example 1-3 and measuring the residual stress. The broken line in FIG. 6 is the result of Example 1-3, the solid line is the result of Comparative Example 1, the one-point long chain line is the result of Comparative Example 2, and the two-point long chain line is the result of Comparative Example 3. In the comparative example, effects such as a decrease in controllability and an increase in distribution of the residual stress of the AlN layer frequently occurred. In addition, the substrate potential distribution also affects the crystallinity, and in the piezoelectric thin film in which the central portion of the substrate is particularly grown, an influence on the structural characteristics such as a significant deterioration of the piezoelectric characteristics was also observed. On the other hand, in the case of the example in which the conductive film and the through wiring were formed on the substrate, it was found that the residual stress generated in the AlN layer and its film thickness distribution were extremely small even if the original substrate was an insulator or semiconductor. . It has been found that the substrate of this example has a significant effect on the yield improvement by improving the distribution state in the wafer. As a result of uniformizing the substrate potential by the conductive film and the through wiring, the average residual stress value in each example is about 50 MPa, and the standard deviation of the residual stress value in the wafer in-plane distribution is 10%. Evaluation results were obtained.

(Example 4, comparative example 4)
In Example 4 and Comparative Example 4, etching was performed on the 6-inch glass wafer on which the piezoelectric layer was formed in Example 1 and Comparative Example 1. Etching was performed using the RF ion etching apparatus of FIG. The results are shown in the graph of FIG. The solid line in the graph indicates the etching rate of Example 4, the broken line, the one-point long chain line, and the two-point long chain line. A large difference is observed in the etching rate of the 1 μm thick AlN thin film formed on the substrate depending on the presence or absence of the conductive film and the through wiring. This effect was achieved when the conductive film and through wiring were used, and the acceleration effect of the ion species by the RF power source was made uniform by improving the distribution of the substrate potential, resulting in an improved distribution of the etching rate in the wafer surface. It is thought that it depends. The large deviation of the etching rate when the conductive thin film is not used is considered to be due to local ion acceleration variation due to the difference in electric field distribution. As a result of uniformizing the substrate potential by the conductive film and the through wiring, in Example 6, in the glass wafer of 6 inch size, in Example 4, the etching rate is about 100 nm / min, and the standard deviation of the wafer in-plane distribution is 10%. Good etching characteristics were obtained. On the other hand, in Comparative Example 4, the standard deviation is 50%, and it is considered that the etching rate is not good due to the residual stress of the AlN layer.

(Example 5-8)
In Example 5-8, a conductive film and a through wiring were formed on a 6-inch glass substrate with different patterns, and the distribution of the residual stress value of each substrate was measured. The pattern of the conductive thin film in Example 5-8 and the electrical connection method thereof are shown in the schematic diagram of the substrate pattern in FIG. The fifth embodiment has a pattern as shown in FIG. 9A and is the same as the first embodiment. In the pattern as shown in FIG. 9B of Example 6, a part of the conductive film formed on the surface is patterned, and at least a part of the surface conductive film 2 and the electrode on the back surface are electrically connected. Is connected to. In the pattern as in FIG. 9C of Example 7, the embedded surface conductive film and the back surface conductive film are connected. Further, the pattern as shown in FIG. 9D of Example 8 is characterized in that the original device fabrication substrate is bonded to the upper portions of the connected front and back conductors by some method. FIG. 10 shows the distribution of residual stress in an AlN thin film produced using these methods using a glass substrate. The solid line in FIG. 10 indicates the residual stress of Example 5, the broken line indicates the residual stress of Example 6, the one-dot long chain line indicates the residual stress of Example 7, and the two-dot long chain line indicates the residual stress of Example 8. As standard deviation values of residual stress in a 6-inch wafer, values of 5% were obtained in Example 5, 8% in Example 6, 7% in Example 7, and 10% in Example 8. It can be seen that the film has good characteristics as compared with the standard deviation of 50% or more in the case where the film is formed directly on the substrate and the high-resistance semiconductor substrate (Comparative Examples 1 and 2).

(Example 9 (reference example) )
In Example 9 (reference example) , in order to ensure the conductivity of the substrate surface, the conductive film and the through wiring formed in advance before the formation of the piezoelectric element are used as at least a part of the electrode layer forming the piezoelectric element. An example of manufacturing a piezoelectric element will be described. An example of manufacturing a tunable capacitor (piezoelectric element) will be described with reference to a schematic diagram showing a manufacturing process of FIG. In this example, a unimorph type tunable capacitor having a cantilever type bridge was manufactured.

  A glass substrate in which the entire front and back surfaces were covered with a 1 μm thick Ti film as shown in the schematic diagram of FIG. 11A was used. The Ti films on the front and back surfaces are electrically connected by through wiring. In the step of FIG. 11B, AlN finally functioning as the dielectric layer 23 of the capacitor was patterned on one through wiring on the surface of the substrate. In the step of FIG. 11C, 2 μm-thick poly-Si was formed as the sacrificial layer 24 on the region including the dielectric layer 23. In the step of FIG. 11D, an Al film having a thickness of 1 μm was formed as the lower electrode layer 25 on the sacrificial layer 24. Further, after patterning the Al lower electrode layer 25, the surface Ti layer was separated so as to electrically separate the two through wirings. Next, in the step of FIG. 11E, AlN having a thickness of 500 nm was formed as the piezoelectric layer 26 on the lower electrode layer 25. The film forming conditions are the same as those shown in Table 3. In the step of FIG. 11F, as the upper electrode layer 27, a 200 nm thick Al layer was formed on the through wiring on the piezoelectric layer. In the process of FIG. 11G, before the sacrifice layer 24 removal process, the Ti film formed on the back surface of the substrate was electrically separated by etching for the purpose of ensuring the function as each electrode pad. Next, in the process of FIG. 11H, a slit is opened in an area where the sacrificial layer is to be removed in order to improve the etching rate in the sacrificial layer 24 removing process and to ensure in-plane uniformity of etching. Finally, in the step of FIG. 11I, the sacrificial layer and the unprotected conductive film are etched to complete the tunable capacitor structure (piezoelectric element).

  Here, in the finally completed tunable capacitor, as in the process of FIG. 11I, a fixed electrode (through electrode 32 and electrode) is formed by patterning the Ti film formed on the surface at the time of FIG. 11A. Pad 28 and the like). The Ti film on the surface can be selectively etched by selecting an appropriate etching condition in the sacrificial layer removing step using a fluorine-based gas. In FIG. 11I, a Ti film (conductive film) remains in a portion protected by the Al electrode, the AlN piezoelectric layer, and the AlN dielectric layer, and as a result, it can be patterned as shown in FIG. 11I. It was. The feature of the process of this example is that there is no fixed electrode bulge in the process as seen in the conventional example, and the influence on the orientation of the layer formed on the upper part and the residual stress can be reduced. Is mentioned. In addition, this process improves the controllability of residual stress and at the same time has an advantage that the number of process steps can be reduced.

  The characteristics of the piezoelectric tunable capacitor manufactured based on the method of this example were evaluated. The result of the characteristic evaluation is shown in the graph of FIG. As shown in FIG. 12, good electrical characteristics with an operating voltage of 2.5 V and a capacity change rate of 10 times were obtained. Further, when the Q value of this tunable capacitor was evaluated by a vector network analyzer, it was found that about 100 was obtained in the frequency band of 2 GHz, and that it had good characteristics.

(Example 10 (reference example) )
In Example 10 (reference example) , an example of a process in which a piezoelectric element is packaged using a conductive film on a substrate surface separated by dicing as a metal film for a package (package lid) will be described. FIG. 13 shows a schematic diagram of the piezoelectric device manufacturing process. In FIG. 13, the reference numerals shown in FIG. 11 are omitted. The procedure up to FIG. 13A is the same as that of Example 9 except that an Au / Ti laminated film is used instead of the Ti film as the conductor layer on the front and back surfaces. In the schematic diagram of the piezoelectric device manufacturing process of FIG. 13A, the film thicknesses of Au and Ti were 200 nm and 500 nm, respectively, and were sequentially formed on the substrate surface by sputtering in the order of Ti → Au. In order to form the package pattern on the substrate, it is necessary to leave an Au / Ti conductive film. Therefore, as shown in the schematic diagram of the piezoelectric device manufacturing process of FIG. 13B, about 100 nm of SiO ₂ films 37 and 38 are laminated and patterned as an etching protective layer during the sacrifice layer etching. Next, in the schematic diagram of the piezoelectric device manufacturing process of FIG. 13C, the patterned SiO ₂ film was dry-etched through photolithography to remove the etching protection layer and the unprotected conductive film. Then, the conductive film at the site protected by SiO ₂ remained, and the metal films for packaging 39 and 40 were formed. Finally, as shown in the schematic diagram of the piezoelectric device manufacturing process in FIG. 13D, an HTCC (High Temperature Sintered Ceramic Multilayer Substrate) ceramic-based package material 43 is bonded with Au—Sn alloys 41 and 42 by a crimping device, and the piezoelectric device is Manufactured.

  In a conventional tunable capacitor after packaging, the pad must be taken out from the ceramic substrate side. Therefore, it is necessary to form the electrode layer on the ceramic substrate by plating, vapor deposition, damascene method, etc. Although it was disadvantageous in terms of production, the structure of the ceramic substrate was simplified by using the method of this embodiment, and there was no fear of occurrence of a failure mode such as contact failure due to bonding. Is easily possible.

  The electrical characteristic evaluation of the tunable capacitor after packaging manufactured by this method is shown in the graph of FIG. 14 together with the electrical characteristic evaluation of Example 9. The broken line before the package is Example 9, and the solid line after the package is that of Example 10. From the figure, although the parasitic capacitance of the ceramic package is superimposed, a tunable capacitor having an operating voltage of 2 V and a capacitance change rate of about 5 times was obtained. Further, the Q value including the parasitic capacitance was a good value of about 60.

(Example 11)
Example 11 describes an example in which the patterned conductive film on the substrate surface is also used as a package metal film (package lid) and applied to a wafer level package. Example 11 is the same as Example 10 except that dicing is performed after packaging. In this embodiment, an insulating glass wafer having a Ti conductive film as shown in FIG. 3C is used as a substrate. An example of the application process to the wafer level package is shown in the schematic diagram of FIG. 15A and 15B, the conductive film 2 is formed in a slit shape on the wafer, and the piezoelectric element is formed on the wafer in the same manner as in Example 10 on the insulating substrate as shown in the schematic diagram of FIG. 15A. A wafer provided with a metal film for a package as described above was produced. As shown in the schematic diagram of FIG. 15D, packaging was performed using the packaging material 43 having the same size as the wafer. Then, the packaged wafer was diced as shown in the schematic diagrams of FIGS.
From the electrical characteristics evaluation of the piezoelectric device fabricated using this example, a tunable capacitor having a drive voltage of 3.0 V, a capacitance change rate of 5 times, and a Q value of 50 was obtained.

  In addition to the above-described embodiments, many metal films can be selected, and the same function can be achieved in a multilayer film having another configuration, a functionally gradient material, or the like. Depending on the substrate material, various conductive films can be produced by plating, damascene process, etc., and due to the wide range of application of the present invention, not only piezoelectric elements produced by surface micromachining, but also semiconductor elements. A wide range of applications are considered possible.

If the method described in the present invention is used, the cantilever type tunable by the sputtering method can bring about the same effect not only in the AlN thin film described in the embodiment but also in other piezoelectric materials such as PZT, ZnO, crystalline SiO _{2 and the} like. It was found by capacitor characteristic evaluation. Further, the film forming method is not limited to the sputtering method, but other film forming methods such as a laser ablation method and a CVD method have been found to have the same effect although there is a difference in the magnitude of the effect.

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Conductive film 3 ... Through-wire 4 ... Vacuum chamber 5 ... RF power source for sputtering 6 ... Cathode 7 ... Al target 8 ... Plasma 9 ... Substrate 10 ... Substrate holder 11 ... RF power source for substrate bias 12 ... Substrate holder DESCRIPTION OF SYMBOLS 13 ... Vacuum chamber 14 ... RF power supply for etching 15 ... RF electrode for etching 16 ... Plasma discharge chamber 17 ... Plasma 18 ... AlN film 19 ... Substrate holder (also acceleration electrode)
DESCRIPTION OF SYMBOLS 20 ... RF power source for ion acceleration 21 ... DC power source for ion extraction 22 ... Substrate for device creation 23 ... Dielectric layer 24 ... Sacrificial layer 25 ... Lower electrode layer 26 ... Piezoelectric layer 27 ... Upper electrode layer 28 ... Electrode pad 29 ... Electrode pad DESCRIPTION OF SYMBOLS 30 ... Electrode pad 31 ... Through electrode 32 ... Electrode pad 33 ... Electrode pad 34 ... Through electrode 35 ... Electrode pad 36 ... Through electrode 37 ... Etching protective layer 38 ... Etching protective layer 39 ... Metal film for packages 40 ... Metal film for packages 41 ... Au-Sn alloy layer 42 ... Au-Sn alloy layer 43 ... Packaging material 44 ... Piezoelectric device

Claims (3)

Producing conductive films on the entire front and back surfaces excluding side surfaces of the substrate, and electrically connecting the conductive films on the front and back sides of the substrate through the through holes formed in the substrate;
Forming a piezoelectric layer by sputtering on one surface of the conductive film on the substrate surface ,
In the step of forming the piezoelectric layer, the conductive film on the front and back of the substrate and the conductive film of the through hole are set to the same potential . The method for manufacturing a piezoelectric element according to claim 1 , further comprising a step of processing the conductive film so that the through wiring forms at least a part of an electrode of the piezoelectric element. A step of packaging a piezoelectric device using the conductive film formed on the front and back of the substrate of the piezoelectric element manufactured by the manufacturing method according to claim 1 as at least a part of a metal pattern for packaging. A method for mounting a piezoelectric device.