JP5737053B2 - Electronic circuit and mounting board - Google Patents

Description

  The technology disclosed in the present application relates to an electronic circuit and a mounting substrate. In particular, the present invention relates to an electronic circuit and a mounting board for suppressing so-called simultaneous switching output noise (hereinafter referred to as SSO noise) such as a drop in power supply voltage and a rise in ground voltage that occur when outputting a plurality of signals.

  The SSO noise is generated when a drive current that increases or decreases with time flows in a path of a power supply voltage or a ground voltage when the voltage level of signals output from a plurality of output drivers changes. Since a parasitic inductor component exists in the path of the power supply voltage or the ground voltage, an induced voltage is generated by a drive current that increases and decreases with time. Since this induced voltage is generated in a direction that hinders increase / decrease in drive current, it becomes noise that lowers the power supply voltage or raises the ground voltage. This noise is SSO noise. A method for detecting SSO noise is conventionally known.

  For example, the connection of the integrated circuit to the supply voltage is via package pins, bond wires, bond pads, conductors. In addition, a coil positioned adjacent to the conductor is provided. Since there is inductive coupling between the conductor and the coil, an induced voltage is generated in the coil due to a change in the current flowing through the conductor. This induced voltage is supplied from the coil to the amplifier. There is a technique in which an amplifier is connected to a peak detector and detects whether or not an amplified signal exceeds a predetermined threshold value (for example, Patent Document 1).

  Some inverter logic circuits and LC elements have two inductor conductors on a semiconductor substrate, and these two inductor conductors have a transformer function by being magnetically coupled. One end of the inductor conductor on the primary side of the LC element is connected to the output end of the inverter logic circuit, and the other end is connected to the power supply line. In addition, one end of the inductor conductor on the secondary side of the LC element is directly connected to the input end of the inverter logic circuit via the capacitor, and the other end is directly grounded. As a result, a sine wave is generated (Patent Document 2, etc.).

Japanese National Patent Publication No. 11-510906 JP 7-336137 A

  A plurality of output drivers are provided, and some of the output drivers may change the voltage level of the signal. The increase or decrease of the drive current generated at this time causes the SSO noise induced in the power supply voltage or ground voltage path. The magnitude and the generation period of SSO noise change. In order to reduce SSO noise, control according to the number of transition signals is necessary.

  However, the above background art only discloses that each conductor includes a coil and a peak detector. There is no description regarding performing SSO noise reduction control in accordance with the number of transition signals. In addition, when a configuration in which a change in current is fed back using an LC element is used for SSO noise reduction control, there is a problem in that a phase delay due to feedback occurs and system oscillation tends to occur.

  The technology disclosed in the present application has been proposed in view of the above problems, and when outputting a plurality of signals, the power supply voltage depends on the direction of the voltage level transition of the signal and the number of signals to be transitioned. An electronic circuit and a mounting board that can suppress SSO noise by adding a current that does not pass through the path of the ground voltage and that is not affected by the parasitic inductance component to assist in the transition of the voltage level of the signal. The purpose is to do.

An electronic circuit according to a technique disclosed in the present application includes at least one of an output buffer circuit, an output line through which an output signal output from the output buffer circuit propagates, and a power supply line or a ground line that supplies power to the output buffer circuit On the other hand, a magnetic core surrounded by an output line and a power supply line or a ground line, a control coil wound around the magnetic core, a transition of an output signal is detected in advance, and current supply to the control coil is controlled according to a detection result And a control unit. In accordance with the transition direction of the output signal, an assist current for assisting the signal transition of the output line is caused to flow by electromagnetic induction from the control coil.
Further, the mounting board according to the technology disclosed in the present application detects in advance a transition of an output signal output from the magnetic core, a control coil wound around a part of the magnetic core, an output buffer circuit, and the output buffer circuit. And a semiconductor package containing an electronic circuit including a control unit that controls current supply to the control coil in accordance with the detection result. Here, the semiconductor package includes an output line lead for propagating an output signal output from the output buffer circuit, and at least one of a power line lead and a ground line lead for supplying power to the output buffer circuit. The output line lead and the power supply line or the ground line lead have different lengths led outward, and the magnetic core is sandwiched and mounted between the output line lead and the power supply line or the ground line lead.

  According to the electronic circuit and the mounting board according to the technology disclosed in the present application, when outputting the output signal, the assist current induced in the output line is generated according to the direction of the voltage level transition of the output signal. This can assist the output current when the voltage level of the signal transitions. As a result, it is possible to reduce transient fluctuations in the power supply voltage or the ground voltage accompanying a change in current flowing in the power supply line or the ground line.

It is a block diagram of the output circuit concerning an embodiment. It is a block diagram of the coil current calculator which concerns on embodiment. It is a block diagram of DAC which concerns on embodiment. It is a figure which illustrates the case where a 4-bit data signal propagates to the output circuit which concerns on embodiment. It is a circuit diagram which shows another example of DAC. It is a circuit diagram which shows another example of a coil current calculator. It is a circuit diagram which shows the 2nd another example of DAC. It is a figure which shows the effect by the direction of the assist current with respect to the different voltage level of the output data signal. It is a circuit diagram which shows the 2nd another example of a coil electric current calculator. It is a top view of a semiconductor device (mounting substrate) provided with the output circuit concerning an embodiment. It is sectional drawing of the semiconductor device (mounting board | substrate) which concerns on embodiment. It is a top view which shows another example of a semiconductor device (mounting board | substrate). It is the figure which looked at the semiconductor device (mounting substrate) from the outer lead Lev0 side.

  FIG. 1 is a block diagram of an output circuit 1 according to an embodiment of the present application. When the output circuit 1 outputs the data signals DQ (0) to DQ (n), which are bit signals of (n + 1) bits, according to the direction of the voltage level transition of the signal and the number of transition signals, Assists the output current when transitioning the voltage level of the signal by generating an induced current in each of the signal lines DQL (0) to DQL (n) of the data signals DQ (0) to DQ (n), and SSO noise. It is a device which suppresses.

  The output circuit 1 includes an output control circuit 2, a coil current control circuit 3, an output buffer 4, and a current assist circuit 5. The output control circuit 2 propagates data signals D2 (0) to D2 (n), which are (n + 1) -bit signals, to the output buffer 4. Data storage flip-flops (hereinafter referred to as data FF) 20 and 21 and output stage flip-flops (hereinafter referred to as output stage FF) 22 are provided. The data FF 20 is connected to a control circuit (not shown) via signal lines D2L (0) to D2L (n) through which the data signals D2 (0) to D2 (n) propagate, and the data FF20 is transmitted to the clock signal CLKL. Data signals D2 (0) to D2 (n) are taken in at the rise. The data FF21 is connected to the data FF20 via signal lines D1L (0) to D1L (n) through which the data signals D1 (0) to D1 (n) that are (n + 1) -bit signals propagate, and the data signal D1 (0 ) To D1 (n) are taken in at the rising edge of the clock signal CLK. The output stage FF22 is connected to the data FF21 via signal lines D0L (0) to D0L (n) through which data signals D0 (0) to D0 (n), which are multi-bit signals, propagate, and the data signal D0 (0). ... D0 (n) is taken in at the rising edge of the clock signal CLK. The output stage FF22 is connected to the output buffer 4 via signal lines DL (0) to DL (n) through which data signals D (0) to D (n), which are multi-bit signals, propagate. Accordingly, the output control circuit 2 outputs the data signals D2 (0) to D2 (n) to the output buffer 4 as the data signals D (0) to D (n) through three cycles of the clock signal CLK. Data signals D2 (0) to D2 (n) propagated from a control circuit (not shown) are sequentially propagated to the data FFs 20 and 21 and the output stage FF22 by the clock signal CLK, and the data signal D ( 0) to D (n) are output via the output buffer 4.

  The coil current control circuit 3 includes difference detectors 30 and 31, a coil current calculator 32, and a digital / analog converter (hereinafter referred to as DAC) 33. The difference detector 30 includes (n + 1) AND circuits 300 to 30n and an adder 303. The signal lines D0L (0) to D0L (n) and the signal lines D1L (0) to D1L (n) are connected to each of the AND circuits 300 to 30n for each bit. To the AND circuits 300 to 30n, the data signals D0 (0) to D0 (n) of the signal lines D0L (0) to D0L (n) are input in positive logic, and the signal lines D1L (0) to D1L (n) The data signals D1 (0) to D1 (n) are input with negative logic. When the high-level bit signal among the data signals D0 (0) to D0 (n) and the corresponding bit signal among the data signals D1 (0) to D1 (n) are at the low level, the AND circuits 300 to 30n Outputs a high level. The adder 303 outputs a differential signal Shl indicating the number of bits for which the output signals of the AND circuits 300 to 30n are at a high level. The difference signal Shl is output to the coil current calculator 32 via the signal line ShlL. The difference detector 30 compares the data signals D0 (0) to D0 (n) with the data signals D1 (0) to D1 (n) propagated in the next cycle of the clock signal CLK, and the signal of each bit is determined. The number of transitions from high level to low level is detected.

  The difference detector 31 includes (n + 1) AND circuits 310 to 31n and an adder 313. The signal lines D0L (0) to D0L (n) and the signal lines D1L (0) to D1L (n) are connected to each of the AND circuits 310 to 31n for each bit. To the AND circuits 310 to 31n, the data signals D0 (0) to D0 (n) of the signal lines D0L (0) to D0L (n) are input in negative logic, and the signal lines D1L (0) to D1L (n) Data signals D1 (0) to D1 (n) are input in positive logic. The AND circuits 310 to 31n when the low level bit signal of the data signals D0 (0) to D0 (n) and the corresponding bit signal of the data signals D1 (0) to D1 (n) are high level. Outputs a high level. The adder 313 outputs a difference signal Slh indicating the number of bits for which the output signals of the AND circuits 310 to 31n are at a high level. The difference signal Slh is output to the coil current calculator 32 via the signal line SlhL. The difference detector 31 compares the data signals D0 (0) to D0 (n) with the data signals D1 (0) to D1 (n) propagated in the next cycle of the clock signal CLK, and the signal of each bit is determined. The number of transitions from low level to high level is detected.

  The coil current calculator 32 is connected to the signal lines ShlL and SlhL, the clock line CLKL, the gain signal line GL, the threshold signal line TL, and the signal line DaciL. In the propagation of the data signal from the data signals D0 (0) to D0 (n) to the data signals D1 (0) to D1 (n), the control signal depends on the direction of voltage level transition and the number of transition signals. Calculate Daci. Specifically, in the data signals DQ (0) to DQ (n), a difference signal Shl that indicates the number of signals that transition from a high level to a low level and a difference that indicates the number of signals that transition from a low level to a high level. A control signal Daci is calculated according to the difference from the signal Slh. The control signal Daci is input to the DAC 33 via the signal line DaciL. The control signal Daci is a control signal that controls the direction and magnitude of a current that flows in the control coil 51 described later. The direction and magnitude of the current flowing through the control coil 51 is controlled in accordance with the control signal Daci, and the assist by the induced current flowing through the signal lines DQL (0) to DQL (n) is controlled.

  The control signal Daci is controlled according to the gain signal G and the threshold signal T input to the coil current calculator 32 via the gain signal line GL and the threshold signal line TL. That is, the output / non-output of the control signal Daci is controlled by the threshold signal T with respect to the difference between the difference signal Shl and the difference signal Slh. Thereby, it is controlled whether or not a current is supplied to the control coil 51. The gain signal G adjusts the magnitude of the control signal Daci. When the difference between the difference signal Shl and the difference signal Slh exceeds the threshold value T, a current is passed through the control coil 51. The magnitude of the current at this time is adjusted.

  The coil current calculator 32 is controlled in synchronization with the clock signal CLK. The control signal Daci is calculated in response to the sequential propagation of the data signal to the output control circuit 2 in response to the clock signal CLK.

  The DAC 33 converts the control signal Daci input through the signal line DaciL into a coil current Daco, and outputs the coil current DacoL to the current assist circuit 5 through the current line DacoL.

  The output buffer 4 includes (n + 1) output buffer circuits 40 to 4n. Output buffer circuits 40 to 4n are connected to voltage line VdeL, ground line VgL, signal lines DL (0) to DL (n), and signal lines DQL (0) to DQL (n). The output buffer circuits 40 to 4n receive signals having the same phase as the bit signals D (0) to D (n) input via the signal lines DL (0) to DL (n) as signal lines DQL (0) to DQL. Data signals DQ (0) to DQ (n) are output via (n).

  The current assist circuit 5 includes a magnetic core 50 penetrating a region surrounded by the signal lines DQL (0) to DQL (n), the voltage line VdeL or the ground line VgL, and a control coil 51 wound around the magnetic core 50. Prepare. The signal lines DQL (0) to DQL (n) and the voltage line VdeL, or the signal lines DQL (0) to DQL (n) and the ground line VgL form a coil surrounding the magnetic core 50. The control coil 51 is magnetically coupled to the signal line DQL (0) to DQL (n) and the voltage line VdeL or the signal line DQL (0) to DQL (n) and the ground line VgL via the magnetic core 50. Combined with When any of the data signals DQ (0) to DQ (n) transitions to a high level, the power supply line VdeL is connected to the signal lines DQL (0) to DQL (n) via any of the output buffer circuits 40 to 4n. Therefore, a current flows transiently from the power supply line VdeL toward the signal lines DQL (0) to DQL (n). Similarly, when transitioning to the low level, the ground line VgL is connected to the signal lines DQL (0) to DQL (n) via any of the output buffer circuits 40 to 4n, and thus the signal line DQL (0). Current flows transiently from DQL (n) to ground line VgL. At this time, since the power supply line VdeL or the ground line VgL has a parasitic inductance component, a back electromotive force is generated so as to prevent a transient current change due to a voltage level transition. In order to induce a current that assists the current change due to the voltage level transition against the SSO noise caused by the back electromotive force, a current is passed through the control coil 51.

  FIG. 2 is a block diagram of the coil current calculator 32 according to the embodiment. The coil current calculator 32 includes differential detector flip-flops (hereinafter referred to as differential detector FFs) 320 and 321, a subtractor 322, an arithmetic unit 323, an arithmetic unit flip-flop (hereinafter referred to as arithmetic unit FF) 324, a delay circuit 325, and A chopper circuit 326 is provided. As input lines, a signal line ShLL, a signal line SlhL, a clock line CLKL, a gain signal line GL, and a threshold signal line TL are connected. A signal line DaciL is connected as an output line. The difference detector FF 320 is connected to the signal line ShLL and the clock line CLKL, and takes in the difference signal Shl which is a bit string signal in which the numerical value added by the adder 303 is expressed in binary at the rising edge of the clock signal CLK. To output. The difference detector FF 321 is connected to the signal line SlhL and the clock line CLKL, and takes in the difference signal Slh, which is a bit string signal in which the numerical value added by the adder 313 is represented in binary at the rising edge of the clock signal CLK. To output. When the difference signals Shl and Slh are taken into the difference detector FFs 320 and 321, the subtractor 322 outputs the difference between the difference signal Shl and the difference signal Slh to the signal line UdL as the difference signal Ud. As for the difference signal Ud, data signals D0 (0) to D0 (n) are output as data signals DQ (0) to DQ (n) according to the clock cycle of the clock signal CLK, and the data signal D1 is output in the next clock cycle. When (0) to D1 (n) are output as data signals DQ (0) to DQ (n), they are signals indicating the direction of the voltage level transition of the signal and the number of signals that transition.

  The arithmetic unit 323 is connected to the signal line UdL, the gain signal line GL, and the threshold signal line TL as input lines, and is connected to the arithmetic signal line NcL as output lines. When the input differential signal Ud exceeds the value indicated by the threshold signal T, the calculation signal Nc whose value is adjusted by the gain signal G is calculated and output to the calculator FF 324 via the calculation signal line NcL. Is done. When the value indicated by the difference signal Ud is less than the value indicated by the threshold signal T, the calculation is not performed and the calculation signal Nc is not output. The arithmetic unit FF 324 is connected to the arithmetic signal line NcL and the clock line CLKL as input lines, and takes in and outputs the arithmetic signal Nc at the rising edge of the clock signal CLK. The delay circuit 325 adds a delay to the signal output from the arithmetic unit FF 324 (delay time Td in FIG. 4 described later), and outputs the result as the arithmetic signal Ncd. The chopper circuit 326 includes chopper circuits for the number of bits that can represent the maximum value of the arithmetic signal Nc expressed in binary. Each chopper circuit includes an AND circuit And0, And1,..., And inverter circuits Inv0, Inv1,. Connected to each of the operation signal lines NcdL that propagates each bit value of the operation signal Ncd. Each bit value of the arithmetic signal Ncd is input to one input terminal of each of the AND circuits And0, And1,... And each of the inverter circuits Inv0, Inv1,. Each of the inverter circuits Inv0, Inv1,... Is input to the other input terminal of each of the AND circuits And0, And1,. When each bit value of the arithmetic signal Ncd transitions from low level to high level, one input terminal of each of the AND circuits And0, And1,... Transitions from low level to high level, and the other input terminal Each of the inverter circuits Inv0, Inv1,... Is inverted with a delay, and transits from a high level to a low level. Therefore, during each delay time of the inverter circuits Inv0, Inv1,..., Both input terminals of the AND circuits And0, And1,. As a result, of the arithmetic signal Ncd, the signal that transitions from the low level to the high level controls the high-level pulse having the pulse width of each delay time of the inverter circuits Inv0, Inv1,... From the transition timing. Output as signal Daci. The time of this pulse width is a pulse time Ta described later in FIG.

  In the coil current calculator 32, the difference signals Shl and Slh are taken in the clock cycle of the clock signal CLK, the difference between the difference signals Shl and S1h is calculated as the difference signal Ud by the subtractor 322, and further calculated by the calculator 323. The signal Nc is calculated. In the subsequent second clock cycle, a delay time Td is added to the calculation signal Nc by the delay circuit 325, and then the control signal Daci of the pulse signal is output from the chopper circuit 326, which is decoded by the DAC 33 described later. The coil current Daco is output.

  Here, the first clock cycle corresponds to the clock cycle in which the data signals D1 (0) to D1 (n) are taken into the data FF 21 and output as the data signals D0 (0) to D0 (n). Is a clock cycle in which data signals D0 (0) to D0 (n) are taken into the output stage FF22 and output as data signals D (0) to D (n). When the data signals D (0) to D (n) are output from the output stage FF22 in the second clock cycle, the data signals D (0) to D (n) are transmitted through the buffer circuits 40 to 4n. It is output as DQ (0) to DQ (n).

  Therefore, in order to match the current assist operation to the timing at which the data signals DQ (0) to DQ (n) are output and the voltage level transitions, the data signals DQ (0) to DQ (n) are set in the second clock cycle. The signal propagation delay time of the buffer circuits 40 to 4n until the signal is output corresponds to the time until the signal output from the calculator FF 324 of the coil current calculator 32 is output as the coil current Daco. is necessary. Therefore, a delay time Td is given by the delay circuit 325. The delay time Td is set as a time obtained by subtracting the delay time due to the DAC 33 from the signal propagation delay time due to the buffer circuits 40 to 4n.

  FIG. 3 is a block diagram of the DAC 33 according to the embodiment. The DAC 33 includes constant current sources I0 to I3, switches SW0 to SW3, and a decoder 330. The constant current sources I0 to I3 are interposed between the power supply voltage Vde and the switches SW0 to SW3. The DAC 33 is connected to the signal line DaciL as an input line and to the current line DacoL as an output line. Current line DacoL includes current line Daco0L connected to constant current sources I0 to I3 via switches SW0 to SW3, and current line Daco1L connected to the ground voltage. The decoder 330 decodes the control signal Daci propagating through the signal line DaciL, and outputs coil current setting signals dac0 to dac3 to the switches SW0 to SW3. As a result, any one or any combination of the switches SW0 to SW3 is selected and made conductive.

  The constant current sources I0 to I3 supply the coil current Daco to the control coil 51 from the power supply voltage Vde via the switches SW0 to SW3 and the current line Daco0L. The current capability is set so as to increase with a power of 2 from the constant current source I0. The switches SW0 to SW3 are controlled to be conductive / non-conductive by the coil current setting signals dac0 to dac3, and the constant current is set so that the amount of current output from the DAC 33 increases as the coil current setting signals dac0 to dac3 move upward. Sources I0 through I3 are selected. A coil current Daco having a current value corresponding to the control signal Daci can be supplied to the control coil 51.

  Next, the SSO noise generated at the time of the read operation of the data signals DQ (0) to DQ (n) of the output circuit 1 according to the embodiment and the voltage level transition of the read data signals DQ (0) to DQ (n) is generated. In order to suppress this, the timing with the current assist operation in which a current is additionally supplied to the signal lines DQL (0) to DQL (n) will be described. FIG. 4 illustrates a case where the 4-bit data signals D2 (0) to D2 (3) propagate to the output circuit 1. In synchronization with the rising edge of the clock signal CLK, the data FF 20 takes in the data signals D2 (0) to D2 (3) and outputs them as data signals D1 (0) to D1 (3). At the same time, the data FF21 takes in the data signals D1 (0) to D1 (3) before switching and outputs them as data signals D0 (0) to D0 (3).

  In synchronization with the rising edge of the clock signal CLK in the clock cycle (1), (1111) in which all bits are at a high level is output as the data pattern of the data signals D1 (0) to D1 (3), and the data signal D0 (0 ) To D0 (3), all bits are set to low level (0000). The data signals D1 (0) to D1 (3) and the data signals D0 (0) to D0 (3) are input to the difference detectors 30 and 31 of the coil current control circuit 3, and the difference signals Sh1 and Slh are calculated. . At this time, since the data signals D1 (0) to D1 (3) are (1111) and the data signals D0 (0) to D0 (3) are (0000), the calculated difference signal Sh1 indicates 0, and the difference The signal Slh indicates 4.

  Next, in synchronization with the rising edge of the clock signal CLK in the clock cycle (2), the difference signals Shl and Slh are taken into the coil current calculator 32, and the control signal Daci is calculated. Here, for example, the value of the threshold signal T that determines the difference value at the boundary of whether to output the control signal Daci for the difference between the difference signal Shl and the difference signal S1h is set to 3. Further, the value of the gain signal G is set to 1 for adjusting the value of the output control signal Daci. At this time, since the difference between the difference signal Shl and the difference signal Slh is 4, it exceeds the value 3 of the threshold signal T, and the current assist operation is performed. Since the value of the gain signal G is 1, the basic value 1 is output as the calculation signal Nc.

  Next, in synchronization with the rise of the clock signal CLK in the clock cycle (3), the calculation signal Nc (value is 1) is output from the calculator FF 324 of the coil current calculator 32, and the control signal Daci is a positive value of 1 A pulse signal is output. The delay time Td is added to the control signal Daci by the delay circuit 325 so that the current assist operation is performed at the timing of suppressing the SSO noise due to the voltage level transition of the data signals DQ (0) to DQ (n). The delay period Td is a time obtained by subtracting the delay time by the DAC 33 from the signal propagation delay time of the buffer circuits 40 to 4n. Further, the pulse time Ta set by the chopper circuit 326 of the coil current calculator 32 is the duration time of the current assist operation. During this time, SSO noise due to voltage drop of the power supply voltage Vde is suppressed.

  In synchronization with the rise of the clock signal CLK in the clock cycle (3), (0011) is output as the data pattern of the data signals D1 (0) to D1 (3), and the data signals D0 (0) to D0 (3 (0000) is output as the data pattern. At this time, the calculated difference signal Shl indicates 0, and the difference signal Slh indicates 2.

  Also in this case, simultaneously with the rise of the clock signal CLK in the clock cycle (4), the difference signals Shl and Slh are taken into the coil current calculator 32, and the control signal Daci is calculated. Here, since the difference between the difference signal Shl and the difference signal Slh is 2, it does not reach the value 3 of the threshold signal T, and the calculation signal Nc output from the coil current calculator 32 becomes 0, and the current assist operation. Is not done.

  5 is a circuit diagram showing another example of the DAC 33. The DAC 33a shown in FIG. Similarly to the DAC 33, the DAC 33a includes a decoder 330a, and a signal line DaciL is connected as an input line. The current line DacoL includes a current line Daco0L connected to the constant current sources I0a to I3a via the switches SW0a to SW3a, and a switch. And a current line Daco1L connected to the constant current sources I0b to I3b via SW0b to SW3b. The current line Daco0L and the current line Daco1L are connected to the ground voltage via the switches SWb and SWa, respectively. The decoder 330a decodes the control signal Daci propagated through the signal line DaciL, and outputs the coil current setting signals dac0a to dac3a or the coil current setting signals dac0b to dac3b to one of the switches SW0a to SW3a or the switches SW0b to SW3b. . As a result, any one or any combination of the switches SW0a to SW3a, or any one or any combination of the switches SW0b to SW3b is selected and made conductive. When any of the switches SW0a to SW3a is selected, the switch SWa is selected by the coil current setting signal daca, and when any of the switches SW0b to SW3b is selected, the coil current setting signal dabc is used. Switch SWb is selected.

  The constant current sources I0a to I3a supply the coil current Daco from the power supply voltage Vde via the switches SW0a to SW3a and the current line Daco0L. The current capability of the constant current sources I0a to I3a is set so as to increase by weighting in units of powers of 2 from the constant current source I0a. The switches SW0a to SW3a are controlled to be conductive / non-conductive by the coil current setting signals dac0a to dac3a, and the constant current is set so that the amount of current output from the DAC 33a increases as the coil current setting signals dac0a to dac3a move upward. Sources I0a through I3a are selected. When one of the constant current sources I0a to I3a is selected, the switch SWa connected to the current line Daco1L is turned on by the coil current setting signal daca, and the current line Daco1L is connected to the ground voltage. The coil current Daco supplied from any of the constant current sources I0a to I3a flows from the current line Daco0L to the control coil 51, returns to the current line Daco1L, and flows to the ground voltage.

  Similarly to the constant current sources I0a to I3a, the constant current sources I0b to I3b supply the coil current Daco from the power supply voltage Vde via the switches SW0b to SW3b and the current line Daco1L. The current capability of the constant current sources I0b to I3b is set so as to increase by weighting in units of powers of 2 from the constant current source I0b. The switches SW0b to SW3b are controlled to be conductive / non-conductive by the coil current setting signals dac0b to dac3b. As the coil current setting signals dac0b to dac3b move upward, the constant current is increased so that the amount of current output from the DAC 33a increases. Sources I0b through I3b are selected. When one of the constant current sources I0b to I3b is selected, the switch SWb connected to the current line Daco0L is turned on by the coil current setting signal dacb, and the current line Daco0L is connected to the ground voltage. The coil current Daco supplied from any of the constant current sources I0b to I3b flows from the current line Daco1L to the control coil 51, returns to the current line Daco0L, and flows to the ground voltage.

  Thereby, by decoding the control signal Daci, the direction of the coil current Daco flowing through the control coil 51 can be controlled depending on whether the switches SW0a to SW3a are selected or the switches SW0b to SW3b are selected. In addition to the magnitude of the current value corresponding to the control signal Daci, the coil current Daco whose direction is controlled can be supplied to the control coil 51. The control coil 51 can control the magnitude and direction of the assist current induced in the signal lines DQL (0) to DQL (n).

  A coil current calculator 32 a shown in FIG. 6 is a circuit diagram showing another example of the coil current calculator 32. Similar to the coil current calculator 32, the coil current calculator 32 a includes a subtracter 322, a calculator 323, and a calculator FF 324. Unlike the coil current calculator 32, the coil current calculator 32a does not include the differential detector FFs 320 and 321, and the subtractor 322 is directly connected to the signal line ShlL and the signal line SlhL. Further, the delay circuit 325 and the chopper circuit 326 are not provided.

  The subtracter 322 receives the difference signals Shl and Slh, which are bit string signals in which the numerical values added by the adders 303 and 313 are expressed in binary, and outputs the difference as a difference signal Ud to the signal line UdL. . The arithmetic unit 323 is connected to the signal line UdL, the gain signal line GL, and the threshold signal line TL as input lines, and is connected to the arithmetic signal line NcL as output lines. The arithmetic unit FF 324 is connected to the arithmetic signal line NcL and the clock line CLKL as input lines, takes in the arithmetic signal Nc at the rising edge of the clock signal CLK, and controls the output signal of the arithmetic unit FF 324 via the signal line DaciL. Output as Daci.

  Since the coil current calculator 32a does not include the differential detector FFs 320 and 321, the data signals D0 (0) to D0 (n) and the data signal D1 (0) in the clock cycle (1) shown in FIG. The process from the switching of .about.D1 (n) to the output of the calculation signal Nc is performed. The coil current calculator 32 is a process performed in the clock cycle (1) and the clock cycle (2). As a result, in the coil current calculator 32a, the arithmetic signal Nc is taken into the arithmetic unit FF 324 in synchronization with the rising of the clock signal CLK in the clock cycle (2), and output to the decoder 330 described later in FIG. . That is, the decoding process is performed in the clock cycle (2). In this respect, the coil current calculator 32 and the DAC 33 perform the decoding process one clock cycle ahead of the clock cycle (3) in which the data signals DQ (0) to DQ (n) are output. Is called.

  The DAC 33b illustrated in FIG. 7 is a circuit diagram illustrating a second other example of the DAC 33. Similar to the DAC 33, the DAC 33b includes constant current sources I0 to I3, switches SW0 to SW3, and a decoder 330, to which the signal line DaciL and the current line DacoL are connected. Unlike the DAC 33, the DAC 33b includes a DAC flip-flop (hereinafter referred to as a DAC FF) 331, a delay circuit 332, and a chopper circuit 333 between the decoder 330 and the switches SW0 to SW3. The clock line CLKL is connected to the DAC FF 331.

  The signal output from the decoder 330 is captured by the DAC FF 331 at the rising edge of the clock signal CLK and output to the delay circuit 332. The delay circuit 332 adds a delay time Tdd to the signal output from the DAC FF 331 and outputs the result to the chopper circuit 333. The chopper circuit 333 includes pulse generating elements Pu0 to Pu3, and outputs coil current setting signals dac0 to dac3, which are high-level pulse signals, in response to high-level transitions for each bit of the delayed signal.

  Since the constant current sources I0 to I3 included in the DAC 33b are the same as those of the DAC 33, description thereof is omitted here.

  The delay period Tdd provided by the delay circuit 332 in the DAC 33b is a delay time different from the delay period Td provided by the delay circuit 325. Since decoding is performed by the decoder 330 in the clock cycle (2) preceding the clock cycle (3) in which the data signals DQ (0) to DQ (n) are output, it is synchronized with the rising edge of the clock signal CLK in the clock cycle (3). Then, the decoded signal is taken into the DAC FF 331 and output. Therefore, the delay circuit Tdd is a time obtained by subtracting the time for switching between conduction / non-conduction of the switches SW0 to SW3 of the DAC 33b from the signal propagation delay time by the output buffer circuits 40 to 4n. Unlike the delay time Td, the delay time Tdd does not include the decoding time by the decoder 330. As a result, there is no need to adjust the decoding time of the decoder 330 by the delay circuit 332, and it becomes easy to adjust the delay time Tdd, which is the time for adjusting the timing of supplying the assist current.

  FIG. 8 is a diagram showing the effect of the direction of the assist current with respect to different voltage levels of the output data signals DQ (0) to DQ (n).

  The assist current that assists when the voltage level of the data signals DQ (0) to DQ (n) transitions from the low level to the high level is expressed as (L⇒H) in FIG. 8, and changes from the high level to the low level. The assist current that assists in transition is expressed as (H⇒L) in FIG.

  First, (L⇒H) shows the effect of assist current. Among the data signals DQ (0) to DQ (n), in the data signal line that is maintained at the high level without the voltage level transition, the held high level voltage level is (L⇒H) by the assist current. It will not be adversely affected. In the data signal line transitioning from the high level to the low level, the voltage level transition direction is affected by the direction in which the transition is prevented by the (L → H) assist current, so that the delay increases. In the data signal line that transitions from the low level to the high level, the voltage level transition direction is assisted by the (L → H) assist current, so the delay decreases. In the data signal line in which the voltage level does not change and is maintained at the low level, the low level voltage level to be held is affected by the increase of the voltage level by the (L → H) assist current, and thus returns to the low level. This increases the delay. Accordingly, when the direction of the voltage level transition of the data signals DQ (0) to DQ (n) is dominant when the number of bit signals transitioning from the low level to the high level is dominant, the (L⇒H) assist current is effective. Become.

  Next, the effect of (H → L) assist current will be shown. Among the data signals DQ (0) to DQ (n), in the data signal line that maintains the high level, the held high level voltage level has the effect that the voltage level is lowered by the (H⇒L) assist current. Therefore, a period for returning to the high level is required and the delay increases. In the data signal line that transitions from the high level to the low level, the voltage level transition direction is assisted by the (H → L) assist current, so the delay is reduced. In the data signal line in which the voltage level does not change and is maintained at the low level, the held low level voltage level is not adversely affected by the assist current of (H → L). Therefore, when the direction of the voltage level transition of the data signals DQ (0) to DQ (n) is dominant in the number of bit signals transitioning from the high level to the low level, the (H⇒L) assist current is effective. Become.

  The coil current control circuit 3a shown in FIG. 9 is a circuit diagram including a coil current calculator 32b showing a second alternative example of the coil current calculator 32. Similar to the coil current control circuit 3, the coil current control circuit 3 a includes difference detectors 30 and 31 and a DAC 33. In addition, difference detectors 34 and 35 are provided. Further, a coil current calculator 32 b is provided instead of the coil current calculator 32.

  The difference detector 34 includes (n + 1) NOR circuits 340 to 34n and an adder 343. The signal lines D0L (0) to D0L (n) and the signal lines D1L (0) to D1L (n) are connected to the NOR circuits 340 to 34n for each bit. When the low level bit signal of the data signals D0 (0) to D0 (n) and the corresponding bit signal of the data signals D1 (0) to D1 (n) are low level, the NOR circuits 340 to 34n Outputs a high level. The adder 343 outputs a differential signal Sll indicating the number of bits for which the output signals of the NOR circuits 340 to 34n are at a high level. The difference signal Sll indicates the number of signals that are maintained at low level without voltage level transition. The difference signal Sll is output to the coil current calculator 32b via the signal line SllL. The difference detector 35 includes (n + 1) AND circuits 350 to 35 n and an adder 353. The signal lines D0L (0) to D0L (n) and the signal lines D1L (0) to D1L (n) are connected to each of the AND circuits 350 to 35n for each bit. When the high-level bit signal among the data signals D0 (0) to D0 (n) and the corresponding bit signal among the data signals D1 (0) to D1 (n) are high level, the AND circuits 350 to 35n Outputs a high level. The adder 353 outputs a difference signal Shh indicating the number of bits whose output signals of the AND circuits 350 to 35n are at a high level. The difference signal Shh indicates the number of signals that are maintained at a high level without a voltage level transition. The difference signal Shh is output to the coil current calculator 32b via the signal line ShhL.

  Similar to the coil current calculator 32, the coil current calculator 32 b includes differential detector FFs 320 and 321, a calculator FF 324, a delay circuit 325, and a chopper circuit 326. In addition, FFs 327 and 328 for difference detectors, adders 329a and 329b, subtracters 322a and 322b, and an arithmetic unit 323a are provided. As input lines, signal lines ShlL, SlhL, SllL, ShhL, a clock line CLKL, a gain signal line GL, and a threshold signal line TL are connected. A signal line DaciL is connected as an output line.

  The difference detector FF 327 is connected to the signal line SLLL and the clock line CLKL, and takes in the difference signal Sll that is a bit string signal in which the numerical value added by the adder 343 is expressed in binary at the rising edge of the clock signal CLK. To output. The differential detector FF 328 is connected to the signal line ShhL and the clock line CLKL, and takes in the differential signal Shh which is a bit string signal in which the numerical value added by the adder 353 is expressed in binary at the rising edge of the clock signal CLK. To output. When the difference signals Shl and Sll are input to the difference detector FFs 320 and 327, the adder 329a adds the difference signal Shl and the difference signal Sll, and outputs a signal corresponding to the addition result. When the difference signals Slh and Shh are taken into the difference detector FFs 321 and 328, the adder 329b adds the difference signal Slh and the difference signal Shh, and outputs a signal corresponding to the addition result.

  The subtractor 322a outputs the difference obtained by subtracting the addition result of the difference signal Slh and the difference signal Shh by the adder 329b from the difference signal Shl captured by the difference detector FF 320 to the signal line UdaL as the difference signal Uda. The difference signal Uda is a transition of the number of signals that transition from the low level to the high level and the transition of the voltage level from the number of signals that transition from the high level to the low level in the transition of the data signals DQ (0) to DQ (n). It is the number obtained by subtracting the total from the number of signals that are maintained at a high level. The subtractor 322b outputs the difference obtained by subtracting the addition result of the difference signal Shl and the difference signal Sll by the adder 329a from the difference signal Slh taken into the difference detector FF 321 as a difference signal Udb to the signal line UdbL. The difference signal Udb is based on the number of bit signals that transition from a low level to a high level, the number of bit signals that transition from a high level to a low level, and the number of bit signals that maintain a low level without a voltage level transition. The number obtained by subtracting the sum of and.

  The computing unit 323a is connected to the signal lines UdaL, UdbL, the gain signal line GL, and the threshold signal line TL as input lines, and is connected to the arithmetic signal line NcL as output lines. The value indicated by the input difference signal Uda and the value indicated by the difference signal Udb are compared to determine which value is greater. When the signal having a large value exceeds the value indicated by the threshold signal T, the calculation signal Nc whose value is adjusted by the gain signal G is calculated and output to the calculator FF 324 via the calculation signal line NcL. The calculation signal Nc also includes a flag signal indicating the direction of the assist current obtained by comparing the difference signal Uda and the difference signal Udb. In addition, when both the values indicated by the difference signals Uda and Udb are equal, or when both values indicate negative values, or the value indicated by the signal having a larger value among the difference signal Uda and the difference signal Udb is the threshold signal T For example, when the value is lower than the value indicated, the calculation is not performed and the calculation signal Nc is not output. That is, if the direction of the voltage level transition of the data signals DQ (0) to DQ (n) is not dominant from the high level to the low level or from the low level to the high level, the assist current is not output. It is a setting to do. Alternatively, even if the direction of voltage level transition is dominant in either direction, the assist current is not output even when the threshold value is not reached. Alternatively, when both the values indicated by the difference signals Uda and Udb are equal, the assist current can be caused to flow in a predetermined current direction.

  The arithmetic unit FF 324, the delay circuit 325, and the chopper circuit 326 of the coil current calculator 32b are the same as the coil current calculator 32, and thus the description thereof is omitted here.

  When the data signals DQ (0) to DQ (n) are output, a current required for voltage level transition flows through the voltage line VdeL or the ground line VgL having a parasitic inductance component and the output buffer 4. The parasitic inductance of the voltage line VdeL is defined as an inductance Lv, and the parasitic inductance of the ground line VgL is defined as an inductance Lg. The power supply voltage applied to the output buffer 4 at the time of voltage level transition is Vio.

  In the transition of the data signals DQ (0) to DQ (n), the number of signals that transition from the low level to the high level is the number Nlh. Let Ih be the current flowing through one of the signal lines DQL (0) to DQL (n) when the voltage level transitions from the low level to the high level. The amount of current change per hour of the current Ih is dIh / dt. The counter electromotive force generated in the inductance Lv is a value obtained by multiplying the number of signals transitioning from a low level to a high level, a current change amount generated in one signal line, and the inductance Lv. Also, the number of signals that transition from the high level to the low level in the transition of the data signals DQ (0) to DQ (n) is the number Nhl. The current flowing through one signal line DQL (0) to DQL (n) when the voltage level changes from the high level to the low level is defined as Il. The amount of current change per hour of Il is dIl / dt. The counter electromotive force generated in the inductance Lg is a value obtained by multiplying the number of signals transitioning from a high level to a low level, a current change amount generated in one signal line, and the inductance Lg.

In this case, the voltage Vio is based on the difference between the power supply voltage Vde and the ground voltage, and the counter electromotive force generated in the inductance Lv (Nlh · Lv · dIh / dt) and the counter electromotive force generated in the inductance Lg (Nhl·Lg · dIl / It is a value obtained by subtracting dt). The voltage Vio can be expressed by the following equation.
Vio = Vde−Nlh · Lv · dIh / dt−Nhl·Lg · dIl / dt
Therefore, at the time of transition to the voltage level of the data signals DQ (0) to DQ (n), the power supply voltage applied to the output buffer 4 decreases from the voltage Vde to the voltage Vio.

  The current assist circuit 5 induces an assist current in the signal lines DQL (0) to DQL (n) at the time of voltage level transition by causing a current to flow through the control coil 51, thereby transiently changing the power supply voltage of the output buffer 4. Works to mitigate the decrease. A current induced in each of the signal lines DQL (0) to DQL (n) is defined as an assist current Ia. Of the data signals DQ (0) to DQ (n), the number of data signals that are maintained at a high level without voltage level transition is the number Nhh, and the number of data signals that are maintained at a low level is the number Nll. To do.

  When the assist current Ia is the (L → H) assist current in FIG. 8, the current Ih flowing through the inductance Lv through the signal line that transitions from the low level to the high level is reduced by the assist current Ia. At this time, the current flowing through the inductance Lv is Ih-Ia. (L⇒H) The decrease ΔIh of the current flowing through the inductance Lv due to the assist current is a value obtained by multiplying the number Nlh and the assist current Ia (ΔIh = Nlh · Ia).

  On the other hand, the assist current Ia which is the (L⇒H) assist current is changed to a current Il flowing in the current Il flowing in the inductance Lg via the signal line transitioning from the high level to the low level and the signal line maintained at the low level. Is added. The current Il flowing through the inductance Lg increases by the assist current Ia. At this time, the current flowing through the inductance Lg is Il + Ia. (L⇒H) The increase ΔIl of the current flowing through the inductance Lg due to the assist current is a value obtained by multiplying the sum of the number Nhl and the number Nll by the assist current Ia (ΔIl = (Nhl + Nll) · Ia).

  The power supply voltage of the output buffer 4 when the assist current Ia is induced as the (L → H) assist current in the signal lines DQL (0) to DQL (n) is defined as voltage Viaa. (L => H) The effect of reducing the back electromotive force generated in the inductance Lv by the assist current is due to the decrease ΔIh (= Nlh · Ia) of the current flowing through the inductance Lv. This is the counter-electromotive force cancellation amount (Nlh · Lv · dIa / dt) generated in the inductance Lv related to the current decrease ΔIh.

  Conversely, the effect of increasing the back electromotive force generated in the inductance Lg due to the (L⇒H) assist current is due to the increase ΔIl (= (Nhl + Nll) · Ia) of the current flowing through the inductance Lg. This is an increase in the back electromotive force generated in the inductance Lg ((Nhl + Nll) · Lg · dIa / dt).

Therefore, the voltage Viaa can be expressed by the following equation: Viaa = Vio + Nlh · Lv · dIa / dt− (Nhl + Nll) · Lg · dIa / dt

  When the value obtained by multiplying the number Nlh by the inductance Lv is equal to or larger than the value obtained by multiplying the sum of the number Nhl and the number Nll by the inductance Lg, the counter electromotive force generated in the inductance Lv by the assist current Ia is offset by the inductance Lg. It exceeds the increase in the back electromotive force that occurs. That is, the assist effect works effectively, and the decrease in the power supply voltage of the output buffer 4 at the time of the voltage level transition of the data signals DQ (0) to DQ (n) is improved. Here, since the inductance Lv and the inductance Lg can be assumed to be substantially the same value, the number of signals that transition from the low level to the high level (number Nlh) is the number of signals that transition from the high level to the low level (number Nlh). The case where the number (Nhl) and the number of signals maintained at the low level (number Nll) are greater than the sum (L⇒H) is when the assist current is effective.

  On the other hand, when the assist current Ia is the (H → L) assist current in FIG. 8, the current Il flowing through the inductance Lg via the signal line transitioning from the high level to the low level becomes smaller by the assist current Ia. At this time, the current flowing through the inductance Lg is Il-Ia. (H⇒L) The decrease ΔIl of the current flowing through the inductance Lg due to the assist current is a value obtained by multiplying the number Nhl and the assist current Ia (ΔIl = −Nhl · Ia).

  Conversely, the assist current Ia, which is an (H → L) assist current, is added to the current Ih flowing through the inductance Lv via the signal line that transitions from the low level to the high level and the signal line that is maintained at the high level. The current Ih flowing through the inductance Lv increases by the assist current Ia. At this time, the current flowing through the inductance Lv is Ih + Ia. (H⇒L) The increase ΔIh of the current flowing through the inductance Lv due to the assist current is a value obtained by multiplying the sum of the number Nlh and the number Nhh and the assist current Ia (ΔIh = (Nlh + Nhh) · Ia).

  The power supply voltage of the output buffer 4 when the assist current Ia is induced as the (H → L) assist current in the signal lines DQL (0) to DQL (n) is defined as voltage Viaa. (H⇒L) The effect of reducing the back electromotive force generated in the inductance Lg due to the assist current is due to the decrease ΔIl (= −Nhl · Ia) of the current flowing through the inductance Lg. This is the counter-electromotive force cancellation amount (Nhl·Lg · dIa / dt) generated in the inductance Lg related to the current decrease ΔI1.

  On the contrary, the effect of increasing the back electromotive force generated in the inductance Lv by the (H⇒L) assist current is due to the increase ΔIh (= (Nlh + Nhh) · Ia) of the current flowing through the inductance Lv. This is an increase in the back electromotive force generated in the inductance Lv ((Nlh + Nhh) · Lv · dIa / dt).

Therefore, the voltage Viaa can be expressed by the following formula: Viaa = Vio + Nhl·Lg · dIa / dt− (Nlh + Nhh) · Lv · dIa / dt

  When the value obtained by multiplying the number Nhl by the inductance Lg is equal to or greater than the value obtained by multiplying the sum of the number Nlh and the number Nhh by the inductance Lv, the counter-electromotive force cancellation generated in the inductance Lg by the assist current Ia is the inductance Lv. It exceeds the increase in the back electromotive force that occurs. That is, the assist effect works effectively, and the decrease in the power supply voltage of the output buffer 4 at the time of the voltage level transition of the data signals DQ (0) to DQ (n) is improved. Here, since the inductance Lv and the inductance Lg can be assumed to be substantially equal values, the number of signals that transition from the high level to the low level (number Nhl) is the number of signals that transition from the low level to the high level (number Nhl). The case where the assist current is effective (H⇒L) is greater than the sum of the number Nlh) and the number of signals maintained at the high level (number Nhh).

  FIG. 10 is a plan view of a semiconductor device (mounting substrate) 10 including the output circuit 1 according to the embodiment. The semiconductor device (mounting substrate) 10 includes a bare chip 11 and a chip substrate 12, and the bare chip 11 is mounted on the chip substrate 12. FIG. 11 is a cross-sectional view of the semiconductor device (mounting substrate) 10 according to the embodiment. 2 is a cross-sectional view of a portion of a control coil 51 in a semiconductor device (mounting substrate) 10. FIG.

  In the semiconductor device (mounting substrate) 10, the output circuit 1 that outputs the data signals DQ (0) to DQ (n) is disposed across the bare chip 11 and the chip substrate 12. The output control circuit 2, the coil current control circuit 3, and the output buffer 4 are disposed on the bare chip 11, and the current assist circuit 5 is disposed across the bare chip 11 and the chip substrate 12. The chip substrate 12 is a multilayer wiring substrate having two wiring layers of an upper wiring layer 120 and a lower wiring layer 122 with an interlayer insulating layer 121 made of a general-purpose resin such as glass epoxy resin in between. In the upper wiring layer 120 and the lower wiring layer 122, a wiring pattern is formed by an etching process or the like in order to provide a conductive path. The bare chip 11 is housed in a recess from which a part of the upper wiring layer 120 and the interlayer insulating layer 121 is removed. The magnetic core 50 is disposed between the upper wiring layer 120 and the lower wiring layer 122. The material of the magnetic core 50 is generally a magnetic core material such as iron or ferrite. In addition, the same material as that used for the wiring pattern such as the upper wiring layer 120 and the lower wiring layer 122 can also be used. The magnetic core 50 is embedded and formed when the interlayer insulating layer 121 is formed. Alternatively, it is conceivable to mount a component obtained by molding the magnetic core 50 with resin or the like and to mount the bare chip 11. Further, the magnetic core 50 may have a ring shape in addition to a rod shape. If it is ring-shaped, it is possible to suppress leakage of magnetic flux.

  The bare chip 11 has an electrode pad on the upper surface and a through silicon via (hereinafter referred to as TSV) penetrating the bare chip 11 on the lower surface. A current line Daco0L connected to one of the two output terminals of the DAC 33 is connected to a TSV (not shown in FIG. 11) and taken out to the bottom surface of the bare chip 11. Further, it is connected to the lower layer wiring W0 in the lower layer wiring layer 122 through the bump. The lower layer wiring W0 traverses the lower part of the magnetic core 50 and is led directly below the land La1 formed on the upper surface of the chip substrate. The lower layer wiring W0 and the land La1 are connected through a through hole (not shown) that vertically penetrates the interlayer insulating layer 121. As described above, the current line Daco0L and the land La1 in the upper wiring layer 120 are connected by being wired so that the lower wiring W0 crosses the magnetic core 50 below the magnetic core 50. Further, the land La1 is connected by the bonding wire Bw1 between the current line Daco0L and the pad P1 adjacent to the junction between the through hole (not shown). The bonding wire Bw1 is wired so as to cross over the magnetic core 50.

  The pad P1 is connected to the lower layer wiring W1 adjacent to the lower layer wiring W0 through the TSVTs1 and the bump B1. The lower layer wiring W1 is connected to the land La2 through a through hole Th2 that vertically penetrates the interlayer insulating layer 121. The land La2 is connected to the pad adjacent to the pad P1 with a bonding wire. The bonding wire is wired so as to cross over the magnetic core 50.

  Similarly, the wiring is connected in a coil shape so as to traverse the lower and upper portions of the magnetic core 50 in order to reach the pad Pnc via the land Lanc, and the control coil 51 is formed. The pad Pnc is connected to the DAC 33 via a current line Daco1L connected to the other of the two output terminals of the DAC 33.

  The signal line DQL (0) connected to the output buffer circuit 40 is connected to the pad PDQ0. The bonding wire BDQ0 connects the pad PDQ0 and the land LaDQ0 so as to cross over the magnetic core 50. The voltage line VdeL connected to the output buffer circuit 40 is connected to the lower layer wiring Wv0 crossing below the magnetic core 50 through the TSV and the bump. The lower layer wiring Wv0 crosses the magnetic core 50 and connects the voltage line VdeL and the land Lav0 through a through hole penetrating the interlayer insulating layer 121 vertically. Similarly, the ground line VgL connected to the output buffer circuit 40 is connected to the lower layer wiring Wg0 crossing the lower side of the magnetic core 50 through the TSV and the bump. The lower layer wiring Wg0 connects the ground line VgL and the land Lag0 through a through hole that passes through the lower part of the magnetic core 50 and penetrates the interlayer insulating layer 121 vertically. Thereby, the bonding wire BDQ0 and the lower layer wiring Wv0 or the lower layer wiring Wg0 form a coil surrounding the magnetic core 50. The control coil 51 is magnetically coupled to the coil of the bonding wire BDQ0 and the lower layer wiring Wv0 or the lower layer wiring Wg0 through the magnetic core 50. The power supply voltage Vde and the ground voltage are branched into lands Lav0 to Lavn and lands Lag0 to Lagn. Further, the power supply voltage Vde and the ground voltage may be branched into the bare chip 11 after being input to the bare chip 11 via the lower layer wirings Wv0 and Wg0.

  Here, the chip substrate 12 is not limited to the two layers of the upper wiring layer 120 and the lower wiring layer 122. When the wiring layer is a single layer, the magnetic core 50 is mounted on the chip substrate 12 as a component. Since the wiring layer is a single layer, there is no through-hole penetrating the interlayer insulating layer vertically. In this case, the portion carried by the through hole in the wiring crossing the magnetic core 50 is carried by the bonding wire. A control coil 51 wound around the magnetic core 50 is formed by the wiring crossing the lower side of the magnetic core 50 and the bonding wire crossing the upper side of the magnetic core 50.

  Further, the current assist circuit 5 may be arranged on the semiconductor chip 11. In this case, the magnetic core 50 and the control coil 51 are formed using the multilayer wiring of the semiconductor chip 11. The magnetic core 50 is formed by an intermediate wiring layer in the intermediate layer of the multilayer wiring. Further, if there is a manufacturing process such as embedding a magnetic material in the semiconductor chip 11, it can be used. The control coil 51 is formed by upper and lower wiring layers and via contacts surrounding the magnetic core 50 formed by the intermediate wiring layer.

  In addition, the control coil 51 may be formed by an upper layer wiring, a lower layer wiring, or a through hole surrounding the magnetic core 50 embedded in the chip substrate 12.

  A semiconductor device (mounting substrate) 10a shown in FIG. 12 is a plan view showing another example of the semiconductor device (mounting substrate). The semiconductor device (mounting board) 10a includes a coil component 53, a semiconductor package 11a, and a printed board 12a. FIG. 13 is a view of the semiconductor device (mounting substrate) 10a as seen from the outer lead Lev0 side described later.

  In the semiconductor device (mounting board) 10a, the output circuit 1a that outputs the data signals DQ (0) to DQ (n) is disposed across the semiconductor package 11a and the printed board 12a. The output control circuit 2, the coil current control circuit 3, and the output buffer 4 are disposed on the semiconductor package 11a, and the current assist circuit 5a is disposed on the printed board 12a. The printed circuit board 12a includes a wiring layer 120a on a substrate surface made of a general-purpose resin such as a glass epoxy resin. In the wiring layer 120a, a wiring pattern is formed by an etching process or the like in order to provide a conductive path.

  The semiconductor package 11a is formed by molding a bare chip, and the outer leads Lev0 to Levn, LeDQ0 to LeDQn, Leg0 to Legn, Le0, which are external connection terminals on the side surface for electrically connecting the bare chip and the outside, and Le1 is connected. The semiconductor package 11a is mounted on the surface of the printed circuit board 12a.

  The coil component 53 is a component in which a control coil 51a formed by winding a copper wire around one end of a magnetic core 50a and a magnetic core 50a serving as a core material are combined and molded with a resin or the like. The magnetic core 50a is not particularly limited as long as it is a magnetic material, and composite materials such as iron and ferrite can be applied. The DAC 33 arranged in the semiconductor package 11a is connected to one of the terminals of the coil component 53 through the current line Daco0L and the outer lead Le0, and is connected to the other of the terminals of the coil component 53 through the current line Daco1L and the outer lead Le1. Is done.

  The voltage line VdeL, the signal line DQL (0), and the ground line VgL connected to the output buffer circuit 40 are connected to the outer leads Lev0, LeDQ0, and Leg0 of the semiconductor package 11a, respectively. The outer lead Lev0 and the outer lead LeDQ0 have different lead bending positions (see FIG. 13). The outer lead Lev0 bends in the direction of the surface of the printed circuit board 12a before the magnetic core 50a and is connected to the wiring Wv0a which is a wiring pattern crossing the lower side of the magnetic core 50a. The outer lead LeDQ0 is bent toward the surface of the printed circuit board 12a at the point where it crosses over the magnetic core 50a, and is connected to the wiring WDQ0a that is the wiring pattern of the printed circuit board 12a. The outer lead Leg0 is the same as the outer lead Lev0. It bends in the direction of the surface of the printed circuit board 12a before the magnetic core 50a and is connected to the wiring Wg0a which is a wiring pattern crossing the lower side of the magnetic core 50a. Thus, the outer lead LeDQ0 and the wiring Wv0a or the wiring Wg0a form a coil surrounding the magnetic core 50a. The control coil 51a is magnetically coupled to the coil of the outer lead LeDQ0 and the wiring Wv0a or the wiring Wg0a via the magnetic core 50a. The power supply voltage Vde and the ground voltage are branched to the wirings Wv0a to Wvna and the wirings Wg0a to Wgna. Further, the power supply voltage Vde and the ground voltage may be branched into the semiconductor package 11a after being input to the semiconductor package 11a via the wiring Wv0a, the outer lead Lev0, the wiring Wg0a, and the outer lead Leg0. In this case, it is not necessary to prepare the outer leads for the power supply voltage Vde and the ground voltage for each of the output buffer circuits 40 to 4n, and the outer leads of the semiconductor package 11a can be reduced.

Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, the threshold signal T and the gain signal G may be given a plurality of values. In this case, the threshold signal T is set in multiple stages. The gain signal G is set so that the gain corresponds to the value indicated by each threshold value T. For example, when four values are provided for the threshold value T, the threshold values T0, T1, T2, and T3 are set in descending order of the threshold value T, and the gain signals G corresponding to these are set as the gain signals G0, G1, G2, G3. When the value indicated by the difference signal Ud exceeds the threshold value T0, the calculation signal Nc whose value is adjusted by the gain signal G0 corresponding to the threshold value T0 is calculated. When the threshold value T1 is exceeded and below the threshold value T0, the calculation signal Nc whose value is adjusted by the gain signal G1 corresponding to the threshold value T1 is calculated. The gain signal G2 is applied when it exceeds the threshold value T2 and falls below the threshold value T1, and the gain signal G3 is applied when it exceeds the threshold value T3 and falls below the threshold value T2. Similar to the gain signal G1, the calculation signal Nc whose value is adjusted by the gain signal G2 or G3 is calculated. When the value is lower than the threshold value T3, the calculation is not performed and the calculation signal Nc is not output.
Further, the constant current sources I0 to I3 may be interposed between the ground voltage and the switches SW0 to SW3. In this case, the coil current Daco is discharged from the control coil 51 to the ground voltage via the ground voltage, the constant current sources I0 to I3, the switches SW1 to SW3, and the current line Daco0L. In this case, the current line Daco1L is connected to the power supply voltage Vde.

  Here, the coil current control circuit 3 is an example of a control unit, the output circuit 1 is an example of an electronic circuit, the data FF 21 is an example of a flip-flop circuit, the AND circuits 300 to 30n are examples of an HL detection unit, and the AND circuits 310 to 31n are An example of the LH detection unit, the NOR circuits 340 to 34n are examples of the LL detection unit, the AND circuits 350 to 35n are examples of the HH detection unit, the adder 303 is an example of the HL adder, and an example of the LH adder of the adder 313. is there.

DESCRIPTION OF SYMBOLS 1 Output circuit 2 Output control circuit 3, 3a Coil current control circuit 4 Output buffer 5 Current assist circuit 20, 21 Data FF
22 Output stage FF
30, 31, 34, 35 Difference detector 32, 32a, 32b Coil current calculator 33, 33a, 33b DAC
300-30n, 310-31n AND circuit 303, 313 Adder

Claims (7)

An output buffer circuit;
An output line through which an output signal output from the output buffer circuit propagates;
At least one of a power line or a ground line for supplying power to the output buffer circuit;
A magnetic core surrounded by the output line and the power line or the ground line;
A control coil wound around the magnetic core;
A controller that detects a transition of the output signal in advance and controls current supply to the control coil according to a detection result;
An electronic circuit, wherein an assist current for assisting signal transition of the output line is caused to flow by electromagnetic induction from the control coil in accordance with a transition direction of the output signal. Provided with a flip-flop circuit in the path to the output buffer circuit,
The electronic circuit according to claim 1, wherein the control unit includes a detection unit that detects a difference in signal logic level between input and output of the flip-flop circuit. The detector is
An HL detection unit for detecting that a logic level of a signal output from the flip-flop circuit is a high level and a logic level of a signal input to the flip-flop circuit is a low level;
An LH detection unit for detecting that a logic level of a signal output from the flip-flop circuit is a low level and a logic level of a signal input to the flip-flop circuit is a high level;
The control unit includes a calculation unit that controls a direction of current supply to the control coil in response to detection by the HL or LH detection unit,
The arithmetic unit controls the direction of current supply to the control coil to induce the assist current in the output line in the same direction as the sink current according to the detection of the HL detection unit. The electronic circuit according to claim 2, wherein the assist current is induced in the same direction as the source current in response to the detection of the current. A plurality of the output buffer circuits;
The controller is
An HL adder for counting the number of signals detected by the HL detector;
An LH adder for counting the number of signals detected by the LH detector;
A subtractor for calculating a difference value between the count value of the HL adder and the count value of the LH adder;
The electronic circuit according to claim 3, wherein the arithmetic unit supplies a current to the control coil when the difference value calculated by the subtracter exceeds a reference value. The detector is
An HL detection unit for detecting that a logic level of a signal output from the flip-flop circuit is a high level and a logic level of a signal input to the flip-flop circuit is a low level;
An LH detection unit for detecting that a logic level of a signal output from the flip-flop circuit is a low level and a logic level of a signal input to the flip-flop circuit is a high level;
An HH detector that detects that both of the logic levels of the input and output signals from the flip-flop circuit are high;
An LL detector that detects that both of the logic levels of the input and output signals from the flip-flop circuit are at a low level;
A plurality of the output buffer circuits;
The controller is
An HL adder for counting the number of signals detected by the HL detector;
An LH adder for counting the number of signals detected by the LH detector;
An HH adder for counting the number of signals detected by the HH detector;
An LL adder for counting the number of signals detected by the LL detector;
A first subtractor for subtracting the count value of the LH and HH adders from the count value of the HL adder;
A second subtractor for subtracting the count value of the HL and LL adders from the count value of the LH adder;
An arithmetic unit that controls a direction of current supply to the control coil when a subtraction result of the first or second subtracter exceeds a reference value;
The arithmetic unit controls the direction of current supply to the control coil to induce the assist current in the output line in the same direction as the sink current when the subtraction result of the first subtracter exceeds a reference value. 3. The electronic circuit according to claim 2, wherein when the subtraction result of the second subtracter exceeds a reference value, the assist current is induced in the same direction as the source current. The controller is
A delay unit for adjusting a timing at which the assist current starts to flow;
The delay unit includes a time from when a signal input to the flip-flop circuit is output from the output buffer circuit to a time from detection of a logic level of the signal by the control unit to supply of current to the control coil. 6. The electronic circuit according to claim 2, wherein a delay corresponding to the difference time is provided. With magnetic core,
A control coil wound around a portion of the magnetic core;
A semiconductor package containing an electronic circuit comprising: an output buffer circuit; and a control unit that detects a transition of an output signal output from the output buffer circuit in advance and controls current supply to the control coil according to a detection result; With
The semiconductor package is:
An output line lead that propagates an output signal output from the output buffer circuit;
Including at least one of a power line lead or a ground line lead for supplying power to the output buffer circuit;
The output line lead and the power supply line or the ground line lead have different lengths that are led outward, and the magnetic core is mounted between the output line lead and the power supply line or the ground line lead. A featured mounting board.

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