JP5735509B2 - マルウェアがある状態でユーザが検証可能な信頼性のあるパスを得るための方法および機器 - Google Patents
マルウェアがある状態でユーザが検証可能な信頼性のあるパスを得るための方法および機器 Download PDFInfo
- Publication number
- JP5735509B2 JP5735509B2 JP2012523622A JP2012523622A JP5735509B2 JP 5735509 B2 JP5735509 B2 JP 5735509B2 JP 2012523622 A JP2012523622 A JP 2012523622A JP 2012523622 A JP2012523622 A JP 2012523622A JP 5735509 B2 JP5735509 B2 JP 5735509B2
- Authority
- JP
- Japan
- Prior art keywords
- identity
- hypervisor
- policy
- user interface
- driver shim
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/82—Protecting input, output or interconnection devices
- G06F21/85—Protecting input, output or interconnection devices interconnection devices, e.g. bus-connected or in-line devices
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US27344809P | 2009-08-04 | 2009-08-04 | |
| US61/273,448 | 2009-08-04 | ||
| PCT/US2010/040334 WO2011037665A2 (en) | 2009-08-04 | 2010-06-29 | Methods and apparatuses for user-verifiable trusted path in the presence of malware |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013501300A JP2013501300A (ja) | 2013-01-10 |
| JP2013501300A5 JP2013501300A5 (enExample) | 2013-08-15 |
| JP5735509B2 true JP5735509B2 (ja) | 2015-06-17 |
Family
ID=43796427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2012523622A Expired - Fee Related JP5735509B2 (ja) | 2009-08-04 | 2010-06-29 | マルウェアがある状態でユーザが検証可能な信頼性のあるパスを得るための方法および機器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8832778B2 (enExample) |
| EP (1) | EP2462507B1 (enExample) |
| JP (1) | JP5735509B2 (enExample) |
| DK (1) | DK2462507T3 (enExample) |
| WO (1) | WO2011037665A2 (enExample) |
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-
2010
- 2010-06-29 US US13/389,212 patent/US8832778B2/en active Active - Reinstated
- 2010-06-29 EP EP10819183.4A patent/EP2462507B1/en active Active
- 2010-06-29 DK DK10819183.4T patent/DK2462507T3/da active
- 2010-06-29 WO PCT/US2010/040334 patent/WO2011037665A2/en not_active Ceased
- 2010-06-29 JP JP2012523622A patent/JP5735509B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013501300A (ja) | 2013-01-10 |
| US8832778B2 (en) | 2014-09-09 |
| US20120198514A1 (en) | 2012-08-02 |
| DK2462507T3 (da) | 2019-09-23 |
| EP2462507A4 (en) | 2013-04-03 |
| EP2462507B1 (en) | 2019-07-24 |
| WO2011037665A3 (en) | 2011-05-19 |
| WO2011037665A2 (en) | 2011-03-31 |
| EP2462507A2 (en) | 2012-06-13 |
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