JP5732279B2 - Display device - Google Patents

Description

The technical field relates to maintaining confidentiality of information in a display device having a display memory function.

When the display device having the display memory function stops supplying power, it continues to display the contents displayed at that time. Therefore, there arises a problem that the confidentiality of information cannot be maintained.

Patent Document 1 proposes a display device that rewrites content displayed on a memory-type display body into a state where it is difficult to recognize when the remaining battery level is low.

JP 2005-165232 A

However, when the supply of power to the display device having the display memory function suddenly stops, the display contents cannot be rewritten or erased. Note that cases where the supply of power suddenly stops include a case where a battery supplying power is removed from the device, a case where a power plug is removed, and the like.

According to one aspect of the present invention, when a display unit having a memory property, a detection unit that detects power of the first power supply unit, and a detection unit detect that the power of the first power supply unit is smaller than a predetermined value And a control unit that selects power of the second power supply unit as power to be supplied to the display unit and controls to initialize display contents on the display unit.

The confidentiality of information in a display device having a display memory function can be maintained.

(A) The figure which shows the structure of a display apparatus, (B) The flowchart which shows operation | movement of a display apparatus. (A) The figure which shows the structure of a display apparatus, (B) The flowchart which shows operation | movement of a display apparatus. FIG. 6 illustrates a structure of a display device. FIG. 6 illustrates a structure of a display device. FIG. 14 is a diagram showing an example of a circuit configuration applicable to the display unit 14. FIG. 10 is a circuit diagram for evaluating characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. FIG. 13 shows characteristics of a transistor including an oxide semiconductor. 10A and 10B illustrate an example of a method for manufacturing a transistor. The figure which shows an example of the electric power supply part applicable to a display apparatus.

(Embodiment 1)
The structure of the display device will be described with reference to FIG. The display device includes a first power supply unit 10, a second power supply unit 11, a detection unit 12, a control unit 13, and a display unit 14.

As the first power supply unit 10 and the second power supply unit 11, various types of batteries, wireless power supplies, power supply circuits to which power is supplied from an outlet, and the like can be applied.

The detection unit 12 detects the power of the first power supply unit 10 and transmits the result to the control unit 13.

The control unit 13 selects which power of the first power supply unit 10 or the second power supply unit 11 is supplied to the display unit 14 according to the detection result of the detection unit 12. In addition, when it is selected that the power of the second power supply unit 11 is supplied, control is performed so that the display content of the display unit 14 is initialized.

The initialization means a state in which a screen displayed when the display device is activated is displayed, and also means that the display content is deleted and nothing is displayed on the screen.

The display unit 14 displays characters and images with pixels having a memory property.

Next, the operation of this display device will be described with reference to FIG.

First, in step S1, the power of the first power supply unit 10 is detected.

Next, when it is detected in step S2 that the power of the first power supply unit 10 is greater than or equal to a predetermined value, the power of the first power supply unit 10 is selected as the power to be supplied to the display unit 14 in step S3. In step S4, normal driving is performed.

On the other hand, if it is detected in step S2 that the power of the first power supply unit 10 is smaller than the predetermined value, the power of the second power supply unit 11 is selected as the power to be supplied to the display unit 14 in step S5, and step S6. The display contents are initialized with.

The “predetermined value” means a power value necessary for rewriting all the pixels of the display unit 14. Moreover, when the electric power of the 1st electric power supply part 10 is smaller than predetermined value, the case where the electric power of the 1st electric power supply part 10 is zero is also included.

As described above, when the power of the first power supply unit 10 is smaller than a predetermined value, the information on the display unit 14 can be erased by initializing the display content, so that confidentiality can be improved. it can.

(Embodiment 2)
A structure of a display device that is different from the display device described in Embodiment 1 is described.

The display device illustrated in FIG. 2A is different from the display device described in Embodiment 1 in that the first power supply unit 10 and the display unit 14 are connected without the control unit 13 interposed therebetween. .

A flowchart of the operation of this display device will be described with reference to FIG.

First, in step S11, the power of the first power supply unit 10 is detected.

Next, when it is detected in step S12 that the power of the first power supply unit 10 is equal to or greater than a predetermined value, normal driving is performed in step S13.

On the other hand, if it is detected in step S12 that the power of the first power supply unit 10 is smaller than the predetermined value, the power of the second power supply unit 11 is selected as the power to be supplied to the display unit 14 in step S14, and step S15. The display contents are initialized with.

As described above, since it is possible to suppress the power supplied by the first power supply unit 10 from being consumed in the control unit 13, it is possible to reduce power consumption.

Here, with reference to FIGS. 11A to 11C, a power supply unit that can be used for one or both of the first power supply unit 10 and the second power supply unit 11 using a battery. Will be described.

The power supply unit 30 illustrated in FIG. 11A includes a battery pack 31 and a power supply circuit 32. As shown in FIG. 11B, the battery pack 31 includes a battery 33, a protection circuit 34, and the like. Alternatively, as shown in FIG. 11C, the battery pack 31 includes a battery 33, a protection circuit 34, a thermistor 37, a thermal fuse 38, and the like. The power supply circuit includes a switching regulator 35, a voltage regulator 36, and the like.

The battery pack 31 is a container in which a battery and circuits and elements for protecting the battery are collected.

The power supply circuit 32 generates a voltage required for each circuit or each IC using the electric power taken out from the battery pack.

Examples of the battery 33 include a lead storage battery, a nickel / cadmium battery, a nickel metal hydride battery, a lithium secondary battery, and a lithium ion battery.

The protection circuit 34 measures the voltage of the battery 33. Alternatively, the protection circuit 34 measures the voltages of a plurality of cells constituting the battery 33 for each cell. And if the measured voltage is a voltage more than regulation, supply of the voltage or electric current to the battery 33 will be interrupted | blocked, and the overcharge to the battery 33 will be prevented. The protection circuit 34 measures the voltage or current supplied to the battery 33. Alternatively, the protection circuit 34 measures voltage or current supplied to a plurality of cells constituting the battery 33 for each cell. If the measured voltage or current is equal to or higher than a specified voltage, supply of the voltage or current to the battery 33 is interrupted to prevent overcurrent to the battery 33.

The thermistor 37 measures the temperature of the battery 33 or the temperature in the battery pack 31. When the temperature of the battery 33 or the temperature in the battery pack 31 exceeds a specified value by the thermistor 37, the supply of voltage or current to the battery 33 is cut off. Whether to supply voltage or current to the battery 33 may be controlled by the protection circuit 34 or may be controlled by a newly provided control circuit. Further, by providing the control circuit outside the battery pack 31, a general-purpose product can be used as the battery pack 31, and the cost of components can be reduced.

The thermal fuse 38 is connected between the battery 33 and a supply source of voltage or current to the battery 33. Then, when the temperature of the battery 33 or the temperature in the battery pack 31 becomes equal to or higher than a specified value, supply of voltage or current to the battery pack 31 is interrupted. By providing the thermal fuse 38, overcharging and overcurrent to the battery 33 can be prevented even when the protection circuit 34 does not operate normally or when the thermistor 37 does not exhibit normal characteristics. Therefore, the ignition etc. by the heat_generation | fever of the battery 33 can be prevented and safety | security can be improved.

The display device shown in FIG. 3A includes the first battery pack 15 and the second battery pack 16 as power supply means, and does not have a configuration in which a power circuit is provided independently for each battery pack. The circuit 17 is shared. By using the common power supply circuit 17 for the first battery pack 15 and the second battery pack 16, the circuit scale can be reduced. In addition, the number of parts can be reduced, and the manufacturing cost can be reduced.

The display device shown in FIG. 3B includes a first battery 18 and a second battery 19 as power supply means, and shares a protection circuit 20 and a power supply circuit 17. By using the power supply circuit 17 and the protection circuit 20 common to the first battery pack 15 and the second battery pack 16, the circuit scale can be reduced. In addition, the number of parts can be reduced, and the manufacturing cost can be reduced.

The display device shown in FIG. 4 has a configuration in which the power of the second power supply unit 11 is not supplied to components other than the display unit 14, for example, the RF unit 21 and the sensor unit 22. By preventing the power of the second power supply unit 11 from being supplied to components other than the display unit 14, the capacity of the second power supply unit 11 can be reduced.

(Embodiment 3)
An example of a display unit that displays characters and images using pixels having memory characteristics shown in the first and second embodiments will be described.

A pixel having a memory property can include a display element having a memory property. Examples of the display element having a memory property include microcapsules for electrophoretic display.

In addition, the pixel having a memory property can include a display element and a transistor including an oxide semiconductor. In this case, a display element having a memory property or a display element having no memory property can be applied as the display element. As an example of a display element having no memory property, a liquid crystal element or the like can be given.

Based on FIGS. 5A and 5B, an example of a circuit structure which can be applied to a pixel having a memory property including a display element and a transistor including an oxide semiconductor will be described.

FIG. 5A is a schematic view of a display panel including a display element and a transistor including an oxide semiconductor. The display panel 50 includes a pixel portion 51, a gate signal line 52, a gate signal line drive circuit 52D, a data signal line 53, a data signal line drive circuit 53D, a pixel 54, a common electrode 55, a capacitance line 56, and a terminal portion 57. ing.

FIG. 5B is a diagram illustrating the pixel 54 illustrated in FIG. The pixel 54 includes a transistor Q1, a display element 58, and a storage capacitor C1 using an oxide semiconductor.

Next, an example of a method for driving the display panel 50 will be described with reference to FIG. First, in order to write the image signal V / I to the pixel, a period T1 in which the transistor Q1 is turned on and a voltage based on the image signal is supplied to the pixel electrode of the display element 58 (hereinafter referred to as “writing period T1”). Provide. In the writing period T1, since the drive circuit control signal is supplied to the drive circuit of the display unit 14, these circuits are operating.

After the writing period T1, a voltage V _pix is generated in the pixel electrode of the display element 58. Thereafter, the transistor V1 is turned off, whereby the voltage V _pix is held in the pixel electrode of the display element 58.

In the subsequent period T2 in which the voltage V _pix is held in the pixel electrode of the display element 58 (hereinafter referred to as “holding period T2”), the image signal V / I is not written. Further, since the drive circuit control signal is not supplied to the drive circuit of the display unit 14, these circuits are not operated.

The length of the holding period T2 varies depending on the off-current I _Q1 of the transistor _Q1 and the leakage current I ₅₈ of the display element 58. This is because a refresh operation for periodically rewriting the screen is necessary for the purpose of preventing the flickering of the screen due to these current fluctuations.

Here, the off-current I _Q1 of the transistor Q1 using an oxide semiconductor is extremely small. Therefore, the holding period T2, it can be said that only fluctuates by the influence of the leakage current I ₅₈ of the display device 58. Therefore, the image signal V / I written in the pixel can be held for a long time.

Further, even in normal driving, it is possible to rewrite the screen, which is normally performed 60 times per second, to about 1/1000 times. That is, power consumption can be reduced. Further, the driving circuit of the display unit 14 is not operating during the holding period T2. Therefore, the power consumption by the display unit 14 can be reduced to about 1/1000.

(About transistors using oxide semiconductors)
The oxide semiconductor disclosed in this specification will be described.
Oxide semiconductors used in transistors have the purpose of eliminating impurities such as hydrogen, moisture, hydroxyl groups, or hydroxides (also referred to as hydrogen compounds) that are the cause of donors, and then reducing these impurities at the same time. By supplying such oxygen, it is highly purified and electrically i-type (intrinsic). This is for suppressing variation in electrical characteristics of the transistor.

As described above, a transistor including a highly purified oxide semiconductor has little light deterioration.

By removing hydrogen contained in the oxide semiconductor as much as possible, the carrier density in the oxide semiconductor is less than 1 × 10 ¹⁴ / cm ³ , preferably less than 1 × 10 ¹² / cm ³ , more preferably 1 × 10 ^10. / Cm ^{3 or} less.

An oxide semiconductor that is a wide gap semiconductor has a low minority carrier density and is less likely to induce minority carriers. Therefore, in a transistor including an oxide semiconductor, it can be said that a tunnel current hardly occurs and an off current hardly flows.

In a transistor including an oxide semiconductor that is a wide gap semiconductor, collision ionization and avalanche breakdown are unlikely to occur. Therefore, it can be said that a transistor including an oxide semiconductor has resistance to hot carrier deterioration. Note that the main cause of hot carrier deterioration is that carriers increase due to avalanche breakdown, and carriers accelerated at high speed are injected into the gate insulating film.

Note that in this specification, off-state current is an n-channel in which a threshold voltage Vth is positive when an arbitrary gate voltage is applied in a range of −20 [V] to −5 [V] at room temperature. A current flowing between the source and drain of a type transistor. In addition, room temperature refers to the temperature of 15 degreeC or more and 25 degrees C or less.

A transistor using a highly purified and electrically i-type (intrinsic) oxide semiconductor has a current value per channel width W = 1 [μm] of 10 ⁻¹⁶ [A / μm] or less at room temperature. 10 ⁻¹⁸ [A / μm] = 1 [aA / μm] (a: atto) or less, more preferably 10 ⁻²¹ [A / μm] = 1 [zA / μm] (z: zept) or less is there.

(About measurement results of off-current)
The results of measuring off-state current of a transistor including a highly purified and electrically i-type (intrinsic) oxide semiconductor will be described.

First, the element for characteristic evaluation used in the current measurement method will be described with reference to FIG.
In the element for characteristic evaluation shown in FIG. 6, three measurement systems 60 are connected in parallel. Each measurement system 60 includes a capacitor C60, transistors M60 and 61 and transistors M62 and M63 using a highly purified and electrically i-type (intrinsic) oxide semiconductor.

One of the source and the drain of the transistor M60 is connected to a power source that supplies the voltage V2, the other of the source and the drain is connected to one of the source and the drain of the transistor M61, and the gate is connected to a wiring that supplies the voltage Vext_b2.

The other of the source and the drain of the transistor M61 is connected to the power supply that supplies the voltage V1, and the gate is connected to a wiring that supplies the voltage Vext_b1.

One of a source and a drain of the transistor M62 is connected to a power source that supplies the voltage V2, the other of the source and the drain is connected to an output terminal, and a gate is connected to one end of the capacitor C60.

One of a source and a drain of the transistor M63 is connected to the output terminal, and the other of the source and the drain is connected to the gate.

The other end of the capacitor C60 is connected to a power source that supplies the voltage V2.

Next, a current measurement method using the characteristic evaluation element shown in FIG. 6 will be described.
First, an initial period in which a potential difference for measuring off current is applied will be described. In the initial period, a voltage Vext_b1 that turns on the transistor M61 is input to the gate of the transistor M61, so that the transistor M61 is turned on. Then, a voltage is applied to node A which is a node connected to the other of the source and the drain of transistor M60 (that is, a node connected to one of the source and the drain of transistor M61, one end of capacitor C60, and the gate of transistor M62). V1 is input. Here, the voltage V1 is a high voltage. Further, the transistor M60 is kept in a non-conductive state.

After that, the voltage Vext_b1 that turns off the transistor M61 is input to the gate of the transistor M61, and the transistor M61 is turned off. After the transistor M61 is turned off, the voltage V1 is set to a low voltage. Here again, the transistor M60 is kept off. Further, the voltage V2 is set to a low voltage similarly to the voltage V1.

This completes the initial period. In the state where the initial period is completed, a potential difference is generated between the node A and one of the source and the drain of the transistor M60. A potential difference is also generated between the node A and the other of the source and the drain of the transistor M61. Therefore, a slight amount of charge flows through the transistor M60 and the transistor M61. That is, an off current is generated.

Next, the off-current measurement period will be described. In the measurement period, the voltages V1 and V2 are both fixed at a low voltage. Node A is in a floating state. As a result, charge flows through the transistor M60, and the amount of charge held at the node A varies with time. That is, the potential of the node A varies, and the output voltage _Vout at the output terminal also varies.

Next, a method for calculating an off-current from the obtained output potential V _out will be described. Node potential _{V A} of A is represented by the following formula (1) as a function of the output potential _{V out.}

Further, the charge Q _{A of the} node A is expressed by the following equation (2).
C _A : capacitance connected to node A (sum of capacitance of capacitor C60 and other capacitance)

Node current I _A of A is determined by the time derivative of charge (or charge flowing from the node A) flowing into the node A. Therefore, the current _{I A} of the node A is expressed by the following equation (3).

In the current measurement described below, the transistors M60 to M63 of the element for characteristic evaluation are transistors using highly purified and electrically i-type (intrinsic) oxide semiconductors. The transistor has W / L = 50/10 [μm]. In each measurement system 60 arranged in parallel, the capacitance values of the capacitor C60 are 100 [fF], 1 [pF], and 3 [pF], respectively.

The high voltage was 5V and the low voltage was 0V. In principle, the voltage V1 is a low voltage in the measurement period, but it is necessary to operate the output circuit at the timing of measuring the output potential Vout. High voltage was used. In addition, Δt in Equation (3) was about 30000 [sec].

FIG. 7 is a diagram showing the relationship between the elapsed time Time for current measurement and the output potential Vout. From this, it can be confirmed that the potential changes as time passes.

FIG. 8 is a diagram showing the off-current at room temperature (25 ° C.) calculated by current measurement. FIG. 8 shows the relationship between the source-drain voltage V and the off-current I. FIG. 8 shows that the off-state current I is about 40 [zA / μm] under the condition that the source-drain voltage is 4 [V]. Further, it can be seen that the off-state current is 10 [zA / μm] or less under the condition where the source-drain voltage is 3.1 [V].

FIG. 9 is a diagram showing the off-current in a temperature environment of 85 ° C. calculated by current measurement. FIG. 9 shows the relationship between the source-drain voltage V and the off-current I under a temperature environment of 85 ° C. FIG. 9 shows that the off-state current is 100 [zA / μm] or less under the condition where the source-drain voltage is 3.1 [V].

(Example of manufacturing method of transistor using oxide semiconductor)
Next, an example of a method for manufacturing a transistor using a highly purified and electrically i-type (intrinsic) oxide semiconductor will be described with reference to FIGS.

First, the insulating layer 101 serving as a base film is formed over the substrate 100. The insulating layer 101 is preferably formed while moisture remaining in the treatment chamber is removed. This is for preventing the insulating layer 101 from containing hydrogen, water, a hydroxyl group, a hydroxide, or the like.

Next, an oxide semiconductor layer is formed over the insulating layer 101 by a sputtering method. Note that before the oxide semiconductor layer is formed, the substrate 100 over which the insulating layer 101 is formed is preferably preheated. This is for preventing hydrogen, moisture, and a hydroxyl group from being contained in the oxide semiconductor layer as much as possible. By preheating, impurities such as hydrogen and moisture adsorbed on the substrate 100 are desorbed and exhausted.

As a target for the oxide semiconductor layer, a metal oxide target containing zinc oxide as a main component can be used. For example, as a composition ratio, a target of In ₂ O ₃ : Ga ₂ O ₃ : ZnO = 1: 1: 1, that is, In: Ga: Zn = 1: 1: 0.5 can be used. In addition, a target having a composition ratio of In: Ga: Zn = 1: 1: 1 or In: Ga: Zn = 1: 1: 2 can also be used.

In addition, In-Sn-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn- O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, Zn-O, etc. The metal oxide can be used as a target.

As the oxide semiconductor layer, a thin film represented by InMO ₃ (ZnO) _m (m> 0) can also be used. Here, M is one or more metal elements selected from Ga, Al, Mn, and Co. For example, M includes Ga, Ga and Al, Ga and Mn, or Ga and Co.

The formed oxide semiconductor layer is processed into the island-shaped oxide semiconductor layer 102 through a first photolithography step (see FIG. 10A). After that, in order to remove hydrogen, water, hydroxyl groups, and the like from the oxide semiconductor layer 102, the substrate is introduced into an electric furnace and subjected to heat treatment. This heat treatment has an effect of dehydration and dehydrogenation on the oxide semiconductor layer 102.

The temperature of this heat treatment is 400 ° C. or higher and 750 ° C. or lower, preferably 400 ° C. or higher and lower than the strain point of the substrate. In addition, the atmosphere of the heat treatment is made free from water, hydrogen, and the like.

After this heat treatment, heat treatment may be continuously performed in an oxygen atmosphere or an atmosphere containing nitrogen and oxygen (for example, a volume ratio of nitrogen: oxygen = 4: 1). This is because oxygen vacancies generated in the oxide semiconductor layer 102 are repaired.

After that, the first electrode 103a and the second electrode 103b are formed over the insulating layer 101 and the oxide semiconductor layer 102 (see FIG. 10B). The first electrode 103a functions as one of a source electrode and a drain electrode. The second electrode 103b functions as the other of the source electrode and the drain electrode.

Next, the gate insulating layer 104 is formed over the insulating layer 101, the oxide semiconductor layer 102, the first electrode 103a, and the second electrode 103b (see FIG. 10C). Note that it is preferable that hydrogen be not contained in the deposition atmosphere of the gate insulating layer 104.

Subsequently, by removing part of the gate insulating layer 104, openings 105a and 105b reaching the first electrode 103a and the second electrode 103b are formed (see FIG. 10D).

Then, the gate electrode 106, the first wiring 107a, and the second wiring 107b are formed over the gate insulating layer 104 and the openings 105a and 105b (see FIG. 10E).

As described above, a transistor including a highly purified and electrically i-type (intrinsic) oxide semiconductor can be manufactured.

DESCRIPTION OF SYMBOLS 10 1st power supply part 11 2nd power supply part 12 Detection part 13 Control part 14 Display part 15 1st battery pack 16 2nd battery pack 17 Power supply circuit 18 1st battery 19 2nd battery 20 Protection Circuit 21 RF unit 22 Sensor unit 31 Battery pack 32 Power supply circuit 33 Battery 34 Protection circuit 35 Switching regulator 36 Voltage regulator 37 Thermistor 38 Thermal fuse

Claims (7)

A display unit having memory characteristics;
A first power supply unit;
A second power supply unit;
A detection unit for detecting the power of the first power supply unit;
When the detection unit detects that the power of the first power supply unit is smaller than a predetermined value, the power of the second power supply unit is selected as the power to be supplied to the display unit, and in the display unit A control unit for controlling display contents to be initialized;
An RF unit or a sensor unit to which power is supplied from the first power supply unit and power is not supplied from the second power supply unit ,
The first power supply unit and the second power supply unit are both connected to the display unit via the control unit,
The first power supply unit is connected to the RF unit or the sensor unit without passing through the control unit . A display unit having memory characteristics;
A first power supply unit;
A second power supply unit;
A detection unit for detecting the power of the first power supply unit;
When the detection unit detects that the power of the first power supply unit is smaller than a predetermined value, the power of the second power supply unit is selected as the power to be supplied to the display unit, and in the display unit A control unit for controlling display contents to be initialized;
An RF unit or a sensor unit to which power is supplied from the first power supply unit and power is not supplied from the second power supply unit ,
The first power supply unit is connected to the display unit without going through the control unit,
The second power supply unit is connected to the display unit via the control unit ,
The first power supply unit is connected to the RF unit or the sensor unit without passing through the control unit . In claim 1 or claim 2 ,
The first power supply unit and the second power supply unit both include a battery pack,
The display device, wherein the first power supply unit and the second power supply unit share a power supply circuit. In claim 3 ,
The battery pack includes a protection circuit, a thermistor, and a thermal fuse. In claim 1 or claim 2 ,
The first power supply unit and the second power supply unit both include a battery,
The display device, wherein the first power supply unit and the second power supply unit share a protection circuit and a power supply circuit. In any one of Claims 1 thru | or 5 ,
The display unit includes a plurality of pixels,
Each of the plurality of pixels includes a transistor including an oxide semiconductor having an off-state current of 100 [zA / μm] or less under a condition of a source-drain voltage of 3.1 [V] in a temperature environment of 85 ° C. A display element and a storage capacitor;
One of a source and a drain of the transistor is connected to a source signal line;
The other of the source and drain of the transistor is connected to the display element and the storage capacitor;
A display device, wherein a gate of the transistor is connected to a gate signal line. In any one of Claims 1 thru | or 5 ,
The display unit includes a plurality of pixels,
Each of the plurality of pixels includes an electrophoretic element.