JP5723752B2 - Data transmission system and receiving apparatus - Google Patents

Description

  The present invention includes a transmission device, a reception device, and a network, and the transmission device transfers data packets and FEC packets including redundant data for FEC (Forward Error Correction) to the network, The present invention relates to a data transmission system that performs error correction using a data packet received by a receiving apparatus and the FEC packet.

  With the expansion of the IP network and the advance of QoS (Quality of Service) technology, real-time data such as video and audio can be transferred through the IP network. When transferring such real-time data, RTP (Real time Transport Protocol) is often used, and FEC is generally used as error correction for packet loss in an IP network. The packet format using RTP and the FEC method are standardized by SMPTE (Society of Motion Picture and Television Engineers), and a typical standard is to transmit TS (Transport Streams) on the IP network. There are SMPTE 2022-1 that defines the FEC scheme and SMPTE 2022-2 that defines the packet format (see Non-Patent Documents 1 and 2).

  FIG. 4 shows the FEC method defined by SMPTE 2022-1. In the SMPTE 2022-1 method, the transmission apparatus transmits an FEC packet including FEC data in addition to the data packet. This FEC packet is generated by arranging data packets to be transmitted by a transmitting apparatus on a matrix and performing an exclusive OR operation on the row side and column side of the matrix. In the receiving device, the same matrix as that created by the transmitting device is created, and when there is an unreceived packet, an exclusive OR operation including the FEC packet is performed on the row side and the column side to reproduce the unreceived packet. I can do it. As long as the operation used for error correction is exclusive OR, when there are a plurality of unreceived packets in one row and one column, recovery by error correction may not be possible. This is even more apparent when considering the use of a one-dimensional FEC consisting only of rows rather than a two-dimensional FEC consisting of rows and columns. Therefore, in order to ensure the effect of FEC in the receiving apparatus, it is necessary to receive as many packets as possible for the matrix.

  However, it does not make sense to wait forever for packets that have lost packets in the network. For this reason, the receiving apparatus generally provides a waiting time until receiving a packet to be subjected to the matrix, in other words, a time for determining a packet loss if not received by that time. This waiting time may be embodied as another parameter such as a reception buffer size depending on the implementation of the receiving device, but it is setting information that is externally set for the receiving device through a GUI or the like. It is common.

The waiting time (t) until receiving the packet at the receiving device is a function of the input rate of the packet. That is, the packet input rate is x megabits / second, the payload length in the packet is fixed to 1400 bytes, the FEC matrix size is n rows and m columns, and the estimated maximum value of packet jitter in the network estimated in advance is set. And can be calculated as follows.
Number of packets required for FEC calculation = number of data packets + number of FEC packets
= N * m + (n + m) (Formula 1)
Time required to receive packets for matrix (microseconds) = (n * m + (n + m)) × 1400 bytes × 8 bits / x megabit (Formula 2)
t = time until reception of packets for matrix + maximum predicted value of packet jitter in network (Formula 3)
It becomes. Qualitatively, this means that a long waiting time is required if the packet input rate to the receiving device is low, and a short waiting time is sufficient if the packet input rate to the receiving device is high. Conventional receivers often use a one-to-one dedicated link on the network in combination with the transmitter, and this waiting time setting or equivalent parameters such as the receive buffer size are not used when installing the device. It was set from outside through GUI etc.

SMPTE Standard ST 2022-1-2007, 2007 SMPTE Standard ST 2022-22007, 2007

  However, in recent years, when a transmission apparatus and a reception apparatus are operated in an N-to-N form through a wide area network, or when a plurality of videos are switched by a switching apparatus and transmitted to the network, the transmission source of the data packet is Therefore, the packet input rate to the receiving apparatus changes.

  FIG. 1 is a diagram showing a configuration example of a transmission system that operates a transmission apparatus and a reception apparatus in an N-to-N form. The transmission apparatuses 101 and 102 packetize the uncompressed video signals 1011 and 1021, respectively, and output data packets and FEC packets to the network 11. Here, the video signal 1011 packetized by the transmission apparatus 101 is an HD-SDI signal, for example, and the video signal 1021 packetized by the transmission apparatus 102 is an SD-SDI signal, for example. Therefore, the valid data in the data packet transmitted by the transmission apparatus 101 is 1.5 Gbps, and the valid data in the data packet transmitted by the transmission apparatus 101 is 270 Mbps. The receiving device 105 selects one of the transmission data of the transmitting devices 101 and 102 received from the network, de-packets it, and outputs it as a video signal 106. When the receiving device selects a data packet of 1.5 Gbps and when a data packet of 270 Mbps is selected, the time until the receiving device receives a packet for a matrix is greatly different, so the setting of the receiving device 105 needs to be changed. There is. In order to make this change, there is a method of controlling the receiving apparatus 105 from the control system 107 in FIG. 1 or providing another control system for controlling the receiving apparatus 105 and performing control synchronized with the control system 107. However, each method has a problem that the control is complicated in a large scale system and the cost is increased because the control is performed across the network.

  FIG. 2 is a diagram illustrating a configuration example of a transmission system that switches a plurality of uncompressed videos by a switching device and transmits and receives them via a network. The switching device 201 selects one of the uncompressed video signals input from the HD-SDI signals 2011 and 2013 and the SD-SDI signal 2012 according to an instruction from the control system 202 and outputs the selected video signal 2014. The signal rate of the HD-SDI signals 2011 and 2013 is 1.5 Gbps, and the signal rate of the SD-SDI signal 2012 is 270 Mbps. The transmission device 203 converts the uncompressed video signal 2014 input from the video signal 2014 into data packets, generates FEC packets at the same time, and sends both of these packets to the network 204. The receiving device 205 receives the packet transmitted from the transmitting device 203 from the network, performs error correction by FEC, extracts an uncompressed video signal from the packet, and outputs it as, for example, a video signal HD-SDI signal 2051. In this case, according to the rate of the uncompressed video signal selected by the switching device 201, it is necessary to change the setting of the time until the reception device 205 receives a matrix packet. In order to make this change, there is a method of controlling the receiving apparatus 205 from the control system 202 in FIG. 2 or providing another control system for controlling the receiving apparatus 205 and performing control synchronized with the control system 202. However, as in the case of FIG. 1, each method has a problem that the control is complicated in a large scale system and the cost is increased because the control is performed across the network.

  The present invention has been made in order to solve the above-described problems, and the object of the present invention is to allow the receiving device to be a target of the matrix without any external control when the input rate of packets input to the receiving device changes. It is to provide a method for autonomously changing the waiting time until a packet to be received is received.

  In order to solve the above-described problem, the receiving apparatus of the present invention has means for changing the time-out time of the means for monitoring the reception time-out using information for identifying the video signal in the received data packet.

  According to the present invention, when the input rate of packets to the receiving device changes, the waiting time until the receiving device receives a packet to be subjected to matrix can be autonomously changed without external control. it can.

It is a figure which shows an example of the system configuration | structure which can apply the Example of this invention. It is a figure which shows an example of the system configuration | structure which can apply the Example of this invention. It is a figure which shows an example of a structure of the receiver of the data transmission system of the Example of this invention. It is a figure which shows the example of the method of FEC of SMPTE2022-1. It is a figure which shows an example of a structure of the classification identification circuit in the receiver of the data transmission system of the Example of this invention. It is a figure which shows an example of a format of an RTP packet.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to these embodiments, and can be carried out in various modes without departing from the scope of the invention.

  The configuration of the data transmission system applied in the present embodiment may be the system configuration shown in FIG. 1 described above or the system configuration shown in FIG.

  The configuration of the receiving device 300 of the data transmission system of this embodiment will be described with reference to the block diagram of FIG. The receiving apparatus 300 of this embodiment receives a data packet of the format shown in FIG. 6, for example, from the network, receives an FEC packet conforming to SMPTE 2022-1 and corrects an error, and converts the resulting video stream into a video signal (eg, HD -SDI signal).

  As shown in FIG. 6, the payload of a packet received by the receiving apparatus includes a format type 64 as information for identifying a video signal. The format type 64 includes values indicating whether the payload data is HD-SDI or SD-SDI as hexadecimal numbers 00 and 10, respectively.

  3 includes, for example, a MAC circuit 301, a buffer memory 302, a waiting time circuit 303, a type identification circuit 304, an FEC circuit 305, and a video signal output circuit 306. A MAC circuit 301 is a circuit that realizes a function of a MAC (Media Access Control) sublayer of Ethernet (registered trademark), a buffer memory 302 is a buffer memory that stores received packets, and a waiting time circuit 303 is an FEC circuit. The FEC circuit 305 is a circuit that performs FEC conforming to SMPTE 2022-1, and the video signal output circuit 306 is a circuit for outputting an uncompressed video signal.

  Next, an example of a series of operations from the reception of a packet by the receiving device in this embodiment will be described.

  The MAC circuit 301 performs the MAC processing of the packet input from the Ethernet 3011, judges the packet to be received with the VLAN and the destination MAC address, and checks the normality of the packet by performing the FCS check, the packet length check, etc. The invalid packet is discarded, and the packet addressed to itself judged to be normal is written in the buffer memory 302. In this embodiment, it is assumed that the receiving apparatus can handle only one video data. Therefore, the MAC circuit 301 writes only one RTP stream packet to the buffer memory 302. Note that the packets written in the buffer memory 302 include the data packet and the FEC packet shown in FIG.

  The waiting time circuit 303 has a waiting time register 3031. After the MAC circuit 301 writes a packet to the buffer memory 302, the waiting time circuit 303 waits for the time specified by the waiting time register 3031, and then reads data from the buffer memory 302. The read data is transferred to the FEC circuit 305.

  The type identifying circuit 304 identifies the format type 64 in the data packet that the MAC circuit 301 writes to the buffer memory 302, and writes the waiting time corresponding to the format type to the waiting time register 3031. Specifies the time to wait for reading from the memory 302.

  The FEC circuit 305 uses the data received from the waiting time circuit 303 to construct an FEC matrix, performs error correction processing, recovers packet lost packets as much as possible, and obtains the data after error recovery as a result. The video signal is output to the video signal output circuit 306. The video signal output circuit 306 extracts a video stream from the data received from the FEC circuit 305 and outputs it on the uncompressed video signal.

  As described above, the waiting time in the buffer memory 302 is determined by the format type identification in the type identification circuit 304. Hereinafter, the configuration and operation of the type identification circuit 304 will be described.

  FIG. 5 is a diagram illustrating an example of the configuration of the type identification circuit 304. The type identification circuit 304 includes a format type register 5011 that extracts and holds the format type 64 from the data packet output from the MAC circuit output 3012, a rate conversion table 501, and a time calculation circuit 502.

  The type identification circuit 304 holds the format type value in the payload of the packet written by the MAC circuit 301 in the buffer memory 302 in the format type register 5011, uses the value to subtract the rate conversion table 501, and inputs the RTP stream to be input Find the input rate x. In the example shown in FIG. 5, 1500 Mbps is given to x when the format type is HD-SDI, and 270 Mbps is given to x when the format type is SD-SDI.

When the input rate value x is determined, the type identification circuit 304 uses the wait time calculation circuit 502 to calculate the time that the wait time circuit 303 waits. This waiting time calculation is performed based on the aforementioned calculation formula. That is, in order to obtain the waiting time (t), assuming that the matrix size processed by the FEC circuit 305 is n rows and m columns, and the predicted maximum value of packet jitter in the network is 50000 microseconds, the following calculation is performed.
Number of packets required for FEC calculation = n * m + (n + m) (Formula 1)
Time required to receive packets for matrix (microseconds) = (n * m + (n + m)) × 1400 bytes × 8 bits / x megabit (Formula 2)
t = time to receive packets for matrix + 50000 microseconds (Formula 4)
After calculating the waiting time value t by the above formula, the type identification circuit 304 writes the waiting time value t into the waiting time register 3031 in the waiting time circuit 303.

  The waiting time circuit 303 waits for the time specified by the waiting time register 3031 after the MAC circuit 301 writes the packet to the buffer memory 302, and then reads out and transfers the read packet to the FEC circuit 305. As a result, the packet received by the MAC circuit 301 waits for t time in the buffer memory 302.

  Through the series of operations described above, the type identifying circuit 304 identifies the format type of the packet output from the MAC circuit output 3011 and changes the waiting time in the buffer memory 302 according to the input rate of the format type. Is possible. Looking at this behavior as a receiving device, when the input rate of packets received by the receiving device changes, the waiting time until the receiving device receives a packet subject to the matrix without external control. It is possible to change autonomously.

  In the embodiment, the type identification circuit 304 has been described as a logic circuit. However, it is obvious that an equivalent function can be realized using a microprocessor and a program.

  Further, in the embodiment, for the sake of simplicity of explanation, it has been described that only one video data can be handled by the receiving device, but a configuration in which the receiving device can handle a plurality of video data may be used. The buffer memory may be increased according to the number of video data to be handled.

  The present invention operates a transmission device and a reception device in an N-to-N form, or switches a plurality of uncompressed videos using, for example, a matrix switcher and receives a transmission transmitted to a network. System control is simplified by autonomously changing the waiting time until the receiving device receives a packet subject to FEC without external control for a system in which the input rate of packets to the network changes It is extremely useful as a technique that can be realized.

Claims (4)

From a network, a transmitting apparatus for transmitting data including the FEC packets including redundant data for error correction of the data packet and the data packet of the video signal to the network, a receiving apparatus for receiving the data from the network becomes, before Symbol receiving device in the data transmission system which performs error correction by using said data packet received and the packet for FEC,
The receiving device is:
An FEC circuit that performs error correction on the received data packet using the received FEC packet;
A waiting time circuit in which a reception waiting time of a packet to be subjected to error correction in the FEC circuit is written;
The input rate to the receiving device before Symbol received packet, selected from the rate conversion table the input rate is stored corresponding to the information identifying the video signal of the received the data packet, wherein the selected input A data transmission system comprising: a type identification circuit for writing a reception waiting time corresponding to a rate into the waiting time circuit.   The data transmission system according to claim 1, wherein the type identification circuit uses a value included in a format type in a payload of the data packet as information for identifying the video signal. From transmit device, the data including the FEC packets including redundant data for error correction of the data packet and the data packet of the video signal, a receiver for receiving via the network,
An FEC circuit that performs error correction of the data packet received from the network using the FEC packet received from the network;
A waiting time circuit in which a reception waiting time of a packet to be subjected to error correction in the FEC circuit is written;
The input rate to the receiving device before Symbol received packet, selected from the rate conversion table the input rate is stored corresponding to the information identifying the video signal of the received the data packet, wherein the selected input And a type identification circuit for writing a reception waiting time corresponding to the rate into the waiting time circuit. The receiving apparatus according to claim 3 , wherein the type identifying circuit uses a value included in a format type in a payload of the data packet as information for identifying the video signal.

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